38907 lines
2.6 MiB
38907 lines
2.6 MiB
; --------------------------------------------------------------------------------
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; @Title: STM32x On-Chip Peripherals
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; @Props: Released
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; @Author: ADI, BIC, CNA, DAN, PAC, ZUB
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; @Changelog:
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; 2007-11-09
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; 2008-11-15
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; 2009-03-30
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; 2010-05-28
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; 2012-06-19
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; @Manufacturer: STM - ST Microelectronics N.V.
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; @Doc: 13902.pdf; 15056.pdf; 13259.pdf; 14610.pdf; 14611.pdf; 13587.pdf
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; 13586.pdf; 15057.pdf; 15058.pdf; 15060.pdf; 13902.pdf; 16188.pdf; 13259.pdf
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; 16211.pdf; 16455.pdf; 17143.pdf; 17144.pdf; CD00264852.pdf; 15274.pdf
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; RM0008_STM32_connectivity_02.pdf; CD00161561.pdf (2011-04)
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; CD00161566.pdf (2011-04); CD00171190.pdf (2011-10); CD00212417.pdf (2012-06)
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; CD00246267.pdf (2012-07)
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; @Core: Cortex-M3
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; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perstm32f10x.per 17736 2024-04-08 09:26:07Z kwisniewski $
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tree.close "Core Registers (Cortex-M3)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 11.
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group 0x10--0x1b
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,Clock Source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "Not SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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;group 0x14++0x03
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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;group 0x18++0x03
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current Value"
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rgroup 0x1c++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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textline " "
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rgroup 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " CONSTANT ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Number of Processor"
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bitfld.long 0x00 0.--3. " REVISION ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group 0xd04--0xd17
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Not set,Set"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not set,Set"
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bitfld.long 0x00 27. " PENDSVCLR ,Clear Pending pendSV Bit" "Not cleared,Cleared"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not set,Set"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "Not cleared,Cleared"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending"
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hexmask.long.word 0x00 12.--21. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active ISR Number Field"
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;group 0xd08++0x03
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line.long 0x04 "VTOR,Vector Table Offset Register"
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bitfld.long 0x04 29. " TBLBASE ,Table Base" "Code,RAM"
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hexmask.long.tbyte 0x04 7.--28. 1. " TBLOFF ,Vector Table Base Offset Field"
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;group 0xd0c++0x03
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "Not cleared,Cleared all"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No reset,Reset"
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;group 0xd10++0x03
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line.long 0x0c "SCR,System Control Register"
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bitfld.long 0x0c 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0c 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0c 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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;group 0xd14++0x03
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte,8-byte"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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group 0xd18--0xd23
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line.long 0x00 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x04 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x04 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x04 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x08 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x08 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x08 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x08 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x08 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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group 0xd24++0x3
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line.long 0x00 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x00 18. " USGFAULTENA ,USGFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 17. " BUSFAULTENA ,BUSFAULTENA" "Disabled,Enabled"
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bitfld.long 0x00 16. " MEMFAULTENA ,MEMFAULTENA" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault is Pended Started" "Not replaced,Replaced"
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bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced"
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textline " "
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bitfld.long 0x00 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x00 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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bitfld.long 0x00 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x00 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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bitfld.long 0x00 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x00 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group 0xd28--0xd3b
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line.byte 0x0 "MMFSR,Memory Manage Fault Status Register"
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bitfld.byte 0x0 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x0 4. " MSTKERR ,Stacking Access Violations" "No error,Error"
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bitfld.byte 0x0 3. " MUNSTKERR ,Unstack Access Violations" "No error,Error"
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textline " "
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bitfld.byte 0x0 1. " DACCVIOL ,Data Access Violation" "No error,Error"
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bitfld.byte 0x0 0. " IACCVIOL ,Instruction Access Violation" "No error,Error"
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;group 0xd29++0x00
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid" "Not valid,Valid"
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bitfld.byte 0x01 4. " STKERR ,Stacking from Exception has Caused Bus Faults" "No error,Error"
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bitfld.byte 0x01 3. " UNSTKERR ,Unstack from Exception Return has Caused Bus Faults" "No error,Error"
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textline " "
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise Data Bus Error" "No error,Error"
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bitfld.byte 0x01 1. " PRECISERR ,Precise Data Bus Error Return" "No error,Error"
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bitfld.byte 0x01 0. " IBUSERR ,Instruction Bus Error Flag" "No error,Error"
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;group 0xd2a++0x01
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line.word 0x02 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x02 9. " DIVBYZERO ,Illegal PC Load" "No error,Error"
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bitfld.word 0x02 8. " UNALIGNED ,Illegal Unaligned Access" "No error,Error"
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bitfld.word 0x02 3. " NOCP ,Attempt to use a coprocessor instruction" "No error,Error"
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textline " "
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bitfld.word 0x02 2. " INVPC ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error"
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bitfld.word 0x02 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x02 0. " UNDEFINSTR ,Illegal Processor State" "No error,Error"
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;group 0xd2c++0x03
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line.long 0x04 "HFSR,Hard Fault Status Register"
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bitfld.long 0x04 31. " DEBUGEVT ,This Bit is Set if There is a Fault Related to Debug" "No error,Error"
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bitfld.long 0x04 30. " FORCED ,Hard Fault Activated" "No error,Error"
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bitfld.long 0x04 1. " VECTTBL ,Bus Fault" "No error,Error"
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;group 0xd30++0x03
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line.long 0x08 "DFSR,Debug Fault Status Register"
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bitfld.long 0x08 4. " EXTERNAL ,External Debug Request Flag" "Not asserted,Asserted"
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bitfld.long 0x08 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x08 2. " DWTTRAP ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched"
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textline " "
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bitfld.long 0x08 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x08 0. " HALTED ,Halt Request Flag" "Not requested,Requested"
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;group 0xd34++0x03
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line.long 0xc "MMFAR,Memory Manage Fault Address Register"
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;group 0xd38++0x03
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line.long 0x10 "BFAR,Bus Fault Address Register"
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wgroup 0xf00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Feature Registers"
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width 10.
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
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bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
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line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
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bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
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bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
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textline " "
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bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
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bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
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bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
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tree.end
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tree "CoreSight Identification Registers"
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width 6.
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "PID0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "PID1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 5. " C_SNAPSTALL ,Halting debug to gain control of the core" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001)
|
|
group 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step"
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..."
|
|
group 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group 0x00--0x27
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
hexmask.long.tbyte 0x04 5.--28. 1. " REMAP ,Remap Base Address Field"
|
|
;group 0x08++0x03
|
|
line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x8 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x8 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0xC 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0xC 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x10 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x10 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x14 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x14 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x18 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x18 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x1C 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x1C 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x20 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x20 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x24 2.--28. 1. " COMP ,Comparison Address"
|
|
bitfld.long 0x24 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID0"
|
|
line.long 0x14 "PID1,Peripheral ID1"
|
|
line.long 0x18 "PID2,Peripheral ID2"
|
|
line.long 0x1c "PID3,Peripheral ID3"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group 0x00--0x1B
|
|
line.long 0x00 "DWT_CTRL,DWT Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables Cycle Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables Folded Instruction Count Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables LSU Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables Interrupt Overhead Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables CPI Count Event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables Interrupt Event Tracing" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10"
|
|
bitfld.long 0x00 5.--8. " POSTCNT ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled"
|
|
;group 0x04++0x03
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
;group 0x08++0x03
|
|
line.long 0x08 "DWT_CPICNT,DWT CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
;group 0x0c++0x03
|
|
line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
;group 0x10++0x03
|
|
line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
;group 0x14++0x03
|
|
line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
;group 0x18++0x03
|
|
line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res"
|
|
bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set"
|
|
bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..."
|
|
endif
|
|
tree "Coresight Management Registers"
|
|
rgroup 0xfd0--0xfff
|
|
line.long 0x00 "PID4,Peripheral ID4"
|
|
line.long 0x04 "PID5,Peripheral ID5"
|
|
line.long 0x08 "PID6,Peripheral ID6"
|
|
line.long 0x0c "PID7,Peripheral ID7"
|
|
line.long 0x10 "PID0,Peripheral ID1"
|
|
line.long 0x14 "PID1,Peripheral ID2"
|
|
line.long 0x18 "PID2,Peripheral ID3"
|
|
line.long 0x1c "PID3,Peripheral ID4"
|
|
line.long 0x20 "CID0,Component ID0"
|
|
line.long 0x24 "CID1,Component ID1"
|
|
line.long 0x28 "CID2,Component ID2"
|
|
line.long 0x2c "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "Flash Memory Interface"
|
|
base ad:0x40022000
|
|
width 15.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "FLASH_ACR,Flash Access Control Register"
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&(!cpuis("STM32F100RC"))&&(!cpuis("STM32F100RD"))&&(!cpuis("STM32F100RE"))&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&(!cpuis("STM32F100VC"))&&(!cpuis("STM32F100VD"))&&(!cpuis("STM32F100VE"))&&(!cpuis("STM32F100ZC"))&&(!cpuis("STM32F100ZD"))&&(!cpuis("STM32F100ZE")))
|
|
bitfld.long 0x00 5. " PRFTBS ,Prefetch Buffer Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRFTBE ,Prefetch Buffer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " HLFCYA ,Flash Half Cycle Access Enable" "Disabled,Enabled"
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&(!cpuis("STM32F100RC"))&&(!cpuis("STM32F100RD"))&&(!cpuis("STM32F100RE"))&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&(!cpuis("STM32F100VC"))&&(!cpuis("STM32F100VD"))&&(!cpuis("STM32F100VE"))&&(!cpuis("STM32F100ZC"))&&(!cpuis("STM32F100ZD"))&&(!cpuis("STM32F100ZE")))
|
|
bitfld.long 0x00 0.--2. " LATENCY ,Latency" "Zero if 0<SYSCLK<=24,One if 24<SYSCLK<=48,Two if 48<SYSCLK<=72,?..."
|
|
endif
|
|
wgroup.long 0x04++0x7
|
|
line.long 0x00 "FLASH_KEYR,FPEC Key Register"
|
|
line.long 0x04 "FLASH_OPTKEYR,Flash OPTKEY Register"
|
|
group.long 0x0C++0x7
|
|
line.long 0x00 "FLASH_SR,Flash Status Register"
|
|
eventfld.long 0x00 5. " EOP ,End of operation" "No effect,Completed"
|
|
eventfld.long 0x00 4. " WRPRTERR ,Write Protection Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PGERR ,Programming Error" "No error,Error"
|
|
bitfld.long 0x00 0. " BSY ,Busy" "Not busy/Error,Busy"
|
|
line.long 0x04 "FLASH_CR,Flash Control Register"
|
|
bitfld.long 0x04 12. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ERRIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OPTWRE ,Option Bytes Write Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " LOCK ,Lock" "Unlock,Lock"
|
|
textline " "
|
|
bitfld.long 0x04 6. " STRT ,Start" "No effect,ERASE"
|
|
bitfld.long 0x04 5. " OPTER ,Option Byte Erase" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " OPTPG ,Option Byte Programming" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " MER ,Mass Erase" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PER ,Page Erase" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PG ,Programming" "Disabled,Enabled"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x00 "FLASH_AR,Flash Address Register"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x00 "FLASH_OBR,Option Byte Register"
|
|
hexmask.long.byte 0x00 18.--25. 1. " DATA1 ,Data bits 1"
|
|
hexmask.long.byte 0x00 10.--17. 1. " DATA0 ,Data bits 0"
|
|
textline " "
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F103*F")||cpuis("STM32F103*G"))
|
|
bitfld.long 0x00 5. " BFB2 ,BFB2" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " nRST_STDBY ,Reset event when entering Standby mode" "Reset,No reset"
|
|
bitfld.long 0x00 3. " nRST_STOP ,Reset event when entering Stop mode" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WDG_SW ,Select the watchdog event: Hardware or software" "Hardware,Software"
|
|
bitfld.long 0x00 1. " RDPRT ,Read protection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPTERR ,Option Byte Error" "No error,Error"
|
|
line.long 0x04 "FLASH_WRPR,Write Protection Register"
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F103*F")||cpuis("STM32F103*G"))
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "FLASH_KEYR2,FPEC Key Register 2"
|
|
group.long 0x4c++0x07
|
|
line.long 0x00 "FLASH_SR2,Flash Status Register 2"
|
|
eventfld.long 0x00 5. " EOP ,End of operation" "No effect,Completed"
|
|
eventfld.long 0x00 4. " WRPRTERR ,Write Protection Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PGERR ,Programming Error" "No error,Error"
|
|
bitfld.long 0x00 0. " BSY ,Busy" "Not busy/Error,Busy"
|
|
line.long 0x04 "FLASH_CR2,Flash Control Register 2"
|
|
bitfld.long 0x04 12. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ERRIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LOCK ,Lock" "Unlock,Lock"
|
|
bitfld.long 0x04 6. " STRT ,Start" "No effect,ERASE"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MER ,Mass Erase" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PER ,Page Erase" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PG ,Programming" "Disabled,Enabled"
|
|
wgroup.long 0x54++0x3
|
|
line.long 0x00 "FLASH_AR2,Flash Address Register 2"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40023000
|
|
width 9.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CRC_DR,Data Register"
|
|
sif cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L15??6-A")||cpuis("STM32L15??8-A")||cpuis("STM32L15??B-A")||cpuis("STM32L15??C-A")||cpuis("STM32L15??C")||cpuis("STM32L162?C-A")||cpuis("STM32L162?C")||cpuis("STM32L15??E")||cpuis("STM32L16??E")||cpuis("STM32L15?VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRC_IDR,Independent Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDR ,General-purpose 8-bit Data Register Bits"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "CRC_IDR,Independent Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " IDR ,General-purpose 8-bit Data Register Bits"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CRC_CR,Control Register"
|
|
bitfld.long 0x00 0. " RESET ,Reset Bit" "No reset,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWR_CR (Power Control Register)"
|
|
base ad:0x40007000
|
|
width 9.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "PWR_CR,Power control register"
|
|
bitfld.long 0x00 8. " DBP ,Disable Backup Domain write protection" "No,Yes"
|
|
bitfld.long 0x00 5.--7. " PLS ,PVD Level Selection" "2.2V,2.3V,2.4V,2.5V,2.6V,2.7V,2.8V,2.9V"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PVDE ,Power Voltage Detector Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CSBF ,Clear STANDBY Flag" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CWUF ,Clear Wake-up Flag" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " PDDS ,Power Down Deepsleep" "Stop,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPDS ,Low-Power Deepsleep" "Normal,Low-power"
|
|
line.long 0x04 "PWR_CSR,Power control/status register"
|
|
bitfld.long 0x04 8. " EWUP ,Enable WKUP pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PVDO ,PVD Output" "VDD>PVD threshold,VDD<PVD threshold"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SBF ,STANDBY Flag" "No standby,Standby"
|
|
bitfld.long 0x04 0. " WUF ,Wake-Up Flag" "No wake-up,Wake-up"
|
|
width 0xB
|
|
tree.end
|
|
tree "BKP (Backup)"
|
|
base ad:0x40006C00
|
|
width 11.
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BKP_DR1,Backup data register 1"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BKP_DR2,Backup data register 2"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BKP_DR3,Backup data register 3"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "BKP_DR4,Backup data register 4"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "BKP_DR5,Backup data register 5"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "BKP_DR6,Backup data register 6"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BKP_DR7,Backup data register 7"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BKP_DR8,Backup data register 8"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "BKP_DR9,Backup data register 9"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "BKP_DR10,Backup data register 10"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&(!cpuis("STM32F100RC"))&&(!cpuis("STM32F100RD"))&&(!cpuis("STM32F100RE"))&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&(!cpuis("STM32F100VC"))&&(!cpuis("STM32F100VD"))&&(!cpuis("STM32F100VE"))&&(!cpuis("STM32F100ZC"))&&(!cpuis("STM32F100ZD"))&&(!cpuis("STM32F100ZE")))
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "BKP_DR11,Backup data register 11"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "BKP_DR12,Backup data register 12"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "BKP_DR13,Backup data register 13"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "BKP_DR14,Backup data register 14"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "BKP_DR15,Backup data register 15"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x54++0x1
|
|
line.word 0x00 "BKP_DR16,Backup data register 16"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x58++0x1
|
|
line.word 0x00 "BKP_DR17,Backup data register 17"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x5C++0x1
|
|
line.word 0x00 "BKP_DR18,Backup data register 18"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x60++0x1
|
|
line.word 0x00 "BKP_DR19,Backup data register 19"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x64++0x1
|
|
line.word 0x00 "BKP_DR20,Backup data register 20"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x68++0x1
|
|
line.word 0x00 "BKP_DR21,Backup data register 21"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x6C++0x1
|
|
line.word 0x00 "BKP_DR22,Backup data register 22"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x70++0x1
|
|
line.word 0x00 "BKP_DR23,Backup data register 23"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x74++0x1
|
|
line.word 0x00 "BKP_DR24,Backup data register 24"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x78++0x1
|
|
line.word 0x00 "BKP_DR25,Backup data register 25"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x7C++0x1
|
|
line.word 0x00 "BKP_DR26,Backup data register 26"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x80++0x1
|
|
line.word 0x00 "BKP_DR27,Backup data register 27"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x84++0x1
|
|
line.word 0x00 "BKP_DR28,Backup data register 28"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x88++0x1
|
|
line.word 0x00 "BKP_DR29,Backup data register 29"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x8C++0x1
|
|
line.word 0x00 "BKP_DR30,Backup data register 30"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x90++0x1
|
|
line.word 0x00 "BKP_DR31,Backup data register 31"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x94++0x1
|
|
line.word 0x00 "BKP_DR32,Backup data register 32"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x98++0x1
|
|
line.word 0x00 "BKP_DR33,Backup data register 33"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0x9C++0x1
|
|
line.word 0x00 "BKP_DR34,Backup data register 34"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0xA0++0x1
|
|
line.word 0x00 "BKP_DR35,Backup data register 35"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0xA4++0x1
|
|
line.word 0x00 "BKP_DR36,Backup data register 36"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0xA8++0x1
|
|
line.word 0x00 "BKP_DR37,Backup data register 37"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0xAC++0x1
|
|
line.word 0x00 "BKP_DR38,Backup data register 38"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0xB0++0x1
|
|
line.word 0x00 "BKP_DR39,Backup data register 39"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0xB4++0x1
|
|
line.word 0x00 "BKP_DR40,Backup data register 40"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0xB8++0x1
|
|
line.word 0x00 "BKP_DR41,Backup data register 41"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
group.word 0xBC++0x1
|
|
line.word 0x00 "BKP_DR42,Backup data register 42"
|
|
hexmask.word 0x00 0.--15. 1. " D ,Backup data"
|
|
endif
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "BKP_RTCCR,RTC clock calibration register"
|
|
bitfld.word 0x00 9. " ASOS ,Alarm or Second Output Selection" "Alarm,Second"
|
|
bitfld.word 0x00 8. " ASOE ,Alarm or Second Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CCO ,Calibration Clock Output" "No effect,RTC/64"
|
|
hexmask.word.byte 0x00 0.--6. 1. " CAL ,Calibration value"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "BKP_CR,Backup control register"
|
|
bitfld.word 0x00 1. " TPAL ,Tamper pin active level" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TPE ,Tamper pin enable" "Free,Activated"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "BKP_CSR,Backup control/status register"
|
|
bitfld.word 0x00 9. " TIF ,Tamper Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 8. " TEF ,Tamper Event Flag" "No event,Event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TPIE ,Tamper Pin interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CTI ,Clear Tamper Interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CTE ,Clear Tamper event" "No effect,Reset"
|
|
width 0xB
|
|
tree.end
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
sif (cpuis("STM32F102*"))
|
|
width 14.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
bitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HSERDY ,External High Speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,External High Speed clock enable" "Off,On"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,Internal High Speed clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,Internal High Speed clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSIRDY ,Internal High Speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,Internal High Speed clock enable" "Off,On"
|
|
line.long 0x04 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x04 24.--26. " MCO ,Microcontroller Clock Output" "No clock,No clock,No clock,No clock,System,Internal,External,PLL/2"
|
|
bitfld.long 0x04 22. " USBPRE ,USB prescaler" "PLL/1.5,PLL"
|
|
textline " "
|
|
bitfld.long 0x04 18.--21. " PLLMUL ,PLL Multiplication Factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
bitfld.long 0x04 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PLLSRC ,PLL entry clock source" "HSI/2,HSE"
|
|
bitfld.long 0x04 14.--15. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4,PLCK2/6,PLCK2/8"
|
|
textline " "
|
|
bitfld.long 0x04 11.--13. " PPRE2 ,APB High speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
bitfld.long 0x04 8.--10. " PPRE1 ,APB Low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
bitfld.long 0x04 2.--3. " SWS ,System Clock Switch Status" "HSI,HSE,PLL,Not applicable"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SW ,System clock Switch" "HSI,HSE,PLL,Not allowed"
|
|
line.long 0x08 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x08 23. " CSSC ,Clock Security System Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " PLLRDYC ,PLL Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HSERDYC ,HSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " HSIRDYC ,HSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " LSERDYC ,LSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " LSIRDYC ,LSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSSF ,Clock Security System Interrupt flag" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PLLRDYF ,PLL Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 3. " HSERDYF ,HSE Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 2. " HSIRDYF ,HSI Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 1. " LSERDYF ,LSE Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 0. " LSIRDYF ,LSI Ready Interrupt flag" "Not ready,Ready"
|
|
line.long 0x0C "RCC_APB2RSTR,APB2 Peripheral reset register"
|
|
bitfld.long 0x0C 14. " USART1RST ,USART1 reset" "No effect,Reset"
|
|
bitfld.long 0x0C 12. " SPI1RST ,SPI 1 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " ADC1RST ,ADC 1 interface reset" "No effect,Reset"
|
|
bitfld.long 0x0C 5. " IOPDRST ,IO port D reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " IOPCRST ,IO port C reset" "No effect,Reset"
|
|
bitfld.long 0x0C 3. " IOPBRST ,IO port B reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
bitfld.long 0x0C 0. " AFIORST ,Alternate Function I/O reset" "No effect,Reset"
|
|
line.long 0x10 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
bitfld.long 0x10 28. " PWRRST ,Power interface reset" "No effect,Reset"
|
|
bitfld.long 0x10 27. " BKPRST ,Backup interface reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 23. " USBRST ,USB reset" "No effect,Reset"
|
|
sif (cpuis("STM32F102*8")||cpuis("STM32F102*B"))
|
|
bitfld.long 0x10 22. " I2C2RST ,I2C 2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
bitfld.long 0x10 18. " USART3RST ,USART 3 reset" "No effect,Reset"
|
|
else
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
sif (cpuis("STM32F102*8")||cpuis("STM32F102*B"))
|
|
bitfld.long 0x10 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
bitfld.long 0x10 2. " TIM4RST ,Timer 4 reset" "No effect,Reset"
|
|
else
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
line.long 0x14 "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
bitfld.long 0x14 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DMAEN ,DMA clock enable" "Disabled,Enabled"
|
|
line.long 0x18 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
bitfld.long 0x18 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " SPI1EN ,SPI 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " AFIOEN ,Alternate Function I/O clock enable" "Disabled,Enabled"
|
|
line.long 0x1C "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
bitfld.long 0x1C 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 27. " BKPEN ,Backup interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " USBEN ,USB clock enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32F102*8")||cpuis("STM32F102*B"))
|
|
bitfld.long 0x1C 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 18. " USART3EN ,USART 3 clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x1C 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1C 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32F102*8")||cpuis("STM32F102*B"))
|
|
bitfld.long 0x1C 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " TIM4EN ,Timer 4 clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x1C 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1C 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
line.long 0x20 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x20 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x20 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x20 2. " LSEBYP ,External Low Speed oscillator Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x20 1. " LSERDY ,External Low Speed oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x20 0. " LSEON ,External Low Speed oscillator enable" "Off,On"
|
|
line.long 0x24 "RCC_CSR,Control/status register"
|
|
bitfld.long 0x24 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 24. " RMVF ,Remove reset flag" "Not activated,Reset"
|
|
bitfld.long 0x24 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x24 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
width 0xB
|
|
elif (cpuis("STM32F100*"))
|
|
width 14.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
bitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HSERDY ,External High Speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,External High Speed clock enable" "Off,On"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,Internal High Speed clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,Internal High Speed clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSIRDY ,Internal High Speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,Internal High Speed clock enable" "Off,On"
|
|
line.long 0x04 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x04 24.--26. " MCO ,Microcontroller Clock Output" "No clock,No clock,No clock,No clock,System,Internal,External,PLL/2"
|
|
bitfld.long 0x04 18.--21. " PLLMUL ,PLL Multiplication Factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
bitfld.long 0x04 16. " PLLSRC ,PLL entry clock source" "HSI/2,HSE"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4,PLCK2/6,PLCK2/8"
|
|
bitfld.long 0x04 11.--13. " PPRE2 ,APB High speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " PPRE1 ,APB Low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
bitfld.long 0x04 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " SWS ,System Clock Switch Status" "HSI,HSE,PLL,Not applicable"
|
|
bitfld.long 0x04 0.--1. " SW ,System clock Switch" "HSI,HSE,PLL,Not allowed"
|
|
line.long 0x08 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x08 23. " CSSC ,Clock Security System Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " PLLRDYC ,PLL Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HSERDYC ,HSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " HSIRDYC ,HSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " LSERDYC ,LSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " LSIRDYC ,LSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSSF ,Clock Security System Interrupt flag" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PLLRDYF ,PLL Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 3. " HSERDYF ,HSE Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 2. " HSIRDYF ,HSI Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 1. " LSERDYF ,LSE Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 0. " LSIRDYF ,LSI Ready Interrupt flag" "Not ready,Ready"
|
|
line.long 0x0c "RCC_APB2RSTR,APB2 Peripheral reset register"
|
|
bitfld.long 0x0c 18. " TIM17RST ,TIM17 timer reset" "No effect,Reset"
|
|
bitfld.long 0x0c 17. " TIM16RST ,TIM16 timer reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " TIM15RST ,TIM15 timer reset" "No effect,Reset"
|
|
bitfld.long 0x0c 14. " USART1RST ,USART1 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " SPI1RST ,SPI1 reset" "No effect,Reset"
|
|
bitfld.long 0x0c 11. " TIM1RST ,TIM1 timer reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " ADC1RST ,ADC 1 interface reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x0c 8. " IOPGRST ,IO port G reset" "No effect,Reset"
|
|
bitfld.long 0x0c 7. " IOPFRST ,IO port F reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F100V*"))
|
|
bitfld.long 0x0c 6. " IOPERST ,IO port E reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 5. " IOPDRST ,IO port D reset" "No effect,Reset"
|
|
bitfld.long 0x0c 4. " IOPCRST ,IO port C reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " IOPBRST ,IO port B reset" "No effect,Reset"
|
|
bitfld.long 0x0c 2. " IOPARST ,IO port A reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " AFIORST ,Alternate function I/O reset" "No effect,Reset"
|
|
line.long 0x10 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
bitfld.long 0x10 30. " CECRST ,CEC reset" "No effect,Reset"
|
|
bitfld.long 0x10 29. " DACRST ,DAC interface reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 28. " PWRRST ,Power interface reset" "No effect,Reset"
|
|
bitfld.long 0x10 27. " BKPRST ,Backup interface reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32F100*8")||cpuis("STM32F100*B")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x10 22. " I2C2RST ,I2C 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x10 20. " UART5RST ,USART 5 reset" "No effect,Reset"
|
|
bitfld.long 0x10 19. " UART4RST ,USART 4 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 18. " USART3RST ,USART 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x10 15. " SPI3RST ,SPI 3 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 11. " WWDGRST ,Window watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
bitfld.long 0x10 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 11. " WWDGRST ,Window watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x10 8. " TIM14RST ,TIM14 timer reset" "No effect,Reset"
|
|
bitfld.long 0x10 7. " TIM13RST ,TIM13 timer reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 6. " TIM12RST ,TIM12 timer reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("STM32F100RC"))&&(!cpuis("STM32F100RD"))&&(!cpuis("STM32F100RE"))&&(!cpuis("STM32F100VC"))&&(!cpuis("STM32F100VD"))&&(!cpuis("STM32F100VE"))&&(!cpuis("STM32F100ZC"))&&(!cpuis("STM32F100ZD"))&&(!cpuis("STM32F100ZE")))
|
|
bitfld.long 0x10 5. " TIM7RST ,TIM7 timer reset" "No effect,Reset"
|
|
bitfld.long 0x10 4. " TIM6RST ,TIM6 timer reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F100*8")||cpuis("STM32F100*B")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x10 3. " TIM5RST ,TIM5 timer reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 2. " TIM4RST ,TIM4 timer reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 1. " TIM3RST ,TIM3 timer reset" "No effect,Reset"
|
|
bitfld.long 0x10 0. " TIM2RST ,TIM2 timer reset" "No effect,Reset"
|
|
line.long 0x14 "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
sif (cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x14 8. " FSMCEN ,FSMC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x14 1. " DMA2EN ,DMA2 clock enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 0. " DMA1EN ,DMA1 clock enable" "Disabled,Enabled"
|
|
line.long 0x18 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
bitfld.long 0x18 18. " TIM17EN ,TIM17 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 12. " SPI1EN ,SPI 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " TIM1EN ,TIM1 Timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x18 8. " IOPGEN ,I/O port G clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " IOPFEN ,I/O port F clock enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32F100V*"))
|
|
bitfld.long 0x18 6. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 5. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " AFIOEN ,Alternate Function I/O clock enable" "Disabled,Enabled"
|
|
line.long 0x1c "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
bitfld.long 0x1c 30. " CECEN ,CEC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 29. " DACEN ,DAC interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 27. " BKPEN ,Backup interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F100*8")||cpuis("STM32F100*B")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x1c 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x1c 20. " UART5EN ,USART 5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 19. " UART4EN ,USART 4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1c 18. " USART3EN ,USART 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x1c 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1c 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1c 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("STM32F100RC"))&&(!cpuis("STM32F100RD"))&&(!cpuis("STM32F100RE"))&&(!cpuis("STM32F100VC"))&&(!cpuis("STM32F100VD"))&&(!cpuis("STM32F100VE"))&&(!cpuis("STM32F100ZC"))&&(!cpuis("STM32F100ZD"))&&(!cpuis("STM32F100ZE")))
|
|
bitfld.long 0x1c 5. " TIM7EN ,Timer 7 enable" "No effect,Reset"
|
|
bitfld.long 0x1c 4. " TIM6EN ,Timer 6 enable" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F100*8")||cpuis("STM32F100*B")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x1c 3. " TIM5EN ,Timer 5 enable" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1c 2. " TIM4EN ,Timer 4 enable" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1c 1. " TIM3EN ,Timer 3 enable" "No effect,Reset"
|
|
bitfld.long 0x1c 0. " TIM2EN ,Timer 2 enable" "No effect,Reset"
|
|
line.long 0x20 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x20 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x20 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x20 2. " LSEBYP ,External Low Speed oscillator Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x20 1. " LSERDY ,External Low Speed oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x20 0. " LSEON ,External Low Speed oscillator enable" "Off,On"
|
|
line.long 0x24 "RCC_CSR,Control/status register"
|
|
bitfld.long 0x24 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 24. " RMVF ,Remove reset flag" "Not activated,Reset"
|
|
bitfld.long 0x24 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x24 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RCC_CFGR2,Clock configuration register 2"
|
|
bitfld.long 0x00 0.--3. " PREDIV1 ,PREDIV1 division factor" "PREDIV1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
width 0xB
|
|
elif (cpuis("STM32F101*"))
|
|
width 14.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
bitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HSERDY ,External High Speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,External High Speed clock enable" "Off,On"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,Internal High Speed clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,Internal High Speed clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSIRDY ,Internal High Speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,Internal High Speed clock enable" "Off,On"
|
|
line.long 0x04 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x04 24.--26. " MCO ,Microcontroller Clock Output" "No clock,No clock,No clock,No clock,System,Internal,External,PLL/2"
|
|
bitfld.long 0x04 18.--21. " PLLMUL ,PLL Multiplication Factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
bitfld.long 0x04 16. " PLLSRC ,PLL entry clock source" "HSI/2,HSE"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4,PLCK2/6,PLCK2/8"
|
|
bitfld.long 0x04 11.--13. " PPRE2 ,APB High speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " PPRE1 ,APB Low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
bitfld.long 0x04 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " SWS ,System Clock Switch Status" "HSI,HSE,PLL,Not applicable"
|
|
bitfld.long 0x04 0.--1. " SW ,System clock Switch" "HSI,HSE,PLL,Not allowed"
|
|
line.long 0x08 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x08 23. " CSSC ,Clock Security System Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " PLLRDYC ,PLL Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HSERDYC ,HSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " HSIRDYC ,HSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " LSERDYC ,LSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " LSIRDYC ,LSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSSF ,Clock Security System Interrupt flag" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PLLRDYF ,PLL Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 3. " HSERDYF ,HSE Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 2. " HSIRDYF ,HSI Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 1. " LSERDYF ,LSE Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 0. " LSIRDYF ,LSI Ready Interrupt flag" "Not ready,Ready"
|
|
line.long 0x0c "RCC_APB2RSTR,APB2 Peripheral reset register"
|
|
sif (cpuis("STM32F101*F")||cpuis("STM32F101*G"))
|
|
bitfld.long 0x0c 21. " TIM11RST ,TIM11 timer reset" "No effect,Reset"
|
|
bitfld.long 0x0c 20. " TIM10RST ,TIM10 timer reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " TIM9RST ,TIM9 timer reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0c 14. " USART1RST ,USART1 reset" "No effect,Reset"
|
|
bitfld.long 0x0c 12. " SPI1RST ,SPI 1 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32F101Z*")||cpu()=="STM32F101")
|
|
bitfld.long 0x0c 9. " ADC1RST ,ADC 1 interface reset" "No effect,Reset"
|
|
bitfld.long 0x0c 8. " IOPGRST ,IO port G reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " IOPFRST ,IO port F reset" "No effect,Reset"
|
|
bitfld.long 0x0c 6. " IOPERST ,IO port E reset" "No effect,Reset"
|
|
elif (cpuis("STM32F101V*"))
|
|
bitfld.long 0x0c 9. " ADC1RST ,ADC 1 interface reset" "No effect,Reset"
|
|
bitfld.long 0x0c 6. " IOPERST ,IO port E reset" "No effect,Reset"
|
|
else
|
|
bitfld.long 0x0c 9. " ADC1RST ,ADC 1 interface reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 5. " IOPDRST ,IO port D reset" "No effect,Reset"
|
|
sif (cpu()!="STM32F101T8"&&cpu()!="STM32F101T6"&&cpu()!="STM32F101T4"&&(!cpuis("STM32F101TB")))
|
|
textline " "
|
|
bitfld.long 0x0c 4. " IOPCRST ,IO port C reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 3. " IOPBRST ,IO port B reset" "No effect,Reset"
|
|
bitfld.long 0x0c 2. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " AFIORST ,Alternate Function I/O reset" "No effect,Reset"
|
|
line.long 0x10 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F101*E")||cpuis("STM32F101*D")||cpuis("STM32F101*C")||cpu()=="STM32F101")
|
|
bitfld.long 0x10 29. " DACRST ,DAC interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 28. " PWRRST ,Power interface reset" "No effect,Reset"
|
|
bitfld.long 0x10 27. " BKPRST ,Backup interface reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()==("STM32F101T8")||cpuis("STM32F101TB")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 22. " I2C2RST ,I2C 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F101*E")||cpuis("STM32F101*D")||cpuis("STM32F101*C")||cpu()=="STM32F101")
|
|
bitfld.long 0x10 20. " UART5RST ,USART 5 reset" "No effect,Reset"
|
|
bitfld.long 0x10 19. " UART4RST ,USART 4 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 18. " USART3RST ,USART 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
elif (cpu()=="STM32F101T8"||cpuis("STM32F101TB")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x10 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 18. " USART3RST ,USART 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F101*E")||cpuis("STM32F101*D")||cpuis("STM32F101*C")||cpu()=="STM32F101")
|
|
bitfld.long 0x10 15. " SPI3RST ,SPI 3 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
elif (cpu()=="STM32F101T8"||cpuis("STM32F101TB")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F"))
|
|
bitfld.long 0x10 8. " TIM14RST , Timer 14 reset" "No effect,Reset"
|
|
bitfld.long 0x10 7. " TIM13RST , Timer 13 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 6. " TIM12RST , Timer 12 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F101*E")||cpuis("STM32F101*D")||cpuis("STM32F101*C")||cpu()=="STM32F101")
|
|
bitfld.long 0x10 5. " TIM7RST ,Timer 7 reset" "No effect,Reset"
|
|
bitfld.long 0x10 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TIM5RST ,Timer 5 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x10 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
else
|
|
bitfld.long 0x10 2. " TIM4RST ,Timer 4 reset" "No effect,Reset"
|
|
bitfld.long 0x10 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
endif
|
|
line.long 0x14 "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
sif (cpu()=="STM32F101VC"||cpu()=="STM32F101VD"||cpu()=="STM32F101VE"||cpu()=="STM32F101ZC"||cpu()=="STM32F101ZD"||cpu()=="STM32F101ZE"||cpu()=="STM32F101"||cpu()=="STM32F101VF"||cpu()=="STM32F101VG"||cpu()=="STM32F101ZF"||cpu()=="STM32F101ZG")
|
|
bitfld.long 0x14 8. " FSMCEN ,FSMC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F101*E")||cpuis("STM32F101*D")||cpuis("STM32F101*C")||cpu()=="STM32F101")
|
|
bitfld.long 0x14 1. " DMA2EN ,DMA2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DMA1EN ,DMA1 clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 0. " DMAEN ,DMA clock enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x18 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
sif (cpuis("STM32F101*F")||cpuis("STM32F101*G"))
|
|
bitfld.long 0x18 21. " TIM11EN ,TIM11 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " TIM10EN ,TIM10 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 19. " TIM9EN ,TIM9 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " SPI1EN ,SPI 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F101Z*")||cpu()=="STM32F101")
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " IOPGEN ,I/O port G clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " IOPFEN ,I/O port F clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
elif (cpuis("STM32F101V*"))
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 5. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
sif (cpu()!="STM32F101T8"&&cpu()!="STM32F101T6"&&cpu()!="STM32F101T4"&&(!cpuis("STM32F101TB")))
|
|
textline " "
|
|
bitfld.long 0x18 4. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 3. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " AFIOEN ,Alternate Function I/O clock enable" "Disabled,Enabled"
|
|
line.long 0x1C "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F101*E")||cpuis("STM32F101*D")||cpuis("STM32F101*C")||cpu()=="STM32F101")
|
|
bitfld.long 0x1c 29. " DACEN ,DAC interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1c 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 27. " BKPEN ,Backup interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="STM32F101T8"||cpuis("STM32F101TB")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x1c 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1c 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F101*E")||cpuis("STM32F101*D")||cpuis("STM32F101*C")||cpu()=="STM32F101")
|
|
bitfld.long 0x1c 20. " UART5EN ,USART 5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 19. " UART4EN ,USART 4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 18. " USART3EN ,USART 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpu()=="STM32F101T8"||cpuis("STM32F101TB")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x1c 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1c 18. " USART3EN ,USART 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F101*E")||cpuis("STM32F101*D")||cpuis("STM32F101*C")||cpu()=="STM32F101")
|
|
bitfld.long 0x1c 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F101T8"||cpuis("STM32F101TB")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x1c 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1c 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F"))
|
|
bitfld.long 0x1c 8. " TIM14 ,Timer 14 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 7. " TIM13 ,Timer 13 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 6. " TIM12 ,Timer 12 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpu()=="STM32F101")
|
|
bitfld.long 0x1c 5. " TIM7EN ,Timer 7 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " TIM5EN ,Timer 5 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x1C 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x1C 2. " TIM4EN ,Timer 4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x20 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x20 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x20 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x20 2. " LSEBYP ,External Low Speed oscillator Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x20 1. " LSERDY ,External Low Speed oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x20 0. " LSEON ,External Low Speed oscillator enable" "Off,On"
|
|
line.long 0x24 "RCC_CSR,Control/status register"
|
|
bitfld.long 0x24 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 24. " RMVF ,Remove reset flag" "Not activated,Reset"
|
|
bitfld.long 0x24 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x24 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
width 0xB
|
|
elif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
width 14.
|
|
group.long 0x00++0x2f
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
bitfld.long 0x00 29. " PLL3RDY ,PLL3 clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 28. " PLL3ON ,PLL3 enable" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLL2RDY ,PLL2 clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 26. " PLL2ON ,PLL2 enable" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PLL1RDY ,PLL1 clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLL1ON ,PLL1 enable" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HSERDY ,External High Speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,External High Speed clock enable" "Off,On"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,Internal High Speed clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,Internal High Speed clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSIRDY ,Internal High Speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,Internal High Speed clock enable" "Off,On"
|
|
line.long 0x04 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x04 24.--27. " MCO ,Microcontroller Clock Output" "No clock,No clock,No clock,No clock,System,Internal,External,PLL1/2,PLL2,PLL3/2,XT1,PLL3,No clock,No clock,No clock,No clock"
|
|
bitfld.long 0x04 22. " OTGFSPRE ,USB prescaler" "PLL/1.5,PLL"
|
|
textline " "
|
|
bitfld.long 0x04 18.--21. " PLL1MUL ,PLL Multiplication Factor" "Reserved,Reserved,4,5,6,7,8,9,Reserved,Reserved,Reserved,Reserved,Reserved,6.5,?..."
|
|
bitfld.long 0x04 17. " PLL1XTPRE ,LSB of division factor PREDIV1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PLLSRC ,PLL entry clock source" "HSI/2,PREDIV1"
|
|
bitfld.long 0x04 14.--15. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4,PLCK2/6,PLCK2/8"
|
|
textline " "
|
|
bitfld.long 0x04 11.--13. " PPRE2 ,APB High speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
bitfld.long 0x04 8.--10. " PPRE1 ,APB Low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
bitfld.long 0x04 2.--3. " SWS ,System Clock Switch Status" "HSI,HSE,PLL,Not applicable"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SW ,System clock Switch" "HSI,HSE,PLL,Not allowed"
|
|
line.long 0x08 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x08 23. " CSSC ,Clock Security System Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 22. " PL3RDYC ,PLL3 Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " PL2RDYC ,PLL2 Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " PLL1RDYC ,PLL1 Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HSERDYC ,HSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " HSIRDYC ,HSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " LSERDYC ,LSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " LSIRDYC ,LSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 14. " PLL3RDYIE ,PLL3 Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " PLL2RDYIE ,PLL2 Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PLL1RDYIE ,PLL1 Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSSF ,Clock Security System Interrupt flag" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PLL3RDYF ,PLL3 Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 5. " PLL2RDYF ,PLL2 Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PLL1RDYF ,PLL1 Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 3. " HSERDYF ,HSE Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 2. " HSIRDYF ,HSI Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 1. " LSERDYF ,LSE Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 0. " LSIRDYF ,LSI Ready Interrupt flag" "Not ready,Ready"
|
|
line.long 0x0C "RCC_APB2RSTR,APB2 Peripheral reset register"
|
|
bitfld.long 0x0C 14. " USART1RST ,USART1 reset" "No effect,Reset"
|
|
bitfld.long 0x0C 12. " SPI1RST ,SPI 1 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " TIM1RST ,TIM1 Timer reset" "No effect,Reset"
|
|
bitfld.long 0x0C 10. " ADC2RST ,ADC 2 interface reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " ADC1RST ,ADC 1 interface reset" "No effect,Reset"
|
|
sif (cpuis("STM32F105V*")||cpuis("STM32F107V*"))
|
|
bitfld.long 0x0c 6. " IOPERST ,IO port E reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " IOPDRST ,IO port D reset" "No effect,Reset"
|
|
bitfld.long 0x0C 4. " IOPCRST ,IO port C reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " IOPBRST ,IO port B reset" "No effect,Reset"
|
|
bitfld.long 0x0C 2. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " AFIORST ,Alternate Function I/O reset" "No effect,Reset"
|
|
line.long 0x10 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
bitfld.long 0x10 29. " DACRST ,DAC interface reset" "No effect,Reset"
|
|
bitfld.long 0x10 28. " PWRRST ,Power interface reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 27. " BKPRST ,Backup interface reset" "No effect,Reset"
|
|
bitfld.long 0x10 26. " CAN2RST ,CAN2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 25. " CAN1RST ,CAN1 reset" "No effect,Reset"
|
|
bitfld.long 0x10 22. " I2C2RST ,I2C 2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
bitfld.long 0x10 20. " UART5RST ,UART 5 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 19. " UART4RST ,UART 4 reset" "No effect,Reset"
|
|
bitfld.long 0x10 18. " USART3RST ,USART 3 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 15. " SPI3RST ,SPI 3 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 5. " TIM7RST ,Timer 7 reset" "No effect,Reset"
|
|
bitfld.long 0x10 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TIM5RST ,Timer 5 reset" "No effect,Reset"
|
|
bitfld.long 0x10 2. " TIM4RST ,Timer 4 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
line.long 0x14 "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
sif (cpuis("STM32F107*"))
|
|
bitfld.long 0x14 16. " ETHMACRXEN ,Ethernet MAC RX clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " ETHMACTXEN ,Ethernet MAC TX clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 14. " ETHMACEN ,Ethernet MAC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " OTGFSEN ,USB OTG FS clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 12. " OTGFSEN ,USB OTG FS clock enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " DMA2EN ,DMA2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " DMA1EN ,DMA1 clock enable" "Disabled,Enabled"
|
|
line.long 0x18 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
bitfld.long 0x18 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " SPI1EN ,SPI 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " TIM1EN ,TIM1 Timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " ADC2EN ,ADC 2 interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F105R*")||cpuis("STM32F107R*"))
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 5. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " AFIOEN ,Alternate Function I/O clock enable" "Disabled,Enabled"
|
|
line.long 0x1C "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
bitfld.long 0x1c 29. " DACEN ,DAC interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " BKPEN ,Backup interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 26. " CAN2EN ,CAN2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " CAN1EN ,CAN1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 20. " UART5EN ,USART 5 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 19. " UART4EN ,USART 4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 18. " USART3EN ,USART 3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 5. " TIM7EN ,Timer 7 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " TIM5EN ,Timer 5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " TIM4EN ,Timer 4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
line.long 0x20 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x20 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x20 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x20 2. " LSEBYP ,External Low Speed oscillator Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x20 1. " LSERDY ,External Low Speed oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x20 0. " LSEON ,External Low Speed oscillator enable" "Off,On"
|
|
line.long 0x24 "RCC_CSR,Control/status register"
|
|
bitfld.long 0x24 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 24. " RMVF ,Remove reset flag" "Not activated,Reset"
|
|
bitfld.long 0x24 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x24 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
line.long 0x28 "RCC_AHBRSTR,AHB Peripheral Clock reset register"
|
|
sif (cpuis("STM32F107*"))
|
|
bitfld.long 0x28 14. " ETHMACRST ,Ethernet MAC reset" "No reset,Reset"
|
|
bitfld.long 0x28 12. " OTGFSRST ,USB OTG FS reset" "No reset,Reset"
|
|
else
|
|
bitfld.long 0x28 12. " OTGFSRST ,USB OTG FS reset" "No reset,Reset"
|
|
endif
|
|
line.long 0x2c "RCC_CFGR2,Clock configuration register2"
|
|
bitfld.long 0x2C 18. " I2S3SRC ,I2S3 clock source" "System,PLL3 VCO"
|
|
bitfld.long 0x2C 17. " I2S2SRC ,I2S2 clock source" "System,PLL3 VCO"
|
|
textline " "
|
|
bitfld.long 0x2C 16. " PREDIV1SRC ,PREDIV1 entry clock source" "HSE,PLL2"
|
|
bitfld.long 0x2C 12.--15. " PLL3MUL ,PLL3 Multiplication Factor" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8,9,10,11,12,13,14,Reserved,16,20"
|
|
textline " "
|
|
bitfld.long 0x2C 8.--11. " PLL2MUL ,PLL2 Multiplication Factor" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8,9,10,11,12,13,14,Reserved,16,20"
|
|
bitfld.long 0x2C 4.--7. " PREDIV2 ,PREDIV2 division factor" "Not divided,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--3. " PREDIV1 ,PREDIV1 division factor" "Not divided,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
width 0xB
|
|
else
|
|
width 14.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
bitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HSERDY ,External High Speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,External High Speed clock enable" "Off,On"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,Internal High Speed clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,Internal High Speed clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSIRDY ,Internal High Speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,Internal High Speed clock enable" "Off,On"
|
|
line.long 0x04 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x04 24.--26. " MCO ,Microcontroller Clock Output" "No clock,No clock,No clock,No clock,System,Internal,External,PLL/2"
|
|
bitfld.long 0x04 22. " USBPRE ,USB prescaler" "PLL/1.5,PLL"
|
|
textline " "
|
|
bitfld.long 0x04 18.--21. " PLLMUL ,PLL Multiplication Factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
bitfld.long 0x04 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PLLSRC ,PLL entry clock source" "HSI/2,HSE"
|
|
bitfld.long 0x04 14.--15. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4,PLCK2/6,PLCK2/8"
|
|
textline " "
|
|
bitfld.long 0x04 11.--13. " PPRE2 ,APB High speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
bitfld.long 0x04 8.--10. " PPRE1 ,APB Low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
bitfld.long 0x04 2.--3. " SWS ,System Clock Switch Status" "HSI,HSE,PLL,Not applicable"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SW ,System clock Switch" "HSI,HSE,PLL,Not allowed"
|
|
line.long 0x08 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x08 23. " CSSC ,Clock Security System Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " PLLRDYC ,PLL Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HSERDYC ,HSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " HSIRDYC ,HSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " LSERDYC ,LSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " LSIRDYC ,LSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSSF ,Clock Security System Interrupt flag" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PLLRDYF ,PLL Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 3. " HSERDYF ,HSE Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 2. " HSIRDYF ,HSI Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 1. " LSERDYF ,LSE Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 0. " LSIRDYF ,LSI Ready Interrupt flag" "Not ready,Ready"
|
|
line.long 0x0C "RCC_APB2RSTR,APB2 Peripheral reset register"
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F"))
|
|
bitfld.long 0x0C 21. " TIM11RST ,TIM11 timer clock reset" "No effect,Reset"
|
|
bitfld.long 0x0C 20. " TIM10RST ,TIM10 timer clock reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " TIM9RST ,TIM9 timer clock reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x0C 15. " ADC3RST ,ADC3 interface reset" "No effect,Reset"
|
|
bitfld.long 0x0C 14. " USART1RST ,USART1 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " TIM8RST ,TIM8 timer reset" "No effect,Reset"
|
|
bitfld.long 0x0C 12. " SPI1RST ,SPI 1 reset" "No effect,Reset"
|
|
else
|
|
bitfld.long 0x0C 14. " USART1RST ,USART1 reset" "No effect,Reset"
|
|
bitfld.long 0x0C 12. " SPI1RST ,SPI 1 reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 11. " TIM1RST ,TIM1 Timer reset" "No effect,Reset"
|
|
bitfld.long 0x0C 10. " ADC2RST ,ADC 2 interface reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x0C 9. " ADC1RST ,ADC 1 interface reset" "No effect,Reset"
|
|
bitfld.long 0x0c 8. " IOPGRST ,IO port G reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " IOPFRST ,IO port F reset" "No effect,Reset"
|
|
bitfld.long 0x0c 6. " IOPERST ,IO port E reset" "No effect,Reset"
|
|
elif (cpuis("STM32F103V*"))
|
|
bitfld.long 0x0C 9. " ADC1RST ,ADC 1 interface reset" "No effect,Reset"
|
|
bitfld.long 0x0c 6. " IOPERST ,IO port E reset" "No effect,Reset"
|
|
else
|
|
bitfld.long 0x0C 9. " ADC1RST ,ADC 1 interface reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " IOPDRST ,IO port D reset" "No effect,Reset"
|
|
sif (cpu()!="STM32F103T8"&&cpu()!="STM32F103T6"&&cpu()!="STM32F103T4"&&(!cpuis("STM32F103TB")))
|
|
textline " "
|
|
bitfld.long 0x0C 4. " IOPCRST ,IO port C reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 3. " IOPBRST ,IO port B reset" "No effect,Reset"
|
|
bitfld.long 0x0C 2. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " AFIORST ,Alternate Function I/O reset" "No effect,Reset"
|
|
line.long 0x10 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x10 29. " DACRST ,DAC interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 28. " PWRRST ,Power interface reset" "No effect,Reset"
|
|
bitfld.long 0x10 27. " BKPRST ,Backup interface reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 25. " CANRST ,CAN reset" "No effect,Reset"
|
|
bitfld.long 0x10 23. " USBRST ,USB reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()=="STM32F103T8"||cpuis("STM32F103*4")||cpuis("STM32F103*6")||cpuis("STM32F103TB"))
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 22. " I2C2RST ,I2C 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x10 20. " UART5RST ,USART 5 reset" "No effect,Reset"
|
|
bitfld.long 0x10 19. " UART4RST ,USART 4 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 18. " USART3RST ,USART 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
elif (cpu()=="STM32F103T8"||cpuis("STM32F103*4")||cpuis("STM32F103*6")||cpuis("STM32F103TB"))
|
|
bitfld.long 0x10 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 18. " USART3RST ,USART 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x10 15. " SPI3RST ,SPI 3 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
elif (cpu()=="STM32F103T8"||cpuis("STM32F103*4")||cpuis("STM32F103*6")||cpuis("STM32F103TB"))
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F"))
|
|
bitfld.long 0x10 8. " TIM14RST ,Timer 14 reset" "No effect,Reset"
|
|
bitfld.long 0x10 7. " TIM13RST ,Timer 13 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 6. " TIM12RST ,Timer 12 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x10 5. " TIM7RST ,Timer 7 reset" "No effect,Reset"
|
|
bitfld.long 0x10 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TIM5RST ,Timer 5 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F103C4"||cpu()=="STM32F103R4"||cpu()=="STM32F103T4"||cpu()=="STM32F103C6"||cpu()=="STM32F103R6"||cpu()=="STM32F103T6")
|
|
bitfld.long 0x10 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
else
|
|
bitfld.long 0x10 2. " TIM4RST ,Timer 4 reset" "No effect,Reset"
|
|
bitfld.long 0x10 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
endif
|
|
line.long 0x14 "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
sif ((!(cpuis("STM32F103R*"))))
|
|
bitfld.long 0x14 10. " SDIOEN ,SDIO clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " FSMCEN ,FSMC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x14 10. " SDIOEN ,SDIO clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x14 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x14 1. " DMA2EN ,DMA2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " DMA1EN ,DMA1 clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 0. " DMAEN ,DMA clock enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x18 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F"))
|
|
bitfld.long 0x18 21. " TIM11EN ,TIM11 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " TIM10EN ,TIM10 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 19. " TIM9EN ,TIM9 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x18 15. " ADC3EN ,ADC 3 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " TIM8EN ,TIM8 Timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " SPI1EN ,SPI 1 clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x18 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " SPI1EN ,SPI 1 clock enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 11. " TIM1EN ,TIM1 Timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " ADC2EN ,ADC 2 interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " IOPGEN ,I/O port G clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " IOPFEN ,I/O port F clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
elif (cpuis("STM32F103V*"))
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC 1 interface clock enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 5. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
sif (cpu()!="STM32F103T8"&&cpu()!="STM32F103T6"&&cpu()!="STM32F103T4"&&(!cpuis("STM32F103TB")))
|
|
textline " "
|
|
bitfld.long 0x18 4. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 3. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " AFIOEN ,Alternate Function I/O clock enable" "Disabled,Enabled"
|
|
line.long 0x1C "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x1c 29. " DACEN ,DAC interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 27. " BKPEN ,Backup interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " CANEN ,CAN clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 23. " USBEN ,USB clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="STM32F103T8"||cpuis("STM32F103*4")||cpuis("STM32F103*6")||cpuis("STM32F103TB"))
|
|
bitfld.long 0x1C 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x1c 20. " UART5EN ,USART 5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 19. " UART4EN ,USART 4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 18. " USART3EN ,USART 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpu()=="STM32F103T8"||cpuis("STM32F103*4")||cpuis("STM32F103*6")||cpuis("STM32F103TB"))
|
|
bitfld.long 0x1C 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 18. " USART3EN ,USART 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x1c 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F103T8"||cpuis("STM32F103*4")||cpuis("STM32F103*6")||cpuis("STM32F103TB"))
|
|
bitfld.long 0x1C 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F"))
|
|
bitfld.long 0x1C 8. " TIM14EN ,TIM14 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 7. " TIM13EN ,TIM13 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " TIM12EN ,TIM12 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x1c 5. " TIM7EN ,Timer 7 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1c 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " TIM5EN ,Timer 5 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.long 0x1C 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x1C 2. " TIM4EN ,Timer 4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x20 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x20 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x20 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x20 2. " LSEBYP ,External Low Speed oscillator Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x20 1. " LSERDY ,External Low Speed oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x20 0. " LSEON ,External Low Speed oscillator enable" "Off,On"
|
|
line.long 0x24 "RCC_CSR,Control/status register"
|
|
bitfld.long 0x24 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 24. " RMVF ,Remove reset flag" "Not activated,Reset"
|
|
bitfld.long 0x24 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x24 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree.open "GPIO/AFIO (General Purpose and Alternate Function I/O)"
|
|
tree "GPIO"
|
|
tree "GPIO A"
|
|
width 12.
|
|
base ad:0x40010800
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPIOA_CRL,Port configuration register low"
|
|
bitfld.long 0x00 30.--31. " CNF7 ,Port 7 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE7 ,Port 7 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF6 ,Port 6 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE6 ,Port 6 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF5 ,Port 5 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE5 ,Port 5 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF4 ,Port 4 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE4 ,Port 4 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF3 ,Port 3 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE3 ,Port 3 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF2 ,Port 2 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Port 2 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF1 ,Port 1 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE1 ,Port 1 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF0 ,Port 0 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE0 ,Port 0 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "GPIOA_CRH,Port configuration register high"
|
|
bitfld.long 0x00 30.--31. " CNF15 ,Port 15 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE15 ,Port 15 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF14 ,Port 14 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE14 ,Port 14 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF13 ,Port 13 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE13 ,Port 13 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF12 ,Port 12 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE12 ,Port 12 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF11 ,Port 11 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE11 ,Port 11 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF10 ,Port 10 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE10 ,Port 10 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF9 ,Port 9 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE9 ,Port 9 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF8 ,Port 8 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE8 ,Port 8 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOA_IDR,Port input data register"
|
|
bitfld.long 0x00 15. " IDR15 , Port input data" "0,1"
|
|
bitfld.long 0x00 14. " IDR14 , Port input data" "0,1"
|
|
bitfld.long 0x00 13. " IDR13 , Port input data" "0,1"
|
|
bitfld.long 0x00 12. " IDR12 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 , Port input data" "0,1"
|
|
bitfld.long 0x00 10. " IDR10 , Port input data" "0,1"
|
|
bitfld.long 0x00 9. " IDR9 , Port input data" "0,1"
|
|
bitfld.long 0x00 8. " IDR8 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 , Port input data" "0,1"
|
|
bitfld.long 0x00 6. " IDR6 , Port input data" "0,1"
|
|
bitfld.long 0x00 5. " IDR5 , Port input data" "0,1"
|
|
bitfld.long 0x00 4. " IDR4 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 , Port input data" "0,1"
|
|
bitfld.long 0x00 2. " IDR2 , Port input data" "0,1"
|
|
bitfld.long 0x00 1. " IDR1 , Port input data" "0,1"
|
|
bitfld.long 0x00 0. " IDR0 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOA_ODR,Port output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BR13 ,Reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Reset bit 0" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOA_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Lock bit 15" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LCK14 ,Lock bit 14" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Lock bit 13" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Lock bit 9" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Lock bit 8" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Lock bit 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Lock bit 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Lock bit 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Lock bit 0" "Not locked,Locked"
|
|
width 0xB
|
|
tree.end
|
|
tree "GPIO B"
|
|
sif (cpuis("STM32F103T*")||cpuis("STM32F101T*"))
|
|
width 12.
|
|
base ad:0x40010C00
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPIOB_CRL,Port configuration register low"
|
|
bitfld.long 0x00 30.--31. " CNF7 ,Port 7 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE7 ,Port 7 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF6 ,Port 6 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE6 ,Port 6 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF5 ,Port 5 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE5 ,Port 5 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF4 ,Port 4 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE4 ,Port 4 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF3 ,Port 3 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE3 ,Port 3 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF2 ,Port 2 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Port 2 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF1 ,Port 1 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE1 ,Port 1 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF0 ,Port 0 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE0 ,Port 0 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x00 "GPIOB_CRH,Port configuration register high"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOB_IDR,Port input data register"
|
|
bitfld.long 0x00 7. " IDR7 , Port input data" "0,1"
|
|
bitfld.long 0x00 6. " IDR6 , Port input data" "0,1"
|
|
bitfld.long 0x00 5. " IDR5 , Port input data" "0,1"
|
|
bitfld.long 0x00 4. " IDR4 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 , Port input data" "0,1"
|
|
bitfld.long 0x00 2. " IDR2 , Port input data" "0,1"
|
|
bitfld.long 0x00 1. " IDR1 , Port input data" "0,1"
|
|
bitfld.long 0x00 0. " IDR0 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOB_ODR,Port output data register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_BRR,Port bit reset register"
|
|
bitfld.long 0x00 7. " BR7 ,Reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Reset bit 0" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOB_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 7. " LCK7 ,Lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Lock bit 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Lock bit 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Lock bit 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Lock bit 0" "Not locked,Locked"
|
|
width 0xB
|
|
else
|
|
width 12.
|
|
base ad:0x40010C00
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPIOB_CRL,Port configuration register low"
|
|
bitfld.long 0x00 30.--31. " CNF7 ,Port 7 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE7 ,Port 7 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF6 ,Port 6 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE6 ,Port 6 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF5 ,Port 5 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE5 ,Port 5 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF4 ,Port 4 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE4 ,Port 4 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF3 ,Port 3 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE3 ,Port 3 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF2 ,Port 2 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Port 2 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF1 ,Port 1 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE1 ,Port 1 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF0 ,Port 0 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE0 ,Port 0 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "GPIOB_CRH,Port configuration register high"
|
|
bitfld.long 0x00 30.--31. " CNF15 ,Port 15 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE15 ,Port 15 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF14 ,Port 14 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE14 ,Port 14 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF13 ,Port 13 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE13 ,Port 13 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF12 ,Port 12 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE12 ,Port 12 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF11 ,Port 11 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE11 ,Port 11 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF10 ,Port 10 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE10 ,Port 10 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF9 ,Port 9 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE9 ,Port 9 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF8 ,Port 8 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE8 ,Port 8 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOB_IDR,Port input data register"
|
|
bitfld.long 0x00 15. " IDR15 , Port input data" "0,1"
|
|
bitfld.long 0x00 14. " IDR14 , Port input data" "0,1"
|
|
bitfld.long 0x00 13. " IDR13 , Port input data" "0,1"
|
|
bitfld.long 0x00 12. " IDR12 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 , Port input data" "0,1"
|
|
bitfld.long 0x00 10. " IDR10 , Port input data" "0,1"
|
|
bitfld.long 0x00 9. " IDR9 , Port input data" "0,1"
|
|
bitfld.long 0x00 8. " IDR8 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 , Port input data" "0,1"
|
|
bitfld.long 0x00 6. " IDR6 , Port input data" "0,1"
|
|
bitfld.long 0x00 5. " IDR5 , Port input data" "0,1"
|
|
bitfld.long 0x00 4. " IDR4 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 , Port input data" "0,1"
|
|
bitfld.long 0x00 2. " IDR2 , Port input data" "0,1"
|
|
bitfld.long 0x00 1. " IDR1 , Port input data" "0,1"
|
|
bitfld.long 0x00 0. " IDR0 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOB_ODR,Port output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BR13 ,Reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Reset bit 0" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOB_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Lock bit 15" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LCK14 ,Lock bit 14" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Lock bit 13" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Lock bit 9" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Lock bit 8" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Lock bit 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Lock bit 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Lock bit 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Lock bit 0" "Not locked,Locked"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="STM32F103T8"&&cpu()!="STM32F103T6"&&cpu()!="STM32F103T4"&&cpu()!="STM32F103TB"&&cpu()!="STM32F101T8"&&cpu()!="STM32F101T6"&&cpu()!="STM32F101T4"&&cpu()!="STM32F101TB")
|
|
tree "GPIO C"
|
|
sif (cpuis("STM32F103C*")||cpuis("STM32F102C*")||cpuis("STM32F101C*")||(cpuis("STM32F100*")))
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
width 12.
|
|
base ad:0x40011000
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPIOC_CRL,Port configuration register low"
|
|
bitfld.long 0x00 30.--31. " CNF7 ,Port 7 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE7 ,Port 7 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF6 ,Port 6 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE6 ,Port 6 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF5 ,Port 5 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE5 ,Port 5 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF4 ,Port 4 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE4 ,Port 4 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF3 ,Port 3 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE3 ,Port 3 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF2 ,Port 2 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Port 2 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF1 ,Port 1 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE1 ,Port 1 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF0 ,Port 0 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE0 ,Port 0 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "GPIOC_CRH,Port configuration register high"
|
|
bitfld.long 0x00 30.--31. " CNF15 ,Port 15 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE15 ,Port 15 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF14 ,Port 14 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE14 ,Port 14 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF13 ,Port 13 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE13 ,Port 13 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF12 ,Port 12 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE12 ,Port 12 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF11 ,Port 11 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE11 ,Port 11 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF10 ,Port 10 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE10 ,Port 10 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF9 ,Port 9 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE9 ,Port 9 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF8 ,Port 8 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE8 ,Port 8 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOC_IDR,Port input data register"
|
|
bitfld.long 0x00 15. " IDR15 , Port input data" "0,1"
|
|
bitfld.long 0x00 14. " IDR14 , Port input data" "0,1"
|
|
bitfld.long 0x00 13. " IDR13 , Port input data" "0,1"
|
|
bitfld.long 0x00 12. " IDR12 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 , Port input data" "0,1"
|
|
bitfld.long 0x00 10. " IDR10 , Port input data" "0,1"
|
|
bitfld.long 0x00 9. " IDR9 , Port input data" "0,1"
|
|
bitfld.long 0x00 8. " IDR8 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 , Port input data" "0,1"
|
|
bitfld.long 0x00 6. " IDR6 , Port input data" "0,1"
|
|
bitfld.long 0x00 5. " IDR5 , Port input data" "0,1"
|
|
bitfld.long 0x00 4. " IDR4 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 , Port input data" "0,1"
|
|
bitfld.long 0x00 2. " IDR2 , Port input data" "0,1"
|
|
bitfld.long 0x00 1. " IDR1 , Port input data" "0,1"
|
|
bitfld.long 0x00 0. " IDR0 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOC_ODR,Port output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BR13 ,Reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Reset bit 0" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOC_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Lock bit 15" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LCK14 ,Lock bit 14" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Lock bit 13" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Lock bit 9" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Lock bit 8" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Lock bit 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Lock bit 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Lock bit 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Lock bit 0" "Not locked,Locked"
|
|
width 0xB
|
|
else
|
|
width 12.
|
|
base ad:0x40011000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "GPIOC_CRL,Port configuration register low"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "GPIOC_CRH,Port configuration register high"
|
|
bitfld.long 0x00 30.--31. " CNF15 ,Port 15 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE15 ,Port 15 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF14 ,Port 14 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE14 ,Port 14 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF13 ,Port 13 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE13 ,Port 13 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOC_IDR,Port input data register"
|
|
bitfld.long 0x00 15. " IDR15 , Port input data" "0,1"
|
|
bitfld.long 0x00 14. " IDR14 , Port input data" "0,1"
|
|
bitfld.long 0x00 13. " IDR13 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOC_ODR,Port output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BR13 ,Reset bit 13" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOC_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Lock bit 15" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LCK14 ,Lock bit 14" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Lock bit 13" "Not locked,Locked"
|
|
width 0xB
|
|
endif
|
|
else
|
|
width 12.
|
|
base ad:0x40011000
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPIOC_CRL,Port configuration register low"
|
|
bitfld.long 0x00 30.--31. " CNF7 ,Port 7 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE7 ,Port 7 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF6 ,Port 6 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE6 ,Port 6 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF5 ,Port 5 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE5 ,Port 5 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF4 ,Port 4 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE4 ,Port 4 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF3 ,Port 3 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE3 ,Port 3 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF2 ,Port 2 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Port 2 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF1 ,Port 1 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE1 ,Port 1 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF0 ,Port 0 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE0 ,Port 0 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "GPIOC_CRH,Port configuration register high"
|
|
bitfld.long 0x00 30.--31. " CNF15 ,Port 15 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE15 ,Port 15 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF14 ,Port 14 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE14 ,Port 14 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF13 ,Port 13 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE13 ,Port 13 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF12 ,Port 12 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE12 ,Port 12 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF11 ,Port 11 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE11 ,Port 11 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF10 ,Port 10 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE10 ,Port 10 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF9 ,Port 9 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE9 ,Port 9 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF8 ,Port 8 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE8 ,Port 8 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOC_IDR,Port input data register"
|
|
bitfld.long 0x00 15. " IDR15 , Port input data" "0,1"
|
|
bitfld.long 0x00 14. " IDR14 , Port input data" "0,1"
|
|
bitfld.long 0x00 13. " IDR13 , Port input data" "0,1"
|
|
bitfld.long 0x00 12. " IDR12 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 , Port input data" "0,1"
|
|
bitfld.long 0x00 10. " IDR10 , Port input data" "0,1"
|
|
bitfld.long 0x00 9. " IDR9 , Port input data" "0,1"
|
|
bitfld.long 0x00 8. " IDR8 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 , Port input data" "0,1"
|
|
bitfld.long 0x00 6. " IDR6 , Port input data" "0,1"
|
|
bitfld.long 0x00 5. " IDR5 , Port input data" "0,1"
|
|
bitfld.long 0x00 4. " IDR4 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 , Port input data" "0,1"
|
|
bitfld.long 0x00 2. " IDR2 , Port input data" "0,1"
|
|
bitfld.long 0x00 1. " IDR1 , Port input data" "0,1"
|
|
bitfld.long 0x00 0. " IDR0 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOC_ODR,Port output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BR13 ,Reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Reset bit 0" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOC_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Lock bit 15" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LCK14 ,Lock bit 14" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Lock bit 13" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Lock bit 9" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Lock bit 8" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Lock bit 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Lock bit 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Lock bit 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Lock bit 0" "Not locked,Locked"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "GPIO D"
|
|
sif (cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101R*")||cpuis("STM32F100R*")||cpuis("STM32F105R*")||cpuis("STM32F107R*"))
|
|
width 12.
|
|
base ad:0x40011400
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPIOD_CRL,Port configuration register low"
|
|
bitfld.long 0x00 10.--11. " CNF2 ,Port 2 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Port 2 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF1 ,Port 1 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE1 ,Port 1 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF0 ,Port 0 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE0 ,Port 0 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
width 12.
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x00 "GPIOD_CRH,Port configuration register high"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOD_IDR,Port input data register"
|
|
bitfld.long 0x00 2. " IDR2 , Port input data" "0,1"
|
|
bitfld.long 0x00 1. " IDR1 , Port input data" "0,1"
|
|
bitfld.long 0x00 0. " IDR0 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOD_ODR,Port output data register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_BRR,Port bit reset register"
|
|
bitfld.long 0x00 2. " BR2 ,Reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Reset bit 0" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOD_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 2. " LCK2 ,Lock bit 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Lock bit 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Lock bit 0" "Not locked,Locked"
|
|
width 0xB
|
|
elif (cpuis("STM32F103C*")||cpuis("STM32F103T*")||cpuis("STM32F102C*")||cpuis("STM32F101C*")||cpuis("STM32F100*")||cpuis("STM32F101T*"))
|
|
width 12.
|
|
base ad:0x40011400
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPIOD_CRL,Port configuration register low"
|
|
bitfld.long 0x00 6.--7. " CNF1 ,Port 1 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE1 ,Port 1 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF0 ,Port 0 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE0 ,Port 0 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x00 "GPIOD_CRH,Port configuration register high"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOD_IDR,Port input data register"
|
|
bitfld.long 0x00 1. " IDR1 , Port input data" "0,1"
|
|
bitfld.long 0x00 0. " IDR0 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOD_ODR,Port output data register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_BRR,Port bit reset register"
|
|
bitfld.long 0x00 1. " BR1 ,Reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Reset bit 0" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOD_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 1. " LCK1 ,Lock bit 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Lock bit 0" "Not locked,Locked"
|
|
width 0xB
|
|
else
|
|
width 12.
|
|
base ad:0x40011400
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPIOD_CRL,Port configuration register low"
|
|
bitfld.long 0x00 30.--31. " CNF7 ,Port 7 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE7 ,Port 7 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF6 ,Port 6 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE6 ,Port 6 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF5 ,Port 5 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE5 ,Port 5 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF4 ,Port 4 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE4 ,Port 4 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF3 ,Port 3 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE3 ,Port 3 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF2 ,Port 2 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Port 2 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF1 ,Port 1 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE1 ,Port 1 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF0 ,Port 0 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE0 ,Port 0 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "GPIOD_CRH,Port configuration register high"
|
|
bitfld.long 0x00 30.--31. " CNF15 ,Port 15 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE15 ,Port 15 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF14 ,Port 14 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE14 ,Port 14 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF13 ,Port 13 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE13 ,Port 13 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF12 ,Port 12 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE12 ,Port 12 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF11 ,Port 11 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE11 ,Port 11 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF10 ,Port 10 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE10 ,Port 10 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF9 ,Port 9 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE9 ,Port 9 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF8 ,Port 8 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE8 ,Port 8 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOD_IDR,Port input data register"
|
|
bitfld.long 0x00 15. " IDR15 , Port input data" "0,1"
|
|
bitfld.long 0x00 14. " IDR14 , Port input data" "0,1"
|
|
bitfld.long 0x00 13. " IDR13 , Port input data" "0,1"
|
|
bitfld.long 0x00 12. " IDR12 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 , Port input data" "0,1"
|
|
bitfld.long 0x00 10. " IDR10 , Port input data" "0,1"
|
|
bitfld.long 0x00 9. " IDR9 , Port input data" "0,1"
|
|
bitfld.long 0x00 8. " IDR8 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 , Port input data" "0,1"
|
|
bitfld.long 0x00 6. " IDR6 , Port input data" "0,1"
|
|
bitfld.long 0x00 5. " IDR5 , Port input data" "0,1"
|
|
bitfld.long 0x00 4. " IDR4 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 , Port input data" "0,1"
|
|
bitfld.long 0x00 2. " IDR2 , Port input data" "0,1"
|
|
bitfld.long 0x00 1. " IDR1 , Port input data" "0,1"
|
|
bitfld.long 0x00 0. " IDR0 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOD_ODR,Port output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BR13 ,Reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Reset bit 0" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOD_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Lock bit 15" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LCK14 ,Lock bit 14" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Lock bit 13" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Lock bit 9" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Lock bit 8" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Lock bit 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Lock bit 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Lock bit 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Lock bit 0" "Not locked,Locked"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32F103Z*")||cpuis("STM32F103V*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F100V*")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F105V*")||cpuis("STM32F107V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
tree "GPIO E"
|
|
width 12.
|
|
base ad:0x40011800
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPIOE_CRL,Port configuration register low"
|
|
bitfld.long 0x00 30.--31. " CNF7 ,Port 7 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE7 ,Port 7 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF6 ,Port 6 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE6 ,Port 6 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF5 ,Port 5 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE5 ,Port 5 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF4 ,Port 4 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE4 ,Port 4 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF3 ,Port 3 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE3 ,Port 3 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF2 ,Port 2 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Port 2 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF1 ,Port 1 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE1 ,Port 1 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF0 ,Port 0 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE0 ,Port 0 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "GPIOE_CRH,Port configuration register high"
|
|
bitfld.long 0x00 30.--31. " CNF15 ,Port 15 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE15 ,Port 15 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF14 ,Port 14 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE14 ,Port 14 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF13 ,Port 13 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE13 ,Port 13 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF12 ,Port 12 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE12 ,Port 12 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF11 ,Port 11 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE11 ,Port 11 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF10 ,Port 10 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE10 ,Port 10 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF9 ,Port 9 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE9 ,Port 9 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF8 ,Port 8 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE8 ,Port 8 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOE_IDR,Port input data register"
|
|
bitfld.long 0x00 15. " IDR15 , Port input data" "0,1"
|
|
bitfld.long 0x00 14. " IDR14 , Port input data" "0,1"
|
|
bitfld.long 0x00 13. " IDR13 , Port input data" "0,1"
|
|
bitfld.long 0x00 12. " IDR12 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 , Port input data" "0,1"
|
|
bitfld.long 0x00 10. " IDR10 , Port input data" "0,1"
|
|
bitfld.long 0x00 9. " IDR9 , Port input data" "0,1"
|
|
bitfld.long 0x00 8. " IDR8 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 , Port input data" "0,1"
|
|
bitfld.long 0x00 6. " IDR6 , Port input data" "0,1"
|
|
bitfld.long 0x00 5. " IDR5 , Port input data" "0,1"
|
|
bitfld.long 0x00 4. " IDR4 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 , Port input data" "0,1"
|
|
bitfld.long 0x00 2. " IDR2 , Port input data" "0,1"
|
|
bitfld.long 0x00 1. " IDR1 , Port input data" "0,1"
|
|
bitfld.long 0x00 0. " IDR0 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOE_ODR,Port output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOE_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BR13 ,Reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Reset bit 0" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOE_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Lock bit 15" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LCK14 ,Lock bit 14" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Lock bit 13" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Lock bit 9" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Lock bit 8" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Lock bit 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Lock bit 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Lock bit 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Lock bit 0" "Not locked,Locked"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F103Z*")||cpuis("STM32F101Z*")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
tree "GPIO F"
|
|
width 12.
|
|
base ad:0x40011C00
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPIOF_CRL,Port configuration register low"
|
|
bitfld.long 0x00 30.--31. " CNF7 ,Port 7 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE7 ,Port 7 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF6 ,Port 6 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE6 ,Port 6 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF5 ,Port 5 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE5 ,Port 5 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF4 ,Port 4 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE4 ,Port 4 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF3 ,Port 3 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE3 ,Port 3 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF2 ,Port 2 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Port 2 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF1 ,Port 1 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE1 ,Port 1 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF0 ,Port 0 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE0 ,Port 0 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "GPIOF_CRH,Port configuration register high"
|
|
bitfld.long 0x00 30.--31. " CNF15 ,Port 15 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE15 ,Port 15 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF14 ,Port 14 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE14 ,Port 14 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF13 ,Port 13 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE13 ,Port 13 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF12 ,Port 12 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE12 ,Port 12 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF11 ,Port 11 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE11 ,Port 11 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF10 ,Port 10 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE10 ,Port 10 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF9 ,Port 9 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE9 ,Port 9 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF8 ,Port 8 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE8 ,Port 8 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOF_IDR,Port input data register"
|
|
bitfld.long 0x00 15. " IDR15 , Port input data" "0,1"
|
|
bitfld.long 0x00 14. " IDR14 , Port input data" "0,1"
|
|
bitfld.long 0x00 13. " IDR13 , Port input data" "0,1"
|
|
bitfld.long 0x00 12. " IDR12 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 , Port input data" "0,1"
|
|
bitfld.long 0x00 10. " IDR10 , Port input data" "0,1"
|
|
bitfld.long 0x00 9. " IDR9 , Port input data" "0,1"
|
|
bitfld.long 0x00 8. " IDR8 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 , Port input data" "0,1"
|
|
bitfld.long 0x00 6. " IDR6 , Port input data" "0,1"
|
|
bitfld.long 0x00 5. " IDR5 , Port input data" "0,1"
|
|
bitfld.long 0x00 4. " IDR4 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 , Port input data" "0,1"
|
|
bitfld.long 0x00 2. " IDR2 , Port input data" "0,1"
|
|
bitfld.long 0x00 1. " IDR1 , Port input data" "0,1"
|
|
bitfld.long 0x00 0. " IDR0 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOF_ODR,Port output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BR13 ,Reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Reset bit 0" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOF_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Lock bit 15" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LCK14 ,Lock bit 14" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Lock bit 13" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Lock bit 9" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Lock bit 8" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Lock bit 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Lock bit 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Lock bit 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Lock bit 0" "Not locked,Locked"
|
|
width 0xB
|
|
tree.end
|
|
tree "GPIO G"
|
|
width 12.
|
|
base ad:0x40012000
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "GPIOG_CRL,Port configuration register low"
|
|
bitfld.long 0x00 30.--31. " CNF7 ,Port 7 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE7 ,Port 7 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF6 ,Port 6 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE6 ,Port 6 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF5 ,Port 5 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE5 ,Port 5 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF4 ,Port 4 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE4 ,Port 4 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF3 ,Port 3 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE3 ,Port 3 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF2 ,Port 2 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Port 2 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF1 ,Port 1 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE1 ,Port 1 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF0 ,Port 0 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE0 ,Port 0 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "GPIOG_CRH,Port configuration register high"
|
|
bitfld.long 0x00 30.--31. " CNF15 ,Port 15 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " MODE15 ,Port 15 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CNF14 ,Port 14 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODE14 ,Port 14 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CNF13 ,Port 13 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE13 ,Port 13 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CNF12 ,Port 12 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MODE12 ,Port 12 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CNF11 ,Port 11 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODE11 ,Port 11 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CNF10 ,Port 10 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE10 ,Port 10 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CNF9 ,Port 9 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODE9 ,Port 9 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CNF8 ,Port 8 configuration bits input/output" "Analog/Push-pull,Floating/Open-drain,Pull-up/pull-down/Alternate push-pull,Reserved/Alternate open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE8 ,Port 8 mode bits" "Input,Output 10MHz,Output 2MHz,Output 50MHz"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "GPIOG_IDR,Port input data register"
|
|
bitfld.long 0x00 15. " IDR15 , Port input data" "0,1"
|
|
bitfld.long 0x00 14. " IDR14 , Port input data" "0,1"
|
|
bitfld.long 0x00 13. " IDR13 , Port input data" "0,1"
|
|
bitfld.long 0x00 12. " IDR12 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 , Port input data" "0,1"
|
|
bitfld.long 0x00 10. " IDR10 , Port input data" "0,1"
|
|
bitfld.long 0x00 9. " IDR9 , Port input data" "0,1"
|
|
bitfld.long 0x00 8. " IDR8 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 , Port input data" "0,1"
|
|
bitfld.long 0x00 6. " IDR6 , Port input data" "0,1"
|
|
bitfld.long 0x00 5. " IDR5 , Port input data" "0,1"
|
|
bitfld.long 0x00 4. " IDR4 , Port input data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 , Port input data" "0,1"
|
|
bitfld.long 0x00 2. " IDR2 , Port input data" "0,1"
|
|
bitfld.long 0x00 1. " IDR1 , Port input data" "0,1"
|
|
bitfld.long 0x00 0. " IDR0 , Port input data" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOG_ODR,Port output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port output data" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port output data" "0,1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port output data" "0,1"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "GPIOG_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BR13 ,Reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Reset bit 0" "No effect,Reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPIOG_LCKR,Port configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Lock bit 15" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " LCK14 ,Lock bit 14" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Lock bit 13" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Lock bit 9" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Lock bit 8" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Lock bit 3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Lock bit 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Lock bit 1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Lock bit 0" "Not locked,Locked"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "AFIO"
|
|
base ad:0x40010000
|
|
width 14.
|
|
group.long 0x00++0x1b
|
|
line.long 0x00 "AFIO_EVCR,Event control register"
|
|
bitfld.long 0x00 7. " EVOE ,Event Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F103Z*")||cpuis("STM32F103V*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F100V*")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F105V*")||cpuis("STM32F107V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x00 4.--6. " PORT ,Port selection" "PA,PB,PC,PD,PE,?..."
|
|
elif (cpuis("STM32F103R*")||cpuis("STM32F103C*")||cpuis("STM32F102C*")||cpuis("STM32F100C*")||cpuis("STM32F102R*")||cpuis("STM32F101R*")||cpuis("STM32F100R*")||cpuis("STM32F101C*")||cpuis("STM32F105R*")||cpuis("STM32F107R*"))
|
|
bitfld.long 0x00 4.--6. " PORT ,Port selection" "PA,PB,PC,PD,?..."
|
|
else
|
|
bitfld.long 0x00 4.--6. " PORT ,Port selection" "PA,PB,Reserved,PD,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PIN ,Pin selection" "P0,P1,P2,P3,P4,P5,P6,P7,P8,P9,P10,P11,P12,P13,P14,P15"
|
|
line.long 0x04 "AFIO_MAPR,AF remap and debug I/O configuration register"
|
|
sif (cpuis("STM32F107*"))
|
|
bitfld.long 0x04 30. " PTP_PPS_REMAP ,Ethernet PTP PPS remapping (PB5 Output)" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x04 29. " TIM2ITR1_IREMAP ,TIM2 internal trigger 1 remapping" "TIM2_ITR1 to Ethernet PTP,USB OTG SOF to TIM2_ITR1"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x04 28. " SPI3_REMAP ,SPI3 remapping" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24.--26. " SWJ_CFG ,Serial Wire JTAG configuration" "SWJ/Reset State,SWJ without JNTRST,SW-DP Enabled,Forbidden,SW-DP Disabled,Forbidden,Forbidden,Forbidden"
|
|
textline " "
|
|
sif (cpuis("STM32F107*"))
|
|
bitfld.long 0x04 23. " MII_RMII_SEL ,MII/RMII selection" "MII PHY,RMII PHY"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x04 22. " CAN2_REMAP ,CAN2 I/O remapping" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F107*"))
|
|
bitfld.long 0x04 21. " ETH_REMAP ,Ethernet MAC I/O remapping" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*"))
|
|
bitfld.long 0x04 20. " ADC2_ETRGREG_REMAP ,ADC 2 external trigger regular conversion remapping" "EXTI11,TIM8_TRGO"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ADC2_ETRGINJ_REMAP ,ADC 2 external trigger injected conversion remapping" "EXTI15,TIM8_Channel4"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&cpu()!="STM32F105R8"&&cpu()!="STM32F105RB"&&cpu()!="STM32F105RC"&&cpu()!="STM32F105V8"&&cpu()!="STM32F105VB"&&cpu()!="STM32F105VC"&&cpu()!="STM32F107RB"&&cpu()!="STM32F107RC"&&cpu()!="STM32F107VB"&&cpu()!="STM32F107VC")
|
|
bitfld.long 0x04 18. " ADC1_ETRGREG_REMAP ,ADC 1 external trigger regular conversion remapping" "EXTI11,TIM8_TRGO"
|
|
textline " "
|
|
bitfld.long 0x04 17. " ADC1_ETRGINJ_REMAP ,ADC 1 External trigger injected conversion remapping" "EXTI15,TIM8_Channel4"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x04 16. " TIM5CH4_IREMAP ,TIM5 channel4 internal remap" "PA3,Calibration"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 15. " PD01_REMAP ,Port D0/Port D1 mapping on OSC_IN/OSC_OUT" "No remapping,Remapped"
|
|
textline " "
|
|
sif (cpuis("STM32F103*")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x04 13.--14. " CAN1_REMAP ,CAN1 Alternate function remapping" "RX to PA11/TX to PA12,Not used,RX to PB8/TX to PB9,RX to PD0/TX to PD1"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F103C4"&&cpu()!="STM32F103R4"&&cpu()!="STM32F103T4"&&cpu()!="STM32F103C6"&&cpu()!="STM32F103R6"&&cpu()!="STM32F103T6"&&cpu()!="STM32F102C4"&&cpu()!="STM32F102R4"&&cpu()!="STM32F102C6"&&cpu()!="STM32F102R6"&&cpu()!="STM32F101C4"&&cpu()!="STM32F101R4"&&cpu()!="STM32F101T4"&&cpu()!="STM32F101C6"&&cpu()!="STM32F101R6"&&cpu()!="STM32F101T6"&&cpu()!="STM32F100C4"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100R6")
|
|
bitfld.long 0x04 12. " TIM4_REMAP ,TIM4 remapping" "No remap,Full remap"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 10.--11. " TIM3_REMAP ,TIM3 remapping" "No remap,Not used,Partial,Full"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " TIM2_REMAP ,TIM2 remapping" "No remap,Partial,Partial,Full"
|
|
textline " "
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F103*")||cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x04 6.--7. " TIM1_REMAP ,TIM1 remapping" "No remap,Partial,Not used,Full"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F103T8"&&cpu()!="STM32F103C4"&&cpu()!="STM32F103R4"&&cpu()!="STM32F103T4"&&cpu()!="STM32F103T8"&&cpu()!="STM32F103C6"&&cpu()!="STM32F103R6"&&cpu()!="STM32F103T6"&&cpu()!="STM32F102C4"&&cpu()!="STM32F102R4"&&cpu()!="STM32F102C6"&&cpu()!="STM32F102R6"&&cpu()!="STM32F101T8"&&cpu()!="STM32F101C4"&&cpu()!="STM32F101R4"&&cpu()!="STM32F101T4"&&cpu()!="STM32F101T8"&&cpu()!="STM32F101C6"&&cpu()!="STM32F101R6"&&cpu()!="STM32F101T6"&&cpu()!="STM32F100C4"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100R6")
|
|
bitfld.long 0x04 4.--5. " USART3_REMAP ,USART3 remapping" "No remap,Partial,Not used,Full"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 3. " USART2_REMAP ,USART2 remapping" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x04 2. " USART1_REMAP ,USART1 remapping" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x04 1. " I2C1_REMAP ,I2C1 remapping" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SPI1_REMAP ,SPI1 remapping" "No remap,Remap"
|
|
width 14.
|
|
line.long 0x08 "AFIO_EXTICR1,External interrupt configuration register 1"
|
|
sif (cpuis("STM32F103Z*")||cpuis("STM32F101Z*")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
elif (cpuis("STM32F100V*")||cpuis("STM32F101V*")||cpuis("STM32F103V*")||cpuis("STM32F105V*")||cpuis("STM32F107V*"))
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA,PB,PC,PD,PE,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA,PB,PC,PD,PE,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA,PB,PC,PD,PE,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA,PB,PC,PD,PE,?..."
|
|
elif (cpuis("STM32F103R*")||cpuis("STM32F103C*")||cpuis("STM32F102*")||cpuis("STM32F101R*")||cpuis("STM32F101C*")||cpuis("STM32F100R*")||cpuis("STM32F100C*")||cpuis("STM32F105R*")||cpuis("STM32F107R*"))
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA,PB,PC,PD,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA,PB,PC,PD,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA,PB,PC,PD,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA,PB,PC,PD,?..."
|
|
else
|
|
bitfld.long 0x08 12.--15. " EXTI3 ,EXTI 3 configuration" "PA,PB,Reserved,PD,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI2 ,EXTI 2 configuration" "PA,PB,Reserved,PD,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI1 ,EXTI 1 configuration" "PA,PB,Reserved,PD,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " EXTI0 ,EXTI 0 configuration" "PA,PB,Reserved,PD,?..."
|
|
endif
|
|
line.long 0x0C "AFIO_EXTICR2,External interrupt configuration register 2"
|
|
sif (cpuis("STM32F103Z*")||cpuis("STM32F101Z*")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
elif (cpuis("STM32F100V*")||cpuis("STM32F101V*")||cpuis("STM32F103V*")||cpuis("STM32F105V*")||cpuis("STM32F107V*"))
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA,PB,PC,PD,PE,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA,PB,PC,PD,PE,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA,PB,PC,PD,PE,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA,PB,PC,PD,PE,?..."
|
|
elif (cpuis("STM32F103R*")||cpuis("STM32F103C*")||cpuis("STM32F102*")||cpuis("STM32F101R*")||cpuis("STM32F101C*")||cpuis("STM32F100R*")||cpuis("STM32F100C*")||cpuis("STM32F105R*")||cpuis("STM32F107R*"))
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA,PB,PC,PD,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA,PB,PC,PD,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA,PB,PC,PD,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA,PB,PC,PD,?..."
|
|
else
|
|
bitfld.long 0x0C 12.--15. " EXTI7 ,EXTI 7 configuration" "PA,PB,Reserved,PD,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI6 ,EXTI 6 configuration" "PA,PB,Reserved,PD,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI5 ,EXTI 5 configuration" "PA,PB,Reserved,PD,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " EXTI4 ,EXTI 4 configuration" "PA,PB,Reserved,PD,?..."
|
|
endif
|
|
line.long 0x10 "AFIO_EXTICR3,External interrupt configuration register 3"
|
|
sif (cpuis("STM32F103Z*")||cpuis("STM32F101Z*")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
elif (cpuis("STM32F100V*")||cpuis("STM32F101V*")||cpuis("STM32F103V*")||cpuis("STM32F105V*")||cpuis("STM32F107V*"))
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA,PB,PC,PD,PE,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA,PB,PC,PD,PE,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA,PB,PC,PD,PE,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA,PB,PC,PD,PE,?..."
|
|
elif (cpuis("STM32F103R*")||cpuis("STM32F103C*")||cpuis("STM32F102*")||cpuis("STM32F101R*")||cpuis("STM32F101C*")||cpuis("STM32F100R*")||cpuis("STM32F100C*")||cpuis("STM32F105R*")||cpuis("STM32F107R*"))
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA,PB,PC,PD,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA,PB,PC,PD,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA,PB,PC,PD,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA,PB,PC,PD,?..."
|
|
else
|
|
bitfld.long 0x10 12.--15. " EXTI11 ,EXTI 11 configuration" "PA,PB,Reserved,PD,?..."
|
|
bitfld.long 0x10 8.--11. " EXTI10 ,EXTI 10 configuration" "PA,PB,Reserved,PD,?..."
|
|
bitfld.long 0x10 4.--7. " EXTI9 ,EXTI 9 configuration" "PA,PB,Reserved,PD,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " EXTI8 ,EXTI 8 configuration" "PA,PB,Reserved,PD,?..."
|
|
endif
|
|
line.long 0x14 "AFIO_EXTICR4,External interrupt configuration register 4"
|
|
sif (cpuis("STM32F103Z*")||cpuis("STM32F101Z*")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA,PB,PC,PD,PE,PF,PG,?..."
|
|
elif (cpuis("STM32F100V*")||cpuis("STM32F101V*")||cpuis("STM32F103V*")||cpuis("STM32F105V*")||cpuis("STM32F107V*"))
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA,PB,PC,PD,PE,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA,PB,PC,PD,PE,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA,PB,PC,PD,PE,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA,PB,PC,PD,PE,?..."
|
|
elif (cpuis("STM32F103R*")||cpuis("STM32F103C*")||cpuis("STM32F102*")||cpuis("STM32F101R*")||cpuis("STM32F101C*")||cpuis("STM32F100R*")||cpuis("STM32F100C*")||cpuis("STM32F105R*")||cpuis("STM32F107R*"))
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA,PB,PC,PD,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA,PB,PC,PD,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA,PB,PC,PD,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA,PB,PC,PD,?..."
|
|
else
|
|
bitfld.long 0x14 12.--15. " EXTI15 ,EXTI 15 configuration" "PA,PB,Reserved,PD,?..."
|
|
bitfld.long 0x14 8.--11. " EXTI14 ,EXTI 14 configuration" "PA,PB,Reserved,PD,?..."
|
|
bitfld.long 0x14 4.--7. " EXTI13 ,EXTI 13 configuration" "PA,PB,Reserved,PD,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " EXTI12 ,EXTI 12 configuration" "PA,PB,Reserved,PD,?..."
|
|
endif
|
|
line.long 0x18 "AFIO_MAPR2,AF remap and debug I/O configuration register2"
|
|
sif (cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F103*C")||cpuis("STM32F103*D")||cpuis("STM32F103*E")||cpuis("STM32F103*F")||cpuis("STM32F103*G"))
|
|
sif ((!(cpuis("STM32F101R*")))&&(!(cpuis("STM32F103R*"))))
|
|
bitfld.long 0x18 10. " FSMC_NADV ,NADV signal Connect/Disconnect status" "Not connected,Connected"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F103*F")||cpuis("STM32F103*G"))
|
|
bitfld.long 0x18 9. " TIM14_REMAP ,TIM14 remapping" "No remap,Remap"
|
|
bitfld.long 0x18 8. " TIM13_REMAP ,TIM13 remapping" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x18 7. " TIM11_REMAP ,TIM11 remapping" "No remap,Remap"
|
|
bitfld.long 0x18 6. " TIM10_REMAP ,TIM10 remapping" "No remap,Remap"
|
|
bitfld.long 0x18 5. " TIM9_REMAP ,TIM9 remapping" "No remap,Remap"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F100*"))
|
|
sif ((cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")))
|
|
bitfld.long 0x18 9. " TIM14_REMAP ,TIM14 remapping" "No remap,Remap"
|
|
bitfld.long 0x18 8. " TIM13_REMAP ,TIM13 remapping" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 4. " TIM1_DMA_REMAP ,TIM1 DMA remapping" "No remap,Remap"
|
|
bitfld.long 0x18 3. " CEC_REMAP ,CEC remapping" "No remap,Remap"
|
|
bitfld.long 0x18 2. " TIM17_REMAP ,TIM17 remapping" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TIM16_REMAP ,TIM16 remapping" "No remap,Remap"
|
|
bitfld.long 0x18 0. " TIM15_REMAP ,TIM15 remapping" "No remap,Remap"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "EXTI (External Interrupt/Event Controller)"
|
|
base ad:0x40010400
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EXTI_IMR,Interrupt mask register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x00 19. " MR19 ,Interrupt Mask on line 19" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&cpu()!="STM32F100RC"&&cpu()!="STM32F100RD"&&cpu()!="STM32F100RE"&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&cpu()!="STM32F100VC"&&cpu()!="STM32F100VD"&&cpu()!="STM32F100VE"&&cpu()!="STM32F100ZC"&&cpu()!="STM32F100ZD"&&cpu()!="STM32F100ZE")
|
|
bitfld.long 0x00 18. " MR18 ,Interrupt Mask on line 18" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " MR17 ,Interrupt Mask on line 17" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MR16 ,Interrupt Mask on line 16" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " MR15 ,Interrupt Mask on line 15" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MR14 ,Interrupt Mask on line 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " MR13 ,Interrupt Mask on line 13" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MR12 ,Interrupt Mask on line 12" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " MR11 ,Interrupt Mask on line 11" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MR10 ,Interrupt Mask on line 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " MR9 ,Interrupt Mask on line 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR8 ,Interrupt Mask on line 8" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " MR7 ,Interrupt Mask on line 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MR6 ,Interrupt Mask on line 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " MR5 ,Interrupt Mask on line 5" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MR4 ,Interrupt Mask on line 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " MR3 ,Interrupt Mask on line 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR2 ,Interrupt Mask on line 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " MR1 ,Interrupt Mask on line 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MR0 ,Interrupt Mask on line 0" "Masked,Not masked"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EXTI_EMR,Event mask register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x00 19. " MR19 ,Event Mask on line 19" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&cpu()!="STM32F100RC"&&cpu()!="STM32F100RD"&&cpu()!="STM32F100RE"&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&cpu()!="STM32F100VC"&&cpu()!="STM32F100VD"&&cpu()!="STM32F100VE"&&cpu()!="STM32F100ZC"&&cpu()!="STM32F100ZD"&&cpu()!="STM32F100ZE")
|
|
bitfld.long 0x00 18. " MR18 ,Event Mask on line 18" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " MR17 ,Event Mask on line 17" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MR16 ,Event Mask on line 16" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " MR16 ,Event Mask on line 15" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MR14 ,Event Mask on line 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " MR14 ,Event Mask on line 13" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MR12 ,Event Mask on line 12" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " MR12 ,Event Mask on line 11" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MR10 ,Event Mask on line 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " MR9 ,Event Mask on line 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MR8 ,Event Mask on line 8" "Masked,Not masked"
|
|
bitfld.long 0x00 7. " MR7 ,Event Mask on line 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MR6 ,Event Mask on line 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " MR5 ,Event Mask on line 5" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MR4 ,Event Mask on line 4" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " MR3 ,Event Mask on line 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MR2 ,Event Mask on line 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " MR1 ,Event Mask on line 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MR0 ,Event Mask on line 0" "Masked,Not masked"
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EXTI_RTSR,Rising Trigger selection register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x00 19. " TR19 ,Rising trigger event configuration bit of line 19" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&cpu()!="STM32F100RC"&&cpu()!="STM32F100RD"&&cpu()!="STM32F100RE"&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&cpu()!="STM32F100VC"&&cpu()!="STM32F100VD"&&cpu()!="STM32F100VE"&&cpu()!="STM32F100ZC"&&cpu()!="STM32F100ZD"&&cpu()!="STM32F100ZE")
|
|
bitfld.long 0x00 18. " TR18 ,Rising trigger event configuration bit of line 18" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " TR17 ,Rising trigger event configuration bit of line 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TR16 ,Rising trigger event configuration bit of line 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TR15 ,Rising trigger event configuration bit of line 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TR14 ,Rising trigger event configuration bit of line 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TR13 ,Rising trigger event configuration bit of line 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TR12 ,Rising trigger event configuration bit of line 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TR11 ,Rising trigger event configuration bit of line 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TR10 ,Rising trigger event configuration bit of line 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TR9 ,Rising trigger event configuration bit of line 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TR8 ,Rising trigger event configuration bit of line 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TR7 ,Rising trigger event configuration bit of line 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TR6 ,Rising trigger event configuration bit of line 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TR5 ,Rising trigger event configuration bit of line 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TR4 ,Rising trigger event configuration bit of line 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TR3 ,Rising trigger event configuration bit of line 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TR2 ,Rising trigger event configuration bit of line 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TR1 ,Rising trigger event configuration bit of line 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TR0 ,Rising trigger event configuration bit of line 0" "Disabled,Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EXTI_FTSR,Falling Trigger selection register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x00 19. " TR19 ,Falling trigger event configuration bit of line 19" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&cpu()!="STM32F100RC"&&cpu()!="STM32F100RD"&&cpu()!="STM32F100RE"&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&cpu()!="STM32F100VC"&&cpu()!="STM32F100VD"&&cpu()!="STM32F100VE"&&cpu()!="STM32F100ZC"&&cpu()!="STM32F100ZD"&&cpu()!="STM32F100ZE")
|
|
bitfld.long 0x00 18. " TR18 ,Falling trigger event configuration bit of line 18" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " TR17 ,Falling trigger event configuration bit of line 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TR16 ,Falling trigger event configuration bit of line 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TR15 ,Falling trigger event configuration bit of line 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TR14 ,Falling trigger event configuration bit of line 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TR13 ,Falling trigger event configuration bit of line 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TR12 ,Falling trigger event configuration bit of line 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TR11 ,Falling trigger event configuration bit of line 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TR10 ,Falling trigger event configuration bit of line 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TR9 ,Falling trigger event configuration bit of line 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TR8 ,Falling trigger event configuration bit of line 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TR7 ,Falling trigger event configuration bit of line 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TR6 ,Falling trigger event configuration bit of line 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TR5 ,Falling trigger event configuration bit of line 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TR4 ,Falling trigger event configuration bit of line 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TR3 ,Falling trigger event configuration bit of line 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TR2 ,Falling trigger event configuration bit of line 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TR1 ,Falling trigger event configuration bit of line 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TR0 ,Falling trigger event configuration bit of line 0" "Disabled,Enabled"
|
|
width 12.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "EXTI_SWIER,Software interrupt event register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x00 19. " SWIER19 ,Software Interrupt on line 19" "No effect,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&cpu()!="STM32F100RC"&&cpu()!="STM32F100RD"&&cpu()!="STM32F100RE"&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&cpu()!="STM32F100VC"&&cpu()!="STM32F100VD"&&cpu()!="STM32F100VE"&&cpu()!="STM32F100ZC"&&cpu()!="STM32F100ZD"&&cpu()!="STM32F100ZE")
|
|
bitfld.long 0x00 18. " SWIER18 ,Software Interrupt on line 18" "No effect,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " SWIER17 ,Software Interrupt on line 17" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SWIER16 ,Software Interrupt on line 16" "No effect,Interrupt"
|
|
bitfld.long 0x00 15. " SWIER15 ,Software Interrupt on line 15" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWIER14 ,Software Interrupt on line 14" "No effect,Interrupt"
|
|
bitfld.long 0x00 13. " SWIER13 ,Software Interrupt on line 13" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWIER12 ,Software Interrupt on line 12" "No effect,Interrupt"
|
|
bitfld.long 0x00 11. " SWIER11 ,Software Interrupt on line 11" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SWIER10 ,Software Interrupt on line 10" "No effect,Interrupt"
|
|
bitfld.long 0x00 9. " SWIER9 ,Software Interrupt on line 9" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SWIER8 ,Software Interrupt on line 8" "No effect,Interrupt"
|
|
bitfld.long 0x00 7. " SWIER7 ,Software Interrupt on line 7" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SWIER6 ,Software Interrupt on line 6" "No effect,Interrupt"
|
|
bitfld.long 0x00 5. " SWIER5 ,Software Interrupt on line 5" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SWIER4 ,Software Interrupt on line 4" "No effect,Interrupt"
|
|
bitfld.long 0x00 3. " SWIER3 ,Software Interrupt on line 3" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SWIER2 ,Software Interrupt on line 2" "No effect,Interrupt"
|
|
bitfld.long 0x00 1. " SWIER1 ,Software Interrupt on line 1" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SWIER0 ,Software Interrupt on line 0" "No effect,Interrupt"
|
|
width 12.
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EXTI_PR,Pending register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
eventfld.long 0x00 19. " PR19 ,Pending bit" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&cpu()!="STM32F100RC"&&cpu()!="STM32F100RD"&&cpu()!="STM32F100RE"&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&cpu()!="STM32F100VC"&&cpu()!="STM32F100VD"&&cpu()!="STM32F100VE"&&cpu()!="STM32F100ZC"&&cpu()!="STM32F100ZD"&&cpu()!="STM32F100ZE")
|
|
eventfld.long 0x00 18. " PR18 ,Pending bit" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 17. " PR17 ,Pending bit" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 16. " PR16 ,Pending bit" "Not requested,Requested"
|
|
eventfld.long 0x00 15. " PR15 ,Pending bit" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 14. " PR14 ,Pending bit" "Not requested,Requested"
|
|
eventfld.long 0x00 13. " PR13 ,Pending bit" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 12. " PR12 ,Pending bit" "Not requested,Requested"
|
|
eventfld.long 0x00 11. " PR11 ,Pending bit" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 10. " PR10 ,Pending bit" "Not requested,Requested"
|
|
eventfld.long 0x00 9. " PR9 ,Pending bit" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PR8 ,Pending bit" "Not requested,Requested"
|
|
eventfld.long 0x00 7. " PR7 ,Pending bit" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 6. " PR6 ,Pending bit" "Not requested,Requested"
|
|
eventfld.long 0x00 5. " PR5 ,Pending bit" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 4. " PR4 ,Pending bit" "Not requested,Requested"
|
|
eventfld.long 0x00 3. " PR3 ,Pending bit" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 2. " PR2 ,Pending bit" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " PR1 ,Pending bit" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 0. " PR0 ,Pending bit" "Not requested,Requested"
|
|
width 0xB
|
|
tree.end
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
tree.open "DMA Controller"
|
|
tree "DMA 1"
|
|
base ad:0x40020000
|
|
width 12.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x00 27. " TEIF7 ,Channel 7 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 26. " HTIF7 ,Channel 7 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TCIF7 ,Channel 7 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " GIF7 ,Channel 7 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEIF6 ,Channel 6 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 22. " HTIF6 ,Channel 6 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TCIF6 ,Channel 6 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " GIF6 ,Channel 6 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TEIF5 ,Channel 5 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 18. " HTIF5 ,Channel 5 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TCIF5 ,Channel 5 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " GIF5 ,Channel 5 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEIF4 ,Channel 4 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 14. " HTIF4 ,Channel 4 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TCIF4 ,Channel 4 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " GIF4 ,Channel 4 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TEIF3 ,Channel 3 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 10. " HTIF3 ,Channel 3 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TCIF3 ,Channel 3 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " GIF3 ,Channel 3 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TEIF2 ,Channel 2 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 6. " HTIF2 ,Channel 2 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TCIF2 ,Channel 2 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " GIF2 ,Channel 2 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIF1 ,Channel 1 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 2. " HTIF1 ,Channel 1 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIF1 ,Channel 1 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " GIF1 ,Channel 1 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x00 27. " CTEIF7 ,Channel 7 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CHTIF7 ,Channel 7 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CTCIF7 ,Channel 7 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CGIF7 ,Channel 7 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CTEIF6 ,Channel 6 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " CHTIF6 ,Channel 6 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CTCIF6 ,Channel 6 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CGIF6 ,Channel 6 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x00 27. " CTEIF7 ,Channel 7 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CHTIF7 ,Channel 7 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CTCIF7 ,Channel 7 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CGIF7 ,Channel 7 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CTEIF6 ,Channel 6 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " CHTIF6 ,Channel 6 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CTCIF6 ,Channel 6 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CGIF6 ,Channel 6 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTEIF2 ,Channel 2 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CHTIF2 ,Channel 2 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CTCIF2 ,Channel 2 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CTEIF1 ,Channel 1 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CHTIF1 ,Channel 1 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CTCIF1 ,Channel 1 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
endif
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA channel 1 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA channel 1 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA channel 2 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA channel 2 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA channel 3 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA channel 3 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA channel 4 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA channel 4 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA channel 5 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
group.long 0x6C++0x0F "Channel 6"
|
|
line.long 0x00 "DMA_CCR6,DMA channel 6 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR6,DMA channel 6 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR6,DMA channel 6 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR6,DMA channel 6 memory address register"
|
|
group.long 0x80++0x0F "Channel 7"
|
|
line.long 0x00 "DMA_CCR7,DMA channel 7 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR7,DMA channel 7 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR7,DMA channel 7 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR7,DMA channel 7 memory address register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA 2"
|
|
base ad:0x40020400
|
|
width 12.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x00 19. " TEIF5 ,Channel 5 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 18. " HTIF5 ,Channel 5 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TCIF5 ,Channel 5 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " GIF5 ,Channel 5 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEIF4 ,Channel 4 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 14. " HTIF4 ,Channel 4 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TCIF4 ,Channel 4 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " GIF4 ,Channel 4 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TEIF3 ,Channel 3 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 10. " HTIF3 ,Channel 3 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TCIF3 ,Channel 3 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " GIF3 ,Channel 3 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TEIF2 ,Channel 2 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 6. " HTIF2 ,Channel 2 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TCIF2 ,Channel 2 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " GIF2 ,Channel 2 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIF1 ,Channel 1 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 2. " HTIF1 ,Channel 1 Half Transfer flag" "Not transfered,Transfered"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIF1 ,Channel 1 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " GIF1 ,Channel 1 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 7 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTEIF2 ,Channel 2 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CHTIF2 ,Channel 2 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CTCIF2 ,Channel 2 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CTEIF1 ,Channel 1 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CHTIF1 ,Channel 1 Half Transfer clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CTCIF1 ,Channel 1 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
endif
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA channel 1 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA channel 1 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA channel 2 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA channel 2 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA channel 3 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA channel 3 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA channel 4 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA channel 4 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA channel 5 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "DMA"
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base ad:0x40020000
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width 12.
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rgroup.long 0x00++0x03
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line.long 0x00 "DMA_ISR,DMA interrupt status register"
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bitfld.long 0x00 27. " TEIF7 ,Channel 7 Transfer Error flag" "No error,Error"
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bitfld.long 0x00 26. " HTIF7 ,Channel 7 Half Transfer flag" "Not transfered,Transfered"
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textline " "
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bitfld.long 0x00 25. " TCIF7 ,Channel 7 Transfer Complete flag" "Not completed,Completed"
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bitfld.long 0x00 24. " GIF7 ,Channel 7 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
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textline " "
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bitfld.long 0x00 23. " TEIF6 ,Channel 6 Transfer Error flag" "No error,Error"
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bitfld.long 0x00 22. " HTIF6 ,Channel 6 Half Transfer flag" "Not transfered,Transfered"
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textline " "
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bitfld.long 0x00 21. " TCIF6 ,Channel 6 Transfer Complete flag" "Not completed,Completed"
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bitfld.long 0x00 20. " GIF6 ,Channel 6 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
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textline " "
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bitfld.long 0x00 19. " TEIF5 ,Channel 5 Transfer Error flag" "No error,Error"
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bitfld.long 0x00 18. " HTIF5 ,Channel 5 Half Transfer flag" "Not transfered,Transfered"
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textline " "
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bitfld.long 0x00 17. " TCIF5 ,Channel 5 Transfer Complete flag" "Not completed,Completed"
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bitfld.long 0x00 16. " GIF5 ,Channel 5 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
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textline " "
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bitfld.long 0x00 15. " TEIF4 ,Channel 4 Transfer Error flag" "No error,Error"
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bitfld.long 0x00 14. " HTIF4 ,Channel 4 Half Transfer flag" "Not transfered,Transfered"
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textline " "
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bitfld.long 0x00 13. " TCIF4 ,Channel 4 Transfer Complete flag" "Not completed,Completed"
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bitfld.long 0x00 12. " GIF4 ,Channel 4 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
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textline " "
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bitfld.long 0x00 11. " TEIF3 ,Channel 3 Transfer Error flag" "No error,Error"
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bitfld.long 0x00 10. " HTIF3 ,Channel 3 Half Transfer flag" "Not transfered,Transfered"
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textline " "
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bitfld.long 0x00 9. " TCIF3 ,Channel 3 Transfer Complete flag" "Not completed,Completed"
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bitfld.long 0x00 8. " GIF3 ,Channel 3 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
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textline " "
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bitfld.long 0x00 7. " TEIF2 ,Channel 2 Transfer Error flag" "No error,Error"
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bitfld.long 0x00 6. " HTIF2 ,Channel 2 Half Transfer flag" "Not transfered,Transfered"
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textline " "
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bitfld.long 0x00 5. " TCIF2 ,Channel 2 Transfer Complete flag" "Not completed,Completed"
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bitfld.long 0x00 4. " GIF2 ,Channel 2 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
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textline " "
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bitfld.long 0x00 3. " TEIF1 ,Channel 1 Transfer Error flag" "No error,Error"
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bitfld.long 0x00 2. " HTIF1 ,Channel 1 Half Transfer flag" "Not transfered,Transfered"
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textline " "
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bitfld.long 0x00 1. " TCIF1 ,Channel 1 Transfer Complete flag" "Not completed,Completed"
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bitfld.long 0x00 0. " GIF1 ,Channel 1 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
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sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")
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wgroup.long 0x04++0x03
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line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
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bitfld.long 0x00 27. " CTEIF7 ,Channel 7 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 26. " CHTIF7 ,Channel 7 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 25. " CTCIF7 ,Channel 7 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 24. " CGIF7 ,Channel 7 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 23. " CTEIF6 ,Channel 6 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 22. " CHTIF6 ,Channel 6 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 21. " CTCIF6 ,Channel 6 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 20. " CGIF6 ,Channel 6 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 7. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
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bitfld.long 0x00 6. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 5. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
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bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 3. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
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bitfld.long 0x00 2. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 1. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
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bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
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else
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group.long 0x04++0x03
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line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
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bitfld.long 0x00 27. " CTEIF7 ,Channel 7 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 26. " CHTIF7 ,Channel 7 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 25. " CTCIF7 ,Channel 7 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 24. " CGIF7 ,Channel 7 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 23. " CTEIF6 ,Channel 6 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 22. " CHTIF6 ,Channel 6 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 21. " CTCIF6 ,Channel 6 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 20. " CGIF6 ,Channel 6 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 7. " CTEIF2 ,Channel 2 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 6. " CHTIF2 ,Channel 2 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 5. " CTCIF2 ,Channel 2 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 3. " CTEIF1 ,Channel 1 Transfer Error clear" "No effect,Clear"
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bitfld.long 0x00 2. " CHTIF1 ,Channel 1 Half Transfer clear" "No effect,Clear"
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textline " "
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bitfld.long 0x00 1. " CTCIF1 ,Channel 1 Transfer Complete clear" "No effect,Clear"
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bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
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endif
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group.long 0x8++0x0F "Channel 1"
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line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
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bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
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bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
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textline " "
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bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
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bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
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textline " "
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bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
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bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
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bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
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textline " "
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bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
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line.long 0x04 "DMA_CNDTR1,DMA channel 1 number of data register"
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hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
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line.long 0x08 "DMA_CPAR1,DMA channel 1 peripheral address register"
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line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
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group.long 0x1C++0x0F "Channel 2"
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line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
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bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
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bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
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textline " "
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bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
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bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
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textline " "
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bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
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bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
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bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
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textline " "
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bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
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line.long 0x04 "DMA_CNDTR2,DMA channel 2 number of data register"
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hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
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line.long 0x08 "DMA_CPAR2,DMA channel 2 peripheral address register"
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line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
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group.long 0x30++0x0F "Channel 3"
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line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
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bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
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bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
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textline " "
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bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
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bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
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textline " "
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bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
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bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
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bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
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textline " "
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bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
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line.long 0x04 "DMA_CNDTR3,DMA channel 3 number of data register"
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hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
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line.long 0x08 "DMA_CPAR3,DMA channel 3 peripheral address register"
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line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
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group.long 0x44++0x0F "Channel 4"
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line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
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bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
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bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
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textline " "
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bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
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bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
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textline " "
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bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
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bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
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bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
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textline " "
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bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
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line.long 0x04 "DMA_CNDTR4,DMA channel 4 number of data register"
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hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
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line.long 0x08 "DMA_CPAR4,DMA channel 4 peripheral address register"
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line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
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group.long 0x58++0x0F "Channel 5"
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line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
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bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
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bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
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textline " "
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bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
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bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
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textline " "
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bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
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bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
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bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
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textline " "
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bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
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textline " "
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bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
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bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
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line.long 0x04 "DMA_CNDTR5,DMA channel 5 number of data register"
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hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
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line.long 0x08 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
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line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
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group.long 0x6C++0x0F "Channel 6"
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line.long 0x00 "DMA_CCR6,DMA channel 6 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
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bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
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bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
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bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR6,DMA channel 6 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR6,DMA channel 6 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR6,DMA channel 6 memory address register"
|
|
group.long 0x80++0x0F "Channel 7"
|
|
line.long 0x00 "DMA_CCR7,DMA channel 7 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,"
|
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bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
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bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR7,DMA channel 7 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR7,DMA channel 7 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR7,DMA channel 7 memory address register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F103*")||cpu()=="STM32F103"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
tree.open "ADC (Analog/Digital Converter)"
|
|
tree "ADC 1"
|
|
base ad:0x40012400
|
|
width 11.
|
|
group.long 0x00++0x0b
|
|
line.long 0x00 "ADC_SR,ADC status register"
|
|
bitfld.long 0x00 4. " STRT ,Regular channel Start flag" "Not started,Started"
|
|
bitfld.long 0x00 3. " JSTRT ,Injected channel Start flag" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " EOC ,End of conversion" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred"
|
|
line.long 0x04 "ADC_CR1,ADC control register 1"
|
|
bitfld.long 0x04 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&cpu()!="STM32F100RC"&&cpu()!="STM32F100RD"&&cpu()!="STM32F100RE"&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&cpu()!="STM32F100VC"&&cpu()!="STM32F100VD"&&cpu()!="STM32F100VE"&&cpu()!="STM32F100ZC"&&cpu()!="STM32F100ZD"&&cpu()!="STM32F100ZE")
|
|
bitfld.long 0x04 16.--19. " DUALMOD ,Dual mode selection" "Independent,Regular+Injected,Regular+Alternate,Injected+Fast,Injected+Slow,Injected only,Regular only,Fast only,Slow only,Alternate only,?..."
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1 channel,2 channels,3 channels,4 channels,5 channels,6 channels,7 channels,8 channels"
|
|
else
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1 channel,2 channels,3 channels,4 channels,5 channels,6 channels,7 channels,8 channels"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " JAUTO ,Automatic Injected Group conversion" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " AWDIE ,Analog Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,?..."
|
|
elif (cpuis("STM32F103R*")||cpuis("STM32F103V*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101R*")||cpuis("STM32F101V*")||cpu()=="STM32F101"||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..."
|
|
else
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,?..."
|
|
endif
|
|
line.long 0x08 "ADC_CR2,ADC control register 2"
|
|
bitfld.long 0x08 23. " TSVREFE ,Temperature Sensor and VREFINT Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " SWSTART ,Start Conversion of regular channels" "Reset,Start"
|
|
textline " "
|
|
bitfld.long 0x08 21. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x08 20. " EXTTRIG ,External Trigger Conversion mode for regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F103*F")||cpuis("STM32F103*G")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 1 CC1,Timer 1 CC2,Timer 1 CC3,Timer 2 CC2,Timer 3 TRGO,Timer 4 CC4,EXTI 11/TIM8_TRGO,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Reserved,Reserved,Reserved,Timer 2 CC2,Timer 3 TRGO,Reserved,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F102*8")||cpuis("STM32F102*B")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F101*8")||cpuis("STM32F101*B")||cpu()=="STM32F101")
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Reserved,Reserved,Reserved,Timer 2 CC2,Timer 3 TRGO,Timer 4 CC4,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 1 CC1,Timer 1 CC2,Timer 1 CC3,Timer 2 CC2,Timer 3 TRGO,Reserved,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 1 CC1,Timer 1 CC2,Timer 1 CC3,Timer 2 CC2,Timer 3 TRGO,Timer 4 CC4,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("STM32F103*F")||cpuis("STM32F103*G")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Timer 4 TRGO,EXTI 15/TIM8_CC4,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Reserved,Reserved,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Reserved,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F102*8")||cpuis("STM32F102*B")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F101*8")||cpuis("STM32F101*B")||cpu()=="STM32F101")
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Reserved,Reserved,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Timer 4 TRGO,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Reserved,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
else
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Timer 4 TRGO,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " RSTCAL ,Reset Calibration" "Initialized,Initialize"
|
|
textline " "
|
|
bitfld.long 0x08 2. " CAL ,A/D Calibration" "Completed,Enabled"
|
|
bitfld.long 0x08 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
width 11.
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
group.long 0x10++0x2B
|
|
line.long 0x00 "ADC_SMPR2,ADC sample time register 2"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
width 11.
|
|
line.long 0x4 "ADC_JOFR1,ADC injected channel data offset register 1"
|
|
hexmask.long.word 0x4 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1"
|
|
line.long 0x8 "ADC_JOFR2,ADC injected channel data offset register 2"
|
|
hexmask.long.word 0x8 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2"
|
|
line.long 0xC "ADC_JOFR3,ADC injected channel data offset register 3"
|
|
hexmask.long.word 0xC 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3"
|
|
line.long 0x10 "ADC_JOFR4,ADC injected channel data offset register 4"
|
|
hexmask.long.word 0x10 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4"
|
|
line.long 0x14 "ADC_HTR,ADC watchdog high threshold register"
|
|
hexmask.long.word 0x14 0.--11. 1. " HT ,Analog watchdog high threshold"
|
|
line.long 0x18 "ADC_LTR,ADC watchdog low threshold register"
|
|
hexmask.long.word 0x18 0.--11. 1. " LT ,Analog watchdog low threshold"
|
|
width 11.
|
|
line.long 0x1C "ADC_SQR1,ADC regular sequence register 1"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
line.long 0x20 "ADC_SQR2,ADC regular sequence register 2"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
line.long 0x24 "ADC_SQR3,ADC regular sequence register 3"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpu()=="STM32F101"||cpuis("STM32F100V*")||cpuis("STM32F100R*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
width 11.
|
|
line.long 0x28 "ADC_JSQR,ADC injected sequence register"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpu()=="STM32F101"||cpuis("STM32F100V*")||cpuis("STM32F100R*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
rgroup.long 0x3C++0x13
|
|
line.long 0x0 "ADC_JDR1,ADC injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x4 "ADC_JDR2,ADC injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x8 "ADC_JDR3,ADC injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0xC "ADC_JDR4,ADC injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x00 "ADC_DR,ADC regular data register"
|
|
sif (cpuis("STM32F103*")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
hexmask.long.word 0x00 16.--31. 1. " ADC2DATA ,ADC2 data"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "ADC 2"
|
|
base ad:0x40012800
|
|
width 11.
|
|
group.long 0x00++0x0b
|
|
line.long 0x00 "ADC_SR,ADC status register"
|
|
bitfld.long 0x00 4. " STRT ,Regular channel Start flag" "Not started,Started"
|
|
bitfld.long 0x00 3. " JSTRT ,Injected channel Start flag" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " EOC ,End of conversion" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred"
|
|
line.long 0x04 "ADC_CR1,ADC control register 1"
|
|
bitfld.long 0x04 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&cpu()!="STM32F100RC"&&cpu()!="STM32F100RD"&&cpu()!="STM32F100RE"&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&cpu()!="STM32F100VC"&&cpu()!="STM32F100VD"&&cpu()!="STM32F100VE"&&cpu()!="STM32F100ZC"&&cpu()!="STM32F100ZD"&&cpu()!="STM32F100ZE")
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1 channel,2 channels,3 channels,4 channels,5 channels,6 channels,7 channels,8 channels"
|
|
else
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1 channel,2 channels,3 channels,4 channels,5 channels,6 channels,7 channels,8 channels"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " JAUTO ,Automatic Injected Group conversion" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " AWDIE ,Analog Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,?..."
|
|
elif (cpuis("STM32F103R*")||cpuis("STM32F103V*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101R*")||cpuis("STM32F101V*")||cpu()=="STM32F101"||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..."
|
|
else
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,?..."
|
|
endif
|
|
line.long 0x08 "ADC_CR2,ADC control register 2"
|
|
bitfld.long 0x08 23. " TSVREFE ,Temperature Sensor and VREFINT Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " SWSTART ,Start Conversion of regular channels" "Reset,Start"
|
|
textline " "
|
|
bitfld.long 0x08 21. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x08 20. " EXTTRIG ,External Trigger Conversion mode for regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F103*F")||cpuis("STM32F103*G")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 1 CC1,Timer 1 CC2,Timer 1 CC3,Timer 2 CC2,Timer 3 TRGO,Timer 4 CC4,EXTI 11/TIM8_TRGO,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Reserved,Reserved,Reserved,Timer 2 CC2,Timer 3 TRGO,Reserved,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F102*8")||cpuis("STM32F102*B")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F101*8")||cpuis("STM32F101*B")||cpu()=="STM32F101")
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Reserved,Reserved,Reserved,Timer 2 CC2,Timer 3 TRGO,Timer 4 CC4,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 1 CC1,Timer 1 CC2,Timer 1 CC3,Timer 2 CC2,Timer 3 TRGO,Reserved,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 1 CC1,Timer 1 CC2,Timer 1 CC3,Timer 2 CC2,Timer 3 TRGO,Timer 4 CC4,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("STM32F103*F")||cpuis("STM32F103*G")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Timer 4 TRGO,EXTI 15/TIM8_CC4,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Reserved,Reserved,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Reserved,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F102*8")||cpuis("STM32F102*B")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F101*8")||cpuis("STM32F101*B")||cpu()=="STM32F101")
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Reserved,Reserved,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Timer 4 TRGO,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Reserved,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
else
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Timer 4 TRGO,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " RSTCAL ,Reset Calibration" "Initialized,Initialize"
|
|
textline " "
|
|
bitfld.long 0x08 2. " CAL ,A/D Calibration" "Completed,Enabled"
|
|
bitfld.long 0x08 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
width 11.
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
group.long 0x10++0x2B
|
|
line.long 0x00 "ADC_SMPR2,ADC sample time register 2"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
width 11.
|
|
line.long 0x4 "ADC_JOFR1,ADC injected channel data offset register 1"
|
|
hexmask.long.word 0x4 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1"
|
|
line.long 0x8 "ADC_JOFR2,ADC injected channel data offset register 2"
|
|
hexmask.long.word 0x8 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2"
|
|
line.long 0xC "ADC_JOFR3,ADC injected channel data offset register 3"
|
|
hexmask.long.word 0xC 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3"
|
|
line.long 0x10 "ADC_JOFR4,ADC injected channel data offset register 4"
|
|
hexmask.long.word 0x10 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4"
|
|
line.long 0x14 "ADC_HTR,ADC watchdog high threshold register"
|
|
hexmask.long.word 0x14 0.--11. 1. " HT ,Analog watchdog high threshold"
|
|
line.long 0x18 "ADC_LTR,ADC watchdog low threshold register"
|
|
hexmask.long.word 0x18 0.--11. 1. " LT ,Analog watchdog low threshold"
|
|
width 11.
|
|
line.long 0x1C "ADC_SQR1,ADC regular sequence register 1"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
line.long 0x20 "ADC_SQR2,ADC regular sequence register 2"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
line.long 0x24 "ADC_SQR3,ADC regular sequence register 3"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpu()=="STM32F101"||cpuis("STM32F100V*")||cpuis("STM32F100R*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
width 11.
|
|
line.long 0x28 "ADC_JSQR,ADC injected sequence register"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpu()=="STM32F101"||cpuis("STM32F100V*")||cpuis("STM32F100R*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
rgroup.long 0x3C++0x13
|
|
line.long 0x0 "ADC_JDR1,ADC injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x4 "ADC_JDR2,ADC injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x8 "ADC_JDR3,ADC injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0xC "ADC_JDR4,ADC injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x00 "ADC_DR,ADC regular data register"
|
|
sif (cpuis("STM32F103*")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
tree "ADC 3"
|
|
base ad:0x40013C00
|
|
width 11.
|
|
group.long 0x00++0x0b
|
|
line.long 0x00 "ADC_SR,ADC status register"
|
|
bitfld.long 0x00 4. " STRT ,Regular channel Start flag" "Not started,Started"
|
|
bitfld.long 0x00 3. " JSTRT ,Injected channel Start flag" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " EOC ,End of conversion" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred"
|
|
line.long 0x04 "ADC_CR1,ADC control register 1"
|
|
bitfld.long 0x04 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&cpu()!="STM32F100RC"&&cpu()!="STM32F100RD"&&cpu()!="STM32F100RE"&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&cpu()!="STM32F100VC"&&cpu()!="STM32F100VD"&&cpu()!="STM32F100VE"&&cpu()!="STM32F100ZC"&&cpu()!="STM32F100ZD"&&cpu()!="STM32F100ZE")
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1 channel,2 channels,3 channels,4 channels,5 channels,6 channels,7 channels,8 channels"
|
|
else
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1 channel,2 channels,3 channels,4 channels,5 channels,6 channels,7 channels,8 channels"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " JAUTO ,Automatic Injected Group conversion" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " AWDIE ,Analog Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,?..."
|
|
elif (cpuis("STM32F103R*")||cpuis("STM32F103V*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101R*")||cpuis("STM32F101V*")||cpu()=="STM32F101"||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..."
|
|
else
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,?..."
|
|
endif
|
|
line.long 0x08 "ADC_CR2,ADC control register 2"
|
|
bitfld.long 0x08 23. " TSVREFE ,Temperature Sensor and VREFINT Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " SWSTART ,Start Conversion of regular channels" "Reset,Start"
|
|
textline " "
|
|
bitfld.long 0x08 21. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x08 20. " EXTTRIG ,External Trigger Conversion mode for regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F103*F")||cpuis("STM32F103*G")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 3 CC1,Timer 2 CC3,Timer 1 CC3,Timer 8 CC1,Timer 8 TRGO,Timer 5 CC1,Timer 5 CC3,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Reserved,Reserved,Reserved,Timer 2 CC2,Timer 3 TRGO,Reserved,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F102*8")||cpuis("STM32F102*B")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F101*8")||cpuis("STM32F101*B")||cpu()=="STM32F101")
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Reserved,Reserved,Reserved,Timer 2 CC2,Timer 3 TRGO,Timer 4 CC4,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 1 CC1,Timer 1 CC2,Timer 1 CC3,Timer 2 CC2,Timer 3 TRGO,Reserved,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 1 CC1,Timer 1 CC2,Timer 1 CC3,Timer 2 CC2,Timer 3 TRGO,Timer 4 CC4,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("STM32F103*F")||cpuis("STM32F103*G")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 4 CC3,Timer 8 CC2,Timer 8 CC4,Timer 5 TRGO,Timer 5 CC4,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Reserved,Reserved,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Reserved,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F102*8")||cpuis("STM32F102*B")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F101*8")||cpuis("STM32F101*B")||cpu()=="STM32F101")
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Reserved,Reserved,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Timer 4 TRGO,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Reserved,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
else
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Timer 4 TRGO,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " RSTCAL ,Reset Calibration" "Initialized,Initialize"
|
|
textline " "
|
|
bitfld.long 0x08 2. " CAL ,A/D Calibration" "Completed,Enabled"
|
|
bitfld.long 0x08 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
width 11.
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
group.long 0x10++0x2B
|
|
line.long 0x00 "ADC_SMPR2,ADC sample time register 2"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
width 11.
|
|
line.long 0x4 "ADC_JOFR1,ADC injected channel data offset register 1"
|
|
hexmask.long.word 0x4 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1"
|
|
line.long 0x8 "ADC_JOFR2,ADC injected channel data offset register 2"
|
|
hexmask.long.word 0x8 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2"
|
|
line.long 0xC "ADC_JOFR3,ADC injected channel data offset register 3"
|
|
hexmask.long.word 0xC 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3"
|
|
line.long 0x10 "ADC_JOFR4,ADC injected channel data offset register 4"
|
|
hexmask.long.word 0x10 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4"
|
|
line.long 0x14 "ADC_HTR,ADC watchdog high threshold register"
|
|
hexmask.long.word 0x14 0.--11. 1. " HT ,Analog watchdog high threshold"
|
|
line.long 0x18 "ADC_LTR,ADC watchdog low threshold register"
|
|
hexmask.long.word 0x18 0.--11. 1. " LT ,Analog watchdog low threshold"
|
|
width 11.
|
|
line.long 0x1C "ADC_SQR1,ADC regular sequence register 1"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
line.long 0x20 "ADC_SQR2,ADC regular sequence register 2"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
line.long 0x24 "ADC_SQR3,ADC regular sequence register 3"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpu()=="STM32F101"||cpuis("STM32F100V*")||cpuis("STM32F100R*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
width 11.
|
|
line.long 0x28 "ADC_JSQR,ADC injected sequence register"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpu()=="STM32F101"||cpuis("STM32F100V*")||cpuis("STM32F100R*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
rgroup.long 0x3C++0x13
|
|
line.long 0x0 "ADC_JDR1,ADC injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x4 "ADC_JDR2,ADC injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x8 "ADC_JDR3,ADC injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0xC "ADC_JDR4,ADC injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x00 "ADC_DR,ADC regular data register"
|
|
sif (cpuis("STM32F103*")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
else
|
|
tree "ADC (Analog/Digital Converter)"
|
|
base ad:0x40012400
|
|
width 11.
|
|
group.long 0x00++0x0b
|
|
line.long 0x00 "ADC_SR,ADC status register"
|
|
bitfld.long 0x00 4. " STRT ,Regular channel Start flag" "Not started,Started"
|
|
bitfld.long 0x00 3. " JSTRT ,Injected channel Start flag" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " EOC ,End of conversion" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred"
|
|
line.long 0x04 "ADC_CR1,ADC control register 1"
|
|
bitfld.long 0x04 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100C8"&&cpu()!="STM32F100CB"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&cpu()!="STM32F100R8"&&cpu()!="STM32F100RB"&&cpu()!="STM32F100RC"&&cpu()!="STM32F100RD"&&cpu()!="STM32F100RE"&&cpu()!="STM32F100V8"&&cpu()!="STM32F100VB"&&cpu()!="STM32F100VC"&&cpu()!="STM32F100VD"&&cpu()!="STM32F100VE"&&cpu()!="STM32F100ZC"&&cpu()!="STM32F100ZD"&&cpu()!="STM32F100ZE")
|
|
bitfld.long 0x04 16.--19. " DUALMOD ,Dual mode selection" "Independent,Regular+Injected,Regular+Alternate,Injected+Fast,Injected+Slow,Injected only,Regular only,Fast only,Slow only,Alternate only,?..."
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1 channel,2 channels,3 channels,4 channels,5 channels,6 channels,7 channels,8 channels"
|
|
else
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1 channel,2 channels,3 channels,4 channels,5 channels,6 channels,7 channels,8 channels"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " JAUTO ,Automatic Injected Group conversion" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " AWDIE ,Analog Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,?..."
|
|
elif (cpuis("STM32F103R*")||cpuis("STM32F103V*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101R*")||cpuis("STM32F101V*")||cpu()=="STM32F101"||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,?..."
|
|
else
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,?..."
|
|
endif
|
|
line.long 0x08 "ADC_CR2,ADC control register 2"
|
|
bitfld.long 0x08 23. " TSVREFE ,Temperature Sensor and VREFINT Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " SWSTART ,Start Conversion of regular channels" "Reset,Start"
|
|
textline " "
|
|
bitfld.long 0x08 21. " JSWSTART ,Start Conversion of injected channels" "Reset,Start"
|
|
bitfld.long 0x08 20. " EXTTRIG ,External Trigger Conversion mode for regular channels" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F103*F")||cpuis("STM32F103*G")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 1 CC1,Timer 1 CC2,Timer 1 CC3,Timer 2 CC2,Timer 3 TRGO,Timer 4 CC4,EXTI 11/TIM8_TRGO,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Reserved,Reserved,Reserved,Timer 2 CC2,Timer 3 TRGO,Reserved,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F102*8")||cpuis("STM32F102*B")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F101*8")||cpuis("STM32F101*B")||cpu()=="STM32F101")
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Reserved,Reserved,Reserved,Timer 2 CC2,Timer 3 TRGO,Timer 4 CC4,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 1 CC1,Timer 1 CC2,Timer 1 CC3,Timer 2 CC2,Timer 3 TRGO,Reserved,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External Event Select for regular group" "Timer 1 CC1,Timer 1 CC2,Timer 1 CC3,Timer 2 CC2,Timer 3 TRGO,Timer 4 CC4,EXTI 11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External Trigger Conversion mode for injected channels" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("STM32F103*F")||cpuis("STM32F103*G")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Timer 4 TRGO,EXTI 15/TIM8_CC4,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6")||cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Reserved,Reserved,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Reserved,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F102*8")||cpuis("STM32F102*B")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F101*8")||cpuis("STM32F101*B")||cpu()=="STM32F101")
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Reserved,Reserved,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Timer 4 TRGO,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Reserved,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
else
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "Timer 1 TRGO,Timer 1 CC4,Timer 2 TRGO,Timer 2 CC1,Timer 3 CC4,Timer 4 TRGO,Interrupt 15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data Alignment" "Right,Left"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " RSTCAL ,Reset Calibration" "Initialized,Initialize"
|
|
textline " "
|
|
bitfld.long 0x08 2. " CAL ,A/D Calibration" "Completed,Enabled"
|
|
bitfld.long 0x08 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ADON ,A/D Converter ON / OFF" "Disabled,Enabled"
|
|
width 11.
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "ADC_SMPR1,ADC sample time register 1"
|
|
bitfld.long 0x00 21.--23. " SMP17 ,Channel 17 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 18.--20. " SMP16 ,Channel 16 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 15.--17. " SMP15 ,Channel 15 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 12.--14. " SMP14 ,Channel 14 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP13 ,Channel 13 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 6.--8. " SMP12 ,Channel 12 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 3.--5. " SMP11 ,Channel 11 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 0.--2. " SMP10 ,Channel 10 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
group.long 0x10++0x2B
|
|
line.long 0x00 "ADC_SMPR2,ADC sample time register 2"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Channel 9 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Channel 8 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Channel 7 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Channel 6 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Channel 5 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Channel 4 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Channel 3 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Channel 2 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Channel 1 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
bitfld.long 0x00 0.--2. " SMP0 ,Channel 0 Sample time selection" "1.5,7.5,13.5,28.5,41.5,55.5,71.5,239.5"
|
|
width 11.
|
|
line.long 0x4 "ADC_JOFR1,ADC injected channel data offset register 1"
|
|
hexmask.long.word 0x4 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1"
|
|
line.long 0x8 "ADC_JOFR2,ADC injected channel data offset register 2"
|
|
hexmask.long.word 0x8 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2"
|
|
line.long 0xC "ADC_JOFR3,ADC injected channel data offset register 3"
|
|
hexmask.long.word 0xC 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3"
|
|
line.long 0x10 "ADC_JOFR4,ADC injected channel data offset register 4"
|
|
hexmask.long.word 0x10 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4"
|
|
line.long 0x14 "ADC_HTR,ADC watchdog high threshold register"
|
|
hexmask.long.word 0x14 0.--11. 1. " HT ,Analog watchdog high threshold"
|
|
line.long 0x18 "ADC_LTR,ADC watchdog low threshold register"
|
|
hexmask.long.word 0x18 0.--11. 1. " LT ,Analog watchdog low threshold"
|
|
width 11.
|
|
line.long 0x1C "ADC_SQR1,ADC regular sequence register 1"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x1C 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x1C 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x1C 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
line.long 0x20 "ADC_SQR2,ADC regular sequence register 2"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x20 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x20 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
line.long 0x24 "ADC_SQR3,ADC regular sequence register 3"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpu()=="STM32F101"||cpuis("STM32F100V*")||cpuis("STM32F100R*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x24 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x24 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
width 11.
|
|
line.long 0x28 "ADC_JSQR,ADC injected sequence register"
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103")
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
elif (cpuis("STM32F103V*")||cpuis("STM32F103R*")||cpuis("STM32F102R*")||cpuis("STM32F101Z*")||cpuis("STM32F101V*")||cpuis("STM32F101R*")||cpu()=="STM32F101"||cpuis("STM32F100V*")||cpuis("STM32F100R*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
bitfld.long 0x28 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x28 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x28 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x28 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x28 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
endif
|
|
rgroup.long 0x3C++0x13
|
|
line.long 0x0 "ADC_JDR1,ADC injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x4 "ADC_JDR2,ADC injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x8 "ADC_JDR3,ADC injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0xC "ADC_JDR4,ADC injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. " JDATA ,Injected data"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x00 "ADC_DR,ADC regular data register"
|
|
sif (cpuis("STM32F103*")||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
hexmask.long.word 0x00 16.--31. 1. " ADC2DATA ,ADC2 data"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Regular data"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F100*")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
tree "DAC (Digital-to-Analog Converter)"
|
|
base ad:0x40007400
|
|
width 13.
|
|
if ((per.l(ad:0x40007400)&0x40004)==0x40004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 Unmask bits/Amplitude selector" "Bit[0]/1,Bits[1:0]/3,Bits[2:0]/7,Bits[3:0]/15,Bits[4:0]/31,Bits[5:0]/63,Bits[6:0]/127,Bits[7:0]/255,Bits[8:0]/511,Bits[9:0]/1023,Bits[10:0]/2047,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095"
|
|
textline " "
|
|
sif (cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G"))
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpuis("STM32F103*C")||cpuis("STM32F103*D")||cpuis("STM32F103*E")||cpuis("STM32F103*F")||cpuis("STM32F103*G"))
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpu()=="STM32F100C8"||cpu()=="STM32F100CB"||cpu()=="STM32F100R8"||cpu()=="STM32F100RB"||cpu()=="STM32F100RC"||cpu()=="STM32F100RD"||cpu()=="STM32F100RE"||cpuis("STM32F100V*")||cpu()=="STM32F100ZC"||cpu()=="STM32F100ZD"||cpu()=="STM32F100ZE")
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Reserved,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel2 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel2 output buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 Unmask/Amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G"))
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpuis("STM32F103*C")||cpuis("STM32F103*D")||cpuis("STM32F103*E")||cpuis("STM32F103*F")||cpuis("STM32F103*G"))
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpu()=="STM32F100C8"||cpu()=="STM32F100CB"||cpu()=="STM32F100R8"||cpu()=="STM32F100RB"||cpu()=="STM32F100RC"||cpu()=="STM32F100RD"||cpu()=="STM32F100RE"||cpuis("STM32F100V*")||cpu()=="STM32F100ZC"||cpu()=="STM32F100ZD"||cpu()=="STM32F100ZE")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Reserved,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel1 output buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x00004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 Unmask bits/Amplitude selector" "Bit[0]/1,Bits[1:0]/3,Bits[2:0]/7,Bits[3:0]/15,Bits[4:0]/31,Bits[5:0]/63,Bits[6:0]/127,Bits[7:0]/255,Bits[8:0]/511,Bits[9:0]/1023,Bits[10:0]/2047,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel2 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel2 output buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 Unmask/Amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G"))
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpuis("STM32F103*C")||cpuis("STM32F103*D")||cpuis("STM32F103*E")||cpuis("STM32F103*F")||cpuis("STM32F103*G"))
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpu()=="STM32F100C8"||cpu()=="STM32F100CB"||cpu()=="STM32F100R8"||cpu()=="STM32F100RB"||cpu()=="STM32F100RC"||cpu()=="STM32F100RD"||cpu()=="STM32F100RE"||cpuis("STM32F100V*")||cpu()=="STM32F100ZC"||cpu()=="STM32F100ZD"||cpu()=="STM32F100ZE")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Reserved,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel1 output buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x40000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 Unmask bits/Amplitude selector" "Bit[0]/1,Bits[1:0]/3,Bits[2:0]/7,Bits[3:0]/15,Bits[4:0]/31,Bits[5:0]/63,Bits[6:0]/127,Bits[7:0]/255,Bits[8:0]/511,Bits[9:0]/1023,Bits[10:0]/2047,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095"
|
|
textline " "
|
|
sif (cpuis("STM32F103*")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G"))
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpuis("STM32F103*C")||cpuis("STM32F103*D")||cpuis("STM32F103*E")||cpuis("STM32F103*F")||cpuis("STM32F103*G"))
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Timer 8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpu()=="STM32F100C8"||cpu()=="STM32F100CB"||cpu()=="STM32F100R8"||cpu()=="STM32F100RB"||cpu()=="STM32F100RC"||cpu()=="STM32F100RD"||cpu()=="STM32F100RE"||cpuis("STM32F100V*")||cpu()=="STM32F100ZC"||cpu()=="STM32F100ZD"||cpu()=="STM32F100ZE")
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Reserved,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel2 Trigger selection" "Timer 6 TRGO,Reserved,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel2 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel2 output buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 Unmask/Amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel1 output buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel2 Unmask bits/Amplitude selector" "Bit[0]/1,Bits[1:0]/3,Bits[2:0]/7,Bits[3:0]/15,Bits[4:0]/31,Bits[5:0]/63,Bits[6:0]/127,Bits[7:0]/255,Bits[8:0]/511,Bits[9:0]/1023,Bits[10:0]/2047,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel2 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel2 output buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 Unmask/Amplitude selector" "Bit[0]/1,Bits[1:0]/3,Bits[2:0]/7,Bits[3:0]/15,Bits[4:0]/31,Bits[5:0]/63,Bits[6:0]/127,Bits[7:0]/255,Bits[8:0]/511,Bits[9:0]/1023,Bits[10:0]/2047,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095,Bits[11:0]/4095"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel1 Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x27
|
|
line.long 0x00 "DAC_SWTRIGR,DAC Software Trigger Register"
|
|
bitfld.long 0x00 1. " SWTRIG2 ,DAC channel2 software trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,DAC channel1 software trigger" "Disabled,Enabled"
|
|
line.long 0x04 "DAC_DHR12R1,DAC channel1 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DACC1DHR ,DAC channel1 12-bit Right aligned data"
|
|
line.long 0x08 "DAC_DHR12L1,DAC channel1 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x08 4.--15. 1. " DACC1DHR ,DAC channel1 12-bit Left aligned data"
|
|
line.long 0x0c "DAC_DHR8R1,DAC channel1 8-bit Right aligned Data Holding Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " DACC1DHR ,DAC channel1 8-bit Right aligned data"
|
|
line.long 0x10 "DAC_DHR12R2,DAC channel2 12-bit Right aligned Data Holding Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " DACC2DHR ,DAC channel2 12-bit Right aligned data"
|
|
line.long 0x14 "DAC_DHR12L2,DAC channel2 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x14 4.--15. 1. " DACC2DHR ,DAC channel2 12-bit Left aligned data"
|
|
line.long 0x18 "DAC_DHR8R2,DAC channel2 8-bit Right-aligned Data Holding Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DACC2DHR ,DAC channel2 8-bit Right aligned data"
|
|
line.long 0x1c "DAC_DHR12RD,Dual DAC 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x1c 16.--27. 1. " DACC2DHR ,DAC channel2 12-bit Right aligned data"
|
|
hexmask.long.word 0x1c 0.--11. 1. " DACC1DHR ,DAC channel1 12-bit Right aligned data"
|
|
line.long 0x20 "DAC_DHR12LD,DUAL DAC 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x20 20.--31. 1. " DACC2DHR ,DAC channel2 12-bit Left aligned data"
|
|
hexmask.long.word 0x20 4.--15. 1. " DACC1DHR ,DAC channel1 12-bit Left aligned data"
|
|
line.long 0x24 "DAC_DHR8RD,DUAL DAC 8-bit Right aligned Data Holding Register"
|
|
hexmask.long.byte 0x24 8.--15. 1. " DACC2DHR ,DAC channel2 8-bit Right aligned data"
|
|
hexmask.long.byte 0x24 0.--7. 1. " DACC1DHR ,DAC channel1 8-bit Right aligned data"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "DAC_DOR1,DAC channel1 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DOR ,DAC channel1 data output"
|
|
line.long 0x04 "DAC_DOR2,DAC channel2 Data Output Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DACC2DOR ,DAC channel2 data output"
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC_SR,DAC status register"
|
|
eventfld.long 0x00 29. " DMAUDR2 ,DAC channel2 DMA underrun flag" "No error,Error"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,DAC channel1 DMA underrun flag" "No error,Error"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F100*")||cpuis("STM32F103*")||cpuis("STM32F105*")||cpuis("STM32F107*")||cpu()=="STM32F103")
|
|
tree.open "Advanced Control Timer"
|
|
tree "TIM 1"
|
|
base ad:0x40012C00
|
|
width 12.
|
|
if (((per.w(ad:0x40012C00))&0x60)>0)||((((per.w(ad:0x40012C00+0x08))&0x7)>=0x1)&&(((per.w(ad:0x40012C00+0x08))&0x7)<=0x3))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM1_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM1_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40012C00+0x44))&0x300)!=0x0)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM1_CR2,Control register 2"
|
|
rbitfld.word 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
rbitfld.word 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
rbitfld.word 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
rbitfld.word 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
rbitfld.word 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COM bit only,COM bit/Rising edge"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM1_CR2,Control register 2"
|
|
bitfld.word 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
bitfld.word 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
bitfld.word 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
bitfld.word 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
bitfld.word 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COM bit only,COM bit/Rising edge"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded"
|
|
endif
|
|
if (((per.l(ad:0x40012C00+0x8))&0x07)!=0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM1_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
textline " "
|
|
sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
textline " "
|
|
else
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM1_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
textline " "
|
|
sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM1_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM1_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt Flag" "No break,Break"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt Flag" "No COM,COM"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM1_EGR,Event generation register"
|
|
bitfld.word 0x00 7. " BG ,Break Generation" "No effect,Generate"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate"
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare Control Update Generation" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.l(ad:0x40012C00+0x44))&0x300)==0x300)
|
|
if (((per.w((ad:0x40012C00+0x18)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x18)))&0x300)!=0x000)&&(((per.w((ad:0x40012C00+0x18)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40012C00+0x18)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x18)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x18)))&0x300)!=0x000)&&(((per.w((ad:0x40012C00+0x18)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40012C00+0x18)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40012C00+0x44))&0x300)==0x300)
|
|
if (((per.w((ad:0x40012C00+0x1C)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40012C00+0x1C)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40012C00+0x1C)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x1C)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40012C00+0x1C)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40012C00+0x1C)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textline " "
|
|
if (((per.w(ad:0x40012C00+0x44))&0x300)==(0x200||0x300))
|
|
if (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Not inverted,Inverted"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Not inverted,Inverted"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output Polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Off,On"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output Polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Not inverted,Inverted"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM1_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM1_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM1_ARR,Auto-reload register"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "TIM1_RCR,Repetition counter register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition Counter Value"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM1_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM1_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM1_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM1_CCR4,Capture/compare register 4"
|
|
if (((per.l(ad:0x40012C00+0x44))&0x300)==0x100)
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
elif (((per.l(ad:0x40012C00+0x44))&0x300)==0x200)
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
else
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
endif
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM1_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM1_CR1,TIM1_CR2,TIM1_SMCR,TIM1_DIER,TIM1_SR,TIM1_EGR,TIM1_CCMR1,TIM1_CCMR2,TIM1_CCER,TIM1_CNT,TIM1_PSC,TIM1_ARR,TIM1_RCR,TIM1_CCR1,TIM1_CCR2,TIM1_CCR3,TIM1_CCR4,TIM1_BDTR,TIM1_DCR,TIM1_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM1_DMAR,DMA address for burst mode"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
tree "TIM 8"
|
|
base ad:0x40013400
|
|
width 12.
|
|
if (((per.w(ad:0x40013400))&0x60)>0)||((((per.w(ad:0x40013400+0x08))&0x7)>=0x1)&&(((per.w(ad:0x40013400+0x08))&0x7)<=0x3))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM8_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM8_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40013400+0x44))&0x300)!=0x0)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM8_CR2,Control register 2"
|
|
rbitfld.word 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
rbitfld.word 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
rbitfld.word 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
rbitfld.word 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
rbitfld.word 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COM bit only,COM bit/Rising edge"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM8_CR2,Control register 2"
|
|
bitfld.word 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
bitfld.word 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
bitfld.word 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
bitfld.word 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
bitfld.word 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COM bit only,COM bit/Rising edge"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded"
|
|
endif
|
|
if (((per.l(ad:0x40013400+0x8))&0x07)!=0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM8_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
textline " "
|
|
sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
textline " "
|
|
else
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM8_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
textline " "
|
|
sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM8_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM8_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt Flag" "No break,Break"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt Flag" "No COM,COM"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM8_EGR,Event generation register"
|
|
bitfld.word 0x00 7. " BG ,Break Generation" "No effect,Generate"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate"
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare Control Update Generation" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.l(ad:0x40013400+0x44))&0x300)==0x300)
|
|
if (((per.w((ad:0x40013400+0x18)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40013400+0x18)))&0x300)!=0x000)&&(((per.w((ad:0x40013400+0x18)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40013400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40013400+0x18)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40013400+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40013400+0x18)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40013400+0x18)))&0x300)!=0x000)&&(((per.w((ad:0x40013400+0x18)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40013400+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40013400+0x18)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40013400+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40013400+0x44))&0x300)==0x300)
|
|
if (((per.w((ad:0x40013400+0x1C)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40013400+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40013400+0x1C)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40013400+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40013400+0x1C)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40013400+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40013400+0x1C)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40013400+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40013400+0x1C)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40013400+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40013400+0x1C)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40013400+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40013400+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40013400+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textline " "
|
|
if (((per.w(ad:0x40013400+0x44))&0x300)==(0x200||0x300))
|
|
if (((per.w(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x300)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40013400+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x303)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40013400+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40013400+0x18))&0x300)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40013400+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40013400+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x300)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40013400+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x303)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40013400+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40013400+0x18))&0x300)==0x00)&&(((per.w(ad:0x40013400+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013400+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40013400+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40013400+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Not inverted,Inverted"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Not inverted,Inverted"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output Polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Off,On"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output Polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Not inverted,Inverted"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM8_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM8_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM8_ARR,Auto-reload register"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "TIM8_RCR,Repetition counter register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition Counter Value"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM8_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM8_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM8_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM8_CCR4,Capture/compare register 4"
|
|
if (((per.l(ad:0x40013400+0x44))&0x300)==0x100)
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "TIM8_BDTR,Break and dead-time register"
|
|
bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
elif (((per.l(ad:0x40013400+0x44))&0x300)==0x200)
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "TIM8_BDTR,Break and dead-time register"
|
|
bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
else
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "TIM8_BDTR,Break and dead-time register"
|
|
bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
endif
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM8_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM8_CR1,TIM8_CR2,TIM8_SMCR,TIM8_DIER,TIM8_SR,TIM8_EGR,TIM8_CCMR1,TIM8_CCMR2,TIM8_CCER,TIM8_CNT,TIM8_PSC,TIM8_ARR,TIM8_RCR,TIM8_CCR1,TIM8_CCR2,TIM8_CCR3,TIM8_CCR4,TIM8_BDTR,TIM8_DCR,TIM8_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM8_DMAR,DMA address for burst mode"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.open "General Purpose Timer"
|
|
tree "TIM 2"
|
|
base ad:0x40000000
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM2_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM2_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC2,Update"
|
|
width 12.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM2_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpuis("STM32F103*8")||cpuis("STM32F103*B")||cpu()=="STM32F103"||cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F101TB"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "Reserved,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "Reserved,Reserved,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F101*F")||cpuis("STM32F101*G"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "Reserved,Reserved,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
endif
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 12.
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM2_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 12.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM2_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM2_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enabled"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.w((ad:0x40000000+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
endif
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM2_CNT,Counter"
|
|
hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,High Counter Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[0:15] ,Low Counter Value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM2_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM2_ARR,Auto-reload register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High Auto-Reload"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR[0:15] ,Low Auto-Reload"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "TIM2_CCR1,Capture/compare register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High Capture/Compare Value 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[0:15] ,Low Capture/Compare Value 1"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TIM2_CCR2,Capture/compare register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR2[31:16] ,High Capture/Compare Value 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR2[0:15] ,Low Capture/Compare Value 2"
|
|
group.long 0x3c++0x7
|
|
line.long 0x00 "TIM2_CCR3,Capture/compare register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR3[31:16] ,High Capture/Compare Value 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR3[0:15] ,Low Capture/Compare Value 3"
|
|
line.long 0x04 "TIM2_CCR4,Capture/compare register 4"
|
|
hexmask.long.word 0x04 16.--31. 1. " CCR4[31:16] ,High Capture/Compare Value 4"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR4[0:15] ,Low Capture/Compare Value 4"
|
|
else
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM2_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM2_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM2_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM2_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM2_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM2_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM2_CCR4,Capture/compare register 4"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM2_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM2_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM2_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM2_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM2_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM2_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM2_CCR4,Capture/compare register 4"
|
|
endif
|
|
width 12.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM2_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,Reserved,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,Reserved,TIM2_DCR,TIM2_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM2_DMAR,DMA address for burst mode"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE"))
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "TIM2_OR,TIM2 option register"
|
|
bitfld.word 0x00 10.--11. " ITR1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,PTP,USB SOF FS,USB SOF HS"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TIM 3"
|
|
base ad:0x40000400
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM3_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM3_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC3,Update"
|
|
width 12.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM3_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpuis("STM32F103*8")||cpuis("STM32F103*B")||cpu()=="STM32F103"||cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F101TB"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "Reserved,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "Reserved,ITR1,Reserved,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F101*F")||cpuis("STM32F101*G"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "Reserved,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
endif
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 12.
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM3_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 12.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM3_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM3_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enabled"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.w((ad:0x40000400+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40000400+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40000400+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40000400+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
endif
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM3_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[0:15] ,Low Counter Value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM3_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM3_ARR,Auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR[0:15] ,Low Auto-Reload"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "TIM3_CCR1,Capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[0:15] ,Low Capture/Compare Value 1"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TIM3_CCR2,Capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR2[0:15] ,Low Capture/Compare Value 2"
|
|
else
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM3_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM3_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM3_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM3_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM3_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM3_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM3_CCR4,Capture/compare register 4"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM3_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM3_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM3_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM3_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM3_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM3_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM3_CCR4,Capture/compare register 4"
|
|
endif
|
|
width 12.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM3_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM3_CR1,TIM3_CR2,TIM3_SMCR,TIM3_DIER,TIM3_SR,TIM3_EGR,TIM3_CCMR1,TIM3_CCMR2,TIM3_CCER,TIM3_CNT,TIM3_PSC,TIM3_ARR,Reserved,TIM3_CCR1,TIM3_CCR2,TIM3_CCR3,TIM3_CCR4,Reserved,TIM3_DCR,TIM3_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM3_DMAR,DMA address for burst mode"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE"))
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
sif (cpu()!="STM32F102C4"&&cpu()!="STM32F102R4"&&cpu()!="STM32F102C6"&&cpu()!="STM32F102R6"&&cpu()!="STM32F103C4"&&cpu()!="STM32F103R4"&&cpu()!="STM32F103T4"&&cpu()!="STM32F103C6"&&cpu()!="STM32F103R6"&&cpu()!="STM32F103T6"&&cpu()!="STM32F102C4"&&cpu()!="STM32F102R4"&&cpu()!="STM32F102C6"&&cpu()!="STM32F102R6"&&cpu()!="STM32F101C4"&&cpu()!="STM32F101R4"&&cpu()!="STM32F101T4"&&cpu()!="STM32F101C6"&&cpu()!="STM32F101R6"&&cpu()!="STM32F101T6"&&cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100CR4"&&cpu()!="STM32F100R6")
|
|
tree "TIM 4"
|
|
base ad:0x40000800
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM4_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM4_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC4,Update"
|
|
width 12.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM4_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpuis("STM32F103*8")||cpuis("STM32F103*B")||cpu()=="STM32F103"||cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F101TB"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "Reserved,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F101*F")||cpuis("STM32F101*G"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "Reserved,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
endif
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 12.
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM4_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 12.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM4_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM4_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enabled"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.w((ad:0x40000800+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000800+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
endif
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM4_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[0:15] ,Low Counter Value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM4_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM4_ARR,Auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR[0:15] ,Low Auto-Reload"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "TIM4_CCR1,Capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[0:15] ,Low Capture/Compare Value 1"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TIM4_CCR2,Capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR2[0:15] ,Low Capture/Compare Value 2"
|
|
else
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM4_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM4_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM4_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM4_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM4_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM4_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM4_CCR4,Capture/compare register 4"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM4_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM4_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM4_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM4_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM4_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM4_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM4_CCR4,Capture/compare register 4"
|
|
endif
|
|
width 12.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM4_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM4_CR1,TIM4_CR2,TIM4_SMCR,TIM4_DIER,TIM4_SR,TIM4_EGR,TIM4_CCMR1,TIM4_CCMR2,TIM4_CCER,TIM4_CNT,TIM4_PSC,TIM4_ARR,Reserved,TIM4_CCR1,TIM4_CCR2,TIM4_CCR3,TIM4_CCR4,Reserved,TIM4_DCR,TIM4_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM4_DMAR,DMA address for burst mode"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE"))
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F101*E")||cpuis("STM32F101*D")||cpuis("STM32F101*C")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
tree "TIM 5"
|
|
base ad:0x40000C00
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM5_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM5_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CC5,Update"
|
|
width 12.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM5_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpuis("STM32F103*8")||cpuis("STM32F103*B")||cpu()=="STM32F103"||cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F101TB"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F102*4")||cpuis("STM32F102*6"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "Reserved,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F101*4")||cpuis("STM32F101*6"))
|
|
elif (cpuis("STM32F103*4")||cpuis("STM32F103*6"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F101*F")||cpuis("STM32F101*G"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,Reserved,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
elif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
endif
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 12.
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM5_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 12.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM5_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM5_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Enabled"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
textline " "
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
bitfld.word 0x00 13. 15. " CC4NP ,Capture/Compare 4 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,Reserved,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
endif
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM5_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[0:15] ,Low Counter Value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM5_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM5_ARR,Auto-reload register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR[0:15] ,Low Auto-Reload"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "TIM5_CCR1,Capture/compare register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[0:15] ,Low Capture/Compare Value 1"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TIM5_CCR2,Capture/compare register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR2[0:15] ,Low Capture/Compare Value 2"
|
|
else
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM5_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM5_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM5_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM5_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM5_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM5_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM5_CCR4,Capture/compare register 4"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM5_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM5_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM5_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM5_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM5_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM5_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM5_CCR4,Capture/compare register 4"
|
|
endif
|
|
width 12.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM5_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM5_CR1,TIM5_CR2,TIM5_SMCR,TIM5_DIER,TIM5_SR,TIM5_EGR,TIM5_CCMR1,TIM5_CCMR2,TIM5_CCER,TIM5_CNT,TIM5_PSC,TIM5_ARR,Reserved,TIM5_CCR1,TIM5_CCR2,TIM5_CCR3,TIM5_CCR4,Reserved,TIM5_DCR,TIM5_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM5_DMAR,DMA address for burst mode"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE"))
|
|
sif (cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*"))
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F103*F")||cpuis("STM32F103*G"))
|
|
tree "TIM 9"
|
|
base ad:0x40014C00
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM9_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned mode,Center-aligned mode 1,Center-aligned mode 2,Center-aligned mode 3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
sif !cpuis("STM32F4*")
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif (!cpuis("STM32F4*"))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM9_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,?..."
|
|
endif
|
|
if (((per.l(ad:0x40014C00+0x08))&0x07)!=0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM9_SMCR,Slave mode control register"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM9_SMCR,Slave mode control register"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM9_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM9_SR,Status register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM9_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40014C00+0x18)))&0x303)==0x000)
|
|
if (((per.l(ad:0x40014C00+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40014C00+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40014C00+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40014C00+0x18)))&0x300)!=0x0)&&(((per.w((ad:0x40014C00+0x18)))&0x3)==0x0)
|
|
if (((per.l(ad:0x40014C00+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40014C00+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40014C00+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40014C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40014C00+0x18)))&0x03)!=0x00)
|
|
if (((per.l(ad:0x40014C00+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40014C00+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40014C00+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014C00+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40014C00+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40014C00+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM9_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
if (((per.w((ad:0x40014C00+0x18)))&0x303)==0x000)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40014C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40014C00+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40014C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40014C00+0x18)))&0x3)!=0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM9_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity Output/Input CC2NP=0|CC2NP=1" "High/Not inverted Rising edge|,Low/Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity Output/Input CC2NP=0|CC2NP=1" "High/Not inverted Rising edge|,Low/Inverted Falling edge|Not inverted Both edges"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM9_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM9_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM9_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM9_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM9_CCR2,Capture/compare register 2"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM9_OR,TIM9 option register 1"
|
|
bitfld.word 0x00 2. " ITR1_RMP ,Timer 9 ITR1 remap" "Connected to TIM3_TGO,Connected to touch sensing I/O"
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM9 input 1 remapping capability" "TIM9CH1->GPIO,LSE EC->TIM9CH1,TIM9CH1->GPIO,TIM9CH1->GPIO"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TIM 10"
|
|
base ad:0x40015000
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM10_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
sif cpuis("STM32F4*")
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/ug set,Overflow/Overflow"
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM10_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (!cpuis("STM32L162?D")&&!cpuis("STM32L152?D")&&!cpuis("STM32L151?D")&&!cpuis("STM32L151?C")&&!cpuis("STM32L152?C")&&!cpuis("STM32L151?6")&&!cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
endif
|
|
elif (cpuis("STM32F2*"))
|
|
hgroup.word 0x08++0x1
|
|
hide.word 0x00 "TIM10_SMCR,Slave mode control register"
|
|
elif (!cpuis("STM32F4*"))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM10_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,?..."
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM10_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM10_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM10_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40015000+0x20)))&0x1)==0x1)
|
|
if (((per.w((ad:0x40015000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40015000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM10_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
if (((per.w((ad:0x40015000+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM10_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM10_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM10_CCER,Capture/compare enable register"
|
|
sif (cpuis("STM32F4*"))
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "0,1"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output/input CC1NP=0|CC1NP=1" "High/Not inverted Rising edge|Reserved,Low/Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM10_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM10_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM10_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM10_CCR1,Capture/compare register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM10_OR,TIM10 option register 1"
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 3. " TI1_RMP_RI ,Timer10 Input 1 remap for Routing Interface" "Depends on TI1_RMP[1:0],Connected to RI"
|
|
bitfld.word 0x00 2. " ETR_RMP ,Timer10 ETR remap" "Connected to LSE clock,Connected to TIM9_TGO"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM10 Input 1 remapping capability" "TIM10CH1->GPIO,LSE EC->TIM10CH1,LSE EC->TIM10CH1,RTC OE->TIM10CH1"
|
|
elif (cpuis("STM32F2*"))
|
|
elif (cpuis("STM32F4*"))
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TIM 11"
|
|
base ad:0x40015400
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM11_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
sif cpuis("STM32F4*")
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/ug set,Overflow/Overflow"
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM11_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (!cpuis("STM32L162?D")&&!cpuis("STM32L152?D")&&!cpuis("STM32L151?D")&&!cpuis("STM32L151?C")&&!cpuis("STM32L152?C")&&!cpuis("STM32L151?6")&&!cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
endif
|
|
elif (cpuis("STM32F2*"))
|
|
hgroup.word 0x08++0x1
|
|
hide.word 0x00 "TIM11_SMCR,Slave mode control register"
|
|
elif (!cpuis("STM32F4*"))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM11_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,?..."
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM11_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM11_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM11_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40015400+0x20)))&0x1)==0x1)
|
|
if (((per.w((ad:0x40015400+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40015400+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM11_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
if (((per.w((ad:0x40015400+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM11_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM11_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM11_CCER,Capture/compare enable register"
|
|
sif (cpuis("STM32F4*"))
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "0,1"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output/input CC1NP=0|CC1NP=1" "High/Not inverted Rising edge|Reserved,Low/Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM11_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM11_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM11_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM11_CCR1,Capture/compare register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM11_OR,TIM11 option register 1"
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 3. " TI1_RMP_RI ,Timer11 Input 1 remap for Routing Interface" "Depends on TI1_RMP[1:0],Connected to RI"
|
|
bitfld.word 0x00 2. " ETR_RMP ,Timer11 ETR remap" "Connected to LSE clock,Connected to TIM9_TGO"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 Input 1 remapping capability" "TIM11CH1->GPIO,MSI IC->TIM11CH1,HSE EC->TIM9CH1,TIM11CH1->GPIO"
|
|
elif (cpuis("STM32F2*"))
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM11_OR,TIM11 option register 1"
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 Input 1 remapping capability" "TIM11CH1->GPIO,TIM11CH1->GPIO,HSE IC->TIM11CH1,TIM11CH1->GPIO"
|
|
textline " "
|
|
elif (cpuis("STM32F4*"))
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM11_OR,TIM11 option register 1"
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM11 Input 1 remapping capability" "TIM11CH1->GPIO,TIM11CH1->GPIO,HSE RTC->TIM11CH1,TIM11CH1->GPIO"
|
|
textline " "
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpuis("STM32F101*G")||cpuis("STM32F101*F")||cpuis("STM32F101*E")||cpuis("STM32F101*D")||cpuis("STM32F101*C")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
tree "TIM 12"
|
|
base ad:0x40001800
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM12_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge-aligned mode,Center-aligned mode 1,Center-aligned mode 2,Center-aligned mode 3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Upcounter,Downcounter"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
sif !cpuis("STM32F4*")
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif (!cpuis("STM32F4*"))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM12_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,?..."
|
|
endif
|
|
if (((per.l(ad:0x40001800+0x08))&0x07)!=0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM12_SMCR,Slave mode control register"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM12_SMCR,Slave mode control register"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM12_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM12_SR,Status register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM12_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40001800+0x18)))&0x303)==0x000)
|
|
if (((per.l(ad:0x40001800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40001800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40001800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40001800+0x18)))&0x300)!=0x0)&&(((per.w((ad:0x40001800+0x18)))&0x3)==0x0)
|
|
if (((per.l(ad:0x40001800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40001800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40001800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40001800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40001800+0x18)))&0x03)!=0x00)
|
|
if (((per.l(ad:0x40001800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40001800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40001800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40001800+0x20))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40001800+0x20))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.l(ad:0x40001800+0x20))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6")||cpuis("STM32F4*"))
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
endif
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
if (((per.w((ad:0x40001800+0x18)))&0x303)==0x000)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM12_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40001800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40001800+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM12_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
elif (((per.w((ad:0x40001800+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40001800+0x18)))&0x3)!=0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM12_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM12_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 5. 7. " CC2NP ,Capture/Compare 2 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 input polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 input enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM12_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 1 complementary output Polarity" "0,1"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity Output/Input CC2NP=0|CC2NP=1" "High/Not inverted Rising edge|,Low/Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output Polarity" "0,?..."
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 2 output polarity Output/Input CC2NP=0|CC2NP=1" "High/Not inverted Rising edge|,Low/Inverted Falling edge|Not inverted Both edges"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM12_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM12_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM12_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM12_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM12_CCR2,Capture/compare register 2"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L152?C")||cpuis("STM32L152?6"))
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM12_OR,TIM12 option register 1"
|
|
bitfld.word 0x00 2. " ITR1_RMP ,Timer 9 ITR1 remap" "Connected to TIM3_TGO,Connected to touch sensing I/O"
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,TIM9 input 1 remapping capability" "TIM9CH1->GPIO,LSE EC->TIM9CH1,TIM9CH1->GPIO,TIM9CH1->GPIO"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TIM 13"
|
|
base ad:0x40001C00
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM13_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
sif cpuis("STM32F4*")
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/ug set,Overflow/Overflow"
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM13_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (!cpuis("STM32L162?D")&&!cpuis("STM32L152?D")&&!cpuis("STM32L151?D")&&!cpuis("STM32L151?C")&&!cpuis("STM32L152?C")&&!cpuis("STM32L151?6")&&!cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
endif
|
|
elif (cpuis("STM32F2*"))
|
|
hgroup.word 0x08++0x1
|
|
hide.word 0x00 "TIM13_SMCR,Slave mode control register"
|
|
elif (!cpuis("STM32F4*"))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM13_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,?..."
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM13_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM13_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM13_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40001C00+0x20)))&0x1)==0x1)
|
|
if (((per.w((ad:0x40001C00+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40001C00+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
if (((per.w((ad:0x40001C00+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM13_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM13_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM13_CCER,Capture/compare enable register"
|
|
sif (cpuis("STM32F4*"))
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "0,1"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output/input CC1NP=0|CC1NP=1" "High/Not inverted Rising edge|Reserved,Low/Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM13_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM13_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM13_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM13_CCR1,Capture/compare register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x50++0x1
|
|
elif (cpuis("STM32F2*"))
|
|
elif (cpuis("STM32F4*"))
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TIM 14"
|
|
base ad:0x40002000
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM14_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
sif cpuis("STM32F4*")
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/ug set,Overflow/Overflow"
|
|
else
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM14_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
sif (!cpuis("STM32L162?D")&&!cpuis("STM32L152?D")&&!cpuis("STM32L151?D")&&!cpuis("STM32L151?C")&&!cpuis("STM32L152?C")&&!cpuis("STM32L151?6")&&!cpuis("STM32L152?6"))
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
endif
|
|
elif (cpuis("STM32F2*"))
|
|
hgroup.word 0x08++0x1
|
|
hide.word 0x00 "TIM14_SMCR,Slave mode control register"
|
|
elif (!cpuis("STM32F4*"))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM14_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,?..."
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM14_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM14_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM14_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.w((ad:0x40002000+0x20)))&0x1)==0x1)
|
|
if (((per.w((ad:0x40002000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40002000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32L15*")||cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32L162?D")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,?..."
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F4*")
|
|
if (((per.w((ad:0x40002000+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM14_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "0,?..."
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM14_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1NP ,Capture/Compare 1 output polarity" "Not inverted/Rising,Inverted/Falling,,Not inverted/Both"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM14_CCER,Capture/compare enable register"
|
|
sif (cpuis("STM32F4*"))
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "0,1"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output/input CC1NP=0|CC1NP=1" "High/Not inverted Rising edge|Reserved,Low/Inverted Falling edge|Not inverted Both edges"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high/Not inverted/Rising edge,Active low/Inverted/Falling edge"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM14_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM14_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM14_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM14_CCR1,Capture/compare register 1"
|
|
sif (cpuis("STM32L15*")||cpuis("STM32L162?D"))
|
|
group.word 0x50++0x1
|
|
elif (cpuis("STM32F2*"))
|
|
elif (cpuis("STM32F4*"))
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F100*"))
|
|
tree "TIM 15"
|
|
base ad:0x40014000
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM15_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.l(ad:0x40014000+0x44))&0x300)==0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM15_CR2,Control Register 2"
|
|
bitfld.word 0x00 10. " OIS2 ,Output idle state 2 (OC2 output)" "0,1"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,?..."
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CC,Update"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "By COMG,By COMG/Rising"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preload control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM15_CR2,Control Register 2"
|
|
rbitfld.word 0x00 10. " OIS2 ,Output idle state 2 (OC2 output)" "0,1"
|
|
rbitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
rbitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,?..."
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CC,Update"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "By COMG,By COMG/Rising"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preload control" "Not preloaded,Preloaded"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "TIM15_SMCR,Slave Mode Control Register"
|
|
bitfld.word 0x00 7. " MSM ,Master/Slave mode" "No action,Delayed"
|
|
textline " "
|
|
sif (CPU()=="STM32F100RC"||CPU()=="STM32F100RD"||CPU()=="STM32F100RE"||CPU()=="STM32F100VC"||CPU()=="STM32F100VD"||CPU()=="STM32F100VE"||CPU()=="STM32F100ZC"||CPU()=="STM32F100ZD"||CPU()=="STM32F100ZE"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||(cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8")&&!CPUIS("STM32F058T8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F091?C"))||(cpuis("STM32F098?C"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,TI2FP2"
|
|
textline " "
|
|
elif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
elif CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB")
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" ",ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" ",,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External clock"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM15_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM15_SR,Status Register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM15_EGR,Event Generation Register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Generate"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enabled"
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No action,Update"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
if (((per.w((ad:0x40014000+0x18)))&0x303)==0x00)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x300)==0x00)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
width 12.
|
|
if (((per.l(ad:0x40014000+0x20))&0x03)==0x00)
|
|
if (((per.l(ad:0x40014000+0x20))&0x300)==0x00)
|
|
if (((per.l(ad:0x40014000+0x44))&0x300)==(0x200||0x300))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x44))&0x300)==(0x200||0x300))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x20))&0x300)==0x00)
|
|
if (((per.l(ad:0x40014000+0x44))&0x300)==(0x200||0x300))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x44))&0x300)==(0x200||0x300))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM15_CNT,Counter"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM15_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM15_ARR,Auto-reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM15_RCR,Repetition Counter Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM15_CCR1,Capture/Compare Register 1"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "TIM15_CCR2,Capture/Compare Register 2"
|
|
if (((per.w(ad:0x40014000+0x044))&0x300)==0x300)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM15_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014000+0x044))&0x300)==0x200)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM15_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014000+0x044))&0x300)==0x100)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM15_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM15_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM15_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM15_CR1,TIM15_CR2,TIM15_SMCR,TIM15_DIER,TIM15_SR,TIM15_EGR,TIM15_CCMR1,,TIM15_CCER,TIM15_CNT,TIM15_PSC,TIM15_ARR,TIM15_RCR,TIM15_CCR1,TIM15_CCR2,,,TIM15_BDTR,TIM15_DCR,TIM15_DMAR,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM15_DMAR,DMA Address for Burst Mode"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 16"
|
|
base ad:0x40014400
|
|
width 13.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM16_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)||(((per.w(ad:0x40014400+0x044))&0x300)==0x200)||(((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM16_CR2,Control Register 2"
|
|
rbitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
rbitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM16_CR2,Control Register 2"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM16_DIER,DMA/Interrupt Enable Register"
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&(!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE"))
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM16_SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 over-capture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM16_EGR,Event Generation Register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Generate"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No update,Update"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((((per.w(ad:0x40014400+0x044))&0x300)==0x300)||(((per.w(ad:0x40014400+0x044))&0x300)==0x200))
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.w(ad:0x40014400)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if ((per.w(ad:0x40014400)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM16_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM16_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM16_ARR,Auto-Reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM16_RCR,Repetition Counter Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM16_CCR1,Capture/Compare Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x200)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x200)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM16_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM16_CR1,TIM16_CR2,,TIM16_DIER,TIM16_SR,TIM16_EGR,TIM16_CMR1,,TIM16_CCER,TIM16_CNT,TIM16_PSC,TIM16_ARR,TIM16_RCR,TIM16_CCR1,,,,TIM16_BDTR,TIM16_DCR,TIM16_DMAR,TIM16_OR,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM16_CR1,TIM16_CR2,,TIM16_DIER,TIM16_SR,TIM16_EGR,TIM16_CMR1,,TIM16_CCER,TIM16_CNT,TIM16_PSC,TIM16_ARR,TIM16_RCR,TIM16_CCR1,,,,TIM16_BDTR,TIM16_DCR,TIM16_DMAR,?..."
|
|
endif
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM16_DMAR,DMA Address for Full Transfer"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TIM16_OR,TIM16 Option Register"
|
|
bitfld.long 0x00 0.--1. " TI1_RMP ,Timer 16 input 1 connection" "GPIO,RTC_clock,HSE/32,MCO"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 17"
|
|
base ad:0x40014800
|
|
width 13.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM17_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)||(((per.w(ad:0x40014800+0x044))&0x300)==0x200)||(((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM17_CR2,Control Register 2"
|
|
rbitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
rbitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM17_CR2,Control Register 2"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM17_DIER,DMA/Interrupt Enable Register"
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&(!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE"))
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM17_SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 over-capture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM17_EGR,Event Generation Register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Generate"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No update,Update"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((((per.w(ad:0x40014800+0x044))&0x300)==0x300)||(((per.w(ad:0x40014800+0x044))&0x300)==0x200))
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.w(ad:0x40014800)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if ((per.w(ad:0x40014800)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM17_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM17_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM17_ARR,Auto-Reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM17_RCR,Repetition Counter Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM17_CCR1,Capture/Compare Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x200)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x200)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM17_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM17_CR1,TIM17_CR2,,TIM17_DIER,TIM17_SR,TIM17_EGR,TIM17_CMR1,,TIM17_CCER,TIM17_CNT,TIM17_PSC,TIM17_ARR,TIM17_RCR,TIM17_CCR1,,,,TIM17_BDTR,TIM17_DCR,TIM17_DMAR,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM17_CR1,TIM17_CR2,,TIM17_DIER,TIM17_SR,TIM17_EGR,TIM17_CMR1,,TIM17_CCER,TIM17_CNT,TIM17_PSC,TIM17_ARR,TIM17_RCR,TIM17_CCR1,,,,TIM17_BDTR,TIM17_DCR,TIM17_DMAR,?..."
|
|
endif
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM17_DMAR,DMA Address for Full Transfer"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32F103*C")||cpuis("STM32F103*D")||cpuis("STM32F103*E")||cpuis("STM32F103*F")||cpuis("STM32F103*G")||cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpuis("STM32F100C*")||cpuis("STM32F100R*")||cpuis("STM32F100V*")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
tree.open "Basic Timer"
|
|
tree "TIM 6"
|
|
base ad:0x40001000
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM6_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM6_CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM6_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM6_SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM6_EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.l(ad:0x40001000)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM6_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM6_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM6_ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM 7"
|
|
base ad:0x40001400
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM7_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM7_CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM7_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM7_SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM7_EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.l(ad:0x40001400)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM7_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM7_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM7_ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40002800
|
|
width 10.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "RTC_CRH,RTC control register High"
|
|
bitfld.long 0x00 2. " OWIE ,OverfloW Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALRIE ,Alarm Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SECIE ,Second Interrupt Enable" "Masked,Enabled"
|
|
line.long 0x04 "RTC_CRL,RTC control register low"
|
|
bitfld.long 0x04 5. " RTOFF ,RTC operation OFF" "Running,Terminated"
|
|
bitfld.long 0x04 4. " CNF ,Configuration Flag" "Exit,Enter"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSF ,Registers Synchronized Flag" "Not synchronized,Synchronized"
|
|
bitfld.long 0x04 2. " OWF ,OverfloW Flag" "Not detected,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ALRF ,Alarm Flag" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " SECF ,Second Flag" "Not occurred,Occurred"
|
|
wgroup.long 0x08++0x7
|
|
line.long 0x00 "RTC_PRLH,RTC prescaler load register high"
|
|
bitfld.long 0x00 0.--3. " PRL ,RTC Prescaler Reload Value High" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "RTC_PRLL,RTC prescaler load register low"
|
|
hexmask.long.word 0x04 0.--15. 1. " PRL ,RTC Prescaler Reload Value Low"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x00 "RTC_DIVH,RTC prescaler divider register high"
|
|
bitfld.long 0x00 0.--3. " RTC_DIV ,RTC Clock Divider High" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "RTC_DIVL,RTC prescaler divider register low"
|
|
hexmask.long.word 0x04 0.--15. 1. " RTC_DIV ,RTC Clock Divider Low"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "RTC_CNTH,RTC counter register high"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTC_CNT ,RTC Counter High"
|
|
line.long 0x04 "RTC_CNTL,RTC counter register low"
|
|
hexmask.long.word 0x04 0.--15. 1. " RTC_CNT ,RTC Counter low"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x00 "RTC_ALRH,RTC alarm register high"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTC_ALR ,RTC Alarm High"
|
|
line.long 0x04 "RTC_ALRL,RTC alarm register low"
|
|
hexmask.long.word 0x04 0.--15. 1. " RTC_ALR ,RTC Alarm low"
|
|
width 0xB
|
|
tree.end
|
|
tree "IWDG (Independent Watchdog)"
|
|
base ad:0x40003000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "IWDG_KR,Key Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " KEY ,Key value"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "IWDG_PR,Prescaler Register"
|
|
bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256"
|
|
line.long 0x04 "IWDG_RLR,Reload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " RL ,Watchdog counter reload value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "IWDG_SR,Status Register"
|
|
sif ((cpu()=="STM32F050C4")||(cpu()=="STM32F050C6")||(cpu()=="STM32F050K4")||(cpu()=="STM32F050K6")||(cpu()=="STM32F051C4")||(cpu()=="STM32F051C6")||(cpu()=="STM32F051C8")||(cpu()=="STM32F051K4")||(cpu()=="STM32F051K6")||(cpu()=="STM32F051K8")||(cpu()=="STM32F051R4")||(cpu()=="STM32F051R6")||(cpu()=="STM32F051R8")||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))
|
|
bitfld.long 0x00 2. " WVU ,Watchdog counter window value update" "Completed,Running"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " RVU ,Watchdog counter reload value update" "Completed,Running"
|
|
bitfld.long 0x00 0. " PVU ,Watchdog prescaler value update" "Completed,Running"
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IWDG_WINR,Window Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " WIN ,Watchdog counter window value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "WWDG (Window Watchdog)"
|
|
base ad:0x40002C00
|
|
width 10.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "WWDG_CR,Control Register"
|
|
bitfld.long 0x00 7. " WDGA ,Activation bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " T ,7-bit counter"
|
|
line.long 0x04 "WWDG_CFR,Configuration Register"
|
|
bitfld.long 0x04 9. " EWI ,Early wakeup interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7.--8. " WDGTB ,Timer base" "Div by 1,Div by 2,Div by 4,Div by 8"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " W ,7-bit window value"
|
|
line.long 0x08 "WWDG_SR,Status Register"
|
|
bitfld.long 0x08 0. " EWIF ,Early wakeup interrupt flag" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32F103Z*")||cpu()=="STM32F103VG"||cpu()=="STM32F103VF"||cpu()=="STM32F103VE"||cpu()=="STM32F103VD"||cpu()=="STM32F103VC"||cpuis("STM32F101Z*")||cpu()=="STM32F101VG"||cpu()=="STM32F101VF"||cpu()=="STM32F101VE"||cpu()=="STM32F101VD"||cpu()=="STM32F101VC"||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
tree "FSMC (Flexible Static Memory Controller)"
|
|
base ad:0xA0000000
|
|
width 12.
|
|
tree "NOR/PSRAM Controller Registers"
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "FSMC_BCR1,SRAM/NOR-Flash Chip-select Control Register 1"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 21. " WFDIS ,Write FIFO disable" "No,Yes"
|
|
bitfld.long 0x00 20. " CCLKEN ,Continuous clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textfld " "
|
|
else
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM(CRAM),NOR/OneNAND,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM/ROM,PSRAM,NOR,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
group.long (0x0+0x4)++0x3
|
|
line.long 0x00 "FSMC_BTR1,SRAM/NOR-Flash Chip-select Timing Register 1"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" "HCLK,HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
else
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x0+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR1,SRAM/NOR-Flash Write Timing Register 1"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
textline " "
|
|
sif (!cpuis("STM32F4*"))
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "FSMC_BCR2,SRAM/NOR-Flash Chip-select Control Register 2"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textfld " "
|
|
else
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM(CRAM),NOR/OneNAND,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM/ROM,PSRAM,NOR,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
group.long (0x8+0x4)++0x3
|
|
line.long 0x00 "FSMC_BTR2,SRAM/NOR-Flash Chip-select Timing Register 2"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" "HCLK,HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
else
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x8+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR2,SRAM/NOR-Flash Write Timing Register 2"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
textline " "
|
|
sif (!cpuis("STM32F4*"))
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "FSMC_BCR3,SRAM/NOR-Flash Chip-select Control Register 3"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textfld " "
|
|
else
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM(CRAM),NOR/OneNAND,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM/ROM,PSRAM,NOR,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
group.long (0x10+0x4)++0x3
|
|
line.long 0x00 "FSMC_BTR3,SRAM/NOR-Flash Chip-select Timing Register 3"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" "HCLK,HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
else
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x10+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR3,SRAM/NOR-Flash Write Timing Register 3"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
textline " "
|
|
sif (!cpuis("STM32F4*"))
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "FSMC_BCR4,SRAM/NOR-Flash Chip-select Control Register 4"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 16.--18. " CPSIZE ,CRAM page size" "No burst,128 bytes,256 bytes,512 bytes,1024 bytes,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textfld " "
|
|
else
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM(CRAM),NOR/OneNAND,?..."
|
|
else
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM/ROM,PSRAM,NOR,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
group.long (0x18+0x4)++0x3
|
|
line.long 0x00 "FSMC_BTR4,SRAM/NOR-Flash Chip-select Timing Register 4"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" "HCLK,HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
else
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x18+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR4,SRAM/NOR-Flash Write Timing Register 4"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
textline " "
|
|
sif (!cpuis("STM32F4*"))
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE")||cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
sif ((!cpuis("STM32F4*"))&&(!cpuis("STM32F2*")))
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15,HCLK*16"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
tree.end
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE")&&!cpuis("STM32L15?R?")&&!cpuis("STM32L15?V?")&&!cpuis("STM32L15?Z?")&&!cpuis("STM32L15?Q?")&&!cpuis("STM32L15?C6")&&!cpuis("STM32L162?D")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
tree "NAND Flash/PC Card Controller Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "FSMC_PCR2,PC Card/NAND Flash Control Registers 2"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBKEN ,PC Card/NAND Flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
group.long (0x60+0x4)++0x03
|
|
line.long 0x00 "FSMC_SR2,FIFO Status and Interrupt Register 2"
|
|
rbitfld.long 0x00 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
group.long (0x60+0x8)++0x03
|
|
line.long 0x00 "FSMC_PMEM2,Common Memory Space Timing Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMHIZ2 ,Common memory 2 data bus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MEMHOLD2 ,Common memory 2 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MEMWAIT2 ,Common memory 2 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MEMSET2 ,Common memory 2 setup time"
|
|
group.long (0x60+0xC)++0x03
|
|
line.long 0x00 "FSMC_PATT2,Attribute Memory Space Timing Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTHIZ2 ,Attribute memory 2 databus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTHOLD2 ,Attribute memory 2 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTWAIT2 ,Attribute memory 2 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTSET2 ,Attribute memory 2 setup time"
|
|
if (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x00)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x20000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x40000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--25. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x60000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--27. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0x80000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--29. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x60)))&0xE0000)==0xA0000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
else
|
|
hgroup.long (0x60+0x14)++0x3
|
|
hide.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FSMC_PCR3,PC Card/NAND Flash Control Registers 3"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBKEN ,PC Card/NAND Flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
group.long (0x80+0x4)++0x03
|
|
line.long 0x00 "FSMC_SR3,FIFO Status and Interrupt Register 3"
|
|
rbitfld.long 0x00 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
group.long (0x80+0x8)++0x03
|
|
line.long 0x00 "FSMC_PMEM3,Common Memory Space Timing Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMHIZ3 ,Common memory 3 data bus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MEMHOLD3 ,Common memory 3 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MEMWAIT3 ,Common memory 3 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MEMSET3 ,Common memory 3 setup time"
|
|
group.long (0x80+0xC)++0x03
|
|
line.long 0x00 "FSMC_PATT3,Attribute Memory Space Timing Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTHIZ3 ,Attribute memory 3 databus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTHOLD3 ,Attribute memory 3 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTWAIT3 ,Attribute memory 3 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTSET3 ,Attribute memory 3 setup time"
|
|
if (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x00)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x20000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x40000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--25. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x60000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--27. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0x80000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--29. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000000+0x80)))&0xE0000)==0xA0000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
else
|
|
hgroup.long (0x80+0x14)++0x3
|
|
hide.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "FSMC_PCR4,PC Card/NAND Flash Control Registers 4"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBKEN ,PC Card/NAND Flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
group.long (0xA0+0x4)++0x03
|
|
line.long 0x00 "FSMC_SR4,FIFO Status and Interrupt Register 4"
|
|
rbitfld.long 0x00 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
group.long (0xA0+0x8)++0x03
|
|
line.long 0x00 "FSMC_PMEM4,Common Memory Space Timing Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMHIZ4 ,Common memory 4 data bus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MEMHOLD4 ,Common memory 4 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MEMWAIT4 ,Common memory 4 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MEMSET4 ,Common memory 4 setup time"
|
|
group.long (0xA0+0xC)++0x03
|
|
line.long 0x00 "FSMC_PATT4,Attribute Memory Space Timing Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTHIZ4 ,Attribute memory 4 databus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTHOLD4 ,Attribute memory 4 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTWAIT4 ,Attribute memory 4 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTSET4 ,Attribute memory 4 setup time"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "FSMC_PIO4,I/O Space Timing Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IOHIZ4 ,I/O 4 databus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IOHOLD4 ,I/O 4 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " IOWAIT4 ,I/O 4 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSET4 ,I/O 4 setup time"
|
|
tree.end
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F103*G")||cpuis("STM32F103*F")||cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpu()=="STM32F103")
|
|
tree "SDIO (SDIO Interface)"
|
|
base ad:0x40018000
|
|
width 14.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "SDIO_POWER,SDIO Power Control Register"
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,Power supply control bits" "Power-off,,Power-up,Power-on"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " PWRCTRL ,Power supply control bits" "Off,,,On"
|
|
textline " "
|
|
endif
|
|
line.long 0x04 "SDIO_CLKCR,SDI Clock Control Register"
|
|
bitfld.long 0x04 14. " HWFC_EN ,HW Flow Control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " NEGEDGE ,SDIO_CK dephasing selection bit" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x04 11.--12. " WIDBUS ,Wide bus mode enable bit" "SDIO_D0,SDIO_D[3:0],SDIO_D[7:0],?..."
|
|
bitfld.long 0x04 10. " BYPASS ,Clock divider bypass enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PWRSAV ,Power saving configuration bit" "Always enabled,Enabled/bus active"
|
|
bitfld.long 0x04 8. " CLKEN ,Clock enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " CLKDIV ,Clock divide factor"
|
|
line.long 0x08 "SDIO_ARG,SDIO Argument Register"
|
|
line.long 0x0C "SDIO_CMD,SDIO Command Register"
|
|
sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x0C 14. " ATACMD ,CE-ATA command" "No transfer,CPSM transfers CMD61"
|
|
bitfld.long 0x0C 13. " NIEN ,not Interrupt Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " ENCMDCOMP1 ,Enable CMD completion" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 11. " SDIOSUSPEND ,SD I/O suspend command" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CPSMEN ,Command path state machine (CPSM) Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " WAITPEND ,CPSM Waits for ends of data transfer (CmdPend internal signal)" "No wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " WAITINT ,CPSM Waits for Interrupt Request" "Not requested,Requested"
|
|
bitfld.long 0x0C 6.--7. " WAITRESP ,Wait for response bits" "No response,Short response,No response,Long response"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--5. " CMDINDEX ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "SDIO_RESPCMD,SDIO Command Response Register"
|
|
bitfld.long 0x00 0.--5. " RESPCMD ,Response command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if ((per.l((ad:0x40018000+0x0C))&0xC0)==0x40)
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "SDIO_RESP1,SDIO Response 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CARDSTATUS1 ,Card Status[31:0]"
|
|
hgroup.long 0x18++0x0B
|
|
hide.long 0x00 "SDIO_RESP2,SDIO Response 2 Register"
|
|
hide.long 0x04 "SDIO_RESP3,SDIO Response 3 Register"
|
|
hide.long 0x08 "SDIO_RESP4,SDIO Response 4 Register"
|
|
elif ((per.l((ad:0x40018000+0x0C))&0xC0)==0xC0)
|
|
rgroup.long 0x14++0xF
|
|
line.long 0x00 "SDIO_RESP1,SDIO Response 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " CARDSTATUS1 ,Card Status [127:96]"
|
|
line.long 0x04 "SDIO_RESP2,SDIO Response 2 Register"
|
|
hexmask.long 0x04 0.--31. 1. " CARDSTATUS2 ,Card Status [95:64]"
|
|
line.long 0x08 "SDIO_RESP3,SDIO Response 3 Register"
|
|
hexmask.long 0x08 0.--31. 1. " CARDSTATUS3 ,Card Status [63:32]"
|
|
line.long 0x0C "SDIO_RESP4,SDIO Response 4 Register"
|
|
hexmask.long 0x0C 0.--31. 1. " CARDSTATUS3 ,Card Status [31:0]"
|
|
else
|
|
hgroup.long 0x14++0xF
|
|
hide.long 0x00 "SDIO_RESP1,SDIO Response 1 Register"
|
|
hide.long 0x04 "SDIO_RESP2,SDIO Response 2 Register"
|
|
hide.long 0x08 "SDIO_RESP3,SDIO Response 3 Register"
|
|
hide.long 0x0C "SDIO_RESP4,SDIO Response 4 Register"
|
|
endif
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "SDIO_DTIMER,SDIO Data Timer Register"
|
|
line.long 0x04 "SDIO_DLEN,SDIO Data Length Register"
|
|
hexmask.long 0x04 0.--24. 1. " DATALENGTH ,Data length value"
|
|
line.long 0x08 "SDIO_DCTRL,SDIO Data Control Register"
|
|
bitfld.long 0x08 11. " SDIOEN ,SD I/O enable functions" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " RWMOD ,Read wait mode" "Stopping SDIO_D2,Using SDIO_CK"
|
|
textline " "
|
|
bitfld.long 0x08 9. " RWSTOP ,Read wait stop" "Not stopped,Stopped"
|
|
bitfld.long 0x08 8. " RWSTART ,Read wait start" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " DBLOCKSIZE ,Data block size" "1 byte,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,16384 bytes,?..."
|
|
bitfld.long 0x08 3. " DMAEN ,DMA enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DTMODE ,Data transfer mode selection" "Block,Stream"
|
|
bitfld.long 0x08 1. " DTDIR ,Data transfer direction selection" "Controller to card,Card to controller"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DTEN ,Data transfer enabled bit" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "SDIO_DCOUNT,SDIO Data Counter Register"
|
|
hexmask.long 0x00 0.--24. 1. " DATACOUNT ,Data count value"
|
|
line.long 0x04 "SDIO_STA,SDIO Status Register"
|
|
sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 23. " CEATAEND ,CE-ATA command completion signal received for CMD61" "Not completed,Completed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 22. " SDIOIT ,SDIO interrupt received" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 21. " RXDAVL ,Data available in receive FIFO" "Not available,Available"
|
|
bitfld.long 0x04 20. " TXDAVL ,Data available in transmit FIFO" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RXFIFOE ,Receive FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x04 18. " TXFIFOE ,Transmit FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 17. " RXFIFOF ,Receive FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 16. " TXFIFOF ,Transmit FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x04 15. " RXFIFOHF ,Receive FIFO Half Full: there are at least 8 words in the FIFO" "Not half full,Half full"
|
|
bitfld.long 0x04 14. " TXFIFOHE ,Transmit FIFO Half Empty: at least 8 words can be written into the FIFO" "Not half empty,Half empty"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RXACT ,Data receive in progress" "Not in progress,In progress"
|
|
bitfld.long 0x04 12. " TXACT ,Data transmit in progress" "Not in progress,In progress"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CMDACT ,Command transfer in progress" "Not in progress,In progress"
|
|
bitfld.long 0x04 10. " DBCKEND ,Data block sent/received" "Not sent/received,Sent/Received"
|
|
textline " "
|
|
sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
bitfld.long 0x04 9. " STBITERR ,Start bit not detected on all data signals in wide bus mode" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " DATAEND ,Data end" "No end,End"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CMDSENT ,Command sent" "Not sent,Sent"
|
|
bitfld.long 0x04 6. " CMDREND ,Command response received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXOVERR ,Received FIFO overrun error" "No overrun,Overrun"
|
|
bitfld.long 0x04 4. " TXUNDERR ,Transmit FIFO underrun error" "No underrun,Underrun"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DTIMEOUT ,Data timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 2. " CTIMEOUT ,Command response timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DCRCFAIL ,Data block sent/received" "Not sent/received,Sent/received"
|
|
bitfld.long 0x04 0. " CCRCFAIL ,Command response received" "Not received,Received"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "SDIO_ICR,SDIO Interrupt Clear Register"
|
|
sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x00 23. " CEATAENDC ,CEATAEND Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " SDIOITC ,SDIOIT Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 10. " DBCKENDC ,DBCKEND Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
bitfld.long 0x00 9. " STBITERRC ,STBITERR Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " DATAENDC ,DATAEND Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 7. " CMDSENTC ,CMDSENT Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CMDRENDC ,CMDREND Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 5. " RXOVERRC ,RXOVERR Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 4. " TXUNDERRC ,TXUNDERR Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DTIMEOUTC ,DTIMEOUT Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CTIMEOUTC ,CTIMEOUT Flag Clear Bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " DCRCFAILC ,DCRCFAIL Flag Clear Bit" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCRCFAILC ,CCRCFAIL Flag Clear Bit" "Not cleared,Cleared"
|
|
line.long 0x04 "SDIO_MASK,SDIO Mask Register"
|
|
sif (!cpuis("STM32F446*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 23. " CEATAENDIE ,CE-ATA command completion signal received Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 22. " SDIOITIE ,SDIO Mode Interrupt Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " RXDAVLIE ,Data available in Rx FIFO Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TXDAVLIE ,Data available in Tx FIFO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " RXFIFOEIE ,Rx FIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " TXFIFOEIE ,Tx FIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " RXFIFOFIE ,Rx FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " TXFIFOFIE ,Tx FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " RXFIFOHFIE ,Rx FIFO Half Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " TXFIFOHEIE ,Tx FIFO Half Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " RXACTIE ,Data Receive Acting Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " TXACTIE ,Data Transmit Acting Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CMDACTIE ,Command Acting Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DBCKENDIE ,Data Block End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
bitfld.long 0x04 9. " STBITERRIE ,Start Bit Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " DATAENDIE ,Data End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " CMDSENTIE ,Command Sent Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CMDRENDIE ,Command Response Received Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RXOVERRIE ,Rx FIFO OverRun Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TXUNDERRIE ,Tx FIFO UnderRun Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " DTIMEOUTIE ,Data TimeOut Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " CTIMEOUTIE ,Command TimeOut Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DCRCFAILIE ,Data CRC Fail Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CCRCFAILIE ,Command CRC Fail Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "SDIO_FIFOCNT,SDIO FIFO Counter Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " FIFOCOUNT ,Remaining number of words to be written to or read from the FIFO"
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "SDIO_FIFO0,SDIO Data FIFO Register 0"
|
|
in
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "SDIO_FIFO1,SDIO Data FIFO Register 1"
|
|
in
|
|
hgroup.long 0x88++0x03
|
|
hide.long 0x00 "SDIO_FIFO2,SDIO Data FIFO Register 2"
|
|
in
|
|
hgroup.long 0x8C++0x03
|
|
hide.long 0x00 "SDIO_FIFO3,SDIO Data FIFO Register 3"
|
|
in
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "SDIO_FIFO4,SDIO Data FIFO Register 4"
|
|
in
|
|
hgroup.long 0x94++0x03
|
|
hide.long 0x00 "SDIO_FIFO5,SDIO Data FIFO Register 5"
|
|
in
|
|
hgroup.long 0x98++0x03
|
|
hide.long 0x00 "SDIO_FIFO6,SDIO Data FIFO Register 6"
|
|
in
|
|
hgroup.long 0x9C++0x03
|
|
hide.long 0x00 "SDIO_FIFO7,SDIO Data FIFO Register 7"
|
|
in
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "SDIO_FIFO8,SDIO Data FIFO Register 8"
|
|
in
|
|
hgroup.long 0xA4++0x03
|
|
hide.long 0x00 "SDIO_FIFO9,SDIO Data FIFO Register 9"
|
|
in
|
|
hgroup.long 0xA8++0x03
|
|
hide.long 0x00 "SDIO_FIFO10,SDIO Data FIFO Register 10"
|
|
in
|
|
hgroup.long 0xAC++0x03
|
|
hide.long 0x00 "SDIO_FIFO11,SDIO Data FIFO Register 11"
|
|
in
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "SDIO_FIFO12,SDIO Data FIFO Register 12"
|
|
in
|
|
hgroup.long 0xB4++0x03
|
|
hide.long 0x00 "SDIO_FIFO13,SDIO Data FIFO Register 13"
|
|
in
|
|
hgroup.long 0xB8++0x03
|
|
hide.long 0x00 "SDIO_FIFO14,SDIO Data FIFO Register 14"
|
|
in
|
|
hgroup.long 0xBC++0x03
|
|
hide.long 0x00 "SDIO_FIFO15,SDIO Data FIFO Register 15"
|
|
in
|
|
hgroup.long 0xC0++0x03
|
|
hide.long 0x00 "SDIO_FIFO16,SDIO Data FIFO Register 16"
|
|
in
|
|
hgroup.long 0xC4++0x03
|
|
hide.long 0x00 "SDIO_FIFO17,SDIO Data FIFO Register 17"
|
|
in
|
|
hgroup.long 0xC8++0x03
|
|
hide.long 0x00 "SDIO_FIFO18,SDIO Data FIFO Register 18"
|
|
in
|
|
hgroup.long 0xCC++0x03
|
|
hide.long 0x00 "SDIO_FIFO19,SDIO Data FIFO Register 19"
|
|
in
|
|
hgroup.long 0xD0++0x03
|
|
hide.long 0x00 "SDIO_FIFO20,SDIO Data FIFO Register 20"
|
|
in
|
|
hgroup.long 0xD4++0x03
|
|
hide.long 0x00 "SDIO_FIFO21,SDIO Data FIFO Register 21"
|
|
in
|
|
hgroup.long 0xD8++0x03
|
|
hide.long 0x00 "SDIO_FIFO22,SDIO Data FIFO Register 22"
|
|
in
|
|
hgroup.long 0xDC++0x03
|
|
hide.long 0x00 "SDIO_FIFO23,SDIO Data FIFO Register 23"
|
|
in
|
|
hgroup.long 0xE0++0x03
|
|
hide.long 0x00 "SDIO_FIFO24,SDIO Data FIFO Register 24"
|
|
in
|
|
hgroup.long 0xE4++0x03
|
|
hide.long 0x00 "SDIO_FIFO25,SDIO Data FIFO Register 25"
|
|
in
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "SDIO_FIFO26,SDIO Data FIFO Register 26"
|
|
in
|
|
hgroup.long 0xEC++0x03
|
|
hide.long 0x00 "SDIO_FIFO27,SDIO Data FIFO Register 27"
|
|
in
|
|
hgroup.long 0xF0++0x03
|
|
hide.long 0x00 "SDIO_FIFO28,SDIO Data FIFO Register 28"
|
|
in
|
|
hgroup.long 0xF4++0x03
|
|
hide.long 0x00 "SDIO_FIFO29,SDIO Data FIFO Register 29"
|
|
in
|
|
hgroup.long 0xF8++0x03
|
|
hide.long 0x00 "SDIO_FIFO30,SDIO Data FIFO Register 30"
|
|
in
|
|
hgroup.long 0xFC++0x03
|
|
hide.long 0x00 "SDIO_FIFO31,SDIO Data FIFO Register 31"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F103*")||cpuis("STM32F102*"))
|
|
tree "USB (USB Full Speed Device)"
|
|
base ad:0x40005C00
|
|
width 12.
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "USB_CNTR,USB control register"
|
|
bitfld.long 0x00 15. " CTRM ,Correct Transfer Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PMAOVRM ,Packet Memory Area Over / Underrun Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERRM ,Error Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WKUPM ,Wake-up Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SUSPM ,Suspend mode Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RESETM ,USB Reset Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SOFM ,Start Of Frame Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ESOFM ,Expected Start Of Frame Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RESUME ,Resume request" "No effect,Resume"
|
|
bitfld.long 0x00 3. " FSUSP ,Force suspend" "No effect,Enter"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LP_MODE ,Low-power mode" "No Low-power,Enter"
|
|
bitfld.long 0x00 1. " PDWN ,Power down" "Exit,Enter"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FRES ,Force USB Reset" "Clear,Reset"
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
line.long 0x04 "USB_ISTR,USB interrupt status register"
|
|
rbitfld.long 0x04 15. " CTR ,Correct Transfer" "No effect,Correct"
|
|
bitfld.long 0x04 14. " PMAOVR ,Packet Memory Area Over / Underrun" "No Over/Underrun,Over/Underrun"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ERR ,Error" "No error,Error"
|
|
bitfld.long 0x04 12. " WKUP ,Wake up" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SUSP ,Suspend mode request" "Normal,Suspend"
|
|
bitfld.long 0x04 10. " RESET ,USB RESET request" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SOF ,Start Of Frame" "No effect,Packet arrives"
|
|
bitfld.long 0x04 8. " ESOF ,Expected Start Of Frame" "No effect,Packet expected"
|
|
textline " "
|
|
rbitfld.long 0x04 4. " DIR ,Direction of transaction" "IN,OUT"
|
|
rbitfld.long 0x04 0.--3. " EP_ID ,Endpoint Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
line.long 0x04 "USB_ISTR,USB interrupt status register"
|
|
bitfld.long 0x04 15. " CTR ,Correct Transfer" "No effect,Correct"
|
|
bitfld.long 0x04 14. " PMAOVR ,Packet Memory Area Over / Underrun" "No Over/Underrun,Over/Underrun"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ERR ,Error" "No error,Error"
|
|
bitfld.long 0x04 12. " WKUP ,Wake up" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SUSP ,Suspend mode request" "Normal,Suspend"
|
|
bitfld.long 0x04 10. " RESET ,USB RESET request" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SOF ,Start Of Frame" "No effect,Packet arrives"
|
|
bitfld.long 0x04 8. " ESOF ,Expected Start Of Frame" "No effect,Packet expected"
|
|
textline " "
|
|
bitfld.long 0x04 4. " DIR ,Direction of transaction" "IN,OUT"
|
|
bitfld.long 0x04 0.--3. " EP_ID ,Endpoint Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.long 0x48++0x13
|
|
line.long 0x00 "USB_FNR,USB frame number register"
|
|
bitfld.long 0x00 15. " RXDP ,Receive Data + Line Status" "No data,Data"
|
|
bitfld.long 0x00 14. " RXDM ,Receive Data - Line Status" "No data,Data"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK ,Locked" "Unlocked,Locked"
|
|
bitfld.long 0x00 11.--12. " LSOF ,Lost SOF" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " FN ,Frame Number"
|
|
group.long 0x4C++0x7
|
|
line.long 0x00 "USB_DADDR,USB device address"
|
|
bitfld.long 0x00 7. " EF ,Enable Function" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ADD ,Device Address"
|
|
line.long 0x04 "USB_BTABLE,Buffer table address"
|
|
hexmask.long.word 0x04 3.--15. 0x8 " BTABLE ,Buffer Table"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "USB_EP0R,USB endpoint 0 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "USB_EP1R,USB endpoint 1 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "USB_EP2R,USB endpoint 2 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "USB_EP3R,USB endpoint 3 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USB_EP4R,USB endpoint 4 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USB_EP5R,USB endpoint 5 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "USB_EP6R,USB endpoint 6 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "USB_EP7R,USB endpoint 7 register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct Transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data Toggle, for reception transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits, for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint Kind" "DBL_BUF,STATUS_OUT"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct Transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data Toggle, for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits, for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 14.
|
|
base ad:((per.l((ad:0x40005C00+0x50))&0xFFF8))+ad:0x40005C00
|
|
tree "Buffer descriptor table"
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")
|
|
if ((per.l((ad:0x40005C00)+0x0)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x0)&0x300)==0x000)
|
|
group.long 0x0++0x0F
|
|
line.long 0x00 "USB_ADDR0_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT0_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR0_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT0_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x0++0x0F
|
|
line.long 0x00 "USB_ADDR0_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT0_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR0_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT0_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x4)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x4)&0x300)==0x000)
|
|
group.long 0x4++0x0F
|
|
line.long 0x00 "USB_ADDR1_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT1_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR1_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT1_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x4++0x0F
|
|
line.long 0x00 "USB_ADDR1_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT1_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR1_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT1_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x8)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x8)&0x300)==0x000)
|
|
group.long 0x8++0x0F
|
|
line.long 0x00 "USB_ADDR2_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT2_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR2_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT2_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x8++0x0F
|
|
line.long 0x00 "USB_ADDR2_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT2_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR2_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT2_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0xC)&0x600)==0x400)||((per.l((ad:0x40005C00)+0xC)&0x300)==0x000)
|
|
group.long 0xC++0x0F
|
|
line.long 0x00 "USB_ADDR3_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT3_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR3_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT3_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0xC++0x0F
|
|
line.long 0x00 "USB_ADDR3_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT3_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR3_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT3_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x10)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x10)&0x300)==0x000)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "USB_ADDR4_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT4_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR4_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT4_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "USB_ADDR4_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT4_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR4_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT4_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x14)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x14)&0x300)==0x000)
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "USB_ADDR5_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT5_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR5_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT5_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "USB_ADDR5_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT5_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR5_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT5_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x18)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x18)&0x300)==0x000)
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "USB_ADDR6_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT6_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR6_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT6_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x18++0x0F
|
|
line.long 0x00 "USB_ADDR6_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT6_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR6_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT6_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
if ((per.l((ad:0x40005C00)+0x1C)&0x600)==0x400)||((per.l((ad:0x40005C00)+0x1C)&0x300)==0x000)
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "USB_ADDR7_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT7_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX_1 ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX_0 ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR7_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT7_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_1 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_1 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX_1 ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX_0 ,Reception Byte Count"
|
|
else
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "USB_ADDR7_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
line.long 0x04 "USB_COUNT7_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
line.long 0x08 "USB_ADDR7_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
line.long 0x0C "USB_COUNT7_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "USB_ADDR_TX,Transmission buffer address"
|
|
hexmask.long.word 0x00 1.--15. 0x2 " ADDR_TX ,Transmission Buffer Address"
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")||cpuis("STM32F103TB"))
|
|
line.long 0x04 "USB_COUNT_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
else
|
|
line.long 0x04 "USB_COUNT_TX,Transmission byte count"
|
|
hexmask.long.word 0x04 16.--25. 1. " COUNT_TX ,Transmission Byte Count"
|
|
hexmask.long.word 0x04 0.--9. 1. " COUNT_TX ,Transmission Byte Count"
|
|
endif
|
|
line.long 0x08 "USB_ADDR_RX,Reception buffer address"
|
|
hexmask.long.word 0x08 1.--15. 0x2 " ADDR_RX ,Reception Buffer Address"
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")||cpuis("STM32F103TB"))
|
|
line.long 0x0C "USB_COUNT_RX,Reception byte count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
else
|
|
line.long 0x0C "USB_COUNT_RX,Reception byte count"
|
|
bitfld.long 0x0C 31. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
hexmask.long.byte 0x0C 26.--30. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
textline " "
|
|
hexmask.long.word 0x0C 16.--25. 1. " COUNT_RX ,Reception Byte Count"
|
|
bitfld.long 0x0C 15. " BL_SIZE_0 ,BLock SIZE" "2 byte,32 byte"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 10.--14. 1. " NUM_BLOCK_0 ,Number of blocks"
|
|
hexmask.long.word 0x0C 0.--9. 1. " COUNT_RX ,Reception Byte Count"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F103*"))
|
|
tree "CAN (Controller Area Network)"
|
|
base ad:0x40006400
|
|
width 11.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "CAN_MCR,CAN Master Control Register"
|
|
bitfld.long 0x00 16. " DBF ,Debug freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " TTCM ,Time Triggered Communication Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ABOM ,Automatic Bus-Off Management" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AWUM ,Automatic Wake-Up Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NART ,No Automatic Retransmission" "Retransmitted,Transmitted once"
|
|
bitfld.long 0x00 3. " RFLM ,Receive FIFO Locked Mode" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " TXFP ,Transmit FIFO Priority" "Identifier,Request order"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEP ,SLEEP Mode Request" "Normal mode,Sleep mode"
|
|
bitfld.long 0x00 0. " INRQ ,Initialization Request" "No effect,Initialize"
|
|
line.long 0x04 "CAN_MSR,CAN Master Status Register"
|
|
rbitfld.long 0x04 11. " RX ,CAN Rx Signal" "0,1"
|
|
rbitfld.long 0x04 10. " SAMP ,Last Sample Point" "0,1"
|
|
rbitfld.long 0x04 9. " RXM ,Receive Mode" "Not receiving,Receiving"
|
|
rbitfld.long 0x04 8. " TXM ,Transmit Mode" "Not transmitting,Transmitting"
|
|
textline " "
|
|
eventfld.long 0x04 4. " SLAKI ,SLEEP Acknowledge Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " WKUI ,Wake-Up Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " ERRI ,Error Interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 1. " SLAK ,SLEEP Acknowledge" "No sleep,Sleep"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " INAK ,Initialization Acknowledge" "No initialization,Initialization"
|
|
line.long 0x08 "CAN_TSR,CAN Transmit Status Register"
|
|
rbitfld.long 0x08 31. " LOW2 ,Lowest Priority Flag for Mailbox 2" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 30. " LOW1 ,Lowest Priority Flag for Mailbox 1" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 29. " LOW0 ,Lowest Priority Flag for Mailbox 0" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 28. " TME2 ,Transmit Mailbox 2 Empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x08 27. " TME1 ,Transmit Mailbox 1 Empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 26. " TME0 ,Transmit Mailbox 0 Empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 24.--25. " CODE ,Mailbox Code" "0,1,2,3"
|
|
bitfld.long 0x08 23. " ABRQ2 ,Abort Request for Mailbox 2" "No effect,Abort"
|
|
textline " "
|
|
eventfld.long 0x08 19. " TERR2 ,Transmission Error of Mailbox 2" "No error,Error"
|
|
eventfld.long 0x08 18. " ALST2 ,Arbitration Lost for Mailbox 2" "Not lost,Lost"
|
|
eventfld.long 0x08 17. " TXOK2 ,Transmission OK of Mailbox 2" "Failed,Successful"
|
|
eventfld.long 0x08 16. " RQCP2 ,Request Completed Mailbox 2" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ABRQ1 ,Abort Request for Mailbox 1" "No effect,Abort"
|
|
eventfld.long 0x08 11. " TERR1 ,Transmission Error of Mailbox 1" "No error,Error"
|
|
eventfld.long 0x08 10. " ALST1 ,Arbitration Lost for Mailbox 1" "Not lost,Lost"
|
|
eventfld.long 0x08 9. " TXOK1 ,Transmission OK of Mailbox 1" "Failed,Successful"
|
|
textline " "
|
|
eventfld.long 0x08 8. " RQCP1 ,Request Completed Mailbox 1" "Not completed,Completed"
|
|
bitfld.long 0x08 7. " ABRQ0 ,Abort Request for Mailbox 0" "No effect,Abort"
|
|
eventfld.long 0x08 3. " TERR0 ,Transmission Error of Mailbox 0" "No error,Error"
|
|
eventfld.long 0x08 2. " ALST0 ,Arbitration Lost for Mailbox 0" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x08 1. " TXOK0 ,Transmission OK of Mailbox 0" "Failed,Successful"
|
|
eventfld.long 0x08 0. " RQCP0 ,Request Completed Mailbox 0" "Not completed,Completed"
|
|
line.long 0x0C "CAN_RF0R,CAN Receive FIFO 0 Register"
|
|
bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 Output Mailbox" "No effect,Release"
|
|
eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0C 3. " FULL0 ,FIFO 0 Full" "Not full,Full"
|
|
rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 Message Pending" "0,1,2,3"
|
|
line.long 0x10 "CAN_RF1R,CAN Receive FIFO 1 Register"
|
|
bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 Output Mailbox" "No effect,Release"
|
|
eventfld.long 0x10 4. " FOVR1 ,FIFO 1 Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x10 3. " FULL1 ,FIFO 1 Full" "Not full,Full"
|
|
rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 Message Pending" "0,1,2,3"
|
|
line.long 0x14 "CAN_IER,CAN Interrupt Enable Register"
|
|
bitfld.long 0x14 17. " SLKIE ,SLEEP Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " WKUIE ,Wake-Up Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " ERRIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " LECIE ,Last Error Code Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " BOFIE ,Bus-Off Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " EPVIE ,Error Passive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " EWGIE ,Error Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " FOVIE1 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " FFIE1 ,FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FMPIE1 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " FOVIE0 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FFIE0 ,FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " FMPIE0 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TMEIE ,Transmit Mailbox Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x18 "CAN_ESR,CAN Error Status Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive Error Counter"
|
|
hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit Transmit Error Counter"
|
|
bitfld.long 0x18 4.--6. " LEC ,Last Error Code" "No error,Stuff,Form,Acknowledgement,Bit recessive,Bit dominant,CRC,Set by software"
|
|
rbitfld.long 0x18 2. " BOFF ,Bus-Off Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x18 1. " EPVF ,Error Passive Flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 0. " EWGF ,Error Warning Flag" "Not occurred,Occurred"
|
|
line.long 0x1C "CAN_BTR,CAN Bit Timing Register"
|
|
bitfld.long 0x1C 31. " SILM ,Silent Mode" "Normal,Silent"
|
|
bitfld.long 0x1C 30. " LBKM ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x1C 24.--25. " SJW ,Resynchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x1C 20.--22. " TS2 ,Time Segment 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--19. " TS1 ,Time Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud Rate Prescaler"
|
|
tree "T0 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x180)))&0x4)==0x4)
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x180+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT0R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL0R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH0R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "T1 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x190)))&0x4)==0x4)
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x190+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT1R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL1R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH1R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "T2 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x1A0)))&0x4)==0x4)
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x1A0+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT2R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL2R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH2R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "FIFO 0"
|
|
if (((per.l((ad:0x40006400+0x1B0)))&0x4)==0x4)
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1B0+0x04)++0x0B
|
|
line.long 0x00 "CAN_RDT0R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_RDL0R,Receive FIFO Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_RDH0R,Receive FIFO Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "FIFO 1"
|
|
if (((per.l((ad:0x40006400+0x1C0)))&0x4)==0x4)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1C0+0x04)++0x0B
|
|
line.long 0x00 "CAN_RDT1R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_RDL1R,Receive FIFO Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_RDH1R,Receive FIFO Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "Filter Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CAN_FMR,CAN Filter Master Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*")&&!cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")||cpuis("STM32F103TB")||cpuis("STM32F7*"))
|
|
hexmask.long.byte 0x00 8.--13. 1. " CAN2SB ,CAN2 start bank"
|
|
bitfld.long 0x00 0. " FINIT ,Filter Init Mode" "Active mode,Initialization"
|
|
else
|
|
sif (cpu()=="STM32F372CB")||(cpuis("STM32F446*"))||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F412*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
hexmask.long.byte 0x00 8.--13. 1. " CANSB ,CAN start bank"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " FINIT ,Filter Init Mode" "Active,Initialization"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "CAN_FM1R,CAN Filter Mode Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FBM27 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 26. " FBM26 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 25. " FBM25 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FBM24 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 23. " FBM23 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 22. " FBM22 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FBM21 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 20. " FBM20 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 19. " FBM19 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FBM18 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 17. " FBM17 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 16. " FBM16 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FBM15 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 14. " FBM14 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FBM13 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 12. " FBM12 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 11. " FBM11 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FBM10 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 9. " FBM9 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 8. " FBM8 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FBM7 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 6. " FBM6 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 5. " FBM5 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FBM4 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 3. " FBM3 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 2. " FBM2 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FBM1 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 0. " FBM0 ,Filter Mode" "Mask,List"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "CAN_FS1R,CAN Filter Scale Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FSC27 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 26. " FSC26 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 25. " FSC25 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FSC24 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 23. " FSC23 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 22. " FSC22 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FSC21 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 20. " FSC20 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 19. " FSC19 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FSC18 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 17. " FSC17 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 16. " FSC16 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FSC15 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 14. " FSC14 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FSC13 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 12. " FSC12 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 11. " FSC11 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSC10 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 9. " FSC9 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 8. " FSC8 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FSC7 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 6. " FSC6 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 5. " FSC5 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FSC4 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 3. " FSC3 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 2. " FSC2 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSC1 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 0. " FSC0 ,Filter Scale Configuration" "Dual,Single"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FFA27 ,Filter FIFO Assignment for Filter 27" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 26. " FFA26 ,Filter FIFO Assignment for Filter 26" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 25. " FFA25 ,Filter FIFO Assignment for Filter 25" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FFA24 ,Filter FIFO Assignment for Filter 24" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 23. " FFA23 ,Filter FIFO Assignment for Filter 23" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 22. " FFA22 ,Filter FIFO Assignment for Filter 22" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FFA21 ,Filter FIFO Assignment for Filter 21" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 20. " FFA20 ,Filter FIFO Assignment for Filter 20" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 19. " FFA19 ,Filter FIFO Assignment for Filter 19" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FFA18 ,Filter FIFO Assignment for Filter 18" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 17. " FFA17 ,Filter FIFO Assignment for Filter 17" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 16. " FFA16 ,Filter FIFO Assignment for Filter 16" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FFA15 ,Filter FIFO Assignment for Filter 15" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 14. " FFA14 ,Filter FIFO Assignment for Filter 14" "FIFO0,FIFO1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FFA13 ,Filter FIFO Assignment for Filter 13" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 12. " FFA12 ,Filter FIFO Assignment for Filter 12" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 11. " FFA11 ,Filter FIFO Assignment for Filter 11" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FFA10 ,Filter FIFO Assignment for Filter 10" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 9. " FFA9 ,Filter FIFO Assignment for Filter 9" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 8. " FFA8 ,Filter FIFO Assignment for Filter 8" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FFA7 ,Filter FIFO Assignment for Filter 7" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 6. " FFA6 ,Filter FIFO Assignment for Filter 6" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 5. " FFA5 ,Filter FIFO Assignment for Filter 5" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FFA4 ,Filter FIFO Assignment for Filter 4" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 3. " FFA3 ,Filter FIFO Assignment for Filter 3" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 2. " FFA2 ,Filter FIFO Assignment for Filter 2" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FFA1 ,Filter FIFO Assignment for Filter 1" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 0. " FFA0 ,Filter FIFO Assignment for Filter 0" "FIFO0,FIFO1"
|
|
else
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "CAN_FM1R,CAN Filter Mode Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FBM27 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 26. " FBM26 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 25. " FBM25 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FBM24 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 23. " FBM23 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 22. " FBM22 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FBM21 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 20. " FBM20 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 19. " FBM19 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FBM18 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 17. " FBM17 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 16. " FBM16 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FBM15 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 14. " FBM14 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FBM13 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 12. " FBM12 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 11. " FBM11 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FBM10 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 9. " FBM9 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 8. " FBM8 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FBM7 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 6. " FBM6 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 5. " FBM5 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FBM4 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 3. " FBM3 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 2. " FBM2 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FBM1 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 0. " FBM0 ,Filter Mode" "Mask,List"
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "CAN_FS1R,CAN Filter Scale Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FSC27 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 26. " FSC26 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 25. " FSC25 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FSC24 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 23. " FSC23 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 22. " FSC22 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FSC21 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 20. " FSC20 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 19. " FSC19 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FSC18 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 17. " FSC17 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 16. " FSC16 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FSC15 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 14. " FSC14 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FSC13 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 12. " FSC12 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 11. " FSC11 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSC10 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 9. " FSC9 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 8. " FSC8 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FSC7 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 6. " FSC6 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 5. " FSC5 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FSC4 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 3. " FSC3 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 2. " FSC2 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSC1 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 0. " FSC0 ,Filter Scale Configuration" "Dual,Single"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FFA27 ,Filter FIFO Assignment for Filter 27" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 26. " FFA26 ,Filter FIFO Assignment for Filter 26" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 25. " FFA25 ,Filter FIFO Assignment for Filter 25" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FFA24 ,Filter FIFO Assignment for Filter 24" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 23. " FFA23 ,Filter FIFO Assignment for Filter 23" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 22. " FFA22 ,Filter FIFO Assignment for Filter 22" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FFA21 ,Filter FIFO Assignment for Filter 21" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 20. " FFA20 ,Filter FIFO Assignment for Filter 20" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 19. " FFA19 ,Filter FIFO Assignment for Filter 19" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FFA18 ,Filter FIFO Assignment for Filter 18" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 17. " FFA17 ,Filter FIFO Assignment for Filter 17" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 16. " FFA16 ,Filter FIFO Assignment for Filter 16" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FFA15 ,Filter FIFO Assignment for Filter 15" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 14. " FFA14 ,Filter FIFO Assignment for Filter 14" "FIFO0,FIFO1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FFA13 ,Filter FIFO Assignment for Filter 13" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 12. " FFA12 ,Filter FIFO Assignment for Filter 12" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 11. " FFA11 ,Filter FIFO Assignment for Filter 11" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FFA10 ,Filter FIFO Assignment for Filter 10" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 9. " FFA9 ,Filter FIFO Assignment for Filter 9" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 8. " FFA8 ,Filter FIFO Assignment for Filter 8" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FFA7 ,Filter FIFO Assignment for Filter 7" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 6. " FFA6 ,Filter FIFO Assignment for Filter 6" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 5. " FFA5 ,Filter FIFO Assignment for Filter 5" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FFA4 ,Filter FIFO Assignment for Filter 4" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 3. " FFA3 ,Filter FIFO Assignment for Filter 3" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 2. " FFA2 ,Filter FIFO Assignment for Filter 2" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FFA1 ,Filter FIFO Assignment for Filter 1" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 0. " FFA0 ,Filter FIFO Assignment for Filter 0" "FIFO0,FIFO1"
|
|
endif
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "CAN_FA1R,CAN Filter Activation Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FACT27 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 26. " FACT26 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FACT25 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 24. " FACT24 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FACT23 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 22. " FACT22 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FACT21 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 20. " FACT20 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FACT19 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 18. " FACT18 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FACT17 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 16. " FACT16 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FACT15 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 14. " FACT14 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FACT13 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 12. " FACT12 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FACT11 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 10. " FACT10 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FACT9 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 8. " FACT8 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FACT7 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 6. " FACT6 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FACT5 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 4. " FACT4 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FACT3 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 2. " FACT2 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FACT1 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 0. " FACT0 ,Filter Active" "Not active,Active"
|
|
tree "Filter Bank Registers"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<0.))==0x00)
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "CAN_F0R1,Filter Bank 0_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "CAN_F0R1,Filter Bank 0_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<0.))==0x00)
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "CAN_F0R2,Filter Bank 0_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x244++0x03
|
|
line.long 0x00 "CAN_F0R2,Filter Bank 0_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<1.))==0x00)
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "CAN_F1R1,Filter Bank 1_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x248++0x03
|
|
line.long 0x00 "CAN_F1R1,Filter Bank 1_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<1.))==0x00)
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "CAN_F1R2,Filter Bank 1_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x24C++0x03
|
|
line.long 0x00 "CAN_F1R2,Filter Bank 1_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<2.))==0x00)
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "CAN_F2R1,Filter Bank 2_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x250++0x03
|
|
line.long 0x00 "CAN_F2R1,Filter Bank 2_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<2.))==0x00)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "CAN_F2R2,Filter Bank 2_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x254++0x03
|
|
line.long 0x00 "CAN_F2R2,Filter Bank 2_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<3.))==0x00)
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "CAN_F3R1,Filter Bank 3_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x258++0x03
|
|
line.long 0x00 "CAN_F3R1,Filter Bank 3_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<3.))==0x00)
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "CAN_F3R2,Filter Bank 3_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "CAN_F3R2,Filter Bank 3_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<4.))==0x00)
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "CAN_F4R1,Filter Bank 4_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x260++0x03
|
|
line.long 0x00 "CAN_F4R1,Filter Bank 4_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<4.))==0x00)
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "CAN_F4R2,Filter Bank 4_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x264++0x03
|
|
line.long 0x00 "CAN_F4R2,Filter Bank 4_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<5.))==0x00)
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "CAN_F5R1,Filter Bank 5_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x268++0x03
|
|
line.long 0x00 "CAN_F5R1,Filter Bank 5_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<5.))==0x00)
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "CAN_F5R2,Filter Bank 5_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "CAN_F5R2,Filter Bank 5_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<6.))==0x00)
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "CAN_F6R1,Filter Bank 6_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x270++0x03
|
|
line.long 0x00 "CAN_F6R1,Filter Bank 6_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<6.))==0x00)
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "CAN_F6R2,Filter Bank 6_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x274++0x03
|
|
line.long 0x00 "CAN_F6R2,Filter Bank 6_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<7.))==0x00)
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "CAN_F7R1,Filter Bank 7_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x278++0x03
|
|
line.long 0x00 "CAN_F7R1,Filter Bank 7_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<7.))==0x00)
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "CAN_F7R2,Filter Bank 7_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x27C++0x03
|
|
line.long 0x00 "CAN_F7R2,Filter Bank 7_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<8.))==0x00)
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "CAN_F8R1,Filter Bank 8_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "CAN_F8R1,Filter Bank 8_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<8.))==0x00)
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "CAN_F8R2,Filter Bank 8_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "CAN_F8R2,Filter Bank 8_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<9.))==0x00)
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "CAN_F9R1,Filter Bank 9_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "CAN_F9R1,Filter Bank 9_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<9.))==0x00)
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "CAN_F9R2,Filter Bank 9_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x28C++0x03
|
|
line.long 0x00 "CAN_F9R2,Filter Bank 9_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<10.))==0x00)
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "CAN_F10R1,Filter Bank 10_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x290++0x03
|
|
line.long 0x00 "CAN_F10R1,Filter Bank 10_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<10.))==0x00)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "CAN_F10R2,Filter Bank 10_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "CAN_F10R2,Filter Bank 10_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<11.))==0x00)
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "CAN_F11R1,Filter Bank 11_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "CAN_F11R1,Filter Bank 11_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<11.))==0x00)
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "CAN_F11R2,Filter Bank 11_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "CAN_F11R2,Filter Bank 11_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<12.))==0x00)
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "CAN_F12R1,Filter Bank 12_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "CAN_F12R1,Filter Bank 12_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<12.))==0x00)
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "CAN_F12R2,Filter Bank 12_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "CAN_F12R2,Filter Bank 12_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<13.))==0x00)
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "CAN_F13R1,Filter Bank 13_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2A8++0x03
|
|
line.long 0x00 "CAN_F13R1,Filter Bank 13_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<13.))==0x00)
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "CAN_F13R2,Filter Bank 13_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2AC++0x03
|
|
line.long 0x00 "CAN_F13R2,Filter Bank 13_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<14.))==0x00)
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "CAN_F14R1,Filter Bank 14_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2B0++0x03
|
|
line.long 0x00 "CAN_F14R1,Filter Bank 14_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<14.))==0x00)
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "CAN_F14R2,Filter Bank 14_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "CAN_F14R2,Filter Bank 14_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<15.))==0x00)
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "CAN_F15R1,Filter Bank 15_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2B8++0x03
|
|
line.long 0x00 "CAN_F15R1,Filter Bank 15_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<15.))==0x00)
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "CAN_F15R2,Filter Bank 15_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2BC++0x03
|
|
line.long 0x00 "CAN_F15R2,Filter Bank 15_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<16.))==0x00)
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "CAN_F16R1,Filter Bank 16_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2C0++0x03
|
|
line.long 0x00 "CAN_F16R1,Filter Bank 16_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<16.))==0x00)
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "CAN_F16R2,Filter Bank 16_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2C4++0x03
|
|
line.long 0x00 "CAN_F16R2,Filter Bank 16_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<17.))==0x00)
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "CAN_F17R1,Filter Bank 17_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2C8++0x03
|
|
line.long 0x00 "CAN_F17R1,Filter Bank 17_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<17.))==0x00)
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "CAN_F17R2,Filter Bank 17_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2CC++0x03
|
|
line.long 0x00 "CAN_F17R2,Filter Bank 17_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<18.))==0x00)
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "CAN_F18R1,Filter Bank 18_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2D0++0x03
|
|
line.long 0x00 "CAN_F18R1,Filter Bank 18_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<18.))==0x00)
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "CAN_F18R2,Filter Bank 18_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2D4++0x03
|
|
line.long 0x00 "CAN_F18R2,Filter Bank 18_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<19.))==0x00)
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "CAN_F19R1,Filter Bank 19_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2D8++0x03
|
|
line.long 0x00 "CAN_F19R1,Filter Bank 19_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<19.))==0x00)
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "CAN_F19R2,Filter Bank 19_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2DC++0x03
|
|
line.long 0x00 "CAN_F19R2,Filter Bank 19_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<20.))==0x00)
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "CAN_F20R1,Filter Bank 20_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2E0++0x03
|
|
line.long 0x00 "CAN_F20R1,Filter Bank 20_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<20.))==0x00)
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "CAN_F20R2,Filter Bank 20_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2E4++0x03
|
|
line.long 0x00 "CAN_F20R2,Filter Bank 20_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<21.))==0x00)
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "CAN_F21R1,Filter Bank 21_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2E8++0x03
|
|
line.long 0x00 "CAN_F21R1,Filter Bank 21_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<21.))==0x00)
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "CAN_F21R2,Filter Bank 21_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2EC++0x03
|
|
line.long 0x00 "CAN_F21R2,Filter Bank 21_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<22.))==0x00)
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "CAN_F22R1,Filter Bank 22_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2F0++0x03
|
|
line.long 0x00 "CAN_F22R1,Filter Bank 22_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<22.))==0x00)
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "CAN_F22R2,Filter Bank 22_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2F4++0x03
|
|
line.long 0x00 "CAN_F22R2,Filter Bank 22_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<23.))==0x00)
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "CAN_F23R1,Filter Bank 23_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2F8++0x03
|
|
line.long 0x00 "CAN_F23R1,Filter Bank 23_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<23.))==0x00)
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "CAN_F23R2,Filter Bank 23_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2FC++0x03
|
|
line.long 0x00 "CAN_F23R2,Filter Bank 23_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<24.))==0x00)
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "CAN_F24R1,Filter Bank 24_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "CAN_F24R1,Filter Bank 24_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<24.))==0x00)
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "CAN_F24R2,Filter Bank 24_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "CAN_F24R2,Filter Bank 24_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<25.))==0x00)
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "CAN_F25R1,Filter Bank 25_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "CAN_F25R1,Filter Bank 25_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<25.))==0x00)
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "CAN_F25R2,Filter Bank 25_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "CAN_F25R2,Filter Bank 25_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<26.))==0x00)
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "CAN_F26R1,Filter Bank 26_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "CAN_F26R1,Filter Bank 26_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<26.))==0x00)
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "CAN_F26R2,Filter Bank 26_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "CAN_F26R2,Filter Bank 26_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<27.))==0x00)
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "CAN_F27R1,Filter Bank 27_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "CAN_F27R1,Filter Bank 27_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<27.))==0x00)
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "CAN_F27R2,Filter Bank 27_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "CAN_F27R2,Filter Bank 27_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
elif cpuis("STM32F103*")
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<0.))==0x00))
|
|
;
|
|
group.long 0x240++0x07
|
|
line.long 0x00 "CAN_F0R0,Filter Bank 0_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F0R1,Filter Bank 0_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x240++0x07
|
|
line.long 0x00 "CAN_F0R0,Filter Bank 0_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F0R1,Filter Bank 0_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<1.))==0x00))
|
|
;
|
|
group.long 0x244++0x07
|
|
line.long 0x00 "CAN_F1R0,Filter Bank 1_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F1R1,Filter Bank 1_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "CAN_F1R0,Filter Bank 1_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F1R1,Filter Bank 1_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<2.))==0x00))
|
|
;
|
|
group.long 0x248++0x07
|
|
line.long 0x00 "CAN_F2R0,Filter Bank 2_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F2R1,Filter Bank 2_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x248++0x07
|
|
line.long 0x00 "CAN_F2R0,Filter Bank 2_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F2R1,Filter Bank 2_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<3.))==0x00))
|
|
;
|
|
group.long 0x24C++0x07
|
|
line.long 0x00 "CAN_F3R0,Filter Bank 3_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F3R1,Filter Bank 3_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x24C++0x07
|
|
line.long 0x00 "CAN_F3R0,Filter Bank 3_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F3R1,Filter Bank 3_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<4.))==0x00))
|
|
;
|
|
group.long 0x250++0x07
|
|
line.long 0x00 "CAN_F4R0,Filter Bank 4_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F4R1,Filter Bank 4_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x250++0x07
|
|
line.long 0x00 "CAN_F4R0,Filter Bank 4_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F4R1,Filter Bank 4_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<5.))==0x00))
|
|
;
|
|
group.long 0x254++0x07
|
|
line.long 0x00 "CAN_F5R0,Filter Bank 5_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F5R1,Filter Bank 5_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x254++0x07
|
|
line.long 0x00 "CAN_F5R0,Filter Bank 5_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F5R1,Filter Bank 5_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<6.))==0x00))
|
|
;
|
|
group.long 0x258++0x07
|
|
line.long 0x00 "CAN_F6R0,Filter Bank 6_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F6R1,Filter Bank 6_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x258++0x07
|
|
line.long 0x00 "CAN_F6R0,Filter Bank 6_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F6R1,Filter Bank 6_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<7.))==0x00))
|
|
;
|
|
group.long 0x25C++0x07
|
|
line.long 0x00 "CAN_F7R0,Filter Bank 7_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F7R1,Filter Bank 7_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x25C++0x07
|
|
line.long 0x00 "CAN_F7R0,Filter Bank 7_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F7R1,Filter Bank 7_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<8.))==0x00))
|
|
;
|
|
group.long 0x260++0x07
|
|
line.long 0x00 "CAN_F8R0,Filter Bank 8_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F8R1,Filter Bank 8_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x260++0x07
|
|
line.long 0x00 "CAN_F8R0,Filter Bank 8_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F8R1,Filter Bank 8_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<9.))==0x00))
|
|
;
|
|
group.long 0x264++0x07
|
|
line.long 0x00 "CAN_F9R0,Filter Bank 9_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F9R1,Filter Bank 9_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x264++0x07
|
|
line.long 0x00 "CAN_F9R0,Filter Bank 9_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F9R1,Filter Bank 9_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<10.))==0x00))
|
|
;
|
|
group.long 0x268++0x07
|
|
line.long 0x00 "CAN_F10R0,Filter Bank 10_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F10R1,Filter Bank 10_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x268++0x07
|
|
line.long 0x00 "CAN_F10R0,Filter Bank 10_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F10R1,Filter Bank 10_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<11.))==0x00))
|
|
;
|
|
group.long 0x26C++0x07
|
|
line.long 0x00 "CAN_F11R0,Filter Bank 11_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F11R1,Filter Bank 11_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x26C++0x07
|
|
line.long 0x00 "CAN_F11R0,Filter Bank 11_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F11R1,Filter Bank 11_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<12.))==0x00))
|
|
;
|
|
group.long 0x270++0x07
|
|
line.long 0x00 "CAN_F12R0,Filter Bank 12_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F12R1,Filter Bank 12_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x270++0x07
|
|
line.long 0x00 "CAN_F12R0,Filter Bank 12_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F12R1,Filter Bank 12_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<13.))==0x00))
|
|
;
|
|
group.long 0x274++0x07
|
|
line.long 0x00 "CAN_F13R0,Filter Bank 13_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F13R1,Filter Bank 13_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x274++0x07
|
|
line.long 0x00 "CAN_F13R0,Filter Bank 13_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F13R1,Filter Bank 13_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
else
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "CAN_F0R1,Filter Bank 0_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "CAN_F0R2,Filter Bank 0_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "CAN_F1R1,Filter Bank 1_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "CAN_F1R2,Filter Bank 1_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "CAN_F2R1,Filter Bank 2_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "CAN_F2R2,Filter Bank 2_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "CAN_F3R1,Filter Bank 3_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "CAN_F3R2,Filter Bank 3_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "CAN_F4R1,Filter Bank 4_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "CAN_F4R2,Filter Bank 4_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "CAN_F5R1,Filter Bank 5_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "CAN_F5R2,Filter Bank 5_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "CAN_F6R1,Filter Bank 6_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "CAN_F6R2,Filter Bank 6_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "CAN_F7R1,Filter Bank 7_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "CAN_F7R2,Filter Bank 7_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "CAN_F8R1,Filter Bank 8_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "CAN_F8R2,Filter Bank 8_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "CAN_F9R1,Filter Bank 9_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "CAN_F9R2,Filter Bank 9_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "CAN_F10R1,Filter Bank 10_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "CAN_F10R2,Filter Bank 10_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "CAN_F11R1,Filter Bank 11_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "CAN_F11R2,Filter Bank 11_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "CAN_F12R1,Filter Bank 12_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "CAN_F12R2,Filter Bank 12_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "CAN_F13R1,Filter Bank 13_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "CAN_F13R2,Filter Bank 13_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
tree.open "CAN (Controller Area Network)"
|
|
tree "CAN 1"
|
|
base ad:0x40006400
|
|
width 11.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "CAN_MCR,CAN Master Control Register"
|
|
bitfld.long 0x00 16. " DBF ,Debug freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " TTCM ,Time Triggered Communication Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ABOM ,Automatic Bus-Off Management" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AWUM ,Automatic Wake-Up Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NART ,No Automatic Retransmission" "Retransmitted,Transmitted once"
|
|
bitfld.long 0x00 3. " RFLM ,Receive FIFO Locked Mode" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " TXFP ,Transmit FIFO Priority" "Identifier,Request order"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEP ,SLEEP Mode Request" "Normal mode,Sleep mode"
|
|
bitfld.long 0x00 0. " INRQ ,Initialization Request" "No effect,Initialize"
|
|
line.long 0x04 "CAN_MSR,CAN Master Status Register"
|
|
rbitfld.long 0x04 11. " RX ,CAN Rx Signal" "0,1"
|
|
rbitfld.long 0x04 10. " SAMP ,Last Sample Point" "0,1"
|
|
rbitfld.long 0x04 9. " RXM ,Receive Mode" "Not receiving,Receiving"
|
|
rbitfld.long 0x04 8. " TXM ,Transmit Mode" "Not transmitting,Transmitting"
|
|
textline " "
|
|
eventfld.long 0x04 4. " SLAKI ,SLEEP Acknowledge Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " WKUI ,Wake-Up Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " ERRI ,Error Interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 1. " SLAK ,SLEEP Acknowledge" "No sleep,Sleep"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " INAK ,Initialization Acknowledge" "No initialization,Initialization"
|
|
line.long 0x08 "CAN_TSR,CAN Transmit Status Register"
|
|
rbitfld.long 0x08 31. " LOW2 ,Lowest Priority Flag for Mailbox 2" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 30. " LOW1 ,Lowest Priority Flag for Mailbox 1" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 29. " LOW0 ,Lowest Priority Flag for Mailbox 0" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 28. " TME2 ,Transmit Mailbox 2 Empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x08 27. " TME1 ,Transmit Mailbox 1 Empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 26. " TME0 ,Transmit Mailbox 0 Empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 24.--25. " CODE ,Mailbox Code" "0,1,2,3"
|
|
bitfld.long 0x08 23. " ABRQ2 ,Abort Request for Mailbox 2" "No effect,Abort"
|
|
textline " "
|
|
eventfld.long 0x08 19. " TERR2 ,Transmission Error of Mailbox 2" "No error,Error"
|
|
eventfld.long 0x08 18. " ALST2 ,Arbitration Lost for Mailbox 2" "Not lost,Lost"
|
|
eventfld.long 0x08 17. " TXOK2 ,Transmission OK of Mailbox 2" "Failed,Successful"
|
|
eventfld.long 0x08 16. " RQCP2 ,Request Completed Mailbox 2" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ABRQ1 ,Abort Request for Mailbox 1" "No effect,Abort"
|
|
eventfld.long 0x08 11. " TERR1 ,Transmission Error of Mailbox 1" "No error,Error"
|
|
eventfld.long 0x08 10. " ALST1 ,Arbitration Lost for Mailbox 1" "Not lost,Lost"
|
|
eventfld.long 0x08 9. " TXOK1 ,Transmission OK of Mailbox 1" "Failed,Successful"
|
|
textline " "
|
|
eventfld.long 0x08 8. " RQCP1 ,Request Completed Mailbox 1" "Not completed,Completed"
|
|
bitfld.long 0x08 7. " ABRQ0 ,Abort Request for Mailbox 0" "No effect,Abort"
|
|
eventfld.long 0x08 3. " TERR0 ,Transmission Error of Mailbox 0" "No error,Error"
|
|
eventfld.long 0x08 2. " ALST0 ,Arbitration Lost for Mailbox 0" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x08 1. " TXOK0 ,Transmission OK of Mailbox 0" "Failed,Successful"
|
|
eventfld.long 0x08 0. " RQCP0 ,Request Completed Mailbox 0" "Not completed,Completed"
|
|
line.long 0x0C "CAN_RF0R,CAN Receive FIFO 0 Register"
|
|
bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 Output Mailbox" "No effect,Release"
|
|
eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0C 3. " FULL0 ,FIFO 0 Full" "Not full,Full"
|
|
rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 Message Pending" "0,1,2,3"
|
|
line.long 0x10 "CAN_RF1R,CAN Receive FIFO 1 Register"
|
|
bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 Output Mailbox" "No effect,Release"
|
|
eventfld.long 0x10 4. " FOVR1 ,FIFO 1 Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x10 3. " FULL1 ,FIFO 1 Full" "Not full,Full"
|
|
rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 Message Pending" "0,1,2,3"
|
|
line.long 0x14 "CAN_IER,CAN Interrupt Enable Register"
|
|
bitfld.long 0x14 17. " SLKIE ,SLEEP Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " WKUIE ,Wake-Up Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " ERRIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " LECIE ,Last Error Code Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " BOFIE ,Bus-Off Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " EPVIE ,Error Passive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " EWGIE ,Error Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " FOVIE1 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " FFIE1 ,FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FMPIE1 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " FOVIE0 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FFIE0 ,FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " FMPIE0 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TMEIE ,Transmit Mailbox Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x18 "CAN_ESR,CAN Error Status Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive Error Counter"
|
|
hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit Transmit Error Counter"
|
|
bitfld.long 0x18 4.--6. " LEC ,Last Error Code" "No error,Stuff,Form,Acknowledgement,Bit recessive,Bit dominant,CRC,Set by software"
|
|
rbitfld.long 0x18 2. " BOFF ,Bus-Off Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x18 1. " EPVF ,Error Passive Flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 0. " EWGF ,Error Warning Flag" "Not occurred,Occurred"
|
|
line.long 0x1C "CAN_BTR,CAN Bit Timing Register"
|
|
bitfld.long 0x1C 31. " SILM ,Silent Mode" "Normal,Silent"
|
|
bitfld.long 0x1C 30. " LBKM ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x1C 24.--25. " SJW ,Resynchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x1C 20.--22. " TS2 ,Time Segment 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--19. " TS1 ,Time Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud Rate Prescaler"
|
|
tree "T0 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x180)))&0x4)==0x4)
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x180+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT0R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL0R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH0R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "T1 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x190)))&0x4)==0x4)
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x190+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT1R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL1R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH1R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "T2 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x1A0)))&0x4)==0x4)
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x1A0+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT2R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL2R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH2R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "FIFO 0"
|
|
if (((per.l((ad:0x40006400+0x1B0)))&0x4)==0x4)
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1B0+0x04)++0x0B
|
|
line.long 0x00 "CAN_RDT0R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_RDL0R,Receive FIFO Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_RDH0R,Receive FIFO Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "FIFO 1"
|
|
if (((per.l((ad:0x40006400+0x1C0)))&0x4)==0x4)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1C0+0x04)++0x0B
|
|
line.long 0x00 "CAN_RDT1R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_RDL1R,Receive FIFO Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_RDH1R,Receive FIFO Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "CAN 2"
|
|
base ad:0x40006800
|
|
width 11.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "CAN_MCR,CAN Master Control Register"
|
|
bitfld.long 0x00 16. " DBF ,Debug freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " TTCM ,Time Triggered Communication Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ABOM ,Automatic Bus-Off Management" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AWUM ,Automatic Wake-Up Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NART ,No Automatic Retransmission" "Retransmitted,Transmitted once"
|
|
bitfld.long 0x00 3. " RFLM ,Receive FIFO Locked Mode" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " TXFP ,Transmit FIFO Priority" "Identifier,Request order"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEP ,SLEEP Mode Request" "Normal mode,Sleep mode"
|
|
bitfld.long 0x00 0. " INRQ ,Initialization Request" "No effect,Initialize"
|
|
line.long 0x04 "CAN_MSR,CAN Master Status Register"
|
|
rbitfld.long 0x04 11. " RX ,CAN Rx Signal" "0,1"
|
|
rbitfld.long 0x04 10. " SAMP ,Last Sample Point" "0,1"
|
|
rbitfld.long 0x04 9. " RXM ,Receive Mode" "Not receiving,Receiving"
|
|
rbitfld.long 0x04 8. " TXM ,Transmit Mode" "Not transmitting,Transmitting"
|
|
textline " "
|
|
eventfld.long 0x04 4. " SLAKI ,SLEEP Acknowledge Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " WKUI ,Wake-Up Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " ERRI ,Error Interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 1. " SLAK ,SLEEP Acknowledge" "No sleep,Sleep"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " INAK ,Initialization Acknowledge" "No initialization,Initialization"
|
|
line.long 0x08 "CAN_TSR,CAN Transmit Status Register"
|
|
rbitfld.long 0x08 31. " LOW2 ,Lowest Priority Flag for Mailbox 2" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 30. " LOW1 ,Lowest Priority Flag for Mailbox 1" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 29. " LOW0 ,Lowest Priority Flag for Mailbox 0" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 28. " TME2 ,Transmit Mailbox 2 Empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x08 27. " TME1 ,Transmit Mailbox 1 Empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 26. " TME0 ,Transmit Mailbox 0 Empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 24.--25. " CODE ,Mailbox Code" "0,1,2,3"
|
|
bitfld.long 0x08 23. " ABRQ2 ,Abort Request for Mailbox 2" "No effect,Abort"
|
|
textline " "
|
|
eventfld.long 0x08 19. " TERR2 ,Transmission Error of Mailbox 2" "No error,Error"
|
|
eventfld.long 0x08 18. " ALST2 ,Arbitration Lost for Mailbox 2" "Not lost,Lost"
|
|
eventfld.long 0x08 17. " TXOK2 ,Transmission OK of Mailbox 2" "Failed,Successful"
|
|
eventfld.long 0x08 16. " RQCP2 ,Request Completed Mailbox 2" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ABRQ1 ,Abort Request for Mailbox 1" "No effect,Abort"
|
|
eventfld.long 0x08 11. " TERR1 ,Transmission Error of Mailbox 1" "No error,Error"
|
|
eventfld.long 0x08 10. " ALST1 ,Arbitration Lost for Mailbox 1" "Not lost,Lost"
|
|
eventfld.long 0x08 9. " TXOK1 ,Transmission OK of Mailbox 1" "Failed,Successful"
|
|
textline " "
|
|
eventfld.long 0x08 8. " RQCP1 ,Request Completed Mailbox 1" "Not completed,Completed"
|
|
bitfld.long 0x08 7. " ABRQ0 ,Abort Request for Mailbox 0" "No effect,Abort"
|
|
eventfld.long 0x08 3. " TERR0 ,Transmission Error of Mailbox 0" "No error,Error"
|
|
eventfld.long 0x08 2. " ALST0 ,Arbitration Lost for Mailbox 0" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x08 1. " TXOK0 ,Transmission OK of Mailbox 0" "Failed,Successful"
|
|
eventfld.long 0x08 0. " RQCP0 ,Request Completed Mailbox 0" "Not completed,Completed"
|
|
line.long 0x0C "CAN_RF0R,CAN Receive FIFO 0 Register"
|
|
bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 Output Mailbox" "No effect,Release"
|
|
eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0C 3. " FULL0 ,FIFO 0 Full" "Not full,Full"
|
|
rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 Message Pending" "0,1,2,3"
|
|
line.long 0x10 "CAN_RF1R,CAN Receive FIFO 1 Register"
|
|
bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 Output Mailbox" "No effect,Release"
|
|
eventfld.long 0x10 4. " FOVR1 ,FIFO 1 Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x10 3. " FULL1 ,FIFO 1 Full" "Not full,Full"
|
|
rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 Message Pending" "0,1,2,3"
|
|
line.long 0x14 "CAN_IER,CAN Interrupt Enable Register"
|
|
bitfld.long 0x14 17. " SLKIE ,SLEEP Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " WKUIE ,Wake-Up Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " ERRIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " LECIE ,Last Error Code Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " BOFIE ,Bus-Off Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " EPVIE ,Error Passive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " EWGIE ,Error Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " FOVIE1 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " FFIE1 ,FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FMPIE1 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " FOVIE0 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FFIE0 ,FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " FMPIE0 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TMEIE ,Transmit Mailbox Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x18 "CAN_ESR,CAN Error Status Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive Error Counter"
|
|
hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit Transmit Error Counter"
|
|
bitfld.long 0x18 4.--6. " LEC ,Last Error Code" "No error,Stuff,Form,Acknowledgement,Bit recessive,Bit dominant,CRC,Set by software"
|
|
rbitfld.long 0x18 2. " BOFF ,Bus-Off Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x18 1. " EPVF ,Error Passive Flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 0. " EWGF ,Error Warning Flag" "Not occurred,Occurred"
|
|
line.long 0x1C "CAN_BTR,CAN Bit Timing Register"
|
|
bitfld.long 0x1C 31. " SILM ,Silent Mode" "Normal,Silent"
|
|
bitfld.long 0x1C 30. " LBKM ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x1C 24.--25. " SJW ,Resynchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x1C 20.--22. " TS2 ,Time Segment 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--19. " TS1 ,Time Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud Rate Prescaler"
|
|
tree "T0 Mailbox"
|
|
if (((per.l((ad:0x40006800+0x180)))&0x4)==0x4)
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x180+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT0R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL0R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH0R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "T1 Mailbox"
|
|
if (((per.l((ad:0x40006800+0x190)))&0x4)==0x4)
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x190+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT1R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL1R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH1R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "T2 Mailbox"
|
|
if (((per.l((ad:0x40006800+0x1A0)))&0x4)==0x4)
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x1A0+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT2R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL2R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH2R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "FIFO 0"
|
|
if (((per.l((ad:0x40006800+0x1B0)))&0x4)==0x4)
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1B0+0x04)++0x0B
|
|
line.long 0x00 "CAN_RDT0R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_RDL0R,Receive FIFO Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_RDH0R,Receive FIFO Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "FIFO 1"
|
|
if (((per.l((ad:0x40006800+0x1C0)))&0x4)==0x4)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1C0+0x04)++0x0B
|
|
line.long 0x00 "CAN_RDT1R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_RDL1R,Receive FIFO Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_RDH1R,Receive FIFO Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI 1"
|
|
base ad:0x40013000
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F2*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,Not match"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
if (((per.w((ad:0x40013000+0x00)))&0x800)==0x800)
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
else
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
sif (cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpuis("STM32F103*F")||cpuis("STM32F103*G")||cpu()=="STM32F103"||cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
tree "SPI 2/I2S2"
|
|
base ad:0x40003800
|
|
width 12.
|
|
if ((per.w((ad:0x40003800+0x1c))&0x800)==0x0)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((per.w((ad:0x40003800+0x1c))&0x800)==0x0)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.w((ad:0x40003800+0x1c))&0x800)==0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,Not match"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif ((per.w((ad:0x40003800+0x1c))&0x830)==0x830)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
if ((((per.w((ad:0x40003800+0x00)))&0x800)==0x800)||(((per.w((ad:0x40003800+0x1c)))&0x800)==0x800))
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
else
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register"
|
|
endif
|
|
if ((((per.w((ad:0x40003800+0x1c)))&0x800)==0x0))
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x10++0x1
|
|
hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hgroup.word 0x14++0x1
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x1
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if ((((per.w((ad:0x40003800+0x1c)))&0x800)==0x00))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
elif ((((per.w((ad:0x40003800+0x1c)))&0x830)==0x830))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Teansmit,Master/Receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
else
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Teansmit,Master/Receive"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
endif
|
|
if ((((per.w((ad:0x40003800+0x1c)))&0xB00)==0xA00)||(((per.w((ad:0x40003800+0x1c)))&0xB00)==0xB00))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler"
|
|
else
|
|
hgroup.word 0x20++0x1
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "SPI 3/I2S3"
|
|
base ad:0x40003C00
|
|
width 12.
|
|
if ((per.w((ad:0x40003C00+0x1c))&0x800)==0x0)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
else
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((per.w((ad:0x40003C00+0x1c))&0x800)==0x0)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
sif (cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.w((ad:0x40003C00+0x1c))&0x800)==0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,Not match"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif ((per.w((ad:0x40003C00+0x1c))&0x830)==0x830)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
if ((((per.w((ad:0x40003C00+0x00)))&0x800)==0x800)||(((per.w((ad:0x40003C00+0x1c)))&0x800)==0x800))
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
else
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register"
|
|
endif
|
|
if ((((per.w((ad:0x40003C00+0x1c)))&0x800)==0x0))
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x10++0x1
|
|
hide.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hgroup.word 0x14++0x1
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x1
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if ((((per.w((ad:0x40003C00+0x1c)))&0x800)==0x00))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
elif ((((per.w((ad:0x40003C00+0x1c)))&0x830)==0x830))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Teansmit,Master/Receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
else
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave/Transmit,Slave/Receive,Master/Teansmit,Master/Receive"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "I2S Phillips,MSB justified,LSB justified,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,steady state clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,Not allowed"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length (number of bits per audio channel)" "16-bit,32-bit"
|
|
endif
|
|
if ((((per.w((ad:0x40003C00+0x1c)))&0xB00)==0xA00)||(((per.w((ad:0x40003C00+0x1c)))&0xB00)==0xB00))
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master Clock Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,(I2SDIV * 2)+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S Linear prescaler"
|
|
else
|
|
hgroup.word 0x20++0x1
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S Prescaler register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
elif (cpuis("STM32F101*C")||cpuis("STM32F101*D")||cpuis("STM32F101*E")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpu()=="STM32F101"||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
tree "SPI 2"
|
|
base ad:0x40003800
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F2*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,Not match"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800)
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
else
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "SPI 3"
|
|
base ad:0x40003C00
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F2*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,Not match"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
if (((per.w((ad:0x40003C00+0x00)))&0x800)==0x800)
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
else
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
elif (cpu()=="STM32F103T8"||cpuis("STM32F103*4")||cpuis("STM32F103*6")||cpuis("STM32F102*4")||cpuis("STM32F102*6")||cpuis("STM32F101T*")||cpuis("STM32F101*4")||cpuis("STM32F101*6")||cpuis("STM32F100*4")||cpuis("STM32F100*6")||cpuis("STM32F103TB"))
|
|
else
|
|
tree "SPI 2"
|
|
base ad:0x40003800
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " DFF ,Data Frame Format" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock=first data,Second clock=first data"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F2*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C"))
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "SPI Motorola,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 2. " SSOE ,SS Output Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx Buffer DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx Buffer DMA Enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 8. " FRE ,Frame error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "No fault,Fault"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Match,Not match"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
if (((per.w((ad:0x40003800+0x00)))&0x800)==0x800)
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
else
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DR ,Data register"
|
|
endif
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
sif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "I2C (Inter-Integrated Circuit)"
|
|
tree "I2C 1"
|
|
base ad:0x40005400
|
|
width 11.
|
|
if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2C_CR1,Control Register 1"
|
|
bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer"
|
|
bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Stop"
|
|
textline " "
|
|
bitfld.word 0x00 8. " START ,Start Generation" "No Start,Repeated"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus"
|
|
bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2C_CR1,Control Register 1"
|
|
bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer"
|
|
bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Released"
|
|
textline " "
|
|
bitfld.word 0x00 8. " START ,Start Generation" "No Start,Start"
|
|
bitfld.word 0x00 7. " NOSTRETCH ,Clock Stretching Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus"
|
|
bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2C_CR2,Control Register 2"
|
|
bitfld.word 0x00 12. " LAST ,DMA Last Transfer" "Not last,Last"
|
|
bitfld.word 0x00 11. " DMAEN ,DMA Requests Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ITBUFEN ,Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ITEVTEN ,Event Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " ITERREN ,Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F2*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F411*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F4*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,?..."
|
|
endif
|
|
if (((per.w((ad:0x40005400+0x08)))&0x8000)==0x8000)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_OAR1,Own Address Register 1"
|
|
bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit"
|
|
hexmask.word 0x00 0.--9. 1. " ADD ,Interface Address"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_OAR1,Own Address Register 1"
|
|
bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit"
|
|
hexmask.word.byte 0x00 1.--7. 0x02 " ADD ,Interface Address"
|
|
endif
|
|
if (((per.w((ad:0x40005400+0x0C)))&0x1)==0x1)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2C_OAR2,Own Address Register 2"
|
|
hexmask.word.byte 0x00 1.--7. 0x02 " ADD2 ,Interface Address"
|
|
bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2C_OAR2,Own Address Register 2"
|
|
bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2"
|
|
endif
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "I2C_DR,Data Register"
|
|
in
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "I2C_SR1,Status Register 1"
|
|
in
|
|
if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1)
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "I2C_SR2,Status Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register"
|
|
bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master"
|
|
else
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "I2C_SR2,Status Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register"
|
|
bitfld.word 0x00 7. " DUALF ,Dual Flag" "OAR1,OAR2"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SMBHOST ,SMBus Host Header" "No SMBus header,SMBus header"
|
|
bitfld.word 0x00 5. " SMBDEFAULT ,SMBus Device Default Address" "No SMBus address,SMBus address"
|
|
textline " "
|
|
bitfld.word 0x00 4. " GENCALL ,General Call Address" "No General Call,General Call"
|
|
bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master"
|
|
endif
|
|
if (((per.l(ad:0x40005400))&0x1)==0x1)
|
|
if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1)
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
textline " "
|
|
hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode"
|
|
else
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
endif
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "I2C_TRISE,TRISE Register"
|
|
bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*"))
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "I2C_FLTR,I2C FLTR register"
|
|
bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled"
|
|
bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40005400+0x18)))&0x1)==0x1)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
textline " "
|
|
hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
endif
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2C_TRISE,TRISE Register"
|
|
bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_FLTR,I2C FLTR register"
|
|
bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled"
|
|
bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpu()!="STM32F103T8"&&cpu()!="STM32F102C4"&&cpu()!="STM32F102R4"&&cpu()!="STM32F102C6"&&cpu()!="STM32F102R6"&&cpu()!="STM32F103C4"&&cpu()!="STM32F103R4"&&cpu()!="STM32F103T4"&&cpu()!="STM32F103C6"&&cpu()!="STM32F103R6"&&cpu()!="STM32F103T6"&&cpu()!="STM32F102C4"&&cpu()!="STM32F102R4"&&cpu()!="STM32F102C6"&&cpu()!="STM32F102R6"&&cpu()!="STM32F101T8"&&cpu()!="STM32F101C4"&&cpu()!="STM32F101R4"&&cpu()!="STM32F101T4"&&cpu()!="STM32F101C6"&&cpu()!="STM32F101R6"&&cpu()!="STM32F101T6"&&(!(cpuis("STM32F100*4")))&&(!(cpuis("STM32F100*6")))&&!cpuis("STM32F101TB")&&!cpuis("STM32F103TB")&&!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
tree "I2C 2"
|
|
base ad:0x40005800
|
|
width 11.
|
|
if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2C_CR1,Control Register 1"
|
|
bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer"
|
|
bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Stop"
|
|
textline " "
|
|
bitfld.word 0x00 8. " START ,Start Generation" "No Start,Repeated"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus"
|
|
bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2C_CR1,Control Register 1"
|
|
bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer"
|
|
bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Released"
|
|
textline " "
|
|
bitfld.word 0x00 8. " START ,Start Generation" "No Start,Start"
|
|
bitfld.word 0x00 7. " NOSTRETCH ,Clock Stretching Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus"
|
|
bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2C_CR2,Control Register 2"
|
|
bitfld.word 0x00 12. " LAST ,DMA Last Transfer" "Not last,Last"
|
|
bitfld.word 0x00 11. " DMAEN ,DMA Requests Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ITBUFEN ,Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ITEVTEN ,Event Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " ITERREN ,Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F2*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F411*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F4*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,?..."
|
|
endif
|
|
if (((per.w((ad:0x40005800+0x08)))&0x8000)==0x8000)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_OAR1,Own Address Register 1"
|
|
bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit"
|
|
hexmask.word 0x00 0.--9. 1. " ADD ,Interface Address"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_OAR1,Own Address Register 1"
|
|
bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit"
|
|
hexmask.word.byte 0x00 1.--7. 0x02 " ADD ,Interface Address"
|
|
endif
|
|
if (((per.w((ad:0x40005800+0x0C)))&0x1)==0x1)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2C_OAR2,Own Address Register 2"
|
|
hexmask.word.byte 0x00 1.--7. 0x02 " ADD2 ,Interface Address"
|
|
bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2C_OAR2,Own Address Register 2"
|
|
bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2"
|
|
endif
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "I2C_DR,Data Register"
|
|
in
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "I2C_SR1,Status Register 1"
|
|
in
|
|
if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1)
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "I2C_SR2,Status Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register"
|
|
bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master"
|
|
else
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "I2C_SR2,Status Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register"
|
|
bitfld.word 0x00 7. " DUALF ,Dual Flag" "OAR1,OAR2"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SMBHOST ,SMBus Host Header" "No SMBus header,SMBus header"
|
|
bitfld.word 0x00 5. " SMBDEFAULT ,SMBus Device Default Address" "No SMBus address,SMBus address"
|
|
textline " "
|
|
bitfld.word 0x00 4. " GENCALL ,General Call Address" "No General Call,General Call"
|
|
bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master"
|
|
endif
|
|
if (((per.l(ad:0x40005800))&0x1)==0x1)
|
|
if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1)
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
textline " "
|
|
hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode"
|
|
else
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
endif
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "I2C_TRISE,TRISE Register"
|
|
bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*"))
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "I2C_FLTR,I2C FLTR register"
|
|
bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled"
|
|
bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40005800+0x18)))&0x1)==0x1)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
textline " "
|
|
hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
endif
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2C_TRISE,TRISE Register"
|
|
bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_FLTR,I2C FLTR register"
|
|
bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled"
|
|
bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
tree "I2C 2"
|
|
base ad:0x40005C00
|
|
width 11.
|
|
if (((per.w((ad:0x40005C00+0x18)))&0x1)==0x1)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2C_CR1,Control Register 1"
|
|
bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer"
|
|
bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Stop"
|
|
textline " "
|
|
bitfld.word 0x00 8. " START ,Start Generation" "No Start,Repeated"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus"
|
|
bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "I2C_CR1,Control Register 1"
|
|
bitfld.word 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.word 0x00 13. " ALERT ,SMBus Alert" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 12. " PEC ,Packet Error Checking" "No transfer,Transfer"
|
|
bitfld.word 0x00 11. " POS ,Acknowledge/PEC Position" "Current byte,Next byte"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ACK ,Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " STOP ,Stop Generation" "No Stop,Released"
|
|
textline " "
|
|
bitfld.word 0x00 8. " START ,Start Generation" "No Start,Start"
|
|
bitfld.word 0x00 7. " NOSTRETCH ,Clock Stretching Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ENGC ,General Call Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " ENPEC ,PEC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENARP ,ARP Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SMBTYPE ,SMBus Type" "Device,Host"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SMBUS ,SMBus Mode" "I2C,SMBus"
|
|
bitfld.word 0x00 0. " PE ,Peripheral Enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2C_CR2,Control Register 2"
|
|
bitfld.word 0x00 12. " LAST ,DMA Last Transfer" "Not last,Last"
|
|
bitfld.word 0x00 11. " DMAEN ,DMA Requests Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " ITBUFEN ,Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ITEVTEN ,Event Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " ITERREN ,Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32L151C6-A")||cpuis("STM32L151C8-A")||cpuis("STM32L151CB-A")||cpuis("STM32L151R6-A")||cpuis("STM32L151R8-A")||cpuis("STM32L151RB-A")||cpuis("STM32L151V8-A")||cpuis("STM32L151VB-A")||cpuis("STM32L152C6-A")||cpuis("STM32L152C8-A")||cpuis("STM32L152CB-A")||cpuis("STM32L152R6-A")||cpuis("STM32L152R8-A")||cpuis("STM32L152RB-A")||cpuis("STM32L152V8-A")||cpuis("STM32L152VB-A")||cpuis("STM32L151CC")||cpuis("STM32L151RC-A")||cpuis("STM32L151UC")||cpuis("STM32L151VC-A")||cpuis("STM32L152CC")||cpuis("STM32L152RC-A")||cpuis("STM32L152VC-A")||cpuis("STM32L162RC")||cpuis("STM32L162RC-A")||cpuis("STM32L162VC")||cpuis("STM32L162VC-A")||cpuis("STM32L151QE")||cpuis("STM32L151RE")||cpuis("STM32L151VE")||cpuis("STM32L152QE")||cpuis("STM32L152RE")||cpuis("STM32L152VE")||cpuis("STM32L162RE")||cpuis("STM32L162VE")||cpuis("STM32L162ZE")||cpuis("STM32L151VD-X")||cpuis("STM32L152VD-X")||cpuis("STM32L162VD-X")||cpuis("STM32L100C6")||cpuis("STM32L100R8")||cpuis("STM32L100RB")||cpuis("STM32L100C6-A")||cpuis("STM32L100R8-A")||cpuis("STM32L100RB-A")||cpuis("STM32L100RC")
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32L15?R?")||cpuis("STM32L15?V?")||cpuis("STM32L15?Z?")||cpuis("STM32L15?Q?")||cpuis("STM32L15?C6")||cpuis("STM32L162?D"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F2*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F427*")||cpuis("STM32F429*")||cpuis("STM32F437*")||cpuis("STM32F439*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F411*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F4*"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,37 MHz,38 MHz,39 MHz,40 MHz,41 MHz,42 MHz,43 MHz,44 MHz,45 MHz,46 MHz,47 MHz,48 MHz,49 MHz,50 MHz,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--5. " FREQ ,Peripheral Clock Frequency" ",,2 MHz,3 MHz,4 MHz,5 MHz,6 MHz,7 MHz,8 MHz,9 MHz,10 MHz,11 MHz,12 MHz,13 MHz,14 MHz,15 MHz,16 MHz,17 MHz,18 MHz,19 MHz,20 MHz,21 MHz,22 MHz,23 MHz,24 MHz,25 MHz,26 MHz,27 MHz,28 MHz,29 MHz,30 MHz,31 MHz,32 MHz,33 MHz,34 MHz,35 MHz,36 MHz,?..."
|
|
endif
|
|
if (((per.w((ad:0x40005C00+0x08)))&0x8000)==0x8000)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_OAR1,Own Address Register 1"
|
|
bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit"
|
|
hexmask.word 0x00 0.--9. 1. " ADD ,Interface Address"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_OAR1,Own Address Register 1"
|
|
bitfld.word 0x00 15. " ADDMODE ,Addressing Mode" "7-bit,10-bit"
|
|
hexmask.word.byte 0x00 1.--7. 0x02 " ADD ,Interface Address"
|
|
endif
|
|
if (((per.w((ad:0x40005C00+0x0C)))&0x1)==0x1)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2C_OAR2,Own Address Register 2"
|
|
hexmask.word.byte 0x00 1.--7. 0x02 " ADD2 ,Interface Address"
|
|
bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2C_OAR2,Own Address Register 2"
|
|
bitfld.word 0x00 0. " ENDUAL ,Dual addressing mode enable" "Only OAR1,OAR1/OAR2"
|
|
endif
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "I2C_DR,Data Register"
|
|
in
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "I2C_SR1,Status Register 1"
|
|
in
|
|
if (((per.w((ad:0x40005C00+0x18)))&0x1)==0x1)
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "I2C_SR2,Status Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register"
|
|
bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master"
|
|
else
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "I2C_SR2,Status Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PEC ,Packet Error Checking Register"
|
|
bitfld.word 0x00 7. " DUALF ,Dual Flag" "OAR1,OAR2"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SMBHOST ,SMBus Host Header" "No SMBus header,SMBus header"
|
|
bitfld.word 0x00 5. " SMBDEFAULT ,SMBus Device Default Address" "No SMBus address,SMBus address"
|
|
textline " "
|
|
bitfld.word 0x00 4. " GENCALL ,General Call Address" "No General Call,General Call"
|
|
bitfld.word 0x00 2. " TRA ,Transmitter/Receiver" "Received,Transmitted"
|
|
textline " "
|
|
bitfld.word 0x00 1. " BUSY ,Bus Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0. " MSL ,Master/Slave" "Slave,Master"
|
|
endif
|
|
if (((per.l(ad:0x40005C00))&0x1)==0x1)
|
|
if (((per.w((ad:0x40005C00+0x18)))&0x1)==0x1)
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
textline " "
|
|
hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode"
|
|
else
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
endif
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "I2C_TRISE,TRISE Register"
|
|
bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*"))
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "I2C_FLTR,I2C FLTR register"
|
|
bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled"
|
|
bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40005C00+0x18)))&0x1)==0x1)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
textline " "
|
|
hexmask.word 0x00 0.--11. 1. " CCR ,Clock Control Register in Fast/Standard mode"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "I2C_CCR,Clock Control Register"
|
|
bitfld.word 0x00 15. " F/S ,Master Mode Selection" "Standard,Fast"
|
|
bitfld.word 0x00 14. " DUTY ,Fast Mode Duty Cycle" "tlow/thigh=2,tlow/thigh=16/9"
|
|
endif
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2C_TRISE,TRISE Register"
|
|
bitfld.word 0x00 0.--5. " TRISE ,Maximum Rise Time in Fast/Standard mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("STM32F401*")||cpuis("STM32F411*")||cpuis("STM32F42*")||cpuis("STM32F43*")||cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*"))
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_FLTR,I2C FLTR register"
|
|
bitfld.word 0x00 4. " ANOFF ,Analog noise filter OFF" "Enabled,Disabled"
|
|
bitfld.word 0x00 0.--3. " DNF ,Digital noise filter" "Disabled,1* TPCLK1,2* TPCLK1,3* TPCLK1,4* TPCLK1,5* TPCLK1,6* TPCLK1,7* TPCLK1,8* TPCLK1,9* TPCLK1,10* TPCLK1,11* TPCLK1,12* TPCLK1,13* TPCLK1,14* TPCLK1,15* TPCLK1"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
tree "USART 1"
|
|
base ad:0x40013800
|
|
width 12.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle"
|
|
bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
width 12.
|
|
line.long 0x08 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x08 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x08 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 12.
|
|
if (((per.l((ad:0x40013800+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
textline " "
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5"
|
|
bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
if (((per.l((ad:0x40013800+0x14)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "USART 2"
|
|
base ad:0x40004400
|
|
width 12.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle"
|
|
bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
width 12.
|
|
line.long 0x08 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x08 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x08 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 12.
|
|
if (((per.l((ad:0x40004400+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
textline " "
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5"
|
|
bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
if (((per.l((ad:0x40004400+0x14)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
sif (cpu()!="STM32F103T8"&&cpu()!="STM32F102C4"&&cpu()!="STM32F102R4"&&cpu()!="STM32F102C6"&&cpu()!="STM32F102R6"&&cpu()!="STM32F103C4"&&cpu()!="STM32F103R4"&&cpu()!="STM32F103T4"&&cpu()!="STM32F103C6"&&cpu()!="STM32F103R6"&&cpu()!="STM32F103T6"&&cpu()!="STM32F102C4"&&cpu()!="STM32F102R4"&&cpu()!="STM32F102C6"&&cpu()!="STM32F102R6"&&cpu()!="STM32F101T8"&&cpu()!="STM32F101C4"&&cpu()!="STM32F101R4"&&cpu()!="STM32F101T4"&&cpu()!="STM32F101C6"&&cpu()!="STM32F101R6"&&cpu()!="STM32F101T6"&&cpu()!="STM32F100C4"&&cpu()!="STM32F100C6"&&cpu()!="STM32F100R4"&&cpu()!="STM32F100R6"&&!cpuis("STM32F101TB")&&!cpuis("STM32F103TB"))
|
|
tree "USART 3"
|
|
base ad:0x40004800
|
|
width 12.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 9. " CTS ,CTS Flag" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle"
|
|
bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
width 12.
|
|
line.long 0x08 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x08 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x08 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 12.
|
|
if (((per.l((ad:0x40004800+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
textline " "
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,0.5,2,1.5"
|
|
bitfld.long 0x00 11. " CLKEN ,Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPOL ,Clock Polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock Phase" "1 clock=1 data,2 clock=1 data"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBCL ,Last Bit Clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 10. " CTSIE ,CTS Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x04 9. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RTSE ,RTS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
if (((per.l((ad:0x40004800+0x14)))&0x20)==0x20)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--4. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
textline " "
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F103*E")||cpuis("STM32F103*D")||cpuis("STM32F103*C")||cpuis("STM32F103*F")||cpuis("STM32F103*G")||cpuis("STM32F101*E")||cpuis("STM32F101*D")||cpuis("STM32F101*C")||cpuis("STM32F101*F")||cpuis("STM32F101*G")||cpu()=="STM32F103"||cpu()=="STM32F101"||cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F100RC")||cpuis("STM32F100RD")||cpuis("STM32F100RE")||cpuis("STM32F100VC")||cpuis("STM32F100VD")||cpuis("STM32F100VE")||cpuis("STM32F100ZC")||cpuis("STM32F100ZD")||cpuis("STM32F100ZE"))
|
|
tree "UART 4"
|
|
base ad:0x40004C00
|
|
width 12.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle"
|
|
bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
width 12.
|
|
line.long 0x08 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x08 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x08 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 12.
|
|
if (((per.l((ad:0x40004C00+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
textline " "
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,Reserved,2,Reseved"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 7. " DMAT ,DMA Enable Transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DMAR ,DMA Enable Receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "UART 5"
|
|
base ad:0x40005000
|
|
width 12.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "USART_SR,Status register"
|
|
bitfld.long 0x00 8. " LBD ,LIN Break Detection Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit Data Register Empty" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TC ,Transmission Complete" "Not completed,Complete"
|
|
bitfld.long 0x00 5. " RXNE ,Read Data Register Not Empty" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,IDLE line detected" "No idle,Idle"
|
|
bitfld.long 0x00 3. " ORE ,OverRun Error" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise Error Flag" "No error,Error"
|
|
bitfld.long 0x00 1. " FE ,Framing Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Parity Error" "No error,Error"
|
|
line.long 0x04 "USART_DR,Data register"
|
|
hexmask.long.word 0x04 0.--8. 1. " DR ,Data value"
|
|
width 12.
|
|
line.long 0x08 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x08 4.--15. 1. " DIV_MANTISSA ,Mantissa of DIV"
|
|
bitfld.long 0x08 0.--3. " DIV_FRACTION ,Fraction of DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 12.
|
|
if (((per.l((ad:0x40005000+0x0C)))&0x400)==0x400)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity Selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||(cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6")))
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 13. " UE ,USART Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,word length" "1Start;8Data;nStop,1Start;9Data;1Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Wake-up method" "Idle Line,Address Mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission Complete Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE Interrupt Enable" "Inhibited,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RWU ,Receiver Wake-Up" "Active,Mute"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SBK ,Send Break" "No break,Break"
|
|
textline " "
|
|
endif
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1,Reserved,2,Reseved"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN Break Detection Interrupt Enable" "Inhibited,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN Break Detection Length" "10 bit,11 bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADD ,Address of the USART node" "0h,1h,2h,3h,4h,5h,6h,7h,8h,9h,Ah,Bh,Ch,Dh,Eh,Fh"
|
|
line.long 0x04 "USART_CR3,Control register 3"
|
|
sif (!cpuis("STM32F100RC")&&!cpuis("STM32F100RD")&&!cpuis("STM32F100RE")&&!cpuis("STM32F100VC")&&!cpuis("STM32F100VD")&&!cpuis("STM32F100VE")&&!cpuis("STM32F100ZC")&&!cpuis("STM32F100ZD")&&!cpuis("STM32F100ZE"))
|
|
sif (cpuis("STM32F100*")||cpuis("STM32L162?D")||cpuis("STM32L152?D")||cpuis("STM32L151?D")||cpuis("STM32L151?C")||cpuis("STM32L152?C")||cpuis("STM32L151?6")||cpuis("STM32L152?6"))
|
|
bitfld.long 0x04 11. " ONEBITE ,One sample bit method enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 3. " HDSEL ,Half-Duplex Selection" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " IRLP ,IrDA Low-Power" "Normal,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IREN ,IrDA mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EIE ,Error Interrupt Enable" "Inhibited,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32F100*"))
|
|
tree "HDMI-CEC (Consumer Electronics Control)"
|
|
base ad:0x40007800
|
|
width 12.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CEC_CFGR,CEC configuration register"
|
|
bitfld.long 0x00 3. " BPEM ,Bit period error mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BTEM ,Bit timing error mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
line.long 0x04 "CEC_OAR,CEC own address register"
|
|
bitfld.long 0x04 0.--3. " OA[3:0] ,Own address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "CEC_PRES,CEC prescaler register"
|
|
hexmask.long.word 0x08 0.--13. 1. " PRESC[13:0] ,Prescaler counter value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CEC_ESR,CEC error status register"
|
|
bitfld.long 0x00 6. " TBTFE ,Tx block transfer finished error" "No error,Error"
|
|
bitfld.long 0x00 5. " LINE ,Line error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACKE ,Block acknowledge error" "No error,Error"
|
|
bitfld.long 0x00 3. " SBE ,Start bit error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RTBFE ,Rx block transfer finished error" "No error,Error"
|
|
bitfld.long 0x00 1. " BPE ,Bit period error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BTE ,Bit timing error" "No error,Error"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CEC_CSR,CEC control and status register"
|
|
bitfld.long 0x00 7. " RBTF ,Rx byte/block transfer finished" "Not finished,Finished"
|
|
bitfld.long 0x00 6. " RERR ,Rx error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " REOM ,Rx end of message" "Not received,Received"
|
|
bitfld.long 0x00 4. " RSOM ,Rx start of message" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TBTRF ,Tx byte transfer request or block transfer finished" "No requested/Not finished,Requested/Finished"
|
|
bitfld.long 0x00 2. " TERR ,Tx error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TEOM ,Tx end of message" "Not ended,Ended"
|
|
bitfld.long 0x00 0. " TSOM ,Tx start of message" "Not started,Started"
|
|
line.long 0x04 "CEC_TXD,CEC Tx data register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXD[7:0] ,Tx Data register"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CEC_RXD,CEC Rx data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXD[7:0] ,Rx data register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*"))
|
|
tree "USB_OTG_FS (USB on-the-go full-speed)"
|
|
base ad:0x50000000
|
|
width 17.
|
|
tree "OTG_FS Global Registers"
|
|
if (((per.l((ad:0x50000000+0x14)))&0x1)==0x1)
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "OTG_FS_GOTGCTL,OTG_FS Control And Status Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x00 20. " OTGVER ,OTG version" "ver 1.3,ver 2.0"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 18. " ASVLD ,A-session valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 17. " DBCT ,Long/short debounce time" "Long,Short"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-Device,B-Device"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x00 12. " EHEN ,Embedded host enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " HSHNPEN ,Host set HNP enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
textline " "
|
|
bitfld.long 0x00 5. " AVALOVAL ,A-peripheral session valid override value" "0,1"
|
|
bitfld.long 0x00 4. " AVALOEN ,A-peripheral session valid override enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VBVALOVAL ,VBUS valid override value" "0,1"
|
|
bitfld.long 0x00 2. " VBVALOEN ,VBUS valid override enable" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "OTG_FS_GOTGINT,OTG_FS Interrupt Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
eventfld.long 0x04 20. " IDCHNG ,Change in the value of the ID input pin" "Not changed,Changed"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x04 19. " DBCDNE ,Debounce done" "Not done,Done"
|
|
eventfld.long 0x04 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x04 17. " HNGDET ,Host negotiation detected" "Not detected,Detected"
|
|
eventfld.long 0x04 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x04 8. " SRSSCHG ,Session request success status change" "Not changed,Changed"
|
|
eventfld.long 0x04 2. " SEDET ,Session end detected" "Not detected,Detected"
|
|
line.long 0x08 "OTG_FS_GAHBCFG,OTG_FS AHB Configuration Register"
|
|
bitfld.long 0x08 8. " PTXFELVL ,Periodic TxFIFO empty level" "Half empty,Empty"
|
|
textline " "
|
|
sif (cpu()=="STM32F4*")
|
|
bitfld.long 0x08 7. " TXFELVL ,TxFIFO empty level" "Half empty,Empty"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0. " GINT ,Global interrupt mask" "Masked,Unmasked"
|
|
line.long 0x0C "OTG_FS_GUSBCFG,OTG_FS USB Configuration Register"
|
|
sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
bitfld.long 0x0C 31. " CTXPKT ,Corrupt Tx packet" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 30. " FDMOD ,Force device mode" "Normal,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " FHMOD ,Force host mode" "Normal,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " HNPCAP ,HNP-capable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " SRPCAP ,SRP-capable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
bitfld.long 0x0C 6. " PHYSEL ,Full Speed serial transceiver select" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "OTG_FS_GRSTCTL,OTG_FS Reset Register"
|
|
rbitfld.long 0x10 31. " AHBIDL ,AHB master idle" "Low,High"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x10 6.--10. " TXFNUM ,TxFIFO number" "Non-periodic,Periodic,,,,,,,,,,,,,,,All,?..."
|
|
else
|
|
bitfld.long 0x10 6.--10. " TXFNUM ,TxFIFO number" "Non-periodic,Periodic,2,3,4,5,6,7,8,9,10,11,12,13,14,15,All,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 5. " TXFFLSH ,TxFIFO flush" "Single,All transmit"
|
|
bitfld.long 0x10 4. " RXFFLSH ,RxFIFO flush" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 2. " FCRST ,Host frame counter reset" "No reset,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x10 1. " PSRST ,Partial soft reset" "No reset,Reset"
|
|
else
|
|
bitfld.long 0x10 1. " HSRST ,HCLK soft reset" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 0. " CSRST ,Core soft reset" "No reset,Reset"
|
|
line.long 0x14 "OTG_FS_GINTSTS,OTG_FS Core Interrupt Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rbitfld.long 0x14 0. " CMOD ,Current mode of operation" "Device mode,Host mode"
|
|
else
|
|
bitfld.long 0x14 0. " CMOD ,Current mode of operation" "Device mode,Host mode"
|
|
endif
|
|
eventfld.long 0x14 31. " WKUPINT ,Resume/remote wakeup detected interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x14 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x14 29. " DISCINT ,Disconnect detected interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x14 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
eventfld.long 0x14 27. " LPMINT ,LPM interrupt" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x14 26. " PTXFE ,Periodic TxFIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x14 25. " HCINT ,Host channels interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x14 24. " HPRTINT ,Host port interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x14 21. " IPXFR ,Incomplete periodic transfer" "No interrupt,Interrupt"
|
|
sif (cpuis("STM32F4*"))||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rbitfld.long 0x14 5. " NPTXFE ,Non-periodic TxFIFO empty" "Not empty,Empty"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x14 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
textline " "
|
|
eventfld.long 0x14 3. " SOF ,Start of frame" "Not started,Started"
|
|
rbitfld.long 0x14 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x14 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
line.long 0x18 "OTG_FS_GINTMSK,OTG_FS Interrupt Mask Register"
|
|
bitfld.long 0x18 31. " WUIM ,Resume/remote wakeup detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 30. " SRQIM ,Session request/new session detected interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
bitfld.long 0x18 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked"
|
|
else
|
|
bitfld.long 0x18 29. " DISCINT ,Disconnect detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked"
|
|
endif
|
|
textline " "
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x18 27. " LPMINTM ,LPM interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 26. " PTXFEM ,Periodic TxFIFO empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 25. " HCIM ,Host channels interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
rbitfld.long 0x18 24. " PRTIM ,Host port interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 21. " IPXFRM ,Incomplete periodic transfer mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x18 5. " NPTXFEM ,Non-periodic TxFIFO empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x18 3. " SOFM ,Start of frame mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x18 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "OTG_FS_GRXSTSR,OTG_FS Receive Status Debug Read Register"
|
|
bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",,IN data packet received,IN transfer completed,,Data toggle error,,Channel halted,?..."
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA1,?..."
|
|
else
|
|
bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA1,DATA2,MDATA"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count"
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "OTG_FS_GRXSTSP,OTG Status Read And Pop Register"
|
|
in
|
|
else
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "OTG_FS_GOTGCTL,OTG_FS Control And Status Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x00 20. " OTGVER ,OTG version" "ver 1.3,ver 2.0"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " BSVLD ,B-session valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 16. " CIDSTS ,Connector ID status" "A-Device,B-Device"
|
|
textline " "
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x00 12. " EHEN ,Embedded host enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " DHNPEN ,Device HNP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HNPRQ ,HNP request" "Not requested,Requested"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " HNGSCS ,Host negotiation success" "Failed,Successful"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x00 7. " BVALOVAL ,B-peripheral session valid override value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BVALOEN ,B-peripheral session valid override enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 1. " SRQ ,Session request" "Not requested,Requested"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " SRQSCS ,Session request success" "Failed,Successful"
|
|
line.long 0x04 "OTG_FS_GOTGINT,OTG_FS Interrupt Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
eventfld.long 0x04 20. " IDCHNG ,Change in the value of the ID input pin" "Not changed,Changed"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x04 18. " ADTOCHG ,A-device timeout change" "Not changed,Changed"
|
|
eventfld.long 0x04 17. " HNGDET ,Host negotiation detected" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x04 9. " HNSSCHG ,Host negotiation success status change" "Not changed,Changed"
|
|
eventfld.long 0x04 8. " SRSSCHG ,Session request success status change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x04 2. " SEDET ,Session end detected" "Not detected,Detected"
|
|
line.long 0x08 "OTG_FS_GAHBCFG,OTG_FS AHB Configuration Register"
|
|
bitfld.long 0x08 7. " TXFELVL ,TxFIFO empty level" "Half empty,Empty"
|
|
bitfld.long 0x08 0. " GINTMSK ,Global interrupt mask" "Masked,Unmasked"
|
|
line.long 0x0C "OTG_FS_GUSBCFG,OTG_FS USB Configuration Register"
|
|
sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
bitfld.long 0x0C 31. " CTXPKT ,Corrupt Tx packet" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 30. " FDMOD ,Force device mode" "Normal,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " FHMOD ,Force host mode" "Normal,Forced"
|
|
sif (!cpuis("STM32F2*")&&!cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x0C 14. " NPTXRWEN , non-periodic TxFIFO rewind enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 10.--13. " TRDT ,USB turnaround time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 9. " HNPCAP ,HNP-capable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " SRPCAP ,SRP-capable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
bitfld.long 0x0C 6. " PHYSEL ,Full Speed serial transceiver select" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 0.--2. " TOCAL ,FS timeout calibration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "OTG_FS_GRSTCTL,OTG_FS Reset Register"
|
|
rbitfld.long 0x10 31. " AHBIDL ,AHB master idle" "Low,High"
|
|
bitfld.long 0x10 6.--10. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x10 5. " TXFFLSH ,TxFIFO flush" "Single,All transmit"
|
|
bitfld.long 0x10 4. " RXFFLSH ,RxFIFO flush" "Low,High"
|
|
textline " "
|
|
sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x10 1. " PSRST ,Partial soft reset" "No reset,Reset"
|
|
else
|
|
bitfld.long 0x10 1. " HSRST ,HCLK soft reset" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 0. " CSRST ,Core soft reset" "No reset,Reset"
|
|
line.long 0x14 "OTG_FS_GINTSTS,OTG_FS Core Interrupt Register"
|
|
rbitfld.long 0x14 0. " CMOD ,Current mode of operation" "Device mode,Host mode"
|
|
eventfld.long 0x14 31. " WKUPINT ,Resume/remote wakeup detected interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x14 30. " SRQINT ,Session request/new session detected interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x14 28. " CIDSCHG ,Connector ID status change" "Not changed,Changed"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
textline " "
|
|
eventfld.long 0x14 27. " LPMINT ,LPM interrupt" "Not occurred,Occurred"
|
|
endif
|
|
sif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textline " "
|
|
eventfld.long 0x14 23. " RSTDET ,Reset detected interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x14 21. " INCOMPISOOUT ,Incomplete isochronous OUT transfer" "No interrupt,Interrupt"
|
|
eventfld.long 0x14 20. " IISOIXFR ,Incomplete isochronous IN transfer" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x14 19. " OEPINT ,OUT endpoint interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x14 18. " IEPINT ,IN endpoint interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x14 15. " EOPF ,End of periodic frame interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x14 14. " ISOODRP ,Isochronous OUT packet dropped interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x14 13. " ENUMDNE ,Enumeration done" "Not done,Done"
|
|
eventfld.long 0x14 12. " USBRST ,USB reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x14 11. " USBSUSP ,USB suspend" "Not suspended,Suspended"
|
|
eventfld.long 0x14 10. " ESUSP ,Early suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
rbitfld.long 0x14 7. " GONAKEFF ,Global OUT NAK effective" "Low,High"
|
|
rbitfld.long 0x14 6. " GINAKEFF ,Global IN non-periodic NAK effective" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x14 4. " RXFLVL ,RxFIFO non-empty" "Empty,Not empty"
|
|
eventfld.long 0x14 3. " SOF ,Start of frame" "Not started,Started"
|
|
textline " "
|
|
rbitfld.long 0x14 2. " OTGINT ,OTG interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x14 1. " MMIS ,Mode mismatch interrupt" "No interrupt,Interrupt"
|
|
line.long 0x18 "OTG_FS_GINTMSK,OTG_FS Interrupt Mask Register"
|
|
bitfld.long 0x18 31. " WUIM ,Resume/remote wakeup detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 30. " SRQIM ,Session request/new session detected interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x18 29. " DISCINT ,Disconnect detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 28. " CIDSCHGM ,Connector ID status change mask" "Masked,Unmasked"
|
|
textline " "
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x18 27. " LPMINTM ,LPM interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x18 23. " RSTDETM ,Reset detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 21. " IISOOXFRM ,Incomplete isochronous OUT transfer mask" "Masked,Unmasked"
|
|
elif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
bitfld.long 0x18 21. " IISOOXFRM ,Incomplete isochronous OUT transfer mask" "Masked,Unmasked"
|
|
else
|
|
bitfld.long 0x18 23. " RSTDETM ,Reset detected interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 22. " FSUSPM ,Data fetch suspended mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 21. " IISOOXFRM ,Incomplete isochronous OUT transfer mask" "Masked,Unmasked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 20. " IISOIXFRM ,Incomplete isochronous IN transfer mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 19. " OEPINT ,OUT endpoints interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x18 18. " IEPINT ,IN endpoints interrupt mask" "Masked,Unmasked"
|
|
sif !cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
textline " "
|
|
bitfld.long 0x18 17. " EPMISM ,Endpoint mismatch interrupt mask" "Masked,Unmasked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 15. " EOPFM ,End of periodic frame interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 14. " ISOODRPM ,Isochronous OUT packet dropped interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ENUMDNEM ,Enumeration done mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 12. " USBRST ,USB reset mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x18 11. " USBSUSPM ,USB suspend mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 10. " ESUSPM ,Early suspend mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x18 7. " GONAKEFFM ,Global OUT NAK effective mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 6. " GINAKEFFM ,Global non-periodic IN NAK effective mask" "Masked,Unmasked"
|
|
textline " "
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
bitfld.long 0x18 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked"
|
|
else
|
|
bitfld.long 0x18 5. " NPTXFEM ,Non-periodic TxFIFO empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 4. " RXFLVLM ,Receive FIFO non-empty mask" "Masked,Unmasked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x18 3. " SOFM ,Start of frame mask" "Masked,Unmasked"
|
|
bitfld.long 0x18 2. " OTGINT ,OTG interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x18 1. " MMISM ,Mode mismatch interrupt mask" "Masked,Unmasked"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "OTG_FS_GRXSTSR,OTG_FS Receive Status Debug Read Register"
|
|
bitfld.long 0x00 21.--24. " FRMNUM ,Frame number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F412*")
|
|
bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",Global OUT NAK,OUT data packet received,OUT transfer completed,SETUP ransaction completed,,SETUP data packet received,?..."
|
|
else
|
|
bitfld.long 0x00 17.--20. " PKTSTS ,Packet status" ",Global OUT NAK,OUT data packet received,OUT transfer completed,Transaction completed,,SETUP data packet received,?..."
|
|
endif
|
|
textline " "
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA1,?..."
|
|
else
|
|
bitfld.long 0x00 15.--16. " DPID ,Data PID" "DATA0,DATA1,DATA2,MDATA"
|
|
endif
|
|
hexmask.long.word 0x00 4.--14. 1. " BCNT ,Byte count"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "OTG_FS_GRXSTSP,OTG Status Read And Pop Register"
|
|
in
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "OTG_FS_GRXFSIZ,OTG_FS Receive FIFO Size Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXFD ,RxFIFO depth"
|
|
if (((per.l((ad:0x50000000+0x14)))&0x1)==0x1)
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "OTG_FS_HNPTXFSIZ,OTG_FS Host Non-periodic Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NPTXFD ,Non-periodic TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " NPTXFSA ,Non-periodic transmit RAM start address"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "OTG_FS_HNPTXSTS,OTG_FS Non-periodic Transmit FIFO/queue Status Register"
|
|
bitfld.long 0x00 27.--30. " NPTXQTOP[30:27] ,Top of the nonperiodic transmit request queue - CH/EP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " NPTXQTOP[26:25] ,Top of the nonperiodic transmit request queue" "IN/OUT Token,Zero-length,,Channel halt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NPTXQTOP[24] ,Top of the nonperiodic transmit request queue" "Not terminated,Terminated"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " NPTQXSAV ,Non-periodic transmit request queue space available"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " NPTXFSAV ,Non-periodic TxFIFO space available"
|
|
else
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "OTG_FS_DIEPTXF0,Endpoint 0 Transmit FIFO Size"
|
|
hexmask.long.word 0x00 16.--31. 1. " TX0FD ,Endpoint 0 TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " TX0FSA ,Endpoint 0 transmit RAM start address"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "OTG_FS_HNPTXSTS,OTG_FS Non-periodic Transmit FIFO/queue Status Register"
|
|
endif
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "OTG_FS_GCCFG,OTG_FS General Core Configuration Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 21. " VBDEM ,USB VBUS detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SDEN ,Secondary detection mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PDEN ,Primary detection mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DCDEN ,Data contact detection mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BCDEN ,Battery charging detector enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F446*")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x00 21. " VBDEN ,USB VBUS detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
bitfld.long 0x00 21. " NOVBUSSENS ,VBUS sensing disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " SOFOUTEN ,SOF output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " VBUSBSEN ,Enable the VBUS sensing B device" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VBUSASEN ,Enable the VBUS sensing A device" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F2*"))
|
|
bitfld.long 0x00 16. " PWRDWN ,Power down" "Not active,Active"
|
|
else
|
|
bitfld.long 0x00 16. " PWRDWN ,Power down" "Powered down,Not powered down"
|
|
endif
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textline " "
|
|
bitfld.long 0x00 3. " PS2DET ,DM pull-up detection status" "Normal,PS2/proprietary"
|
|
bitfld.long 0x00 2. " SDET ,Secondary detection status" "CDP,DCP"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDET ,Primary detection status" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DCDET ,Data contact detection" "Not detected,Detected"
|
|
endif
|
|
line.long 0x04 "OTG_FS_CID,OTG_FS Core ID Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
if (((per.l((ad:0x50000000+0x14)))&0x1)==0x1)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "OTG_GLPMCFG,OTG Core LPM Configuration Register"
|
|
bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled"
|
|
rbitfld.long 0x00 25.--27. " LPMRCNTSTS ,LPM retry count status" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SNDLPM ,Send LPM transaction" "Sending,Cleared"
|
|
bitfld.long 0x00 21.--23. " LPMRCNT ,LPM retry count" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 17.--20. " LPMCHIDX ,LPM Channel Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 16. " L1RSMOK ,Sleep State Resume OK" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "Not in L1,In L1"
|
|
rbitfld.long 0x00 13.--14. " LPMRST ,LPM response" "ERROR,STALL,NYET,ACK"
|
|
textline " "
|
|
bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "75,100,150,250,350,450,950,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " L1SSEN ,L1 Shallow Sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " REMWAKE ,bRemoteWake value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "125,150,200,300,400,500,1000,2000,3000,4000,5000,6000,7000,8000,9000,10000"
|
|
bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "OTG_GLPMCFG,OTG Core LPM Configuration Register"
|
|
bitfld.long 0x00 28. " ENBESL ,Enable best effort service latency" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " L1RSMOK ,Sleep State Resume OK" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SLPSTS ,Port sleep status" "Not in L1,In L1"
|
|
rbitfld.long 0x00 13.--14. " LPMRST ,LPM response" "ERROR,STALL,NYET,ACK"
|
|
textline " "
|
|
bitfld.long 0x00 12. " L1DSEN ,L1 deep sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " BESLTHRS ,BESL threshold" "75,100,150,250,350,450,950,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " L1SSEN ,L1 Shallow Sleep enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " REMWAKE ,bRemoteWake value" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--5. " BESL ,Best effort service latency" "125,150,200,300,400,500,1000,2000,3000,4000,5000,6000,7000,8000,9000,10000"
|
|
bitfld.long 0x00 1. " LPMACK ,LPM token acknowledge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "OTG_FS_HPTXFSIZ,OTG_FS Host Periodic Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PTXFSIZ ,Host periodic TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " PTXSA ,Host periodic TxFIFO start address"
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")&&!cpuis("STM32F446*")&&!cpuis("STM32F412*"))
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF1,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF2,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF3,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
elif cpuis("STM32F446*")||cpuis("STM32F412*")
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF1,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF2,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF3,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF4,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF5,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF1,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF2,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF3,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTXF4,OTG_FS Device IN Endpoint Transmit FIFO Size Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " INEPTXFD ,IN endpoint TxFIFO depth"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTXSA ,IN endpoint FIFOx transmit RAM start address"
|
|
endif
|
|
tree.end
|
|
tree "Host mode registers"
|
|
if (((per.l((ad:0x50000000+0x14)))&0x1)==0x1)
|
|
group.long 0x400++0x07
|
|
line.long 0x00 "OTG_FS_HCFG,OTG_FS Host Configuration Register"
|
|
rbitfld.long 0x00 2. " FSLSS ,FS- and LS-only support" "Not supported,Supported"
|
|
bitfld.long 0x00 0.--1. " FSLSPCS ,FS/LS PHY clock select" ",48 MHz,6 MHz,?..."
|
|
line.long 0x04 "OTG_FS_HFIR,OTG_FS Host Frame Interval Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x04 16. " RLDCTRL ,Reload control" "Cannot reload,Can Reload"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x04 0.--15. 1. " FRIVL ,Frame interval"
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "OTG_FS_HFNUM,OTG_FS Host Frame Number/Frame Time Remaining Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " FTREM ,Frame time remaining"
|
|
hexmask.long.word 0x00 0.--15. 1. " FRNUM ,Frame number"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "OTG_FS_HPTXSTS,OTG_FS_Host Periodic Transmit FIFO/Queue Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PTXQTOP ,Top of the periodic transmit request queue"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PTXQSAV ,Periodic transmit request queue space available"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " PTXFSAVL ,Periodic transmit data FIFO space available"
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "OTG_FS_HAINT,OTG_FS Host All Channels Interrupt Register"
|
|
sif !cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
bitfld.long 0x00 15. " HAINT[15] ,Channel 15 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " HAINT[14] ,Channel 14 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HAINT[13] ,Channel 13 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " HAINT[12] ,Channel 12 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " HAINT[11] ,Channel 11 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " HAINT[10] ,Channel 10 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HAINT[9] ,Channel 9 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " HAINT[8] ,Channel 8 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HAINT[7] ,Channel 7 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " HAINT[6] ,Channel 6 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HAINT[5] ,Channel 5 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " HAINT[4] ,Channel 4 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HAINT[3] ,Channel 3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " HAINT[2] ,Channel 2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HAINT[1] ,Channel 1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " HAINT[0] ,Channel 0 interrupt" "No interrupt,Interrupt"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "OTG_FS_HAINTMSK,OTG_FS Host All Channels Interrupt Mask Register"
|
|
sif !cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
bitfld.long 0x00 15. " HAINTM[15] ,Channel interrupt mask 15" "Masked,Unmasked"
|
|
bitfld.long 0x00 14. " HAINTM[14] ,Channel interrupt mask 14" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HAINTM[13] ,Channel interrupt mask 13" "Masked,Unmasked"
|
|
bitfld.long 0x00 12. " HAINTM[12] ,Channel interrupt mask 12" "Masked,Unmasked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " HAINTM[11] ,Channel interrupt mask 11" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " HAINTM[10] ,Channel interrupt mask 10" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HAINTM[9] ,Channel interrupt mask 9" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " HAINTM[8] ,Channel interrupt mask 8" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HAINTM[7] ,Channel interrupt mask 7" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " HAINTM[6] ,Channel interrupt mask 6" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HAINTM[5] ,Channel interrupt mask 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " HAINTM[4] ,Channel interrupt mask 4" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HAINTM[3] ,Channel interrupt mask 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " HAINTM[2] ,Channel interrupt mask 2" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HAINTM[1] ,Channel interrupt mask 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " HAINTM[0] ,Channel interrupt mask 0" "Masked,Unmasked"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "OTG_FS_HPRT,OTG_FS Host Port Control And Status Register"
|
|
rbitfld.long 0x00 17.--18. " PSPD ,Port speed" ",Full,Low,?..."
|
|
bitfld.long 0x00 13.--16. " PTCTL ,Port test control" "Disabled,J mode,K mode,SE0_NAK mode,Packet mode,Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " PPWR ,Port power" "Off,On"
|
|
rbitfld.long 0x00 11. " PLSTS[1] ,Port line status (Logic level of OTG_FS_FS_DP)" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " PLSTS[0] ,Port line status (Logic level of OTG_FS_FS_DM)" "Low,High"
|
|
bitfld.long 0x00 8. " PRST ,Port reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PSUSP ,Port suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " PRES ,Port resume" "Not resumed,Resumed"
|
|
textline " "
|
|
eventfld.long 0x00 5. " POCCHNG ,Port overcurrent change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " POCA ,Port overcurrent active" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PENCHNG ,Port enable/disable change" "Not changed,Changed"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
eventfld.long 0x00 2. " PENA ,Port enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 2. " PENA ,Port enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 1. " PCDET ,Port connect detected" "Not detected,Detected"
|
|
rbitfld.long 0x00 0. " PCSTS ,Port connect status" "Not device,Device"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR0,OTG_FS Host Channel-0 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x500+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT0,OTG_FS Host Channel-0 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK0,OTG_FS Host Channel-0 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ0,OTG_FS Host Channel-0 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR1,OTG_FS Host Channel-1 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x520+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT1,OTG_FS Host Channel-1 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK1,OTG_FS Host Channel-1 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ1,OTG_FS Host Channel-1 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR2,OTG_FS Host Channel-2 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x540+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT2,OTG_FS Host Channel-2 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK2,OTG_FS Host Channel-2 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ2,OTG_FS Host Channel-2 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR3,OTG_FS Host Channel-3 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x560+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT3,OTG_FS Host Channel-3 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK3,OTG_FS Host Channel-3 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ3,OTG_FS Host Channel-3 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR4,OTG_FS Host Channel-4 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x580+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT4,OTG_FS Host Channel-4 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK4,OTG_FS Host Channel-4 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ4,OTG_FS Host Channel-4 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR5,OTG_FS Host Channel-5 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x5A0+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT5,OTG_FS Host Channel-5 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK5,OTG_FS Host Channel-5 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ5,OTG_FS Host Channel-5 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR6,OTG_FS Host Channel-6 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x5C0+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT6,OTG_FS Host Channel-6 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK6,OTG_FS Host Channel-6 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ6,OTG_FS Host Channel-6 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR7,OTG_FS Host Channel-7 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x5E0+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT7,OTG_FS Host Channel-7 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK7,OTG_FS Host Channel-7 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ7,OTG_FS Host Channel-7 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR8,OTG_FS Host Channel-8 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x600+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT8,OTG_FS Host Channel-8 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK8,OTG_FS Host Channel-8 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ8,OTG_FS Host Channel-8 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR9,OTG_FS Host Channel-9 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x620+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT9,OTG_FS Host Channel-9 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK9,OTG_FS Host Channel-9 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ9,OTG_FS Host Channel-9 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR10,OTG_FS Host Channel-10 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x640+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT10,OTG_FS Host Channel-10 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK10,OTG_FS Host Channel-10 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ10,OTG_FS Host Channel-10 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR11,OTG_FS Host Channel-11 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x660+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT11,OTG_FS Host Channel-11 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK11,OTG_FS Host Channel-11 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ11,OTG_FS Host Channel-11 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,,DATA1,SETUP/-"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,SETUP/-"
|
|
else
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR0,OTG_FS Host Channel-0 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x500+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT0,OTG_FS Host Channel-0 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK0,OTG_FS Host Channel-0 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ0,OTG_FS Host Channel-0 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR1,OTG_FS Host Channel-1 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x520+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT1,OTG_FS Host Channel-1 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK1,OTG_FS Host Channel-1 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ1,OTG_FS Host Channel-1 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR2,OTG_FS Host Channel-2 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x540+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT2,OTG_FS Host Channel-2 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK2,OTG_FS Host Channel-2 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ2,OTG_FS Host Channel-2 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR3,OTG_FS Host Channel-3 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x560+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT3,OTG_FS Host Channel-3 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK3,OTG_FS Host Channel-3 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ3,OTG_FS Host Channel-3 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR4,OTG_FS Host Channel-4 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x580+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT4,OTG_FS Host Channel-4 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK4,OTG_FS Host Channel-4 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ4,OTG_FS Host Channel-4 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR5,OTG_FS Host Channel-5 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x5A0+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT5,OTG_FS Host Channel-5 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK5,OTG_FS Host Channel-5 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ5,OTG_FS Host Channel-5 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR6,OTG_FS Host Channel-6 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x5C0+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT6,OTG_FS Host Channel-6 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK6,OTG_FS Host Channel-6 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ6,OTG_FS Host Channel-6 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "OTG_FS_HCCHAR7,OTG_FS Host Channel-7 Characteristics Register"
|
|
bitfld.long 0x00 31. " CHENA ,Channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CHDIS ,Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODDFRM ,Odd frame" "Even,Odd"
|
|
hexmask.long.word 0x00 22.--28. 0x40 " DAD ,Device address"
|
|
sif (cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MCNT ,Multicount" ",1 transaction,2 transactions,3 transactions"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " LSDEV ,Low-speed device" "No Low-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
bitfld.long 0x00 11.--14. " EPNUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
group.long (0x5E0+0x08)++0x0B
|
|
line.long 0x00 "OTG_FS_HCINT7,OTG_FS Host Channel-7 Interrupt Register"
|
|
eventfld.long 0x00 10. " DTERR ,Data toggle error" "No error,Error"
|
|
eventfld.long 0x00 9. " FRMOR ,Frame overrun" "No overrun,Overrun"
|
|
textline " "
|
|
eventfld.long 0x00 8. " BBERR ,Babble error" "No error,Error"
|
|
eventfld.long 0x00 7. " TXERR ,Transaction error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ACK ,ACK response received/transmitted interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " NAK ,NAK response received interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STALL ,STALL response received interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CHH ,Channel halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed" "Not completed,Completed"
|
|
line.long 0x04 "OTG_FS_HCINTMSK7,OTG_FS Host Channel-7 Interrupt Mask Register"
|
|
bitfld.long 0x04 10. " DTERRM ,Data toggle error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " FRMORM ,Frame overrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BBERRM ,Babble error mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " TXERRM ,Transaction error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NYET ,Response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " ACKM ,ACK response received/transmitted interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " NAKM ,NAK response received interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " STALLM ,STALL response received interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHHM ,Channel halted mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed mask" "Masked,Unmasked"
|
|
line.long 0x08 "OTG_FS_HCTSIZ7,OTG_FS Host Channel-7 Transfer Size Register"
|
|
bitfld.long 0x08 29.--30. " DPID ,Data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x08 19.--28. 1. " PKTCNT ,Packet count"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
else
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "OTG_FS_HCFG,OTG_FS Host Configuration Register"
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "OTG_FS_HFIR,OTG_FS Host Frame Interval Register"
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "OTG_FS_HFNUM,OTG_FS Host Frame Number/Frame Time Remaining Register"
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "OTG_FS_HPTXSTS,OTG_FS_Host Periodic Transmit FIFO/Queue Status Register"
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "OTG_FS_HAINT,OTG_FS Host All Channels Interrupt Register"
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "OTG_FS_HAINTMSK,OTG_FS Host All Channels Interrupt Mask Register"
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "OTG_FS_HPRT,OTG_FS Host Port Control And Status Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
hgroup.long 0x500++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR0,OTG_FS Host Channel-0 Characteristics Register"
|
|
hgroup.long (0x500+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT0,OTG_FS Host Channel-0 Interrupt Register"
|
|
hgroup.long (0x500+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK0,OTG_FS Host Channel-0 Interrupt Mask Register"
|
|
hgroup.long (0x500+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ0,OTG_FS Host Channel-0 Transfer Size Register"
|
|
hgroup.long 0x520++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR1,OTG_FS Host Channel-1 Characteristics Register"
|
|
hgroup.long (0x520+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT1,OTG_FS Host Channel-1 Interrupt Register"
|
|
hgroup.long (0x520+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK1,OTG_FS Host Channel-1 Interrupt Mask Register"
|
|
hgroup.long (0x520+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ1,OTG_FS Host Channel-1 Transfer Size Register"
|
|
hgroup.long 0x540++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR2,OTG_FS Host Channel-2 Characteristics Register"
|
|
hgroup.long (0x540+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT2,OTG_FS Host Channel-2 Interrupt Register"
|
|
hgroup.long (0x540+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK2,OTG_FS Host Channel-2 Interrupt Mask Register"
|
|
hgroup.long (0x540+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ2,OTG_FS Host Channel-2 Transfer Size Register"
|
|
hgroup.long 0x560++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR3,OTG_FS Host Channel-3 Characteristics Register"
|
|
hgroup.long (0x560+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT3,OTG_FS Host Channel-3 Interrupt Register"
|
|
hgroup.long (0x560+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK3,OTG_FS Host Channel-3 Interrupt Mask Register"
|
|
hgroup.long (0x560+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ3,OTG_FS Host Channel-3 Transfer Size Register"
|
|
hgroup.long 0x580++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR4,OTG_FS Host Channel-4 Characteristics Register"
|
|
hgroup.long (0x580+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT4,OTG_FS Host Channel-4 Interrupt Register"
|
|
hgroup.long (0x580+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK4,OTG_FS Host Channel-4 Interrupt Mask Register"
|
|
hgroup.long (0x580+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ4,OTG_FS Host Channel-4 Transfer Size Register"
|
|
hgroup.long 0x5A0++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR5,OTG_FS Host Channel-5 Characteristics Register"
|
|
hgroup.long (0x5A0+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT5,OTG_FS Host Channel-5 Interrupt Register"
|
|
hgroup.long (0x5A0+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK5,OTG_FS Host Channel-5 Interrupt Mask Register"
|
|
hgroup.long (0x5A0+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ5,OTG_FS Host Channel-5 Transfer Size Register"
|
|
hgroup.long 0x5C0++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR6,OTG_FS Host Channel-6 Characteristics Register"
|
|
hgroup.long (0x5C0+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT6,OTG_FS Host Channel-6 Interrupt Register"
|
|
hgroup.long (0x5C0+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK6,OTG_FS Host Channel-6 Interrupt Mask Register"
|
|
hgroup.long (0x5C0+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ6,OTG_FS Host Channel-6 Transfer Size Register"
|
|
hgroup.long 0x5E0++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR7,OTG_FS Host Channel-7 Characteristics Register"
|
|
hgroup.long (0x5E0+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT7,OTG_FS Host Channel-7 Interrupt Register"
|
|
hgroup.long (0x5E0+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK7,OTG_FS Host Channel-7 Interrupt Mask Register"
|
|
hgroup.long (0x5E0+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ7,OTG_FS Host Channel-7 Transfer Size Register"
|
|
hgroup.long 0x600++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR8,OTG_FS Host Channel-8 Characteristics Register"
|
|
hgroup.long (0x600+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT8,OTG_FS Host Channel-8 Interrupt Register"
|
|
hgroup.long (0x600+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK8,OTG_FS Host Channel-8 Interrupt Mask Register"
|
|
hgroup.long (0x600+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ8,OTG_FS Host Channel-8 Transfer Size Register"
|
|
hgroup.long 0x620++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR9,OTG_FS Host Channel-9 Characteristics Register"
|
|
hgroup.long (0x620+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT9,OTG_FS Host Channel-9 Interrupt Register"
|
|
hgroup.long (0x620+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK9,OTG_FS Host Channel-9 Interrupt Mask Register"
|
|
hgroup.long (0x620+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ9,OTG_FS Host Channel-9 Transfer Size Register"
|
|
hgroup.long 0x640++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR10,OTG_FS Host Channel-10 Characteristics Register"
|
|
hgroup.long (0x640+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT10,OTG_FS Host Channel-10 Interrupt Register"
|
|
hgroup.long (0x640+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK10,OTG_FS Host Channel-10 Interrupt Mask Register"
|
|
hgroup.long (0x640+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ10,OTG_FS Host Channel-10 Transfer Size Register"
|
|
hgroup.long 0x660++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR11,OTG_FS Host Channel-11 Characteristics Register"
|
|
hgroup.long (0x660+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT11,OTG_FS Host Channel-11 Interrupt Register"
|
|
hgroup.long (0x660+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK11,OTG_FS Host Channel-11 Interrupt Mask Register"
|
|
hgroup.long (0x660+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ11,OTG_FS Host Channel-11 Transfer Size Register"
|
|
else
|
|
hgroup.long 0x500++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR0,OTG_FS Host Channel-0 Characteristics Register"
|
|
hgroup.long (0x500+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT0,OTG_FS Host Channel-0 Interrupt Register"
|
|
hgroup.long (0x500+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK0,OTG_FS Host Channel-0 Interrupt Mask Register"
|
|
hgroup.long (0x500+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ0,OTG_FS Host Channel-0 Transfer Size Register"
|
|
hgroup.long 0x520++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR1,OTG_FS Host Channel-1 Characteristics Register"
|
|
hgroup.long (0x520+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT1,OTG_FS Host Channel-1 Interrupt Register"
|
|
hgroup.long (0x520+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK1,OTG_FS Host Channel-1 Interrupt Mask Register"
|
|
hgroup.long (0x520+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ1,OTG_FS Host Channel-1 Transfer Size Register"
|
|
hgroup.long 0x540++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR2,OTG_FS Host Channel-2 Characteristics Register"
|
|
hgroup.long (0x540+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT2,OTG_FS Host Channel-2 Interrupt Register"
|
|
hgroup.long (0x540+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK2,OTG_FS Host Channel-2 Interrupt Mask Register"
|
|
hgroup.long (0x540+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ2,OTG_FS Host Channel-2 Transfer Size Register"
|
|
hgroup.long 0x560++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR3,OTG_FS Host Channel-3 Characteristics Register"
|
|
hgroup.long (0x560+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT3,OTG_FS Host Channel-3 Interrupt Register"
|
|
hgroup.long (0x560+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK3,OTG_FS Host Channel-3 Interrupt Mask Register"
|
|
hgroup.long (0x560+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ3,OTG_FS Host Channel-3 Transfer Size Register"
|
|
hgroup.long 0x580++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR4,OTG_FS Host Channel-4 Characteristics Register"
|
|
hgroup.long (0x580+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT4,OTG_FS Host Channel-4 Interrupt Register"
|
|
hgroup.long (0x580+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK4,OTG_FS Host Channel-4 Interrupt Mask Register"
|
|
hgroup.long (0x580+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ4,OTG_FS Host Channel-4 Transfer Size Register"
|
|
hgroup.long 0x5A0++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR5,OTG_FS Host Channel-5 Characteristics Register"
|
|
hgroup.long (0x5A0+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT5,OTG_FS Host Channel-5 Interrupt Register"
|
|
hgroup.long (0x5A0+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK5,OTG_FS Host Channel-5 Interrupt Mask Register"
|
|
hgroup.long (0x5A0+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ5,OTG_FS Host Channel-5 Transfer Size Register"
|
|
hgroup.long 0x5C0++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR6,OTG_FS Host Channel-6 Characteristics Register"
|
|
hgroup.long (0x5C0+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT6,OTG_FS Host Channel-6 Interrupt Register"
|
|
hgroup.long (0x5C0+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK6,OTG_FS Host Channel-6 Interrupt Mask Register"
|
|
hgroup.long (0x5C0+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ6,OTG_FS Host Channel-6 Transfer Size Register"
|
|
hgroup.long 0x5E0++0x03
|
|
hide.long 0x00 "OTG_FS_HCCHAR7,OTG_FS Host Channel-7 Characteristics Register"
|
|
hgroup.long (0x5E0+0x08)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINT7,OTG_FS Host Channel-7 Interrupt Register"
|
|
hgroup.long (0x5E0+0x0C)++0x03
|
|
hide.long 0x00 "OTG_FS_HCINTMSK7,OTG_FS Host Channel-7 Interrupt Mask Register"
|
|
hgroup.long (0x5E0+0x10)++0x03
|
|
hide.long 0x00 "OTG_FS_HCTSIZ7,OTG_FS Host Channel-7 Transfer Size Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 19.
|
|
tree "Device mode registers"
|
|
group.long 0x800++0x07
|
|
line.long 0x00 "OTG_FS_DCFG,OTG_FS Device Configuration Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x00 15. " ERRATIM ,Erratic error interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11.--12. " PFIVL ,Periodic frame interval" "80%,85%,90%,95%"
|
|
hexmask.long.byte 0x00 4.--10. 0x10 " DAD ,Device address"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NZLSOHSK ,Non-zero-length status OUT handshake" "NAK and STALL,STALL"
|
|
bitfld.long 0x00 0.--1. " DSPD ,Device speed" ",,,Full"
|
|
line.long 0x04 "OTG_FS_DCTL,OTG_FS Device Control Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x04 18. " DSBESLRJCT ,Deep sleep BESL reject" "Not rejected,Rejected"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " POPRGDNE ,Power-on programming done" "Not done,Done"
|
|
bitfld.long 0x04 10. " CGONAK ,Clear global OUT NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SGONAK ,Set global OUT NAK" "No effect,Set"
|
|
bitfld.long 0x04 8. " CGINAK ,Clear global IN NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SGINAK ,Set global IN NAK" "No effect,Set"
|
|
bitfld.long 0x04 4.--6. " TCTL ,Test control" "Disabled,J mode,K mode,SE0_NAK mode,Packet mode,Force_Enable,?..."
|
|
textline " "
|
|
rbitfld.long 0x04 3. " GONSTS ,Global OUT NAK status" "Sent NAK and STALL,Sent a NAK"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " GINSTS ,Global IN NAK status" "Data availability,Non-periodic IN endpoints"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SDIS ,Soft disconnect" "Connected,Not connected"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x04 0. " RWUSIG ,Remote wakeup signaling" "No effect,Wakeup"
|
|
else
|
|
bitfld.long 0x04 0. " RWUSIG ,Remote wakeup signaling" "Suspended,Not suspended"
|
|
endif
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "OTG_FS_DSTS,OTG_FS Device Status Register"
|
|
sif cpuis("STM32F446*")
|
|
bitfld.long 0x00 23. " DEVLNSTS ,Device line status" "0,1"
|
|
bitfld.long 0x00 22. " DEVLNSTS ,Device line status" "0,1"
|
|
textline " "
|
|
elif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.long 0x00 23. " DEVLNSTS_D+ ,Device line status - logic level of D+" "Low,High"
|
|
bitfld.long 0x00 22. " DEVLNSTS_D- ,Device line status - logic level of D+" "Low,High"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x00 8.--21. 1. " FNSOF ,Frame number of the received SOF"
|
|
bitfld.long 0x00 3. " EERR ,Erratic error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ENUMSPD ,Enumerated speed" ",,,Full"
|
|
bitfld.long 0x00 0. " SUSPSTS ,Suspend status" "Not suspended,Suspended"
|
|
group.long 0x810++0x07
|
|
line.long 0x00 "OTG_FS_DIEPMSK,OTG_FS Device IN Endpoint Common Interrupt Mask Register"
|
|
sif ((!cpuis("STM32F2*"))&&(!cpuis("STM32F4*")))
|
|
bitfld.long 0x00 9. " BIM ,BNA interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " TXFURM ,FIFO underrun mask" "Masked,Unmasked"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 13. " NAKM ,NAK interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " INEPNEM ,IN endpoint NAK effective mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 5. " INEPNMM ,IN token received with EP mismatch mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITTXFEMSK ,IN token received when TxFIFO empty mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 3. " TOM ,Timeout condition mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked"
|
|
line.long 0x04 "OTG_FS_DOEPMSK,OTG_FS Device OUT Endpoint Common Interrupt Mask Register"
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
bitfld.long 0x04 4. " OTEPDM ,OUT token received when endpoint disabled mask" "Masked,Unmasked"
|
|
else
|
|
bitfld.long 0x04 9. " BOIM ,BNA interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " OPEM ,OUT packet error mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " B2BSTUP ,Back-to-back SETUP packets received mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " OTEPDM ,OUT token received when endpoint disabled mask" "Masked,Unmasked"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 3. " STUPM ,SETUP phase done mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " EPDM ,Endpoint disabled interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " XFRCM ,Transfer completed interrupt mask" "Masked,Unmasked"
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "OTG_FS_DAINT,OTG_FS Device All Endpoints Interrupt Register"
|
|
bitfld.long 0x00 31. " OUTEPINT[15] ,OUT endpoint interrupt bit 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " OUTEPINT[14] ,OUT endpoint interrupt bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " OUTEPINT[13] ,OUT endpoint interrupt bit 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " OUTEPINT[12] ,OUT endpoint interrupt bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OUTEPINT[11] ,OUT endpoint interrupt bit 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " OUTEPINT[10] ,OUT endpoint interrupt bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OUTEPINT[9] ,OUT endpoint interrupt bit 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " OUTEPINT[8] ,OUT endpoint interrupt bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OUTEPINT[7] ,OUT endpoint interrupt bit 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " OUTEPINT[6] ,OUT endpoint interrupt bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " OUTEPINT[5] ,OUT endpoint interrupt bit 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " OUTEPINT[4] ,OUT endpoint interrupt bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OUTEPINT[3] ,OUT endpoint interrupt bit 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " OUTEPINT[2] ,OUT endpoint interrupt bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " OUTEPINT[1] ,OUT endpoint interrupt bit 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " OUTEPINT[0] ,OUT endpoint interrupt bit 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INEPINT[15] ,IN endpoint interrupt bit 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " INEPINT[14] ,IN endpoint interrupt bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INEPINT[13] ,IN endpoint interrupt bit 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " INEPINT[12] ,IN endpoint interrupt bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INEPINT[11] ,IN endpoint interrupt bit 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INEPINT[10] ,IN endpoint interrupt bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INEPINT[9] ,IN endpoint interrupt bit 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " INEPINT[8] ,IN endpoint interrupt bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INEPINT[7] ,IN endpoint interrupt bit 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INEPINT[6] ,IN endpoint interrupt bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INEPINT[5] ,IN endpoint interrupt bit 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " INEPINT[4] ,IN endpoint interrupt bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INEPINT[3] ,IN endpoint interrupt bit 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INEPINT[2] ,IN endpoint interrupt bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INEPINT[1] ,IN endpoint interrupt bit 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INEPINT[0] ,IN endpoint interrupt bit 0" "No interrupt,Interrupt"
|
|
group.long 0x81C++0x03
|
|
line.long 0x00 "OTG_FS_DAINTMSK,OTG_FS All Endpoints Interrupt Mask Register"
|
|
bitfld.long 0x00 31. " OEPM[15] ,OUT EP interrupt mask bit 15" "Masked,Unmasked"
|
|
bitfld.long 0x00 30. " OEPM[14] ,OUT EP interrupt mask bit 14" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " OEPM[13] ,OUT EP interrupt mask bit 13" "Masked,Unmasked"
|
|
bitfld.long 0x00 28. " OEPM[12] ,OUT EP interrupt mask bit 12" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OEPM[11] ,OUT EP interrupt mask bit 11" "Masked,Unmasked"
|
|
bitfld.long 0x00 26. " OEPM[10] ,OUT EP interrupt mask bit 10" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OEPM[9] ,OUT EP interrupt mask bit 9" "Masked,Unmasked"
|
|
bitfld.long 0x00 24. " OEPM[8] ,OUT EP interrupt mask bit 8" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OEPM[7] ,OUT EP interrupt mask bit 7" "Masked,Unmasked"
|
|
bitfld.long 0x00 22. " OEPM[6] ,OUT EP interrupt mask bit 6" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " OEPM[5] ,OUT EP interrupt mask bit 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 20. " OEPM[4] ,OUT EP interrupt mask bit 4" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OEPM[3] ,OUT EP interrupt mask bit 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " OEPM[2] ,OUT EP interrupt mask bit 2" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " OEPM[1] ,OUT EP interrupt mask bit 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 16. " OEPM[0] ,OUT EP interrupt mask bit 0" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IEPM[15] ,IN EP interrupt mask bit 15" "Masked,Unmasked"
|
|
bitfld.long 0x00 14. " IEPM[14] ,IN EP interrupt mask bit 14" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IEPM[13] ,IN EP interrupt mask bit 13" "Masked,Unmasked"
|
|
bitfld.long 0x00 12. " IEPM[12] ,IN EP interrupt mask bit 12" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IEPM[11] ,IN EP interrupt mask bit 11" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " IEPM[10] ,IN EP interrupt mask bit 10" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IEPM[9] ,IN EP interrupt mask bit 9" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " IEPM[8] ,IN EP interrupt mask bit 8" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IEPM[7] ,IN EP interrupt mask bit 7" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " IEPM[6] ,IN EP interrupt mask bit 6" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IEPM[5] ,IN EP interrupt mask bit 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " IEPM[4] ,IN EP interrupt mask bit 4" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IEPM[3] ,IN EP interrupt mask bit 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " IEPM[2] ,IN EP interrupt mask bit 2" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IEPM[1] ,IN EP interrupt mask bit 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " IEPM[0] ,IN EP interrupt mask bit 0" "Masked,Unmasked"
|
|
group.long 0x828++0x07
|
|
line.long 0x00 "OTG_FS_DVBUSDIS,OTG_FS Device VBUS Discharge Time Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VBUSDT ,Device VBUS discharge time"
|
|
line.long 0x04 "OTG_FS_DVBUSPULSE,OTG_FS device VBUS Pulsing Time Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DVBUSP ,Device VBUS pulsing time"
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "OTG_FS_DIEPEMPMSK,OTG_FS Device IN Endpoint FIFO Empty Interrupt Mask Register"
|
|
bitfld.long 0x00 15. " INEPTXFEM[15] ,IN EP Tx FIFO empty interrupt mask bit 15" "Masked,Unmasked"
|
|
bitfld.long 0x00 14. " INEPTXFEM[14] ,IN EP Tx FIFO empty interrupt mask bit 14" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INEPTXFEM[13] ,IN EP Tx FIFO empty interrupt mask bit 13" "Masked,Unmasked"
|
|
bitfld.long 0x00 12. " INEPTXFEM[12] ,IN EP Tx FIFO empty interrupt mask bit 12" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INEPTXFEM[11] ,IN EP Tx FIFO empty interrupt mask bit 11" "Masked,Unmasked"
|
|
bitfld.long 0x00 10. " INEPTXFEM[10] ,IN EP Tx FIFO empty interrupt mask bit 10" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INEPTXFEM[9] ,IN EP Tx FIFO empty interrupt mask bit 9" "Masked,Unmasked"
|
|
bitfld.long 0x00 8. " INEPTXFEM[8] ,IN EP Tx FIFO empty interrupt mask bit 8" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INEPTXFEM[7] ,IN EP Tx FIFO empty interrupt mask bit 7" "Masked,Unmasked"
|
|
bitfld.long 0x00 6. " INEPTXFEM[6] ,IN EP Tx FIFO empty interrupt mask bit 6" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INEPTXFEM[5] ,IN EP Tx FIFO empty interrupt mask bit 5" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " INEPTXFEM[4] ,IN EP Tx FIFO empty interrupt mask bit 4" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INEPTXFEM[3] ,IN EP Tx FIFO empty interrupt mask bit 3" "Masked,Unmasked"
|
|
bitfld.long 0x00 2. " INEPTXFEM[2] ,IN EP Tx FIFO empty interrupt mask bit 2" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INEPTXFEM[1] ,IN EP Tx FIFO empty interrupt mask bit 1" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " INEPTXFEM[0] ,IN EP Tx FIFO empty interrupt mask bit 0" "Masked,Unmasked"
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL0,OTG_FS Device Control IN endpoint 0 Control Register"
|
|
rbitfld.long 0x00 31. " EPENA ,Endpoint enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "Not received,Received"
|
|
textline " "
|
|
rbitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,?..."
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status" "Non-NAK,NAK"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
bitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
if (((per.l(ad:0x50000000+0x920))&0xC0000)==0x40000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x920))&0xC0000)==0x80000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x920))&0xC0000)==0xC0000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x940))&0xC0000)==0x40000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x940))&0xC0000)==0x80000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x940))&0xC0000)==0xC0000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x960))&0xC0000)==0x40000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x960))&0xC0000)==0x80000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x960))&0xC0000)==0xC0000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x980))&0xC0000)==0x40000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x980))&0xC0000)==0x80000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x980))&0xC0000)==0xC0000)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL4,OTG Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x9A0))&0xC0000)==0x40000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x9A0))&0xC0000)==0x80000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x9A0))&0xC0000)==0xC0000)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL5,OTG Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x50000000+0x920))&0xC0000)==0x40000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x920))&0xC0000)==0x80000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x920))&0xC0000)==0xC0000)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL1,OTG Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x940))&0xC0000)==0x40000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x940))&0xC0000)==0x80000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x940))&0xC0000)==0xC0000)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL2,OTG Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x960))&0xC0000)==0x40000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "Not effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x960))&0xC0000)==0x80000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "Not effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0x960))&0xC0000)==0xC0000)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "OTG_FS_DIEPCTL3,OTG Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22.--25. " TXFNUM ,TxFIFO number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("STM32F4*"))
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Low,High"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
endif
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL0,OTG_FS Device Control OUT Endpoint 0 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
rbitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,?..."
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
rbitfld.long 0x00 0.--1. " MPSIZ ,Maximum packet size" "64 bytes,32 bytes,16 bytes,8 bytes"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
if (((per.l(ad:0x50000000+0xB20))&0xC0000)==0x40000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB20))&0xC0000)==0x80000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB20))&0xC0000)==0xC0000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB40))&0xC0000)==0x40000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB40))&0xC0000)==0x80000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB40))&0xC0000)==0xC0000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB60))&0xC0000)==0x40000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB60))&0xC0000)==0x80000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB60))&0xC0000)==0xC0000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB80))&0xC0000)==0x40000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL4,OTG_FS Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB80))&0xC0000)==0x80000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL4,OTG_FS Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB80))&0xC0000)==0xC0000)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL4,OTG_FS Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL4,OTG_FS Device Endpoint-4 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xBA0))&0xC0000)==0x40000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL5,OTG_FS Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xBA0))&0xC0000)==0x80000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL5,OTG_FS Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xBA0))&0xC0000)==0xC0000)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL5,OTG_FS Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL5,OTG_FS Device Endpoint-5 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x50000000+0xB20))&0xC0000)==0x40000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB20))&0xC0000)==0x80000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB20))&0xC0000)==0xC0000)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL1,OTG_FS Device Endpoint-1 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB40))&0xC0000)==0x40000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB40))&0xC0000)==0x80000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB40))&0xC0000)==0xC0000)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL2,OTG_FS Device Endpoint-2 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB60))&0xC0000)==0x40000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SODDFRM ,Set odd frame" "Even,Odd"
|
|
bitfld.long 0x00 28. " SEVNFRM ,Set even frame" "Odd,Even"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " EONUM ,Even/odd frame" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB60))&0xC0000)==0x80000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
elif (((per.l(ad:0x50000000+0xB60))&0xC0000)==0xC0000)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SD0PID ,Set DATA0 PID" "DATA1,DATA0"
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "No effect,Clear"
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
rbitfld.long 0x00 16. " DPID ,Endpoint data PID" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
else
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "OTG_FS_DOEPCTL3,OTG_FS Device Endpoint-3 Control Register"
|
|
bitfld.long 0x00 31. " EPENA ,Endpoint enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " EPDIS ,Endpoint disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SNAK ,Set NAK" "No effect,Set"
|
|
bitfld.long 0x00 26. " CNAK ,Clear NAK" "Not Clear,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " STALL ,STALL handshake" "No effect,Set"
|
|
bitfld.long 0x00 20. " SNPM ,Snoop mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " EPTYP ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
rbitfld.long 0x00 17. " NAKSTS ,NAK status (transmitting handshakes)" "Non-NAK,NAK"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBAEP ,USB active endpoint" "Not active,Active"
|
|
hexmask.long.word 0x00 0.--10. 1. " MPSIZ ,Maximum packet size"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "OTG_FS_DIEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "OTG_FS_DIEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "OTG_FS_DIEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "OTG_FS_DIEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "OTG_FS_DIEPINT4,OTG_FS Device Endpoint-4 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "OTG_FS_DIEPINT5,OTG_FS Device Endpoint-5 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
sif cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rbitfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "OTG_FS_DIEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "OTG_FS_DIEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "OTG_FS_DIEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "OTG_FS_DIEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
rbitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
|
|
eventfld.long 0x00 6. " INEPNE ,IN endpoint NAK effective" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ITTXFE ,IN token received when TxFIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TOC ,Timeout condition" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No,Yes"
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
if ((per.l(ad:0x50000000+0xB08-0x08)&0xC0000)==0x00)
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0xB28-0x08)&0xC0000)==0x00)
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0xB48-0x08)&0xC0000)==0x00)
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0xB68-0x08)&0xC0000)==0x00)
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0xB88-0x08)&0xC0000)==0x00)
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT4,OTG_FS Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT4,OTG_FS Device Endpoint-4 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
if ((per.l(ad:0x50000000+0xBA8-0x08)&0xC0000)==0x00)
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT5,OTG_FS Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT5,OTG_FS Device Endpoint-5 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
else
|
|
sif (!cpuis("STM32F4*"))
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
if ((per.l(ad:0x50000000+0xB08-0x08)&0xC0000)==0x00)
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT0,OTG_FS Device Endpoint-0 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F4*"))
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
if ((per.l(ad:0x50000000+0xB28-0x08)&0xC0000)==0x00)
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT1,OTG_FS Device Endpoint-1 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F4*"))
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
if ((per.l(ad:0x50000000+0xB48-0x08)&0xC0000)==0x00)
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT2,OTG_FS Device Endpoint-2 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F4*"))
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
if ((per.l(ad:0x50000000+0xB68-0x08)&0xC0000)==0x00)
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 6. " B2BSTUP ,Back-to-back SETUP packets received" "Not received,Received"
|
|
eventfld.long 0x00 4. " OTEPDIS ,OUT token received when endpoint disabled" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STUP ,SETUP phase done" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
else
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "OTG_FS_DOEPINT3,OTG_FS Device Endpoint-3 Interrupt Register"
|
|
eventfld.long 0x00 1. " EPDISD ,Endpoint disabled interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " XFRC ,Transfer completed interrupt" "Not completed,Completed"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTSIZ0,OTG_FS Device IN Endpoint 0 Transfer Size Register"
|
|
bitfld.long 0x00 19.--20. " PKTCNT ,Packet count" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ0,OTG_FS Device OUT Endpoint 0 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" ",1,2,3"
|
|
bitfld.long 0x00 19. " PKTCNT ,Packet count" "0,1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTSIZ1,OTG_FS Device IN Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTSIZ2,OTG_FS Device IN Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTSIZ3,OTG_FS Device IN Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTSIZ4,OTG_FS Device IN Endpoint-4 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTSIZ5,OTG_FS Device IN Endpoint-5 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "OTG_FS_DIEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " MCNT ,Multi count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "OTG_FS_DTXFSTS0,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail"
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "OTG_FS_DTXFSTS1,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail"
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "OTG_FS_DTXFSTS2,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail"
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "OTG_FS_DTXFSTS3,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail"
|
|
rgroup.long 0x998++0x03
|
|
line.long 0x00 "OTG_FS_DTXFSTS4,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail"
|
|
rgroup.long 0x9B8++0x03
|
|
line.long 0x00 "OTG_FS_DTXFSTS5,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail"
|
|
else
|
|
rgroup.long 0x918++0x03
|
|
line.long 0x00 "OTG_FS_DTXFSTS0,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail"
|
|
rgroup.long 0x938++0x03
|
|
line.long 0x00 "OTG_FS_DTXFSTS1,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail"
|
|
rgroup.long 0x958++0x03
|
|
line.long 0x00 "OTG_FS_DTXFSTS2,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail"
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "OTG_FS_DTXFSTS3,OTG_FS Device IN Endpoint Transmit FIFO Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INEPTFSAV ,IN endpoint TxFIFO space avail"
|
|
endif
|
|
sif !cpuis("STM32F412*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ0,OTG_FS Device OUT Endpoint 0 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
bitfld.long 0x00 19. " PKTCNT ,Packet count" "Low,High"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
if (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,,DATA1,?..."
|
|
else
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x00000)
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,,DATA1,?..."
|
|
else
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x00000)
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,,DATA1,?..."
|
|
else
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x00000)
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xB90-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ4,OTG_FS Device Endpoint-4 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,,DATA1,?..."
|
|
else
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB90-0x10))&0xC0000)==0x00000)
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ4,OTG_FS Device Endpoint-4 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ4,OTG_FS Device Endpoint-4 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0xBB0-0x10))&0xC0000)==0x40000)
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ5,OTG_FS Device Endpoint-5 Transfer Size Register"
|
|
sif cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,,DATA1,?..."
|
|
else
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
endif
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xBB0-0x10))&0xC0000)==0x00000)
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ5,OTG_FS Device Endpoint-5 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ5,OTG_FS Device Endpoint-5 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
else
|
|
sif (cpuis("STM32F4*"))
|
|
if (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x00000)
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB30-0x10))&0xC0000)==0x00000)
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ1,OTG_FS Device Endpoint-1 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F4*"))
|
|
if (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x00000)
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB50-0x10))&0xC0000)==0x00000)
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ2,OTG_FS Device Endpoint-2 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F4*"))
|
|
if (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x00000)
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
else
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x40000)
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " RXDPID ,Received data PID" "DATA0,DATA2,DATA1,MDATA"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
elif (((per.l(ad:0x50000000+0xB70-0x10))&0xC0000)==0x00000)
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "OTG_FS_DOEPTSIZ3,OTG_FS Device Endpoint-3 Transfer Size Register"
|
|
bitfld.long 0x00 29.--30. " STUPCNT ,SETUP packet count" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--28. 1. " PKTCNT ,Packet count"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " XFRSIZ ,Transfer size"
|
|
endif
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 16.
|
|
tree "Power and clock gating control and status registers"
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "OTG_FS_PCGCCTL,OTG_FS Power And Clock Gating Control Register"
|
|
sif cpuis("STM32F446*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")||cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
rbitfld.long 0x00 7. " SUSP ,Deep Sleep" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " PHYSLEEP ,PHY in Sleep" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENL1GTG ,Enable Sleep clock gating" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " PHYSUSP ,PHY Suspended" "Not suspended,Suspended"
|
|
else
|
|
bitfld.long 0x00 4. " PHYSUSP ,PHY Suspended" "Not suspended,Suspended"
|
|
endif
|
|
bitfld.long 0x00 1. " GATEHCLK ,Gate HCLK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STPPCLK ,Stop PHY clock" "Not stopped,Stopped"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F107*"))
|
|
tree "Ethernet"
|
|
base ad:0x40028000
|
|
width 15.
|
|
tree "MAC Registers"
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
if (((per.l((ad:0x40028000+0x00)))&0x800)==0x800)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ETH_MACCR,Ethernet MAC Configuration Register"
|
|
bitfld.long 0x00 25. " CSTF ,CRC stripping for type frames" "Not stripped,Stripped"
|
|
bitfld.long 0x00 23. " WD ,Watchdog disable" "No,Yes"
|
|
bitfld.long 0x00 22. " JD ,Jabber disable" "No,Yes"
|
|
bitfld.long 0x00 17.--19. " IFG ,Interframe gap" "96 bit,88 bit,80 bit,72 bit,64 bit,56 bit,48 bit,40 bit"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSD ,Carrier sense disable" "No,Yes"
|
|
bitfld.long 0x00 14. " FES ,Fast Ethernet speed" "10 Mbit/s,100 Mbit/s"
|
|
bitfld.long 0x00 12. " LM ,Loopback mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DM ,Duplex mode" "Half-Duplex,Full-Duplex"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IPCO ,IPv4 checksum offload" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " APCS ,Automatic pad/CRC stripping" "No stripping,< 1501 bytes"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ETH_MACCR,Ethernet MAC Configuration Register"
|
|
bitfld.long 0x00 25. " CSTF ,CRC stripping for type frames" "Not stripped,Stripped"
|
|
bitfld.long 0x00 23. " WD ,Watchdog disable" "No,Yes"
|
|
bitfld.long 0x00 22. " JD ,Jabber disable" "No,Yes"
|
|
bitfld.long 0x00 17.--19. " IFG ,Interframe gap" "96 bit,88 bit,80 bit,72 bit,64 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSD ,Carrier sense disable" "No,Yes"
|
|
bitfld.long 0x00 14. " FES ,Fast Ethernet speed" "10 Mbit/s,100 Mbit/s"
|
|
bitfld.long 0x00 13. " ROD ,Receive own disable" "No,Yes"
|
|
bitfld.long 0x00 12. " LM ,Loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DM ,Duplex mode" "Half-Duplex,Full-Duplex"
|
|
bitfld.long 0x00 10. " IPCO ,IPv4 checksum offload" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RD ,Retry disable" "No,Yes"
|
|
bitfld.long 0x00 7. " APCS ,Automatic pad/CRC stripping" "No stripping,< 1501 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " BL ,Back-off limit" "K = min (n.10),K = min (n.8),K = min (n.4),K = min (n.1)"
|
|
bitfld.long 0x00 4. " DC ,Deferral check" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ETH_MACCR,Ethernet MAC Configuration Register"
|
|
sif (cpuis("STM32F2*"))
|
|
bitfld.long 0x00 25. " CSTF ,CRC stripping for type frames" "Not stripped,Stripped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " WD ,Watchdog disable" "No,Yes"
|
|
bitfld.long 0x00 22. " JD ,Jabber disable" "No,Yes"
|
|
bitfld.long 0x00 17.--19. " IFG ,Interframe gap" "96 bit,88 bit,80 bit,72 bit,64 bit,56 bit,48 bit,40 bit"
|
|
bitfld.long 0x00 16. " CSD ,Carrier sense disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FES ,Fast Ethernet speed" "10 Mbit/s,100 Mbit/s"
|
|
bitfld.long 0x00 13. " ROD ,Receive own disable" "No,Yes"
|
|
bitfld.long 0x00 12. " LM ,Loopback mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DM ,Duplex mode" "Half-Duplex,Full-Duplex"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IPCO ,IPv4 checksum offload" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RD ,Retry disable" "No,Yes"
|
|
bitfld.long 0x00 7. " APCS ,Automatic pad/CRC stripping" "No stripping,< 1501 bytes"
|
|
bitfld.long 0x00 5.--6. " BL ,Back-off limit" "K = min (n.10),K = min (n.8),K = min (n.4),K = min (n.1)"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DC ,Deferral check" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
if (((per.l(ad:0x40028000+0x18))&0x04)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ETH_MACFFR,Ethernet MAC Frame Filter Register"
|
|
bitfld.long 0x00 31. " RA ,Receive all" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HPF ,Hash or perfect filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SAF ,Source address filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SAIF ,Source address inverse filtering" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PCF ,Pass control frames" "Filters all,Filters pause frames,Forwards all,Forwards frames that pass"
|
|
bitfld.long 0x00 5. " BFD ,Broadcast frames disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PAM ,Pass all multicast" "Filtered,Passed"
|
|
bitfld.long 0x00 3. " DAIF ,Destination address inverse filtering" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HM ,Hash multicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HU ,Hash unicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PM ,Promiscuous mode" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ETH_MACFFR,Ethernet MAC Frame Filter Register"
|
|
bitfld.long 0x00 31. " RA ,Receive all" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HPF ,Hash or perfect filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SAF ,Source address filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SAIF ,Source address inverse filtering" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PCF ,Pass control frames" "Filters all,Filters all,Forwards all,Forwards frames that pass"
|
|
bitfld.long 0x00 5. " BFD ,Broadcast frames disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PAM ,Pass all multicast" "Filtered,Passed"
|
|
bitfld.long 0x00 3. " DAIF ,Destination address inverse filtering" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HM ,Hash multicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HU ,Hash unicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PM ,Promiscuous mode" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ETH_MACFFR,Ethernet MAC Frame Filter Register"
|
|
bitfld.long 0x00 31. " RA ,Receive all" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HPF ,Hash or perfect filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SAF ,Source address filter" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SAIF ,Source address inverse filtering" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PCF ,Pass control frames" "Filters all,Filters all,Forwards all,Forwards frames that pass"
|
|
bitfld.long 0x00 5. " BFD ,Broadcast frames disable" "No,Yes"
|
|
bitfld.long 0x00 4. " PAM ,Pass all multicast" "Filtered,Passed"
|
|
bitfld.long 0x00 3. " DAIF ,Destination address inverse filtering" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HM ,Hash multicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HU ,Hash unicast" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PM ,Promiscuous mode" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "ETH_MACHTHR,Ethernet MAC Hash Table High Register"
|
|
line.long 0x04 "ETH_MACHTLR,Ethernet MAC Hash Table Low Register"
|
|
line.long 0x08 "ETH_MACMIIAR,Ethernet MAC MII Address Register"
|
|
bitfld.long 0x08 11.--15. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 6.--10. " MR ,MII register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
sif (cpuis("STM32F2*"))
|
|
bitfld.long 0x08 2.--4. " CR ,Clock range (HCLK/MDC Clock)" "60-100 MHz/HCLK/42,100-120 MHz/HCLK/62,20-35 MHz/HCLK/16,35-60 MHz/HCLK/26,?..."
|
|
elif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
bitfld.long 0x08 2.--4. " CR ,Clock range (HCLK/MDC Clock)" "60-100 MHz/HCLK/42,100-150 MHz/HCLK/62,20-35 MHz/HCLK/16,35-60 MHz/HCLK/26,150-168/HCLK/102,?..."
|
|
else
|
|
bitfld.long 0x08 2.--4. " CR ,Clock range (HCLK/MDC Clock)" "60-72 MHz/HCLK/42,,20-35 MHz/HCLK/16,35-60 MHz/HCLK/26,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 1. " MW ,MII write" "Read,Write"
|
|
eventfld.long 0x08 0. " MB ,MII busy" "Not busy,Busy"
|
|
line.long 0x0C "ETH_MACMIIDR,Ethernet MAC MII Data Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MD ,MII data"
|
|
if (((per.l((ad:0x40028000+0x00)))&0x800)==0x800)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ETH_MACFCR,Ethernet MAC Flow Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PT ,Pause time"
|
|
bitfld.long 0x00 7. " ZQPD ,Zero-quanta pause disable" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " PLT ,Pause low threshold" "4 slot,28 slot,144 slot,256 slot"
|
|
bitfld.long 0x00 3. " UPFD ,Unicast pause frame detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RFCE ,Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFCE ,Transmit flow control enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " FCB ,Flow control busy" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ETH_MACFCR,Ethernet MAC Flow Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PT ,Pause time"
|
|
bitfld.long 0x00 7. " ZQPD ,Zero-quanta pause disable" "No,Yes"
|
|
bitfld.long 0x00 4.--5. " PLT ,Pause low threshold" "4 slot,28 slot,144 slot,256 slot"
|
|
bitfld.long 0x00 3. " UPFD ,Unicast pause frame detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RFCE ,Receive flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFCE ,Transmit flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BPA ,Backpressure activate" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ETH_MACVLANTR,Ethernet MAC VLAN Tag Register"
|
|
bitfld.long 0x00 16. " VLANTC ,12-bit VLAN tag comparison" "16-bits,12-bits"
|
|
hexmask.long.word 0x00 0.--15. 1. " VLANTI ,VLAN tag identifier (for receive frames)"
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "ETH_MACRWUFFR,Ethernet MAC Remote Wakeup Frame Filter Register"
|
|
in
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ETH_MACRWUFFR,Ethernet MAC Remote Wakeup Frame Filter Register"
|
|
endif
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "ETH_MACPMTCSR,Ethernet MAC PMT Control And Status Register"
|
|
in
|
|
textline " "
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
if (((per.l((ad:0x40028000+0x00)))&0x800)==0x800)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "ETH_MACDBGR,Ethernet MAC Debug Register"
|
|
bitfld.long 0x00 25. " TFF ,Tx FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TFNE ,Tx FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TFWA ,Tx FIFO write active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " TFRS ,Tx FIFO read status" "Idle state,Read state,Waiting for TxStatus from MAC transmitter,Writing the received TxStatus or flushing the TxFIFO"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MTP ,MAC transmitter in pause (full-duplex mode)" "Not paused,Paused"
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " TFCS ,MAC transmit frame controller status" "Idle,Waiting for status of previous frame or IFG/backoff period to be over,Generating and transmitting a pause control frame,Transferring input frame for transmission"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MMTEA ,MAC MII transmit engine active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RFFL ,Rx FIFO fill level" "Empty,Below flow-control,Above flow-control,Full"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RFRCS ,Rx FIFO read controller status" "IDLE state,Reading frame data,Reading frame status,Flushing the frame data and status"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFWRA ,Rx FIFO write controller active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " MSFRWCS ,MAC small FIFO read/write controllers status" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MMRPEA ,MAC MII receive protocol engine active" "Not activated,Activated"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "ETH_MACDBGR,Ethernet MAC Debug Register"
|
|
bitfld.long 0x00 25. " TFF ,Tx FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TFNE ,Tx FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TFWA ,Tx FIFO write active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " TFRS ,Tx FIFO read status" "Idle state,Read state,Waiting for TxStatus from MAC transmitter,Writing the received TxStatus or flushing the TxFIFO"
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " MTFCS ,MAC transmit frame controller status" "Idle,Waiting for status of previous frame or IFG/backoff period to be over,,Transferring input frame for transmission"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MMTEA ,MAC MII transmit engine active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RFFL ,Rx FIFO fill level" "Empty,Below flow-control,Above flow-control,Full"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RFRCS ,Rx FIFO read controller status" "IDLE state,Reading frame data,Reading frame status,Flushing the frame data and status"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFWRA ,Rx FIFO write controller active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " MSFRWCS ,MAC small FIFO read/write controllers status" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MMRPEA ,MAC MII receive protocol engine active" "Not activated,Activated"
|
|
endif
|
|
elif (cpuis("STM32F2*"))
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "ETH_MACDBGR,Ethernet MAC Debug Register"
|
|
bitfld.long 0x00 25. " TFF ,Tx FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 24. " TFNE ,Tx FIFO not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TFWA ,Tx FIFO write active" "Not activated,Activated"
|
|
bitfld.long 0x00 20.--21. " TFRS ,Tx FIFO read status" "Idle state,Read state,Waiting for TxStatus from MAC transmitter,Writing the received TxStatus or flushing the TxFIFO"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MTP ,MAC transmitter in pause (full-duplex mode)" "Not paused,Paused"
|
|
bitfld.long 0x00 17.--18. " MTFCS ,MAC transmit frame controller status" "Idle,Waiting for status of previous frame or IFG/backoff period to be over,Generating and transmitting a pause control frame (full duplex mode),Transferring input frame for transmission"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MMTEA ,MAC MII transmit engine active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RFFL ,Rx FIFO fill level" "Empty,Below flow-control,Above flow-control,Full"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RFRCS ,Rx FIFO read controller status" "IDLE state,Reading frame data,Reading frame status,Flushing the frame data and status"
|
|
bitfld.long 0x00 4. " RFWRA ,Rx FIFO write controller active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " MSFRWCS ,MAC small FIFO read/write controllers status" "0,1,2,3"
|
|
bitfld.long 0x00 0. " MMRPEA ,MAC MII receive protocol engine active" "Not activated,Activated"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
hgroup.word 0x38++0x01
|
|
hide.word 0x00 "ETH_MACSR,Ethernet MAC Interrupt Status Register"
|
|
in
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "ETH_MACSR,Ethernet MAC Interrupt Status Register"
|
|
in
|
|
endif
|
|
sif (cpuis("STM32F74*")||cpuis("STM32F75*")||cpuis("STM32F76*")||cpuis("STM32F77*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "ETH_MACIMR,Ethernet MAC Interrupt Mask Register"
|
|
bitfld.word 0x00 9. " TSTIM ,Time stamp trigger interrupt mask" "Not masked,Masked"
|
|
bitfld.word 0x00 3. " PMTIM ,PMT interrupt mask" "Not masked,Masked"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ETH_MACIMR,Ethernet MAC Interrupt Mask Register"
|
|
bitfld.long 0x00 9. " TSTIM ,Time stamp trigger interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " PMTIM ,PMT interrupt mask" "Not masked,Masked"
|
|
endif
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "ETH_MACA0HR,Ethernet MAC Address 0 High Register"
|
|
bitfld.long 0x00 31. " MO ,MO" "Low,High"
|
|
hexmask.long.word 0x00 0.--15. 1. " MACA0H ,MAC address0 high [47:32]"
|
|
line.long 0x04 "ETH_MACA0LR,Ethernet MAC Address 0 Low Register"
|
|
line.long 0x08 "ETH_MACA1HR,Ethernet MAC Address 1 High Register"
|
|
bitfld.long 0x08 31. " AE ,Address enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " SA ,Source address" "DA,SA"
|
|
hexmask.long.byte 0x08 24.--29. 1. " MBC ,Mask byte control"
|
|
hexmask.long.word 0x08 0.--15. 1. " MACA1H ,MAC address1 high [47:32]"
|
|
line.long 0x0C "ETH_MACA1LR,Ethernet MAC Address 1 Low Register"
|
|
line.long 0x10 "ETH_MACA2HR,Ethernet MAC Address 2 High Register"
|
|
bitfld.long 0x10 31. " AE ,Address enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " SA ,Source address" "DA,SA"
|
|
hexmask.long.byte 0x10 24.--29. 1. " MBC ,Mask byte control"
|
|
hexmask.long.word 0x10 0.--15. 1. " MACA2H ,MAC address2 high [47:32]"
|
|
line.long 0x14 "ETH_MACA2LR,Ethernet MAC Address 2 Low Register"
|
|
line.long 0x18 "ETH_MACA3HR,Ethernet MAC Address 3 High Register"
|
|
bitfld.long 0x18 31. " AE ,Address enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " SA ,Source address" "DA,SA"
|
|
hexmask.long.byte 0x18 24.--29. 1. " MBC ,Mask byte control"
|
|
hexmask.long.word 0x18 0.--15. 1. " MACA3H ,MAC address2 high [47:32]"
|
|
line.long 0x1C "ETH_MACA3LR,Ethernet MAC Address 3 Low Register"
|
|
tree.end
|
|
width 17.
|
|
tree "MMC Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ETH_MMCCR,Ethernet MMC Control Register"
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 5. " MCFHP ,MMC counter full-half preset" "Not preset,Preset"
|
|
bitfld.long 0x00 4. " MCP ,MMC counter preset" "Not preset,Preset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " MCF ,MMC counter freeze" "Normal,Frozen"
|
|
bitfld.long 0x00 2. " ROR ,Reset on read" "No reset,Reset"
|
|
bitfld.long 0x00 1. " CSR ,Counter stop rollover" "Not stopped,Stopped"
|
|
bitfld.long 0x00 0. " CR ,Counter reset" "No reset,Reset"
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "ETH_MMCRIR,Ethernet MMC Receive Interrupt Register"
|
|
in
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "ETH_MMCTIR,Ethernet MMC Transmit Interrupt Register"
|
|
in
|
|
group.long 0x10C++0x07
|
|
line.long 0x00 "ETH_MMCRIMR,Ethernet MMC Receive Interrupt Mask Register"
|
|
bitfld.long 0x00 17. " RGUFM ,Received good unicast frames mask" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " RFAEM ,Received frames alignment error mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " RFCEM ,Received frame CRC error mask" "Not masked,Masked"
|
|
line.long 0x04 "ETH_MMCTIMR,Ethernet MMC Transmit Interrupt Mask Register"
|
|
bitfld.long 0x04 21. " TGFM ,Transmitted good frames mask" "Not masked,Masked"
|
|
bitfld.long 0x04 15. " TGFMSCM ,Transmitted good frames more single collision mask" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " TGFSCM ,Transmitted good frames single collision mask" "Not masked,Masked"
|
|
endif
|
|
rgroup.long 0x14C++0x07
|
|
line.long 0x00 "ETH_MMCTGFSCCR,Ethernet MMC Transmitted Good Frames After A Single Collision Counter Register"
|
|
line.long 0x04 "ETH_MMCTGFMSCCR,Ethernet MMC Transmitted Good Frames After More Than A Single Collision Counter Register"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "ETH_MMCTGFCR,Ethernet MMC Transmitted Good Frames Counter Register"
|
|
sif (cpuis("STM32F7*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
rgroup.long 0x194++0x07
|
|
line.long 0x00 "ETH_MMCRFCECR,Ethernet MMC Received Frames With CRC Error Counter Register"
|
|
line.long 0x04 "ETH_MMCRFAECR,Ethernet MMC Received Frames With Alignment Error Counter Register"
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "ETH_MMCRGUFCR,MMC Received Good Unicast Frames Counter Register"
|
|
else
|
|
hgroup.long 0x194++0x07
|
|
hide.long 0x00 "ETH_MMCRFCECR,Ethernet MMC Received Frames With CRC Error Counter Register"
|
|
in
|
|
hide.long 0x04 "ETH_MMCRFAECR,Ethernet MMC Received Frames With Alignment Error Counter Register"
|
|
in
|
|
hgroup.long 0x1C4++0x03
|
|
hide.long 0x00 "ETH_MMCRGUFCR,MMC Received Good Unicast Frames Counter Register"
|
|
in
|
|
endif
|
|
tree.end
|
|
width 14.
|
|
tree "IEEE 1588 Time Stamp Registers"
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
if (((per.l(ad:0x40028000+0x700))&0x30000)<=0x10000)
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "ETH_PTPTSCR,Ethernet PTP Time Stamp Control Register"
|
|
bitfld.long 0x00 18. " TSPFFMAE ,Time stamp PTP frame filtering MAC address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TSCNT ,Time stamp clock node type" "Ordinary,Boundary,End-to-end,Peer-to-peer"
|
|
bitfld.long 0x00 15. " TSSMRME ,Time stamp snapshot for message relevant to master enable (Ordinary/boundary clock nodes)" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TSSEME ,Time stamp snapshot for event message enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TSSIPV4FE ,Time stamp snapshot for IPv4 frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TSSIPV6FE ,Time stamp snapshot for IPv6 frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSSPTPOEFE ,Time stamp snapshot for PTP over Ethernet frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TSPTPPSV2E ,Time stamp PTP packet snooping for version2 format enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TSSSR ,Time stamp subsecond rollover enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TSSARFE ,Time stamp snapshot for all received frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TSARU ,Time stamp addend register update" "Not updated,Updated"
|
|
bitfld.long 0x00 4. " TSITE ,Time stamp interrupt trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TSSTU ,Time stamp system time update" "Not updated,Updated"
|
|
bitfld.long 0x00 2. " TSSTI ,Time stamp system time initialize" "Not initialized,Initialized"
|
|
bitfld.long 0x00 1. " TSFCU ,Time stamp fine or coarse update" "Not updated,Updated"
|
|
bitfld.long 0x00 0. " TSE ,Time stamp enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "ETH_PTPTSCR,Ethernet PTP Time Stamp Control Register"
|
|
bitfld.long 0x00 18. " TSPFFMAE ,Time stamp PTP frame filtering MAC address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TSCNT ,Time stamp clock node type" "Ordinary,Boundary,End-to-end,Peer-to-peer"
|
|
bitfld.long 0x00 14. " TSSEME ,Time stamp snapshot for event message enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TSSIPV4FE ,Time stamp snapshot for IPv4 frames enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TSSIPV6FE ,Time stamp snapshot for IPv6 frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSSPTPOEFE ,Time stamp snapshot for PTP over Ethernet frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TSPTPPSV2E ,Time stamp PTP packet snooping for version2 format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TSSSR ,Time stamp subsecond rollover enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TSSARFE ,Time stamp snapshot for all received frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TSARU ,Time stamp addend register update" "Not updated,Updated"
|
|
bitfld.long 0x00 4. " TSITE ,Time stamp interrupt trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSSTU ,Time stamp system time update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TSSTI ,Time stamp system time initialize" "Not initialized,Initialized"
|
|
bitfld.long 0x00 1. " TSFCU ,Time stamp fine or coarse update" "Not updated,Updated"
|
|
bitfld.long 0x00 0. " TSE ,Time stamp enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "ETH_PTPTSCR,Ethernet PTP Time Stamp Control Register"
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
bitfld.long 0x00 18. " TSPFFMAE ,Time stamp PTP frame filtering MAC address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " TSCNT ,Time stamp clock node type" "Ordinary,Boundary,End-to-end,Peer-to-peer"
|
|
bitfld.long 0x00 15. " TSSMRME ,Time stamp snapshot for message relevant to master enable (Ordinary/boundary clock nodes)" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TSSEME ,Time stamp snapshot for event message enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TSSIPV4FE ,Time stamp snapshot for IPv4 frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TSSIPV6FE ,Time stamp snapshot for IPv6 frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSSPTPOEFE ,Time stamp snapshot for PTP over Ethernet frames enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TSPTPPSV2E ,Time stamp PTP packet snooping for version2 format enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TSSSR ,Time stamp subsecond rollover enable" "Binary,Digital"
|
|
bitfld.long 0x00 8. " TSSARFE ,Time stamp snapshot for all received frames enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " TSARU ,Time stamp addend register update" "Not updated,Updated"
|
|
bitfld.long 0x00 4. " TSITE ,Time stamp interrupt trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSSTU ,Time stamp system time update" "Not updated,Updated"
|
|
bitfld.long 0x00 2. " TSSTI ,Time stamp system time initialize" "Not initialized,Initialized"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TSFCU ,Time stamp fine or coarse update" "Coarse,Fine"
|
|
bitfld.long 0x00 0. " TSE ,Time stamp enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x704++0x03
|
|
line.long 0x00 "ETH_PTPSSIR,Ethernet PTP Subsecond Increment Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " STSSI ,System time subsecond increment"
|
|
rgroup.long 0x708++0x07
|
|
line.long 0x00 "ETH_PTPTSHR,Ethernet PTP Time Stamp High Register"
|
|
line.long 0x04 "ETH_PTPTSLR,Ethernet PTP Time Stamp Low Register"
|
|
bitfld.long 0x04 31. " STPNS ,System time positive or negative sign" "Positive,Negative"
|
|
hexmask.long 0x04 0.--30. 1. " STSS ,System time subseconds"
|
|
group.long 0x710++0x13
|
|
line.long 0x00 "ETH_PTPTSHUR,Ethernet PTP Time Stamp High Update Register"
|
|
line.long 0x04 "ETH_PTPTSLUR,Ethernet PTP Time Stamp Low Update Register"
|
|
bitfld.long 0x04 31. " TSUPNS ,Time stamp update positive or negative sign" "Positive,Negative"
|
|
hexmask.long 0x04 0.--30. 1. " TSUSS ,Time stamp update subseconds"
|
|
line.long 0x08 "ETH_PTPTSAR,Ethernet PTP Time Stamp Addend Register"
|
|
line.long 0x0C "ETH_PTPTTHR,Ethernet PTP Target Time High Register"
|
|
line.long 0x10 "ETH_PTPTTLR,Ethernet PTP Target Time Low Register"
|
|
sif (cpuis("STM32F2*"))
|
|
rgroup.long 0x728++0x03
|
|
line.long 0x00 "ETH_PTPTSSR,Ethernet PTP Time Stamp Status Register"
|
|
bitfld.long 0x00 1. " TSTTR ,Time stamp target time reached" "Not reached,Reached"
|
|
bitfld.long 0x00 0. " TSSO ,Time stamp second overflow" "Not overflowed,Overflowed"
|
|
elif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
hgroup.long 0x728++0x03
|
|
hide.long 0x00 "ETH_PTPTSSR,Ethernet PTP Time Stamp Status Register"
|
|
in
|
|
endif
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
rgroup.long 0x72C++0x03
|
|
line.long 0x00 "ETH_PTPPPSCR,Ethernet PTP PPS Control Register"
|
|
bitfld.long 0x00 0.--3. " PPSFREQ ,PPS frequency selection" "1 Hz,2 Hz,4 Hz,8 Hz,16 Hz,32 Hz,64 Hz,128 Hz,256 Hz,512 Hz,1024 Hz,2048 Hz,4096 Hz,8192 Hz,16384 Hz,32768 Hz"
|
|
endif
|
|
tree.end
|
|
width 15.
|
|
tree "DMA Registers"
|
|
sif (cpuis("STM32F4*")||cpuis("STM32F7*"))
|
|
if (((per.l(ad:0x40028000+0x1000))&0x800002)==0x800000)
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "ETH_DMABMR,Ethernet DMA Bus Mode Register"
|
|
bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts"
|
|
bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--22. " RDP ,Rx DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PM ,Rx Tx priority ratio" "1:1,2:1,3:1,4:1"
|
|
bitfld.long 0x00 8.--13. " PBL ,Tx DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first"
|
|
bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset"
|
|
elif (((per.l(ad:0x40028000+0x1000))&0x800002)==0x800002)
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "ETH_DMABMR,Ethernet DMA Bus Mode Register"
|
|
bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts"
|
|
bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--22. " RDP ,Rx DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. " PBL ,Tx DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first"
|
|
bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset"
|
|
elif (((per.l(ad:0x40028000+0x1000))&0x800002)==0x00)
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "ETH_DMABMR,Ethernet DMA Bus Mode Register"
|
|
bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts"
|
|
bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PM ,Rx Tx priority ratio" "1:1,2:1,3:1,4:1"
|
|
bitfld.long 0x00 8.--13. " PBL ,Tx DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first"
|
|
bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset"
|
|
else
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "ETH_DMABMR,Ethernet DMA Bus Mode Register"
|
|
bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts"
|
|
bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--13. " PBL ,Tx DMA programmable burst length" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x00 7. " EDFE ,Enhanced descriptor format enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--6. " DSL ,Descriptor skip length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first"
|
|
bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset"
|
|
endif
|
|
else
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "ETH_DMABMR,Ethernet DMA Bus Mode Register"
|
|
sif (cpuis("STM32F2*"))
|
|
bitfld.long 0x00 26. " MB ,Mixed burst" "Fixed bursts,Mixed bursts"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " AAB ,Address-aligned beats" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " FPM ,4xPBL mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " USP ,Use separate PBL" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 17.--22. 1. " RDP ,Rx DMA PBL"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FB ,Fixed burst" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " RTPR ,Rx Tx priority ratio" "1:1,2:1,3:1,4:1"
|
|
hexmask.long.byte 0x00 8.--13. 1. " PBL ,Programmable burst length"
|
|
hexmask.long.byte 0x00 2.--6. 1. " DSL ,Descriptor skip length"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DA ,DMA arbitration" "Round-robin,Rx first"
|
|
bitfld.long 0x00 0. " SR ,Software reset" "No reset,Reset"
|
|
endif
|
|
group.long 0x1004++0x13
|
|
line.long 0x00 "ETH_DMATPDR,Ethernet DMA Transmit Poll Demand Register"
|
|
line.long 0x04 "ETH_DMARPDR,Ethernet DMA Receive Poll Demand Register"
|
|
line.long 0x08 "ETH_DMARDLAR,Ethernet DMA Receive Descriptor List Address Register"
|
|
line.long 0x0C "ETH_DMATDLAR,Ethernet DMA Transmit Descriptor List Address Register"
|
|
line.long 0x10 "ETH_DMASR,Ethernet DMA Status Register"
|
|
rbitfld.long 0x10 29. " TSTS ,Timestamp trigger status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x10 28. " PMTS ,PMT status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x10 27. " MMCS ,MMC status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x10 25. " EBS[2] ,Error during data buffer/descriptor access" "Data buffer,Descriptor"
|
|
textline " "
|
|
rbitfld.long 0x10 24. " EBS[1] ,Error during write/read transfer" "Write,Read"
|
|
rbitfld.long 0x10 23. " EBS[0] ,Error during data transfer by RxDMA/TxDMA" "RxDMA,TxDMA"
|
|
rbitfld.long 0x10 20.--22. " TPS ,Transmit process state" "Stopped,Running/Fetching,Running/Waiting,Running/Reading,,,Suspended,Running/Closing"
|
|
rbitfld.long 0x10 17.--19. " RPS ,Receive process state" "Stopped,Running/Fetching,,Running/Waiting,Suspended,Running/Closing,,Running/Transferring"
|
|
textline " "
|
|
eventfld.long 0x10 16. " NIS ,Normal interrupt summary" "Not occurred,Occurred"
|
|
eventfld.long 0x10 15. " AIS ,Abnormal interrupt summary" "Not occurred,Occurred"
|
|
eventfld.long 0x10 14. " ERS ,Early receive status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 13. " FBES ,Fatal bus error status" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x10 10. " ETS ,Early transmit status" "Not tranfered,Transfered"
|
|
eventfld.long 0x10 9. " RWTS ,Receive watchdog timeout status" "No timeout,Timeout"
|
|
eventfld.long 0x10 8. " RPSS ,Receive process stopped status" "Not stopped,Stopped"
|
|
eventfld.long 0x10 7. " RBUS ,Receive buffer unavailable status" "Available,Not available"
|
|
textline " "
|
|
eventfld.long 0x10 6. " RS ,Receive status" "Not completed,Completed"
|
|
eventfld.long 0x10 5. " TUS ,Transmit underflow status" "No underflow,Underflow"
|
|
eventfld.long 0x10 4. " ROS ,Receive overflow status" "No overflow,Overflow"
|
|
eventfld.long 0x10 3. " TJTS ,Transmit jabber timeout status" "No timeout,Timeout"
|
|
textline " "
|
|
eventfld.long 0x10 2. " TBUS ,Transmit buffer unavailable status" "Available,Not available"
|
|
eventfld.long 0x10 1. " TPSS ,Transmit process stopped status" "Not stopped,Stopped"
|
|
eventfld.long 0x10 0. " TS ,Transmit status" "Not finished,Finished"
|
|
if (((per.l(ad:0x40028000+0x1018))&0x2200000)==0x00)
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "ETH_DMAOMR,Ethernet DMA Operation Mode Register"
|
|
bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes"
|
|
bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes"
|
|
bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset"
|
|
bitfld.long 0x00 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16"
|
|
bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded"
|
|
bitfld.long 0x00 3.--4. " RTC ,Receive threshold control" "64,32,96,128"
|
|
bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second"
|
|
bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
elif (((per.l(ad:0x40028000+0x1018))&0x2200000)==0x200000)
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "ETH_DMAOMR,Ethernet DMA Operation Mode Register"
|
|
bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes"
|
|
bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes"
|
|
bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset"
|
|
bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded"
|
|
bitfld.long 0x00 3.--4. " RTC ,Receive threshold control" "64,32,96,128"
|
|
bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second"
|
|
bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
elif (((per.l(ad:0x40028000+0x1018))&0x2200000)==0x2000000)
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "ETH_DMAOMR,Ethernet DMA Operation Mode Register"
|
|
bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes"
|
|
bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes"
|
|
bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset"
|
|
bitfld.long 0x00 14.--16. " TTC ,Transmit threshold control" "64,128,192,256,40,32,24,16"
|
|
bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded"
|
|
bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second"
|
|
bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
else
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "ETH_DMAOMR,Ethernet DMA Operation Mode Register"
|
|
bitfld.long 0x00 26. " DTCEFD ,Dropping of TCP/IP checksum error frames disable" "No,Yes"
|
|
bitfld.long 0x00 25. " RSF ,Receive store and forward" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DFRF ,Disable flushing of received frames" "No,Yes"
|
|
bitfld.long 0x00 21. " TSF ,Transmit store and forward" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FTF ,Flush transmit FIFO" "No reset,Reset"
|
|
bitfld.long 0x00 13. " ST ,Start/stop transmission" "Stopped,Started"
|
|
bitfld.long 0x00 7. " FEF ,Forward error frames" "Not forwarded,Forwarded"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FUGF ,Forward undersized good frames" "Not forwarded,Forwarded"
|
|
bitfld.long 0x00 2. " OSF ,Operate on second frame" "Normal,On second"
|
|
bitfld.long 0x00 1. " SR ,Start/stop receive" "Stopped,Started"
|
|
endif
|
|
group.long 0x101C++0x03
|
|
line.long 0x00 "ETH_DMAIER,Ethernet DMA Interrupt Enable Register"
|
|
bitfld.long 0x00 16. " NISE ,Normal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " AISE ,Abnormal interrupt summary enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ERIE ,Early receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " FBEIE ,Fatal bus error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ETIE ,Early transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWTIE ,Receive watchdog timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RPSIE ,Receive process stopped interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RBUIE ,Receive buffer unavailable interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TUIE ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ROIE ,Overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TJTIE ,Transmit jabber timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TBUIE ,Transmit buffer unavailable interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TPSIE ,Transmit process stopped interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x1020++0x03
|
|
hide.long 0x00 "ETH_DMAMFBOCR,Ethernet DMA Missed Frame And Buffer Overflow Counter Register"
|
|
in
|
|
group.long 0x1024++0x03
|
|
line.long 0x00 "ETH_DMARSWTR,Ethernet DMA Receive Status Watchdog Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RSWTC ,Receive status (RS) watchdog timer count"
|
|
rgroup.long 0x1048++0x0F
|
|
line.long 0x00 "ETH_DMACHTDR,Ethernet DMA Current Host Transmit Descriptor Register"
|
|
line.long 0x04 "ETH_DMACHRDR,Ethernet DMA Current Host Receive Descriptor Register"
|
|
line.long 0x08 "ETH_DMACHTBAR,Ethernet DMA Current Host Transmit Buffer Address Register"
|
|
line.long 0x0C "ETH_DMACHRBAR,Ethernet DMA Current Host Receive Buffer Address Register"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "Device Electronic Signature"
|
|
base ad:0x1ffff7e0
|
|
width 8.
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "F_SIZE,Flash Size Register"
|
|
rgroup.word 0x08++0x03
|
|
line.word 0x00 "UD_ID0,Unique Device ID Register 0"
|
|
line.word 0x02 "UD_ID1,Unique Device ID Register 1"
|
|
group.long 0x0c++0x07
|
|
line.long 0x00 "UD_ID2,Unique Device ID Register 2"
|
|
line.long 0x04 "UD_ID3,Unique Device ID Register 3"
|
|
width 0xb
|
|
tree.end
|
|
textline ""
|