21528 lines
1.2 MiB
21528 lines
1.2 MiB
; --------------------------------------------------------------------------------
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; @Title: SAMRH707 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2023-11-17 NEJ
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; @Manufacturer: MICROCHIP - Microchip Technology Inc.
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; @Doc: Generated (TRACE32, build: 164363.), based on:
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; ATSAMRH707F18A.svd (Ver. 0)
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; @Core: Cortex-M7F
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; @Chip: SAMRH707F18B
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: persamrh707.per 17080 2023-11-24 10:50:20Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M7F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes"
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bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes"
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bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes"
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textline " "
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bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes"
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bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes"
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bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
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textline " "
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bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes"
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bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
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textline ""
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..."
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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textline " "
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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textline " "
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x13
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line.long 0x00 "HFSR,HardFault Status Register"
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eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
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eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred"
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eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred"
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eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred"
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eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred"
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line.long 0x08 "MMFAR,MemManage Fault Address Register"
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line.long 0x0C "BFAR,BusFault Address Register"
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line.long 0x10 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Triggered Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..."
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..."
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textline " "
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bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
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bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
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bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
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textline " "
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bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
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bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
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bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..."
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification"
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wgroup.long 0xF58++0x1F
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line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU"
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line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)"
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line.long 0x08 "DCISW,Data cache invalidate by set/way"
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line.long 0x0C "DCCMVAU,Data cache by address to PoU"
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line.long 0x10 "DCCMVAC,Data cache clean by address to PoC"
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line.long 0x14 "DCCSW,Data cache clean by set/way"
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line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC"
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line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way"
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group.long 0xF90++0x13
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line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register"
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bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
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bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
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bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x08 "AHBPCR,AHBP control register"
|
|
bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..."
|
|
bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled"
|
|
line.long 0x0C "CACR,L1 Cache Control Register"
|
|
bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes"
|
|
bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled"
|
|
line.long 0x10 "AHBSCR,AHB Slave Control Register"
|
|
bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion"
|
|
bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI"
|
|
group.long 0xFA8++0x03
|
|
line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register"
|
|
bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR"
|
|
bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred"
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "IEBR0,Instruction Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "IEBR1,Instruction Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB8++0x03
|
|
line.long 0x00 "DEBR0,Data Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFBC++0x03
|
|
line.long 0x00 "DEBR1,Data Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
width 6.
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM7F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
newline
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
newline
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
newline
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x40200000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 4. "CMPRST,Comparison Restart" "0,1"
|
|
bitfld.long 0x0 1. "START,Start Conversion" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "USEQ,User Sequence Enable" "0: Normal mode: The controller converts channels in..,1: User Sequence mode: The sequence respects what.."
|
|
bitfld.long 0x0 30. "MAXSPEED,Maximum Sampling Rate Enable in Freerun Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "TRANSFER,Transfer Time" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TRACKTIM,Tracking Time"
|
|
newline
|
|
bitfld.long 0x0 23. "ANACH,Analog Change" "0: No analog change on channel switching: DIFF0..,1: Allows different analog settings for each.."
|
|
bitfld.long 0x0 20.--21. "SETTLING,Analog Settlings Time" "0: 3 periods of ADCCLK,1: 5 periods of ADCCLK,2: 9 periods of ADCCLK,3: 17 periods of ADCCLK"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "STARTUP,Startup Time"
|
|
hexmask.long.byte 0x0 8.--15. 1. "PRESCAL,Prescaler Rate Selection"
|
|
newline
|
|
bitfld.long 0x0 7. "FREERUN,Free running" "0: Normal Mode,1: Free Run Mode: Never wait for any trigger."
|
|
bitfld.long 0x0 6. "FWUP,Fast Wakeup" "0: If SLEEP is 1 then both ADC core and reference..,1: If SLEEP is 1 then Fast Wakeup Sleep mode: The.."
|
|
newline
|
|
bitfld.long 0x0 5. "SLEEP,Sleep Mode" "0: Normal Mode: The ADC core and reference voltage..,1: Sleep Mode: The wakeup time can be modified by.."
|
|
bitfld.long 0x0 4. "LOWRES,Low resolution" "0: RESOLUTION-bit resolution.,1: RESOLUTION_2-bit resolution"
|
|
newline
|
|
bitfld.long 0x0 1.--3. "TRGSEL,Trigger Selection" "0: ADTRG,1: TIOA0,2: TIOA1,3: TIOA2,4: PWM0 Event 0,5: PWM0 Event 1,6: PWM1 Event 0,7: PWM1 Event 1"
|
|
bitfld.long 0x0 0. "TRGEN,Trigger Enable" "0: Hardware triggers are disabled. Starting a..,1: Hardware trigger selected by TRGSEL is enabled."
|
|
line.long 0x4 "SEQR1,Channel Sequence Register 1"
|
|
hexmask.long.byte 0x4 28.--31. 1. "USCH8,User Sequence Number 8"
|
|
hexmask.long.byte 0x4 24.--27. 1. "USCH7,User Sequence Number 7"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "USCH6,User Sequence Number 6"
|
|
hexmask.long.byte 0x4 16.--19. 1. "USCH5,User Sequence Number 5"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "USCH4,User Sequence Number 4"
|
|
hexmask.long.byte 0x4 8.--11. 1. "USCH3,User Sequence Number 3"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "USCH2,User Sequence Number 2"
|
|
hexmask.long.byte 0x4 0.--3. 1. "USCH1,User Sequence Number 1"
|
|
line.long 0x8 "SEQR2,Channel Sequence Register 2"
|
|
hexmask.long.byte 0x8 28.--31. 1. "USCH16,User Sequence Number 16"
|
|
hexmask.long.byte 0x8 24.--27. 1. "USCH15,User Sequence Number 15"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "USCH14,User Sequence Number 14"
|
|
hexmask.long.byte 0x8 16.--19. 1. "USCH13,User Sequence Number 13"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "USCH12,User Sequence Number 12"
|
|
hexmask.long.byte 0x8 8.--11. 1. "USCH11,User Sequence Number 11"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "USCH10,User Sequence Number 10"
|
|
hexmask.long.byte 0x8 0.--3. 1. "USCH9,User Sequence Number 9"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "CHER,Channel Enable Register"
|
|
bitfld.long 0x0 15. "CH15,Channel 15 Enable" "0,1"
|
|
bitfld.long 0x0 14. "CH14,Channel 14 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CH13,Channel 13 Enable" "0,1"
|
|
bitfld.long 0x0 12. "CH12,Channel 12 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CH11,Channel 11 Enable" "0,1"
|
|
bitfld.long 0x0 10. "CH10,Channel 10 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CH9,Channel 9 Enable" "0,1"
|
|
bitfld.long 0x0 8. "CH8,Channel 8 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CH7,Channel 7 Enable" "0,1"
|
|
bitfld.long 0x0 6. "CH6,Channel 6 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CH5,Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 4. "CH4,Channel 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 2. "CH2,Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CH1,Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 0. "CH0,Channel 0 Enable" "0,1"
|
|
line.long 0x4 "CHDR,Channel Disable Register"
|
|
bitfld.long 0x4 15. "CH15,Channel 15 Disable" "0,1"
|
|
bitfld.long 0x4 14. "CH14,Channel 14 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CH13,Channel 13 Disable" "0,1"
|
|
bitfld.long 0x4 12. "CH12,Channel 12 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CH11,Channel 11 Disable" "0,1"
|
|
bitfld.long 0x4 10. "CH10,Channel 10 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CH9,Channel 9 Disable" "0,1"
|
|
bitfld.long 0x4 8. "CH8,Channel 8 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH7,Channel 7 Disable" "0,1"
|
|
bitfld.long 0x4 6. "CH6,Channel 6 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CH5,Channel 5 Disable" "0,1"
|
|
bitfld.long 0x4 4. "CH4,Channel 4 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CH3,Channel 3 Disable" "0,1"
|
|
bitfld.long 0x4 2. "CH2,Channel 2 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CH1,Channel 1 Disable" "0,1"
|
|
bitfld.long 0x4 0. "CH0,Channel 0 Disable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "CHSR,Channel Status Register"
|
|
bitfld.long 0x0 15. "CH15,Channel 15 Status" "0,1"
|
|
bitfld.long 0x0 14. "CH14,Channel 14 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CH13,Channel 13 Status" "0,1"
|
|
bitfld.long 0x0 12. "CH12,Channel 12 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CH11,Channel 11 Status" "0,1"
|
|
bitfld.long 0x0 10. "CH10,Channel 10 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CH9,Channel 9 Status" "0,1"
|
|
bitfld.long 0x0 8. "CH8,Channel 8 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CH7,Channel 7 Status" "0,1"
|
|
bitfld.long 0x0 6. "CH6,Channel 6 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CH5,Channel 5 Status" "0,1"
|
|
bitfld.long 0x0 4. "CH4,Channel 4 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,Channel 3 Status" "0,1"
|
|
bitfld.long 0x0 2. "CH2,Channel 2 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CH1,Channel 1 Status" "0,1"
|
|
bitfld.long 0x0 0. "CH0,Channel 0 Status" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "LCDR,Last Converted Data Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "CHNBOSR,Channel Number in Oversampling Mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "LDATA,Last Data Converted"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 26. "COMPE,Comparison Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 25. "GOVRE,General Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 15. "EOC15,End of Conversion Interrupt Enable 15" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "EOC14,End of Conversion Interrupt Enable 14" "0,1"
|
|
bitfld.long 0x0 13. "EOC13,End of Conversion Interrupt Enable 13" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EOC12,End of Conversion Interrupt Enable 12" "0,1"
|
|
bitfld.long 0x0 11. "EOC11,End of Conversion Interrupt Enable 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EOC10,End of Conversion Interrupt Enable 10" "0,1"
|
|
bitfld.long 0x0 9. "EOC9,End of Conversion Interrupt Enable 9" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EOC8,End of Conversion Interrupt Enable 8" "0,1"
|
|
bitfld.long 0x0 7. "EOC7,End of Conversion Interrupt Enable 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EOC6,End of Conversion Interrupt Enable 6" "0,1"
|
|
bitfld.long 0x0 5. "EOC5,End of Conversion Interrupt Enable 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EOC4,End of Conversion Interrupt Enable 4" "0,1"
|
|
bitfld.long 0x0 3. "EOC3,End of Conversion Interrupt Enable 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EOC2,End of Conversion Interrupt Enable 2" "0,1"
|
|
bitfld.long 0x0 1. "EOC1,End of Conversion Interrupt Enable 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOC0,End of Conversion Interrupt Enable 0" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 26. "COMPE,Comparison Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 25. "GOVRE,General Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "DRDY,Data Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 15. "EOC15,End of Conversion Interrupt Disable 15" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "EOC14,End of Conversion Interrupt Disable 14" "0,1"
|
|
bitfld.long 0x4 13. "EOC13,End of Conversion Interrupt Disable 13" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "EOC12,End of Conversion Interrupt Disable 12" "0,1"
|
|
bitfld.long 0x4 11. "EOC11,End of Conversion Interrupt Disable 11" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "EOC10,End of Conversion Interrupt Disable 10" "0,1"
|
|
bitfld.long 0x4 9. "EOC9,End of Conversion Interrupt Disable 9" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "EOC8,End of Conversion Interrupt Disable 8" "0,1"
|
|
bitfld.long 0x4 7. "EOC7,End of Conversion Interrupt Disable 7" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EOC6,End of Conversion Interrupt Disable 6" "0,1"
|
|
bitfld.long 0x4 5. "EOC5,End of Conversion Interrupt Disable 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EOC4,End of Conversion Interrupt Disable 4" "0,1"
|
|
bitfld.long 0x4 3. "EOC3,End of Conversion Interrupt Disable 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EOC2,End of Conversion Interrupt Disable 2" "0,1"
|
|
bitfld.long 0x4 1. "EOC1,End of Conversion Interrupt Disable 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EOC0,End of Conversion Interrupt Disable 0" "0,1"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 26. "COMPE,Comparison Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 25. "GOVRE,General Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 15. "EOC15,End of Conversion Interrupt Mask 15" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "EOC14,End of Conversion Interrupt Mask 14" "0,1"
|
|
bitfld.long 0x0 13. "EOC13,End of Conversion Interrupt Mask 13" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EOC12,End of Conversion Interrupt Mask 12" "0,1"
|
|
bitfld.long 0x0 11. "EOC11,End of Conversion Interrupt Mask 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "EOC10,End of Conversion Interrupt Mask 10" "0,1"
|
|
bitfld.long 0x0 9. "EOC9,End of Conversion Interrupt Mask 9" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "EOC8,End of Conversion Interrupt Mask 8" "0,1"
|
|
bitfld.long 0x0 7. "EOC7,End of Conversion Interrupt Mask 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "EOC6,End of Conversion Interrupt Mask 6" "0,1"
|
|
bitfld.long 0x0 5. "EOC5,End of Conversion Interrupt Mask 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "EOC4,End of Conversion Interrupt Mask 4" "0,1"
|
|
bitfld.long 0x0 3. "EOC3,End of Conversion Interrupt Mask 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EOC2,End of Conversion Interrupt Mask 2" "0,1"
|
|
bitfld.long 0x0 1. "EOC1,End of Conversion Interrupt Mask 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOC0,End of Conversion Interrupt Mask 0" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 26. "COMPE,Comparison Event (cleared on read)" "0,1"
|
|
bitfld.long 0x4 25. "GOVRE,General Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "DRDY,Data Ready (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 15. "EOC15,End of Conversion 15 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "EOC14,End of Conversion 14 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 13. "EOC13,End of Conversion 13 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "EOC12,End of Conversion 12 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 11. "EOC11,End of Conversion 11 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "EOC10,End of Conversion 10 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 9. "EOC9,End of Conversion 9 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "EOC8,End of Conversion 8 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 7. "EOC7,End of Conversion 7 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "EOC6,End of Conversion 6 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 5. "EOC5,End of Conversion 5 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "EOC4,End of Conversion 4 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 3. "EOC3,End of Conversion 3 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EOC2,End of Conversion 2 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 1. "EOC1,End of Conversion 1 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EOC0,End of Conversion 0 (automatically set / cleared)" "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "OVER,Overrun Status Register"
|
|
bitfld.long 0x0 15. "OVRE15,Overrun Error 15" "0,1"
|
|
bitfld.long 0x0 14. "OVRE14,Overrun Error 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OVRE13,Overrun Error 13" "0,1"
|
|
bitfld.long 0x0 12. "OVRE12,Overrun Error 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OVRE11,Overrun Error 11" "0,1"
|
|
bitfld.long 0x0 10. "OVRE10,Overrun Error 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OVRE9,Overrun Error 9" "0,1"
|
|
bitfld.long 0x0 8. "OVRE8,Overrun Error 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OVRE7,Overrun Error 7" "0,1"
|
|
bitfld.long 0x0 6. "OVRE6,Overrun Error 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE5,Overrun Error 5" "0,1"
|
|
bitfld.long 0x0 4. "OVRE4,Overrun Error 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRE3,Overrun Error 3" "0,1"
|
|
bitfld.long 0x0 2. "OVRE2,Overrun Error 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OVRE1,Overrun Error 1" "0,1"
|
|
bitfld.long 0x0 0. "OVRE0,Overrun Error 0" "0,1"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 28.--29. "ADCMODE,ADC Running Mode" "0: Normal mode of operation.,1: Offset Error mode to measure the offset error.,2: Gain Error mode to measure the gain error. See..,3: Gain Error mode to measure the gain error. See.."
|
|
bitfld.long 0x0 24. "TAG,Tag of ADC_LCDR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "TRACKX4,Tracking time x4" "0: The ADC_MR.TRACKTIM field effect is multiplied..,1: The ADC_MR.TRACKTIM field effect is multiplied.."
|
|
bitfld.long 0x0 20. "ASTE,Averaging on Single Trigger Event" "0: The average requests several trigger events.,1: The average requests only one trigger event."
|
|
newline
|
|
bitfld.long 0x0 16.--18. "OSR,Over Sampling Rate" "0: No averaging. ADC sample rate is maximum.,1: 1-bit enhanced resolution by averaging. ADC..,2: 2-bit enhanced resolution by averaging. ADC..,3: 3-bit enhanced resolution by averaging. ADC..,4: 4-bit enhanced resolution by averaging. ADC..,?,?,?"
|
|
bitfld.long 0x0 12.--13. "CMPFILTER,Compare Event Filtering" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 9. "CMPALL,Compare All Channels" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CMPSEL,Comparison Selected Channel"
|
|
newline
|
|
bitfld.long 0x0 2. "CMPTYPE,Comparison Type" "0: Any conversion is performed and comparison..,1: Comparison conditions must be met to start the.."
|
|
bitfld.long 0x0 0.--1. "CMPMODE,Comparison Mode" "0: When the converted data is lower than the low..,1: When the converted data is higher than the high..,2: When the converted data is in the comparison..,3: When the converted data is out of the comparison.."
|
|
line.long 0x4 "CWR,Compare Window Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "HIGHTHRES,High Threshold"
|
|
hexmask.long.word 0x4 0.--15. 1. "LOWTHRES,Low Threshold"
|
|
line.long 0x8 "CGR,Channel Gain Register"
|
|
bitfld.long 0x8 30.--31. "GAIN15,Gain for Channel 15" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
bitfld.long 0x8 28.--29. "GAIN14,Gain for Channel 14" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
newline
|
|
bitfld.long 0x8 26.--27. "GAIN13,Gain for Channel 13" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
bitfld.long 0x8 24.--25. "GAIN12,Gain for Channel 12" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
newline
|
|
bitfld.long 0x8 22.--23. "GAIN11,Gain for Channel 11" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
bitfld.long 0x8 20.--21. "GAIN10,Gain for Channel 10" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
newline
|
|
bitfld.long 0x8 18.--19. "GAIN9,Gain for Channel 9" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
bitfld.long 0x8 16.--17. "GAIN8,Gain for Channel 8" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
newline
|
|
bitfld.long 0x8 14.--15. "GAIN7,Gain for Channel 7" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
bitfld.long 0x8 12.--13. "GAIN6,Gain for Channel 6" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
newline
|
|
bitfld.long 0x8 10.--11. "GAIN5,Gain for Channel 5" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
bitfld.long 0x8 8.--9. "GAIN4,Gain for Channel 4" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
newline
|
|
bitfld.long 0x8 6.--7. "GAIN3,Gain for Channel 3" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
bitfld.long 0x8 4.--5. "GAIN2,Gain for Channel 2" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
newline
|
|
bitfld.long 0x8 2.--3. "GAIN1,Gain for Channel 1" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
bitfld.long 0x8 0.--1. "GAIN0,Gain for Channel 0" "0: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,1: Single-ended gain = 1 (ADC_COR.DIFFx = 0)..,2: Single-ended gain = 2 (ADC_COR.DIFFx = 0)..,3: Single-ended gain = 4 (ADC_COR.DIFFx = 0).."
|
|
line.long 0xC "COR,Channel Offset Register"
|
|
bitfld.long 0xC 31. "DIFF15,Differential Inputs for Channel 15" "0,1"
|
|
bitfld.long 0xC 30. "DIFF14,Differential Inputs for Channel 14" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "DIFF13,Differential Inputs for Channel 13" "0,1"
|
|
bitfld.long 0xC 28. "DIFF12,Differential Inputs for Channel 12" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "DIFF11,Differential Inputs for Channel 11" "0,1"
|
|
bitfld.long 0xC 26. "DIFF10,Differential Inputs for Channel 10" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "DIFF9,Differential Inputs for Channel 9" "0,1"
|
|
bitfld.long 0xC 24. "DIFF8,Differential Inputs for Channel 8" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "DIFF7,Differential Inputs for Channel 7" "0,1"
|
|
bitfld.long 0xC 22. "DIFF6,Differential Inputs for Channel 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "DIFF5,Differential Inputs for Channel 5" "0,1"
|
|
bitfld.long 0xC 20. "DIFF4,Differential Inputs for Channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "DIFF3,Differential Inputs for Channel 3" "0,1"
|
|
bitfld.long 0xC 18. "DIFF2,Differential Inputs for Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "DIFF1,Differential Inputs for Channel 1" "0,1"
|
|
bitfld.long 0xC 16. "DIFF0,Differential Inputs for Channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "OFFSET15," "0,1"
|
|
bitfld.long 0xC 14. "OFFSET14," "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "OFFSET13," "0,1"
|
|
bitfld.long 0xC 12. "OFFSET12," "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "OFFSET11," "0,1"
|
|
bitfld.long 0xC 10. "OFFSET10," "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "OFFSET9," "0,1"
|
|
bitfld.long 0xC 8. "OFFSET8," "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "OFFSET7," "0,1"
|
|
bitfld.long 0xC 6. "OFFSET6," "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "OFFSET5," "0,1"
|
|
bitfld.long 0xC 4. "OFFSET4," "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OFFSET3," "0,1"
|
|
bitfld.long 0xC 2. "OFFSET2," "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OFFSET1," "0,1"
|
|
bitfld.long 0xC 0. "OFFSET0," "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "CDR[$1],Channel Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted Data"
|
|
repeat.end
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "ACR,Analog Control Register"
|
|
bitfld.long 0x0 8.--9. "IBCTL,ADC Bias Current Control" "0,1,2,3"
|
|
group.long 0xD4++0x7
|
|
line.long 0x0 "CVR,Correction Values Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "GAINCORR,Gain Correction"
|
|
hexmask.long.word 0x0 0.--15. 1. "OFFSETCORR,Offset Correction"
|
|
line.long 0x4 "CECR,Channel Error Correction Register"
|
|
bitfld.long 0x4 15. "ECORR15,Error Correction Enable for channel 15" "0,1"
|
|
bitfld.long 0x4 14. "ECORR14,Error Correction Enable for channel 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ECORR13,Error Correction Enable for channel 13" "0,1"
|
|
bitfld.long 0x4 12. "ECORR12,Error Correction Enable for channel 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ECORR11,Error Correction Enable for channel 11" "0,1"
|
|
bitfld.long 0x4 10. "ECORR10,Error Correction Enable for channel 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ECORR9,Error Correction Enable for channel 9" "0,1"
|
|
bitfld.long 0x4 8. "ECORR8,Error Correction Enable for channel 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ECORR7,Error Correction Enable for channel 7" "0,1"
|
|
bitfld.long 0x4 6. "ECORR6,Error Correction Enable for channel 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ECORR5,Error Correction Enable for channel 5" "0,1"
|
|
bitfld.long 0x4 4. "ECORR4,Error Correction Enable for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ECORR3,Error Correction Enable for channel 3" "0,1"
|
|
bitfld.long 0x4 2. "ECORR2,Error Correction Enable for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ECORR1,Error Correction Enable for channel 1" "0,1"
|
|
bitfld.long 0x4 0. "ECORR0,Error Correction Enable for channel 0" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCTEN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "CHIPID (Chip Identifier)"
|
|
base ad:0x40100000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CIDR,Chip ID Register"
|
|
bitfld.long 0x0 31. "EXT,Extension Flag" "0,1"
|
|
bitfld.long 0x0 28.--30. "NVPTYP,Nonvolatile Program Memory Type" "0: ROM,1: ROMless or on-chip Flash,2: Embedded Flash Memory,3: ROM and Embedded Flash Memory - NVPSIZ is ROM..,4: SRAM emulating ROM,?,?,?"
|
|
hexmask.long.byte 0x0 20.--27. 1. "ARCH,Architecture Identifier"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SRAMSIZ,Internal SRAM Size"
|
|
hexmask.long.byte 0x0 12.--15. 1. "NVPSIZ2,Second Nonvolatile Program Memory Size"
|
|
hexmask.long.byte 0x0 8.--11. 1. "NVPSIZ,Nonvolatile Program Memory Size"
|
|
newline
|
|
bitfld.long 0x0 5.--7. "EPROC,Embedded Processor" "0: Cortex-M7,1: ARM946ES,2: ARM7TDMI,3: Cortex-M3,4: ARM920T,5: ARM926EJS,6: Cortex-A5,7: Cortex-M4"
|
|
hexmask.long.byte 0x0 0.--4. 1. "VERSION,Version of the Device"
|
|
line.long 0x4 "EXID,Chip ID Extension Register"
|
|
hexmask.long 0x4 0.--31. 1. "EXID,Chip ID Extension"
|
|
tree.end
|
|
tree "COREDEBUG"
|
|
base ad:0xE000EDF0
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x0 25. "S_RESET_ST," "0,1"
|
|
bitfld.long 0x0 24. "S_RETIRE_ST," "0,1"
|
|
bitfld.long 0x0 19. "S_LOCKUP," "0,1"
|
|
bitfld.long 0x0 18. "S_SLEEP," "0,1"
|
|
bitfld.long 0x0 17. "S_HALT," "0,1"
|
|
bitfld.long 0x0 16. "S_REGRDY," "0,1"
|
|
bitfld.long 0x0 5. "C_SNAPSTALL," "0,1"
|
|
bitfld.long 0x0 3. "C_MASKINTS," "0,1"
|
|
bitfld.long 0x0 2. "C_STEP," "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "C_HALT," "0,1"
|
|
bitfld.long 0x0 0. "C_DEBUGEN," "0,1"
|
|
wgroup.long 0xF4++0x3
|
|
line.long 0x0 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x0 16. "REGWnR," "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "REGSEL,"
|
|
group.long 0xF8++0x7
|
|
line.long 0x0 "DCRDR,Debug Core Register Data Register"
|
|
line.long 0x4 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x4 24. "TRCENA," "0,1"
|
|
bitfld.long 0x4 19. "MON_REQ," "0,1"
|
|
bitfld.long 0x4 18. "MON_STEP," "0,1"
|
|
bitfld.long 0x4 17. "MON_PEND," "0,1"
|
|
bitfld.long 0x4 16. "MON_EN," "0,1"
|
|
bitfld.long 0x4 10. "VC_HARDERR," "0,1"
|
|
bitfld.long 0x4 9. "VC_INTERR," "0,1"
|
|
bitfld.long 0x4 8. "VC_BUSERR," "0,1"
|
|
bitfld.long 0x4 7. "VC_STATERR," "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "VC_CHKERR," "0,1"
|
|
bitfld.long 0x4 5. "VC_NOCPERR," "0,1"
|
|
bitfld.long 0x4 4. "VC_MMERR," "0,1"
|
|
bitfld.long 0x4 0. "VC_CORERESET," "0,1"
|
|
tree.end
|
|
tree "CRCCU (Cyclic Redundancy Check)"
|
|
base ad:0x40018000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DSCR,CRCCU Descriptor Base Register"
|
|
hexmask.long.tbyte 0x0 9.--31. 1. "DSCR,Descriptor Base Address"
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "DMA_EN,CRCCU DMA Enable Register"
|
|
bitfld.long 0x0 0. "DMAEN,DMA Enable" "0,1"
|
|
line.long 0x4 "DMA_DIS,CRCCU DMA Disable Register"
|
|
bitfld.long 0x4 0. "DMADIS,DMA Disable" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "DMA_SR,CRCCU DMA Status Register"
|
|
bitfld.long 0x0 0. "DMASR,DMA Status" "0,1"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "DMA_IER,CRCCU DMA Interrupt Enable Register"
|
|
bitfld.long 0x0 0. "DMAIER,Interrupt Enable" "0,1"
|
|
line.long 0x4 "DMA_IDR,CRCCU DMA Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "DMAIDR,Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "DMA_IMR,CRCCU DMA Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "DMAIMR,Interrupt Mask" "0,1"
|
|
line.long 0x4 "DMA_ISR,CRCCU DMA Interrupt Status Register"
|
|
bitfld.long 0x4 0. "DMAISR,Interrupt Status" "0,1"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x0 "CR,CRCCU Control Register"
|
|
bitfld.long 0x0 0. "RESET,CRC Computation Reset" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "MR,CRCCU Mode Register"
|
|
bitfld.long 0x0 17. "BITORDER,Precomputation Bit Swap Operation of the CRC" "0: CRC computation is performed from the most..,1: CRC computation is performed from the least.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "DIVIDER,Request Divider"
|
|
bitfld.long 0x0 2.--3. "PTYPE,Primitive Polynomial" "0: Polynom 0x04C11DB7,1: Polynom 0x1EDC6F41,2: Polynom 0x1021,?"
|
|
bitfld.long 0x0 1. "COMPARE,CRC Compare" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,CRC Enable" "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "SR,CRCCU Status Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRC,Cyclic Redundancy Check Value"
|
|
wgroup.long 0x40++0x7
|
|
line.long 0x0 "IER,CRCCU Interrupt Enable Register"
|
|
bitfld.long 0x0 0. "ERRIER,CRC Error Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,CRCCU Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "ERRIDR,CRC Error Interrupt Disable" "0,1"
|
|
rgroup.long 0x48++0x7
|
|
line.long 0x0 "IMR,CRCCU Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "ERRIMR,CRC Error Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,CRCCU Interrupt Status Register"
|
|
bitfld.long 0x4 0. "ERRISR,CRC Error Interrupt Status" "0,1"
|
|
tree.end
|
|
tree "DACC (Digital-to-Analog Converter Controller)"
|
|
base ad:0x40014000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "STARTUP,Startup Time Selection"
|
|
bitfld.long 0x0 22. "CLKDIV,Shall be always write at '0'" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MAXS,Maximum Speed Mode" "0: Normal mode,1: Maximum speed mode enabled"
|
|
bitfld.long 0x0 20. "TAG,Tag Selection Mode" "0: Tag selection mode disabled. Using USER_SEL to..,1: Tag selection mode enabled"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "USER_SEL,User Channel Selection" "0: Channel 0,1: Channel 1,2: Channel 2,?"
|
|
bitfld.long 0x0 8. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "WORD,Word Transfer" "0: Half-word transfer,1: Word transfer"
|
|
bitfld.long 0x0 1.--3. "TRGSEL,Trigger Selection" "0: External trigger,1: TIOA Output of the Timer Counter Channel 0,2: TIOA Output of the Timer Counter Channel 1,3: TIOA Output of the Timer Counter Channel 2,4: PWM Event Line 0,5: PWM Event Line 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 0. "TRGEN,Trigger Enable" "0: External trigger mode disabled. DACC in..,1: External trigger mode enabled."
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "CHER,Channel Enable Register"
|
|
bitfld.long 0x0 2. "CH2,Channel 2 Enable" "0,1"
|
|
bitfld.long 0x0 1. "CH1,Channel 1 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CH0,Channel 0 Enable" "0,1"
|
|
line.long 0x4 "CHDR,Channel Disable Register"
|
|
bitfld.long 0x4 2. "CH2,Channel 2 Disable" "0,1"
|
|
bitfld.long 0x4 1. "CH1,Channel 1 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CH0,Channel 0 Disable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "CHSR,Channel Status Register"
|
|
bitfld.long 0x0 2. "CH2,Channel 2 Status" "0,1"
|
|
bitfld.long 0x0 1. "CH1,Channel 1 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CH0,Channel 0 Status" "0,1"
|
|
wgroup.long 0x20++0xB
|
|
line.long 0x0 "CDR,Conversion Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data to Convert"
|
|
line.long 0x4 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x4 1. "EOC,End of Conversion Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "TXRDY,Transmit Ready Interrupt Enable" "0,1"
|
|
line.long 0x8 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x8 1. "EOC,End of Conversion Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 0. "TXRDY,Transmit Ready Interrupt Disable." "0,1"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 1. "EOC,End of Conversion Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "TXRDY,Transmit Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 1. "EOC,End of Conversion Interrupt Flag" "0,1"
|
|
bitfld.long 0x4 0. "TXRDY,Transmit Ready Interrupt Flag" "0,1"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "ACR,Analog Current Register"
|
|
bitfld.long 0x0 8.--9. "IBCTLDACCORE,Bias Current Control for DAC Core" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "IBCTLCH2,Analog Output Current Control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IBCTLCH1,Analog Output Current Control" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IBCTLCH0,Analog Output Current Control" "0,1,2,3"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "DWT (Data Watchpoint and Trace Register)"
|
|
base ad:0xE0001000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CTRL,Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "NUMCOMP,"
|
|
bitfld.long 0x0 27. "NOTRCPKT," "0,1"
|
|
bitfld.long 0x0 26. "NOEXTTRIG," "0,1"
|
|
bitfld.long 0x0 25. "NOCYCCNT," "0,1"
|
|
bitfld.long 0x0 24. "NOPRFCNT," "0,1"
|
|
bitfld.long 0x0 22. "CYCEVTENA," "0,1"
|
|
bitfld.long 0x0 21. "FOLDEVTENA," "0,1"
|
|
bitfld.long 0x0 20. "LSUEVTENA," "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "SLEEPEVTENA," "0,1"
|
|
bitfld.long 0x0 18. "EXCEVTENA," "0,1"
|
|
bitfld.long 0x0 17. "CPIEVTENA," "0,1"
|
|
bitfld.long 0x0 16. "EXCTRCENA," "0,1"
|
|
bitfld.long 0x0 12. "PCSAMPLENA," "0,1"
|
|
bitfld.long 0x0 10.--11. "SYNCTAP," "0,1,2,3"
|
|
bitfld.long 0x0 9. "CYCTAP," "0,1"
|
|
hexmask.long.byte 0x0 5.--8. 1. "POSTINIT,"
|
|
newline
|
|
hexmask.long.byte 0x0 1.--4. 1. "POSTPRESET,"
|
|
bitfld.long 0x0 0. "CYCCNTENA," "0,1"
|
|
line.long 0x4 "CYCCNT,Cycle Count Register"
|
|
line.long 0x8 "CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CPICNT,"
|
|
line.long 0xC "EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "EXCCNT,"
|
|
line.long 0x10 "SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SLEEPCNT,"
|
|
line.long 0x14 "LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. "LSUCNT,"
|
|
line.long 0x18 "FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "FOLDCNT,"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PCSR,Program Counter Sample Register"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "COMP0,Comparator Register 0"
|
|
line.long 0x4 "MASK0,Mask Register 0"
|
|
hexmask.long.byte 0x4 0.--4. 1. "MASK,"
|
|
line.long 0x8 "FUNCTION0,Function Register 0"
|
|
bitfld.long 0x8 24. "MATCHED," "0,1"
|
|
hexmask.long.byte 0x8 16.--19. 1. "DATAVADDR1,"
|
|
hexmask.long.byte 0x8 12.--15. 1. "DATAVADDR0,"
|
|
bitfld.long 0x8 10.--11. "DATAVSIZE," "0,1,2,3"
|
|
bitfld.long 0x8 9. "LNK1ENA," "0,1"
|
|
bitfld.long 0x8 8. "DATAVMATCH," "0,1"
|
|
bitfld.long 0x8 7. "CYCMATCH," "0,1"
|
|
bitfld.long 0x8 5. "EMITRANGE," "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "FUNCTION,"
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "COMP1,Comparator Register 1"
|
|
line.long 0x4 "MASK1,Mask Register 1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "MASK,"
|
|
line.long 0x8 "FUNCTION1,Function Register 1"
|
|
bitfld.long 0x8 24. "MATCHED," "0,1"
|
|
hexmask.long.byte 0x8 16.--19. 1. "DATAVADDR1,"
|
|
hexmask.long.byte 0x8 12.--15. 1. "DATAVADDR0,"
|
|
bitfld.long 0x8 10.--11. "DATAVSIZE," "0,1,2,3"
|
|
bitfld.long 0x8 9. "LNK1ENA," "0,1"
|
|
bitfld.long 0x8 8. "DATAVMATCH," "0,1"
|
|
bitfld.long 0x8 7. "CYCMATCH," "0,1"
|
|
bitfld.long 0x8 5. "EMITRANGE," "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "FUNCTION,"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "COMP2,Comparator Register 2"
|
|
line.long 0x4 "MASK2,Mask Register 2"
|
|
hexmask.long.byte 0x4 0.--4. 1. "MASK,"
|
|
line.long 0x8 "FUNCTION2,Function Register 2"
|
|
bitfld.long 0x8 24. "MATCHED," "0,1"
|
|
hexmask.long.byte 0x8 16.--19. 1. "DATAVADDR1,"
|
|
hexmask.long.byte 0x8 12.--15. 1. "DATAVADDR0,"
|
|
bitfld.long 0x8 10.--11. "DATAVSIZE," "0,1,2,3"
|
|
bitfld.long 0x8 9. "LNK1ENA," "0,1"
|
|
bitfld.long 0x8 8. "DATAVMATCH," "0,1"
|
|
bitfld.long 0x8 7. "CYCMATCH," "0,1"
|
|
bitfld.long 0x8 5. "EMITRANGE," "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "FUNCTION,"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "COMP3,Comparator Register 3"
|
|
line.long 0x4 "MASK3,Mask Register 3"
|
|
hexmask.long.byte 0x4 0.--4. 1. "MASK,"
|
|
line.long 0x8 "FUNCTION3,Function Register 3"
|
|
bitfld.long 0x8 24. "MATCHED," "0,1"
|
|
hexmask.long.byte 0x8 16.--19. 1. "DATAVADDR1,"
|
|
hexmask.long.byte 0x8 12.--15. 1. "DATAVADDR0,"
|
|
bitfld.long 0x8 10.--11. "DATAVSIZE," "0,1,2,3"
|
|
bitfld.long 0x8 9. "LNK1ENA," "0,1"
|
|
bitfld.long 0x8 8. "DATAVMATCH," "0,1"
|
|
bitfld.long 0x8 7. "CYCMATCH," "0,1"
|
|
bitfld.long 0x8 5. "EMITRANGE," "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "FUNCTION,"
|
|
wgroup.long 0xFB0++0x3
|
|
line.long 0x0 "LAR,DWT Software Lock Access Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Lock access control"
|
|
rgroup.long 0xFB4++0x3
|
|
line.long 0x0 "LSR,DWT Software Lock Status Register"
|
|
bitfld.long 0x0 2. "nTT,Not thirty-two bit" "0,1"
|
|
bitfld.long 0x0 1. "SLK,Software Lock status" "0,1"
|
|
bitfld.long 0x0 0. "SLI,Software Lock implemented" "0,1"
|
|
rgroup.long 0xFD0++0x2F
|
|
line.long 0x0 "PID4,DWT Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x0 4.--7. 1. "SIZE,4KB count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DES_2,JEP106 continuation code"
|
|
line.long 0x4 "PID5,DWT Peripheral Identification Register 5"
|
|
line.long 0x8 "PID6,DWT Peripheral Identification Register 6"
|
|
line.long 0xC "PID7,DWT Peripheral Identification Register 7"
|
|
line.long 0x10 "PID0,DWT Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PART_0,Part number bits[7:0]"
|
|
line.long 0x14 "PID1,DWT Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x14 4.--7. 1. "DES_0,JEP106 identification code bits [3:0]"
|
|
hexmask.long.byte 0x14 0.--3. 1. "PART_1,Part number bits[11:8]"
|
|
line.long 0x18 "PID2,DWT Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x18 4.--7. 1. "REVISION,Component revision"
|
|
bitfld.long 0x18 3. "JEDEC,JEDEC assignee value is used" "0,1"
|
|
bitfld.long 0x18 0.--2. "DES_1,JEP106 identification code bits[6:4]" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "PID3,DWT Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "REVAND,RevAnd"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "CMOD,Customer Modified"
|
|
line.long 0x20 "CID0,DWT Component Identification Register 0"
|
|
hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,CoreSight component identification preamble"
|
|
line.long 0x24 "CID1,DWT Component Identification Register 1"
|
|
hexmask.long.byte 0x24 4.--7. 1. "CLASS,CoreSight component class"
|
|
hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,CoreSight component identification preamble"
|
|
line.long 0x28 "CID2,DWT Component Identification Register 2"
|
|
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,CoreSight component identification preamble"
|
|
line.long 0x2C "CID3,DWT Component Identification Register 3"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,CoreSight component identification preamble"
|
|
tree.end
|
|
tree "ETM (Embedded Trace Macrocell)"
|
|
base ad:0xE0041000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,ETM Main Control Register"
|
|
bitfld.long 0x0 28. "TSEN,TimeStamp Enable" "0,1"
|
|
bitfld.long 0x0 21. "PORTSIZE3,Port Size bit 3" "0,1"
|
|
bitfld.long 0x0 16.--17. "PORTMODE,Port Mode bits 1:0" "0,1,2,3"
|
|
bitfld.long 0x0 13. "PORTMODE2,Port Mode bit 2" "0,1"
|
|
bitfld.long 0x0 11. "PORTSEL,ETM Port Select" "0,1"
|
|
bitfld.long 0x0 10. "PROG,ETM Programming" "0,1"
|
|
bitfld.long 0x0 9. "DBGRQ,Debug Request Control" "0,1"
|
|
bitfld.long 0x0 8. "BROUT,Branch Output" "0,1"
|
|
bitfld.long 0x0 7. "STALL,Stall Processor" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "PORTSIZE,Port Size bits 2:0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "ETMPD,ETM Power Down" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "CCR,ETM Configuration Code Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "TRIGGER,ETM Trigger Event Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SR,ETM Status Register"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SCR,ETM System Configuration Register"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "TEEVR,ETM TraceEnable Event Register"
|
|
line.long 0x4 "TECR1,ETM TraceEnable Control 1 Register"
|
|
line.long 0x8 "FFLR,ETM FIFO Full Level Register"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "CNTRLDVR1,ETM Free-running Counter Reload Value"
|
|
rgroup.long 0x1E0++0xB
|
|
line.long 0x0 "SYNCFR,ETM Synchronization Frequency Register"
|
|
line.long 0x4 "IDR,ETM ID Register"
|
|
line.long 0x8 "CCER,ETM Configuration Code Extension Register"
|
|
group.long 0x1F0++0x3
|
|
line.long 0x0 "TESSEICR,ETM TraceEnable Start/Stop EmbeddedICE Control Register"
|
|
group.long 0x1F8++0x3
|
|
line.long 0x0 "TSEVT,ETM TimeStamp Event Register"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "TRACEIDR,ETM CoreSight Trace ID Register"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x0 "IDR2,ETM ID Register 2"
|
|
rgroup.long 0x314++0x3
|
|
line.long 0x0 "PDSR,ETM Device Power-Down Status Register"
|
|
rgroup.long 0xEE0++0x3
|
|
line.long 0x0 "ITMISCIN,ETM Integration Test Miscellaneous Inputs"
|
|
wgroup.long 0xEE8++0x3
|
|
line.long 0x0 "ITTRIGOUT,ETM Integration Test Trigger Out"
|
|
rgroup.long 0xEF0++0x3
|
|
line.long 0x0 "ITATBCTR2,ETM Integration Test ATB Control 2"
|
|
wgroup.long 0xEF8++0x3
|
|
line.long 0x0 "ITATBCTR0,ETM Integration Test ATB Control 0"
|
|
group.long 0xF00++0x3
|
|
line.long 0x0 "ITCTRL,ETM Integration Mode Control Register"
|
|
bitfld.long 0x0 0. "INTEGRATION," "0,1"
|
|
group.long 0xFA0++0x7
|
|
line.long 0x0 "CLAIMSET,ETM Claim Tag Set Register"
|
|
line.long 0x4 "CLAIMCLR,ETM Claim Tag Clear Register"
|
|
wgroup.long 0xFB0++0x3
|
|
line.long 0x0 "LAR,ETM Lock Access Register"
|
|
rgroup.long 0xFB4++0x7
|
|
line.long 0x0 "LSR,ETM Lock Status Register"
|
|
bitfld.long 0x0 2. "ByteAcc," "0,1"
|
|
bitfld.long 0x0 1. "Access," "0,1"
|
|
bitfld.long 0x0 0. "Present," "0,1"
|
|
line.long 0x4 "AUTHSTATUS,ETM Authentication Status Register"
|
|
rgroup.long 0xFCC++0x33
|
|
line.long 0x0 "DEVTYPE,ETM CoreSight Device Type Register"
|
|
line.long 0x4 "PIDR4,ETM Peripheral Identification Register #4"
|
|
line.long 0x8 "PIDR5,ETM Peripheral Identification Register #5"
|
|
line.long 0xC "PIDR6,ETM Peripheral Identification Register #6"
|
|
line.long 0x10 "PIDR7,ETM Peripheral Identification Register #7"
|
|
line.long 0x14 "PIDR0,ETM Peripheral Identification Register #0"
|
|
line.long 0x18 "PIDR1,ETM Peripheral Identification Register #1"
|
|
line.long 0x1C "PIDR2,ETM Peripheral Identification Register #2"
|
|
line.long 0x20 "PIDR3,ETM Peripheral Identification Register #3"
|
|
line.long 0x24 "CIDR0,ETM Component Identification Register #0"
|
|
line.long 0x28 "CIDR1,ETM Component Identification Register #1"
|
|
line.long 0x2C "CIDR2,ETM Component Identification Register #2"
|
|
line.long 0x30 "CIDR3,ETM Component Identification Register #3"
|
|
tree.end
|
|
tree "FLEXCOM (Flexible Serial Communication Controller)"
|
|
base ad:0x0
|
|
tree "FLEXCOM0"
|
|
base ad:0x40020000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0xB
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
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bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
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bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
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bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
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bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
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newline
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
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line.long 0x8 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x8 15. "RXSYNH,Received Sync" "0,1"
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newline
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hexmask.long.word 0x8 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.byte 0x4 0.--7. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x250++0x3
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line.long 0x0 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x0 31. "RXIDLEV,Receiver Idle Value" "0,1"
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bitfld.long 0x0 30. "DRIFT,Drift Compensation" "0,1"
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bitfld.long 0x0 29. "ONE,Must Be Set to 1" "0,1"
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bitfld.long 0x0 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
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bitfld.long 0x0 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x0 16.--19. 1. "RX_PL,Receiver Preamble Length"
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newline
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bitfld.long 0x0 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
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newline
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bitfld.long 0x0 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
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newline
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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newline
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
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newline
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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newline
|
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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newline
|
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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newline
|
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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group.long 0x2E4++0x3
|
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
|
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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newline
|
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
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newline
|
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
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|
newline
|
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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|
newline
|
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD8_3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD8_2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD8_1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD8_0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD16_1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD16_0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
rgroup.long 0x6D0++0x3
|
|
line.long 0x0 "FLEX_TWI_DR,TWI Debug Register"
|
|
bitfld.long 0x0 3. "TRP,Transfer Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SWMATCH,SleepWalking Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWEN,SleepWalking Enable" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM1"
|
|
base ad:0x40024000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0xB
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x8 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x8 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x0 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x0 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD8_3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD8_2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD8_1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD8_0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD16_1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD16_0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
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group.long 0x604++0xF
|
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line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
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newline
|
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
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newline
|
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bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
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newline
|
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
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line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
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newline
|
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
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newline
|
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bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
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newline
|
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bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
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hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
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newline
|
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
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newline
|
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
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rgroup.long 0x620++0x3
|
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
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bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
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newline
|
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
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newline
|
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
rgroup.long 0x6D0++0x3
|
|
line.long 0x0 "FLEX_TWI_DR,TWI Debug Register"
|
|
bitfld.long 0x0 3. "TRP,Transfer Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SWMATCH,SleepWalking Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWEN,SleepWalking Enable" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM2"
|
|
base ad:0x40028000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0xB
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x8 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x8 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x250++0x3
|
|
line.long 0x0 "FLEX_US_MAN,USART Manchester Configuration Register"
|
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bitfld.long 0x0 31. "RXIDLEV,Receiver Idle Value" "0,1"
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newline
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bitfld.long 0x0 30. "DRIFT,Drift Compensation" "0,1"
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|
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bitfld.long 0x0 29. "ONE,Must Be Set to 1" "0,1"
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|
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bitfld.long 0x0 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
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bitfld.long 0x0 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
|
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hexmask.long.byte 0x0 16.--19. 1. "RX_PL,Receiver Preamble Length"
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newline
|
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bitfld.long 0x0 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
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newline
|
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bitfld.long 0x0 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
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newline
|
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
|
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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newline
|
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
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rgroup.long 0x2E8++0x3
|
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
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wgroup.long 0x400++0x3
|
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
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|
newline
|
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
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|
newline
|
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
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newline
|
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
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newline
|
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
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group.long 0x404++0x3
|
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
|
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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newline
|
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
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newline
|
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
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newline
|
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
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newline
|
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
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rgroup.long 0x408++0x3
|
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
|
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RD8_3,Receive Data"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD8_2,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RD8_1,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RD8_0,Receive Data"
|
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rgroup.long 0x408++0x3
|
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
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hexmask.long.word 0x0 16.--31. 1. "RD16_1,Receive Data"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD16_0,Receive Data"
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wgroup.long 0x40C++0x3
|
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
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newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
|
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
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rgroup.long 0x410++0x3
|
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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newline
|
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bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
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newline
|
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
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rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
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group.long 0x638++0x3
|
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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group.long 0x640++0x7
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line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
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bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
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newline
|
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bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
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newline
|
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bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
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newline
|
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bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
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line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
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bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
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newline
|
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bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
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group.long 0x650++0x3
|
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line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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|
newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
|
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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rgroup.long 0x660++0x3
|
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
rgroup.long 0x6D0++0x3
|
|
line.long 0x0 "FLEX_TWI_DR,TWI Debug Register"
|
|
bitfld.long 0x0 3. "TRP,Transfer Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SWMATCH,SleepWalking Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWEN,SleepWalking Enable" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM3"
|
|
base ad:0x4002C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0xB
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x8 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x8 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
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hexmask.long.word 0x8 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Character"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Character"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Character"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Character"
|
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wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
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group.long 0x250++0x3
|
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line.long 0x0 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x0 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
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bitfld.long 0x0 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
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newline
|
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hexmask.long.byte 0x0 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
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bitfld.long 0x0 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
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bitfld.long 0x0 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
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newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
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rgroup.long 0x2A4++0x3
|
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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wgroup.long 0x2A8++0x7
|
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Master/Slave Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD8_3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD8_2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD8_1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD8_0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD16_1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD16_0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Slave Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Slave mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Slave Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Slave Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Master Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Master Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Master Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Master Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Slave Mode Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Slave Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Slave Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Slave Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Slave Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Slave Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Slave Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Master Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Slave Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Master Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Slave Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Slave Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Slave Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Slave Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Master or Slave Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Master or Slave Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Master or Slave Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Master or Slave Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Master or Slave Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Master or Slave Transmit Holding Data"
|
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wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Master or Slave Transmit Holding Data 3"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Master or Slave Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Master or Slave Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Master or Slave Transmit Holding Data 0"
|
|
group.long 0x638++0x3
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Master Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Slave Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
group.long 0x640++0x7
|
|
line.long 0x0 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x0 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x0 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0x4 "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0x4 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FILT,RX Digital Filter" "0,1"
|
|
group.long 0x650++0x3
|
|
line.long 0x0 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
rgroup.long 0x6D0++0x3
|
|
line.long 0x0 "FLEX_TWI_DR,TWI Debug Register"
|
|
bitfld.long 0x0 3. "TRP,Transfer Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SWMATCH,SleepWalking Match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKRQ,Clock Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWEN,SleepWalking Enable" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "FLEXRAMECC (Flexible RAM ECC)"
|
|
base ad:0x40100600
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,FLEXRAMECC Control Register"
|
|
bitfld.long 0x0 5. "RST_NOFIX_CPT,reset the un-fixable error counter" "0,1"
|
|
bitfld.long 0x0 4. "RST_FIX_CPT,reset the fixable error counter" "0,1"
|
|
bitfld.long 0x0 2. "TEST_MODE_WR,test mode of ECC protection - write mode" "0,1"
|
|
bitfld.long 0x0 1. "TEST_MODE_RD,test mode of ECC protection - read mode" "0,1"
|
|
bitfld.long 0x0 0. "ONE,Shall be always write at '1'" "0,1"
|
|
line.long 0x4 "TESTCB1,FLEXRAMECC Test mode register 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TCB1,Test Check Bit"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,FLEXRAMECC Status register"
|
|
bitfld.long 0x0 27. "TYPE,write or read access" "0,1"
|
|
bitfld.long 0x0 24.--26. "HES,Hardware Error Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "OVER_NOFIX,counter overflow" "0,1"
|
|
hexmask.long.byte 0x0 10.--14. 1. "CPT_NOFIX,5 bits counter"
|
|
bitfld.long 0x0 8. "MEM_NOFIX,Un-fixable error status" "0,1"
|
|
bitfld.long 0x0 7. "OVER_FIX,counter overflow" "0,1"
|
|
hexmask.long.byte 0x0 2.--6. 1. "CPT_FIX,5 bits counter"
|
|
newline
|
|
bitfld.long 0x0 0. "MEM_FIX,Fixable error status" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,FLEXRAMECC Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "MEM_NOFIX,Un-fixable error" "0,1"
|
|
bitfld.long 0x0 0. "MEM_FIX,Fixable error" "0,1"
|
|
line.long 0x4 "IDR,FLEXRAMECC Interrupt Disable Register"
|
|
bitfld.long 0x4 1. "MEM_NOFIX,un-fixable error" "0,1"
|
|
bitfld.long 0x4 0. "MEM_FIX,fixable error" "0,1"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "IMR,FLEXRAMECC Interrupt Mask Register"
|
|
bitfld.long 0x0 1. "MEM_NOFIX,un-fixable error" "0,1"
|
|
bitfld.long 0x0 0. "MEM_FIX,fixable error" "0,1"
|
|
line.long 0x4 "FAILAR,FLEXRAMECC Fail address register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDRESS,address of the error detected"
|
|
line.long 0x8 "FAILDR,FLEXRAMECC Fail data register"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,data error"
|
|
tree.end
|
|
tree "FPB (Flash Patch and Breakpoint)"
|
|
base ad:0xE0002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FP_CTRL,Flash Patch Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REV,Revision"
|
|
bitfld.long 0x0 12.--14. "NUM_CODE_1,Number of implemented code comparators bits [6:4]" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "NUM_LIT,Number of literal comparators"
|
|
hexmask.long.byte 0x0 4.--7. 1. "NUM_CODE,Number of implemented code comparators bits [3:0]"
|
|
bitfld.long 0x0 1. "KEY,FP_CTRL write-enable key" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,Flash Patch global enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x0 29. "RMPSPT,Remap supported" "0,1"
|
|
hexmask.long.tbyte 0x0 5.--28. 1. "REMAP,Remap address"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "FP_COMP[$1],Flash Patch Comparator Register n"
|
|
bitfld.long 0x0 31. "FE,Flash Patch enable" "0,1"
|
|
hexmask.long 0x0 2.--28. 1. "FPADDR,Flash Patch address"
|
|
bitfld.long 0x0 0. "BE,Breakpoint enable" "0,1"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "FP_COMP_BREAKPOINT_MODE[$1],Flash Patch Comparator Register n"
|
|
hexmask.long 0x0 1.--31. 1. "BPADDR,Breakpoint address"
|
|
bitfld.long 0x0 0. "BE,Breakpoint enable" "0,1"
|
|
repeat.end
|
|
wgroup.long 0xFB0++0x3
|
|
line.long 0x0 "FP_LAR,FPB Software Lock Access Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Lock access control"
|
|
rgroup.long 0xFB4++0x3
|
|
line.long 0x0 "FP_LSR,FPB Software Lock Status Register"
|
|
bitfld.long 0x0 2. "nTT,Not thirty-two bit" "0,1"
|
|
bitfld.long 0x0 1. "SLK,Software Lock status" "0,1"
|
|
bitfld.long 0x0 0. "SLI,Software Lock implemented" "0,1"
|
|
rgroup.long 0xFD0++0x2F
|
|
line.long 0x0 "FP_PID4,FP Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x0 4.--7. 1. "SIZE,4KB count"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DES_2,JEP106 continuation code"
|
|
line.long 0x4 "FP_PID5,FP Peripheral Identification Register 5"
|
|
line.long 0x8 "FP_PID6,FP Peripheral Identification Register 6"
|
|
line.long 0xC "FP_PID7,FP Peripheral Identification Register 7"
|
|
line.long 0x10 "FP_PID0,FP Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PART_0,Part number bits[7:0]"
|
|
line.long 0x14 "FP_PID1,FP Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x14 4.--7. 1. "DES_0,JEP106 identification code bits [3:0]"
|
|
hexmask.long.byte 0x14 0.--3. 1. "PART_1,Part number bits[11:8]"
|
|
line.long 0x18 "FP_PID2,FP Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x18 4.--7. 1. "REVISION,Component revision"
|
|
bitfld.long 0x18 3. "JEDEC,JEDEC assignee value is used" "0,1"
|
|
bitfld.long 0x18 0.--2. "DES_1,JEP106 identification code bits[6:4]" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "FP_PID3,FP Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "REVAND,RevAnd"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "CMOD,Customer Modified"
|
|
line.long 0x20 "FP_CID0,FP Component Identification Register 0"
|
|
hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,CoreSight component identification preamble"
|
|
line.long 0x24 "FP_CID1,FP Component Identification Register 1"
|
|
hexmask.long.byte 0x24 4.--7. 1. "CLASS,CoreSight component class"
|
|
hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,CoreSight component identification preamble"
|
|
line.long 0x28 "FP_CID2,FP Component Identification Register 2"
|
|
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,CoreSight component identification preamble"
|
|
line.long 0x2C "FP_CID3,FP Component Identification Register 3"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,CoreSight component identification preamble"
|
|
tree.end
|
|
tree "FPU (Floating Point Unit)"
|
|
base ad:0xE000EF30
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "FPCCR,Floating-point Context Control Register"
|
|
bitfld.long 0x0 31. "ASPEN,Enables CONTROL.FPCA setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration for floating-point context on exception entry and exit." "0,1"
|
|
bitfld.long 0x0 30. "LSPEN,Enable automatic lazy state preservation for floating-point context." "0,1"
|
|
bitfld.long 0x0 8. "MONRDY,DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated." "0,1"
|
|
bitfld.long 0x0 6. "BFRDY,BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated." "0,1"
|
|
bitfld.long 0x0 5. "MMRDY,MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated." "0,1"
|
|
bitfld.long 0x0 4. "HFRDY,Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "THREAD,Mode was Thread Mode when the floating-point stack frame was allocated." "0,1"
|
|
bitfld.long 0x0 1. "USER,Privilege level was user when the floating-point stack frame was allocated." "0,1"
|
|
bitfld.long 0x0 0. "LSPACT,Lazy state preservation is active. Floating-point stack frame has been allocated but saving state to it has been deferred." "0,1"
|
|
line.long 0x4 "FPCAR,Floating-point Context Address Register"
|
|
hexmask.long 0x4 3.--31. 1. "ADDRESS,The location of the unpopulated floating-point register space allocated on an exception stack frame."
|
|
line.long 0x8 "FPDSCR,Floating-point Default Status Control Register"
|
|
bitfld.long 0x8 26. "AHP,Default value for FPSCR.AHP." "0,1"
|
|
bitfld.long 0x8 25. "DN,Default value for FPSCR.DN." "0,1"
|
|
bitfld.long 0x8 24. "FZ,Default value for FPSCR.FZ." "0,1"
|
|
bitfld.long 0x8 22.--23. "RMode,Default value for FPSCR.RMode." "0,1,2,3"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "MVFR0,Media and VFP Feature Register 0"
|
|
hexmask.long.byte 0x0 28.--31. 1. "FP_rounding_modes,Indicates the rounding modes supported by the FP floating-point hardware"
|
|
hexmask.long.byte 0x0 24.--27. 1. "Short_vectors,Indicates the hardware support for FP short vectors"
|
|
hexmask.long.byte 0x0 20.--23. 1. "Square_root,Indicates the hardware support for FP square root operations"
|
|
hexmask.long.byte 0x0 16.--19. 1. "Divide,Indicates the hardware support for FP divide operations"
|
|
hexmask.long.byte 0x0 12.--15. 1. "FP_excep_trapping,Indicates whether the FP hardware implementation supports exception trapping"
|
|
hexmask.long.byte 0x0 8.--11. 1. "Double_precision,Indicates the hardware support for FP double-precision operations"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "Single_precision,Indicates the hardware support for FP single-precision operations"
|
|
hexmask.long.byte 0x0 0.--3. 1. "A_SIMD_registers,Indicates the size of the FP register bank"
|
|
line.long 0x4 "MVFR1,Media and VFP Feature Register 1"
|
|
hexmask.long.byte 0x4 28.--31. 1. "FP_fused_MAC,Indicates whether the FP supports fused multiply accumulate operations"
|
|
hexmask.long.byte 0x4 24.--27. 1. "FP_HPFP,Floating Point Half-Precision and double-precision"
|
|
hexmask.long.byte 0x4 4.--7. 1. "D_NaN_mode,Indicates whether the FP hardware implementation supports only the Default NaN mode"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FtZ_mode,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation"
|
|
line.long 0x8 "MVFR2,Media and VFP Feature Register 2"
|
|
hexmask.long.byte 0x8 4.--7. 1. "VFP_Misc,Indicates the hardware support for FP miscellaneous features"
|
|
tree.end
|
|
tree "HEFC (Hardened Embedded Flash Controller)"
|
|
base ad:0x40004000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FMR,HEFC Flash Mode Register"
|
|
bitfld.long 0x0 16. "ONE,Must be written to 1" "0,1"
|
|
bitfld.long 0x0 1. "FPSI,Flash Power Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "FRDY,Flash Ready Interrupt Enable" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "FCR,HEFC Flash Command Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "FKEY,Flash Writing Protection Key"
|
|
hexmask.long.word 0x0 8.--23. 1. "FARG,Flash Command Argument"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FCMD,Flash Command"
|
|
rgroup.long 0x8++0x7
|
|
line.long 0x0 "FSR,HEFC Flash Status Register"
|
|
bitfld.long 0x0 4. "WREER,Write Register Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "FLOCKE,Flash Lock Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "FCMDE,Flash Command Error Status (cleared on read or by writing HEFC_FCR)" "0,1"
|
|
bitfld.long 0x0 0. "FRDY,Flash Ready Status (cleared when Flash is busy)" "0,1"
|
|
line.long 0x4 "FRR,HEFC Flash Result Register"
|
|
hexmask.long 0x4 0.--31. 1. "FVALUE,Flash Result Value"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "FPMR,HEFC Flash Power Management Register"
|
|
bitfld.long 0x0 16. "FUNC_ISOL_CTRL_N,Flash insulated Control Status" "0,1"
|
|
hexmask.long.byte 0x0 8.--13. 1. "VAR_FACTOR,Variation Factor"
|
|
bitfld.long 0x0 2.--3. "PWS_DLY,Power switch Delay" "0: delay is set to 75 usec,1: delay is set to 150 usec,2: delay is set to 300 usec,3: delay is set to 600 usec"
|
|
bitfld.long 0x0 1. "PWS_STAT,Power switch Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PWS_EN,Power switch enable" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "USER,User Signature Write Protection" "0,1"
|
|
bitfld.long 0x0 3. "ERASEWP,Page Sector and Plane Write Protection" "0,1"
|
|
bitfld.long 0x0 2. "LOCKWP,Lock Bit Write Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GPNVMWP,GPNVM Bit Write Protection" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "HECC_CR[$1],HECC Control Register ChannelNumbers (ChannelNumbers = 0)"
|
|
bitfld.long 0x0 6. "ECC12_ENABLE,BCH ECC enable" "0,1"
|
|
bitfld.long 0x0 5. "RST_NOFIX_CPT,reset the un-fixable error counter" "0,1"
|
|
bitfld.long 0x0 4. "RST_FIX_CPT,reset the fixable error counter" "0,1"
|
|
bitfld.long 0x0 2. "TEST_MODE_WR,test mode of ECC protection - write mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TEST_MODE_RD,test mode of ECC protection - read mode" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,ECC protection enable" "0,1"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "HECC_TESTCB[$1],HECC Test mode ChannelNumbers (ChannelNumbers = 0)"
|
|
hexmask.long.word 0x0 0.--15. 1. "TCB,test check bit (16 bit)"
|
|
repeat.end
|
|
rgroup.long 0x180++0x3
|
|
line.long 0x0 "HECC_SR,HECC Status register"
|
|
bitfld.long 0x0 28.--29. "MEM_ID,memory identification number" "0,1,2,3"
|
|
bitfld.long 0x0 27. "TYPE,write or read access" "0,1"
|
|
bitfld.long 0x0 24.--26. "HES,Hardware Error Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "OVER_NOFIX,counter overflow" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 10.--14. 1. "CPT_NOFIX,5 bits counter"
|
|
bitfld.long 0x0 8. "MEM_NOFIX,Un-fixable error status" "0,1"
|
|
bitfld.long 0x0 7. "OVER_FIX,counter overflow" "0,1"
|
|
hexmask.long.byte 0x0 2.--6. 1. "CPT_FIX,5 bits counter"
|
|
newline
|
|
bitfld.long 0x0 0. "MEM_FIX,Fixable error status" "0,1"
|
|
wgroup.long 0x184++0x7
|
|
line.long 0x0 "HECC_IER,HECC Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "MEM_NOFIX,Un-fixable error" "0,1"
|
|
bitfld.long 0x0 0. "MEM_FIX,Fixable error" "0,1"
|
|
line.long 0x4 "HECC_IDR,HECC Interrupt Disable Register"
|
|
bitfld.long 0x4 1. "MEM_NOFIX,un-fixable error" "0,1"
|
|
bitfld.long 0x4 0. "MEM_FIX,fixable error" "0,1"
|
|
rgroup.long 0x18C++0xB
|
|
line.long 0x0 "HECC_IMR,HECC Interrupt Mask Register"
|
|
bitfld.long 0x0 1. "MEM_NOFIX,un-fixable error" "0,1"
|
|
bitfld.long 0x0 0. "MEM_FIX,fixable error" "0,1"
|
|
line.long 0x4 "HECC_FAILAR,HECC Fail address register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDRESS,address of the error detected"
|
|
line.long 0x8 "HECC_FAILDR,HECC Fail data register"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,data of the error detected"
|
|
tree.end
|
|
tree "HEMC (Hardened External Memory Controller)"
|
|
base ad:0x40080000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR_NCS0,HEMC Control Register NCS 0"
|
|
bitfld.long 0x0 30. "ECC_ENABLE,ECC Protection Enable" "0,1"
|
|
bitfld.long 0x0 29. "WRITE_ECC_CONF,ECC Configuration Protection Enable" "0,1"
|
|
hexmask.long.tbyte 0x0 7.--24. 1. "ADDBASE,relative base address of NCS area"
|
|
bitfld.long 0x0 6. "TYPE,type of memory used" "0,1"
|
|
hexmask.long.byte 0x0 1.--5. 1. "BANKSIZE,Bank Size"
|
|
newline
|
|
bitfld.long 0x0 0. "ZERO,fixed to 0" "0,1"
|
|
line.long 0x4 "CR_NCS1,HEMC Control Register NCS 1"
|
|
bitfld.long 0x4 30. "ECC_ENABLE,ECC Protection Enable" "0,1"
|
|
hexmask.long.tbyte 0x4 7.--24. 1. "ADDBASE,relative base address of NCS area"
|
|
bitfld.long 0x4 6. "TYPE,type of memory used" "0,1"
|
|
hexmask.long.byte 0x4 1.--5. 1. "BANKSIZE,Bank Size"
|
|
bitfld.long 0x4 0. "ZERO,fixed to 0" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CTRL,HEMC Polarity Control register"
|
|
bitfld.long 0x0 0. "POL,External control buffer active polarity" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "CRP_NCS[$1],HEMC Control Register Protection NCS"
|
|
bitfld.long 0x0 25. "PROTECTON,protection activation" "0,1"
|
|
bitfld.long 0x0 24. "PROTECTZONE,select area protected" "0,1"
|
|
hexmask.long.byte 0x0 19.--23. 1. "SPLITBANKSIZE,bank size internal separation"
|
|
bitfld.long 0x0 18. "RD,Read Access" "0,1"
|
|
bitfld.long 0x0 17. "WR,Write Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SUPERUSER,User or Superuser access" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "MASTERNUMBER,Master Number ID"
|
|
repeat.end
|
|
wgroup.long 0x38++0x7
|
|
line.long 0x0 "IER,HEMC Interrupt Enable Register"
|
|
bitfld.long 0x0 4. "USERERRORACCESS,user or superuser access error" "0,1"
|
|
bitfld.long 0x0 3. "WRERRORACCESS,write access error" "0,1"
|
|
bitfld.long 0x0 2. "RDERRORACCESS,read access error" "0,1"
|
|
bitfld.long 0x0 1. "OUTOFRANGE,out of range" "0,1"
|
|
line.long 0x4 "IDR,HEMC Interrupt Disable Register"
|
|
bitfld.long 0x4 4. "USERERRORACCESS,user or superuser access error" "0,1"
|
|
bitfld.long 0x4 3. "WRERRORACCESS,write access error" "0,1"
|
|
bitfld.long 0x4 2. "RDERRORACCESS,read access error" "0,1"
|
|
bitfld.long 0x4 1. "OUTOFRANGE,out of range" "0,1"
|
|
rgroup.long 0x40++0xB
|
|
line.long 0x0 "IMR,HEMC Interrupt Mask Register"
|
|
bitfld.long 0x0 4. "USERERRORACCESS,user or superuser access error" "0,1"
|
|
bitfld.long 0x0 3. "WRERRORACCESS,write access error" "0,1"
|
|
bitfld.long 0x0 2. "RDERRORACCESS,read access error" "0,1"
|
|
bitfld.long 0x0 1. "OUTOFRANGE,out of range" "0,1"
|
|
line.long 0x4 "ISR,HEMC Interrupt Status Register"
|
|
bitfld.long 0x4 4. "USERERRORACCESS,User or SuperUser Error Access" "0,1"
|
|
bitfld.long 0x4 3. "WRERRORACCESS,Write access error" "0,1"
|
|
bitfld.long 0x4 2. "RDERRORACCESS,read access error" "0,1"
|
|
bitfld.long 0x4 1. "OUTOFRANGE,out of range" "0,1"
|
|
line.long 0x8 "SR,HEMC Status Register"
|
|
bitfld.long 0x8 4. "USERERRORACCESS,User or SuperUser Error Access" "0,1"
|
|
bitfld.long 0x8 3. "WRERRORACCESS,Write access error" "0,1"
|
|
bitfld.long 0x8 2. "RDERRORACCESS,Read access error" "0,1"
|
|
bitfld.long 0x8 1. "OUTOFRANGE,out of range" "0,1"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "HECC_CR,HECC Control Register Channel 0 (HSMC)"
|
|
bitfld.long 0x0 5. "RST_NOFIX_CPT,reset the un-fixable error counter" "0,1"
|
|
bitfld.long 0x0 4. "RST_FIX_CPT,reset the fixable error counter" "0,1"
|
|
bitfld.long 0x0 2. "TEST_MODE_WR,test mode of ECC protection - write mode" "0,1"
|
|
bitfld.long 0x0 1. "TEST_MODE_RD,test mode of ECC protection - read mode" "0,1"
|
|
group.long 0x140++0x3
|
|
line.long 0x0 "HECC_TESTCB,HECC Test mode Register Channel 0 (HSMC)"
|
|
hexmask.long.word 0x0 0.--15. 1. "TCB1,test check bit (16 bit)"
|
|
rgroup.long 0x180++0x3
|
|
line.long 0x0 "HECC_SR,HECC Status Register"
|
|
bitfld.long 0x0 27. "TYPE,write or read access" "0,1"
|
|
bitfld.long 0x0 24.--26. "HES,Hardware Error Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "OVER_NOFIX,counter overflow" "0,1"
|
|
hexmask.long.byte 0x0 10.--14. 1. "CPT_NOFIX,5 bits counter"
|
|
bitfld.long 0x0 8. "MEM_NOFIX,Un-fixable error status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OVER_FIX,counter overflow" "0,1"
|
|
hexmask.long.byte 0x0 2.--6. 1. "CPT_FIX,5 bits counter"
|
|
bitfld.long 0x0 0. "MEM_FIX,Fixable error status" "0,1"
|
|
wgroup.long 0x184++0x7
|
|
line.long 0x0 "HECC_IER,HECC Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "MEM_NOFIX,Un-fixable error" "0,1"
|
|
bitfld.long 0x0 0. "MEM_FIX,Fixable error" "0,1"
|
|
line.long 0x4 "HECC_IDR,HECC Interrupt Disable Register"
|
|
bitfld.long 0x4 1. "MEM_NOFIX,un-fixable error" "0,1"
|
|
bitfld.long 0x4 0. "MEM_FIX,fixable error" "0,1"
|
|
rgroup.long 0x18C++0xB
|
|
line.long 0x0 "HECC_IMR,HECC Interrupt Mask Register"
|
|
bitfld.long 0x0 1. "MEM_NOFIX,un-fixable error" "0,1"
|
|
bitfld.long 0x0 0. "MEM_FIX,fixable error" "0,1"
|
|
line.long 0x4 "HECC_FAILAR,HECC Fail address register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDRESS,address of the error detected"
|
|
line.long 0x8 "HECC_FAILDR,HECC Fail data register"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Data error detected"
|
|
tree.end
|
|
tree "HSMC (Hardened Static Memory Controller)"
|
|
base ad:0x40081000
|
|
repeat 2. (list 0x0 0x1)(list ad:0x40081000 ad:0x40081010)
|
|
tree "HSMC_CS[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "SETUP,HSMC Setup Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "NCS_RD_SETUP,NCS Setup Length in READ Access"
|
|
hexmask.long.byte 0x0 16.--21. 1. "NRD_SETUP,NRD Setup Length"
|
|
hexmask.long.byte 0x0 8.--13. 1. "NCS_WR_SETUP,NCS Setup Length in WRITE Access"
|
|
hexmask.long.byte 0x0 0.--5. 1. "NWE_SETUP,NWE Setup Length"
|
|
line.long 0x4 "PULSE,HSMC Pulse Register"
|
|
hexmask.long.byte 0x4 24.--30. 1. "NCS_RD_PULSE,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. "NRD_PULSE,NRD Pulse Length"
|
|
hexmask.long.byte 0x4 8.--14. 1. "NCS_WR_PULSE,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x4 0.--6. 1. "NWE_PULSE,NWE Pulse Length"
|
|
line.long 0x8 "CYCLE,HSMC Cycle Register"
|
|
hexmask.long.word 0x8 16.--24. 1. "NRD_CYCLE,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. "NWE_CYCLE,Total Write Cycle Length"
|
|
line.long 0xC "MODE,HSMC Mode Register"
|
|
bitfld.long 0xC 8.--9. "DBW,Data Bus Width" "0: 8-bit Data Bus,?,?,?"
|
|
bitfld.long 0xC 4.--5. "EXNW_MODE,NWAIT Mode" "0: Disabled-The NWAIT input signal is ignored on..,?,2: Frozen Mode-If asserted the NWAIT signal freezes..,3: Ready Mode-The NWAIT signal indicates the.."
|
|
bitfld.long 0xC 2. "RMW_ENABLE,Read-Modify Write enable" "0,1"
|
|
bitfld.long 0xC 1. "WRITE_MODE,Write Mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "READ_MODE,Read Mode" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40081000
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "WPMR,HSMC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protect Enable" "0,1"
|
|
rgroup.long 0x74++0x3
|
|
line.long 0x0 "WPSR,HSMC Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "ICM (Integrity Check Monitor)"
|
|
base ad:0x4008C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CFG,Configuration Register"
|
|
bitfld.long 0x0 13.--15. "UALGO,User SHA Algorithm" "0: SHA1 algorithm processed,1: SHA256 algorithm processed,?,?,4: SHA224 algorithm processed,?,?,?"
|
|
bitfld.long 0x0 12. "UIHASH,User Initial Hash Value" "0,1"
|
|
bitfld.long 0x0 9. "DUALBUFF,Dual Input Buffer" "0,1"
|
|
bitfld.long 0x0 8. "ASCD,Automatic Switch To Compare Digest" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "BBC,Bus Burden Control"
|
|
bitfld.long 0x0 2. "SLBDIS,Secondary List Branching Disable" "0,1"
|
|
bitfld.long 0x0 1. "EOMDIS,End of Monitoring Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WBDIS,Write Back Disable" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "CTRL,Control Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RMEN,Region Monitoring Enable"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RMDIS,Region Monitoring Disable"
|
|
hexmask.long.byte 0x0 4.--7. 1. "REHASH,Recompute Internal Hash"
|
|
bitfld.long 0x0 2. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 1. "DISABLE,ICM Disable Register" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,ICM Enable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RMDIS,Region Monitoring Disabled Status"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RAWRMDIS,Region Monitoring Disabled Raw Status"
|
|
bitfld.long 0x0 0. "ENABLE,ICM Enable Register" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "URAD,Undefined Register Access Detection Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "RSU,Region Status Updated Interrupt Disable"
|
|
hexmask.long.byte 0x0 16.--19. 1. "REC,Region End bit Condition Detected Interrupt Enable"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RWC,Region Wrap Condition detected Interrupt Enable"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RBE,Region Bus Error Interrupt Enable"
|
|
hexmask.long.byte 0x0 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Enable"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RHC,Region Hash Completed Interrupt Enable"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "URAD,Undefined Register Access Detection Interrupt Disable" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "RSU,Region Status Updated Interrupt Disable"
|
|
hexmask.long.byte 0x4 16.--19. 1. "REC,Region End bit Condition detected Interrupt Disable"
|
|
hexmask.long.byte 0x4 12.--15. 1. "RWC,Region Wrap Condition Detected Interrupt Disable"
|
|
hexmask.long.byte 0x4 8.--11. 1. "RBE,Region Bus Error Interrupt Disable"
|
|
hexmask.long.byte 0x4 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Disable"
|
|
hexmask.long.byte 0x4 0.--3. 1. "RHC,Region Hash Completed Interrupt Disable"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "URAD,Undefined Register Access Detection Interrupt Mask" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "RSU,Region Status Updated Interrupt Mask"
|
|
hexmask.long.byte 0x0 16.--19. 1. "REC,Region End bit Condition Detected Interrupt Mask"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RWC,Region Wrap Condition Detected Interrupt Mask"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RBE,Region Bus Error Interrupt Mask"
|
|
hexmask.long.byte 0x0 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Mask"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RHC,Region Hash Completed Interrupt Mask"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 24. "URAD,Undefined Register Access Detection Status" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "RSU,Region Status Updated Detected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "REC,Region End Bit Condition Detected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "RWC,Region Wrap Condition Detected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "RBE,Region Bus Error"
|
|
hexmask.long.byte 0x4 4.--7. 1. "RDM,Region Digest Mismatch"
|
|
hexmask.long.byte 0x4 0.--3. 1. "RHC,Region Hash Completed"
|
|
line.long 0x8 "UASR,Undefined Access Status Register"
|
|
bitfld.long 0x8 0.--2. "URAT,Undefined Register Access Trace" "0: Unspecified structure member set to one detected..,1: ICM_CFG modified during active monitoring.,2: ICM_DSCR modified during active monitoring.,3: ICM_HASH modified during active monitoring,4: Write-only register read access,?,?,?"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "DSCR,Region Descriptor Area Start Address Register"
|
|
hexmask.long 0x0 6.--31. 1. "DASA,Descriptor Area Start Address"
|
|
line.long 0x4 "HASH,Region Hash Area Start Address Register"
|
|
hexmask.long 0x4 7.--31. 1. "HASA,Hash Area Start Address"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x38)++0x3
|
|
line.long 0x0 "UIHVAL[$1],User Initial Hash Value 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "VAL,Initial Hash Value"
|
|
repeat.end
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,ICM Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,ICM Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (Cleared on read)" "0,1"
|
|
tree.end
|
|
tree "IP1553 (IP1553 Interface)"
|
|
base ad:0x4003C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,Configuration Register"
|
|
bitfld.long 0x0 11. "RST,Soft Reset" "0,1"
|
|
bitfld.long 0x0 10. "BEC,BCEnableCmd" "0,1"
|
|
bitfld.long 0x0 9. "SRC,SREQBitCmd" "0,1"
|
|
bitfld.long 0x0 8. "BC,BusyBitCmd" "0,1"
|
|
bitfld.long 0x0 7. "SC,SSBitCmd" "0,1"
|
|
bitfld.long 0x0 6. "TC,TRBitCmd" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 1.--5. 1. "TA,TermAddressConf"
|
|
bitfld.long 0x0 0. "PT,POTermConf" "0,1"
|
|
wgroup.long 0xC++0x1B
|
|
line.long 0x0 "CMDR1,Command Register 1"
|
|
hexmask.long.byte 0x0 11.--15. 1. "RTADDRESS,RT ADDRESS"
|
|
bitfld.long 0x0 10. "T_R,T/R" "0,1"
|
|
hexmask.long.byte 0x0 5.--9. 1. "RTSUBADDRESS,RT SUBADDRESS"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DATAWORDCOUNT,DATA WORD COUNT"
|
|
line.long 0x4 "CMDR2,Command Register 2"
|
|
hexmask.long.byte 0x4 11.--15. 1. "RTADDRESS,RT ADDRESS"
|
|
bitfld.long 0x4 10. "T_R,R/T" "0,1"
|
|
hexmask.long.byte 0x4 5.--9. 1. "RTSUBADDRESS,RT SUBADDRESS"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DATAWORDCOUNT,DATA WORD COUNT"
|
|
line.long 0x8 "CMDR3,Command Register 3"
|
|
bitfld.long 0x8 3. "ER,data or command transfer" "0,1"
|
|
bitfld.long 0x8 2. "BCR,1553 receiver" "0,1"
|
|
bitfld.long 0x8 1. "BCE,1553 emitter" "0,1"
|
|
bitfld.long 0x8 0. "BUS,bus used" "0,1"
|
|
line.long 0xC "BITR,BIT Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TOBITWORD,to bit word"
|
|
line.long 0x10 "VWR,Vector Word Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "TOVECTORWORD,to vector word"
|
|
line.long 0x14 "IER,IRQ Mask Enable Register"
|
|
bitfld.long 0x14 24. "IPB,IPBusy" "0,1"
|
|
bitfld.long 0x14 23. "OTF,OvInhibitTermFlagReq" "0,1"
|
|
bitfld.long 0x14 22. "ITF,InhibitTermFlagReq" "0,1"
|
|
bitfld.long 0x14 21. "RRT,ResetRTReq" "0,1"
|
|
bitfld.long 0x14 20. "SWD,SyncWithoutDataReq" "0,1"
|
|
bitfld.long 0x14 19. "SDR,SyncWithDataReq" "0,1"
|
|
newline
|
|
bitfld.long 0x14 18. "OSR,OvTranShutdownReq" "0,1"
|
|
bitfld.long 0x14 17. "TSR,TranShutdownReq" "0,1"
|
|
bitfld.long 0x14 16. "STR,InitSelfTestReq" "0,1"
|
|
bitfld.long 0x14 15. "DBR,DynamicBusContReq" "0,1"
|
|
bitfld.long 0x14 14. "TVR,TransVecWordReq" "0,1"
|
|
bitfld.long 0x14 13. "ITR,IllegalTransferReq" "0,1"
|
|
newline
|
|
bitfld.long 0x14 12. "BE,BufIFErr" "0,1"
|
|
bitfld.long 0x14 11. "TWE,TransWordCounterErr" "0,1"
|
|
bitfld.long 0x14 10. "TTE,TransTimeOutErr" "0,1"
|
|
bitfld.long 0x14 9. "TDE,TransDataTypeErr" "0,1"
|
|
bitfld.long 0x14 8. "TPE,TransParityErr" "0,1"
|
|
bitfld.long 0x14 7. "TCE,TransCodingErr" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "TE,TransErr" "0,1"
|
|
bitfld.long 0x14 4.--5. "ETRANS,EndTransfer" "0,1,2,3"
|
|
bitfld.long 0x14 3. "ETX,EndTransmission" "0,1"
|
|
bitfld.long 0x14 2. "ERX,End reception" "0,1"
|
|
bitfld.long 0x14 1. "MTE,MemTransferErr" "0,1"
|
|
bitfld.long 0x14 0. "EMT,EndMemTransfer" "0,1"
|
|
line.long 0x18 "IDR,IRQ Mask Disable Register"
|
|
bitfld.long 0x18 24. "IPB,IPBusy" "0,1"
|
|
bitfld.long 0x18 23. "OTF,OvInhibitTermFlagReq" "0,1"
|
|
bitfld.long 0x18 22. "ITF,InhibitTermFlagReq" "0,1"
|
|
bitfld.long 0x18 21. "RRT,ResetRTReq" "0,1"
|
|
bitfld.long 0x18 20. "SWD,SyncWithoutDataReq" "0,1"
|
|
bitfld.long 0x18 19. "SDR,SyncWithDataReq" "0,1"
|
|
newline
|
|
bitfld.long 0x18 18. "OSR,OvTranShutdownReq" "0,1"
|
|
bitfld.long 0x18 17. "TSR,TranShutdownReq" "0,1"
|
|
bitfld.long 0x18 16. "STR,InitSelfTestReq" "0,1"
|
|
bitfld.long 0x18 15. "DBR,DynamicBusContReq" "0,1"
|
|
bitfld.long 0x18 14. "TVR,TransVecWordReq" "0,1"
|
|
bitfld.long 0x18 13. "ITR,IllegalTransferReq" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "BE,BufIFErr" "0,1"
|
|
bitfld.long 0x18 11. "TWE,TransWordCounterErr" "0,1"
|
|
bitfld.long 0x18 10. "TTE,TransTimeOutErr" "0,1"
|
|
bitfld.long 0x18 9. "TDE,TransDataTypeErr" "0,1"
|
|
bitfld.long 0x18 8. "TPE,TransParityErr" "0,1"
|
|
bitfld.long 0x18 7. "TCE,TransCodingErr" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "TE,TransErr" "0,1"
|
|
bitfld.long 0x18 4.--5. "ETRANS,EndTransfer" "0,1,2,3"
|
|
bitfld.long 0x18 3. "ETX,EndTransmission" "0,1"
|
|
bitfld.long 0x18 2. "ERX,End reception" "0,1"
|
|
bitfld.long 0x18 1. "MTE,MemTransferErr" "0,1"
|
|
bitfld.long 0x18 0. "EMT,EndMemTransfer" "0,1"
|
|
rgroup.long 0x28++0x13
|
|
line.long 0x0 "IMR,IRQ Mask Register"
|
|
bitfld.long 0x0 24. "IPB,IPBusy" "0,1"
|
|
bitfld.long 0x0 23. "OTF,OvInhibitTermFlagReq" "0,1"
|
|
bitfld.long 0x0 22. "ITF,InhibitTermFlagReq" "0,1"
|
|
bitfld.long 0x0 21. "RRT,ResetRTReq" "0,1"
|
|
bitfld.long 0x0 20. "SWD,SyncWithoutDataReq" "0,1"
|
|
bitfld.long 0x0 19. "SDR,SyncWithDataReq" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "OSR,OvTranShutdownReq" "0,1"
|
|
bitfld.long 0x0 17. "TSR,TranShutdownReq" "0,1"
|
|
bitfld.long 0x0 16. "STR,InitSelfTestReq" "0,1"
|
|
bitfld.long 0x0 15. "DBR,DynamicBusContReq" "0,1"
|
|
bitfld.long 0x0 14. "TVR,TransVecWordReq" "0,1"
|
|
bitfld.long 0x0 13. "ITR,IllegalTransferReq" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BE,BufIFErr" "0,1"
|
|
bitfld.long 0x0 11. "TWE,TransWordCounterErr" "0,1"
|
|
bitfld.long 0x0 10. "TTE,TransTimeOutErr" "0,1"
|
|
bitfld.long 0x0 9. "TDE,TransDataTypeErr" "0,1"
|
|
bitfld.long 0x0 8. "TPE,TransParityErr" "0,1"
|
|
bitfld.long 0x0 7. "TCE,TransCodingErr" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TE,TransErr" "0,1"
|
|
bitfld.long 0x0 4.--5. "ETRANS,EndTransfer" "0,1,2,3"
|
|
bitfld.long 0x0 3. "ETX,EndTransmission" "0,1"
|
|
bitfld.long 0x0 2. "ERX,End reception" "0,1"
|
|
bitfld.long 0x0 1. "MTE,MemTransferErr" "0,1"
|
|
bitfld.long 0x0 0. "EMT,EndMemTransfer" "0,1"
|
|
line.long 0x4 "ISR,IRQ Status Register"
|
|
bitfld.long 0x4 25. "BUS,BUS activated on last transfer" "0,1"
|
|
bitfld.long 0x4 24. "IPB,IPBusy" "0,1"
|
|
bitfld.long 0x4 23. "OTF,OvInhibitTermFlagReq" "0,1"
|
|
bitfld.long 0x4 22. "ITF,InhibitTermFlagReq" "0,1"
|
|
bitfld.long 0x4 21. "RRT,ResetRTReq" "0,1"
|
|
bitfld.long 0x4 20. "SWD,SyncWithoutDataReq" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "SDR,SyncWithDataReq" "0,1"
|
|
bitfld.long 0x4 18. "OSR,OvTranShutdownReq" "0,1"
|
|
bitfld.long 0x4 17. "TSR,TranShutdownReq" "0,1"
|
|
bitfld.long 0x4 16. "STR,InitSelfTestReq" "0,1"
|
|
bitfld.long 0x4 15. "DBR,DynamicBusContReq" "0,1"
|
|
bitfld.long 0x4 14. "TVR,TransVecWordReq" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ITR,IllegalTransferReq" "0,1"
|
|
bitfld.long 0x4 12. "BE,BufIFErr" "0,1"
|
|
bitfld.long 0x4 11. "TWE,TransWordCounterErr" "0,1"
|
|
bitfld.long 0x4 10. "TTE,TransTimeOutErr" "0,1"
|
|
bitfld.long 0x4 9. "TDE,TransDataTypeErr" "0,1"
|
|
bitfld.long 0x4 8. "TPE,TransParityErr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,TransCodingErr" "0,1"
|
|
bitfld.long 0x4 6. "TE,TransErr" "0,1"
|
|
bitfld.long 0x4 4.--5. "ETRANS,EndTransfer" "0,1,2,3"
|
|
bitfld.long 0x4 3. "ETX,EndTransmission" "0,1"
|
|
bitfld.long 0x4 2. "ERX,End reception" "0,1"
|
|
bitfld.long 0x4 1. "MTE,MemTransferErr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "EMT,EndMemTransfer" "0,1"
|
|
line.long 0x8 "CTRL1,Control Register 1"
|
|
hexmask.long.word 0x8 16.--31. 1. "IP1553DATA2,IP1553 data value 2"
|
|
hexmask.long.word 0x8 0.--15. 1. "IP1553DATA1,IP1553 data value 1"
|
|
line.long 0xC "CTRL2,Control Register 2"
|
|
hexmask.long.word 0xC 4.--19. 1. "FROMVECTORWORD,from vector register"
|
|
hexmask.long.byte 0xC 0.--3. 1. "FROMCOMMANDREG,from command register"
|
|
line.long 0x10 "CTRL3,Control Register 3"
|
|
hexmask.long.word 0x10 16.--31. 1. "FROMBITWORD,content of bit word register"
|
|
hexmask.long.word 0x10 0.--15. 1. "FROMSTATUSWORD,content of status word register"
|
|
group.long 0x3C++0x17
|
|
line.long 0x0 "ARW,Address Register Write"
|
|
hexmask.long 0x0 0.--31. 1. "REG_ADDR_APB_W,TX base address"
|
|
line.long 0x4 "ARR,Address Register Read"
|
|
hexmask.long 0x4 0.--31. 1. "REG_ADDR_APB_R,RX base address"
|
|
line.long 0x8 "RXBSR,Rx Buffer Status Register"
|
|
bitfld.long 0x8 31. "RE31,Receive Buffer 31 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 30. "RE30,Receive Buffer 30 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 29. "RE29,Receive Buffer 29 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 28. "RE28,Receive Buffer 28 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 27. "RE27,Receive Buffer 27 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 26. "RE26,Receive Buffer 26 with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "RE25,Receive Buffer 25 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 24. "RE24,Receive Buffer 24 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 23. "RE23,Receive Buffer 23 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 22. "RE22,Receive Buffer 22 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 21. "RE21,Receive Buffer 21 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 20. "RE20,Receive Buffer 20 with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "RE19,Receive Buffer 19 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 18. "RE18,Receive Buffer 18 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 17. "RE17,Receive Buffer 17 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 16. "RE16,Receive Buffer 16 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 15. "RE15,Receive Buffer 15 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 14. "RE14,Receive Buffer 14 with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "RE13,Receive Buffer 13 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 12. "RE12,Receive Buffer 12 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 11. "RE11,Receive Buffer 11 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 10. "RE10,Receive Buffer 10 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 9. "RE9,Receive Buffer 9 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 8. "RE8,Receive Buffer 8 with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RE7,Receive Buffer 7 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 6. "RE6,Receive Buffer 6 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 5. "RE5,Receive Buffer 5 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 4. "RE4,Receive Buffer 4 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 3. "RE3,Receive Buffer 3 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 2. "RE2,Receive Buffer 2 with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RE1,Receive Buffer 1 with x=[0-31]" "0,1"
|
|
bitfld.long 0x8 0. "RE0,Receive Buffer 0 with x=[0-31]" "0,1"
|
|
line.long 0xC "RXBAER,Rx Buffer Access Error Register"
|
|
bitfld.long 0xC 31. "RER31,Receive error 31 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 30. "RER30,Receive error 30 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 29. "RER29,Receive error 29 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 28. "RER28,Receive error 28 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 27. "RER27,Receive error 27 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 26. "RER26,Receive error 26 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "RER25,Receive error 25 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 24. "RER24,Receive error 24 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 23. "RER23,Receive error 23 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 22. "RER22,Receive error 22 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 21. "RER21,Receive error 21 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 20. "RER20,Receive error 20 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "RER19,Receive error 19 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 18. "RER18,Receive error 18 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 17. "RER17,Receive error 17 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 16. "RER16,Receive error 16 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 15. "RER15,Receive error 15 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 14. "RER14,Receive error 14 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "RER13,Receive error 13 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 12. "RER12,Receive error 12 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 11. "RER11,Receive error 11 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 10. "RER10,Receive error 10 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 9. "RER9,Receive error 9 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 8. "RER8,Receive error 8 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "RER7,Receive error 7 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 6. "RER6,Receive error 6 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 5. "RER5,Receive error 5 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 4. "RER4,Receive error 4 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 3. "RER3,Receive error 3 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 2. "RER2,Receive error 2 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "RER1,Receive error 1 x with x=[0-31]" "0,1"
|
|
bitfld.long 0xC 0. "RER0,Receive error 0 x with x=[0-31]" "0,1"
|
|
line.long 0x10 "TXBSR,Tx Buffer Status Register"
|
|
bitfld.long 0x10 31. "TF31,Transmit buffer 31 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 30. "TF30,Transmit buffer 30 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 29. "TF29,Transmit buffer 29 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 28. "TF28,Transmit buffer 28 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 27. "TF27,Transmit buffer 27 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 26. "TF26,Transmit buffer 26 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "TF25,Transmit buffer 25 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 24. "TF24,Transmit buffer 24 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 23. "TF23,Transmit buffer 23 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 22. "TF22,Transmit buffer 22 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 21. "TF21,Transmit buffer 21 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 20. "TF20,Transmit buffer 20 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "TF19,Transmit buffer 19 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 18. "TF18,Transmit buffer 18 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 17. "TF17,Transmit buffer 17 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 16. "TF16,Transmit buffer 16 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 15. "TF15,Transmit buffer 15 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 14. "TF14,Transmit buffer 14 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "TF13,Transmit buffer 13 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 12. "TF12,Transmit buffer 12 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 11. "TF11,Transmit buffer 11 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 10. "TF10,Transmit buffer 10 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 9. "TF9,Transmit buffer 9 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 8. "TF8,Transmit buffer 8 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "TF7,Transmit buffer 7 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 6. "TF6,Transmit buffer 6 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 5. "TF5,Transmit buffer 5 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 4. "TF4,Transmit buffer 4 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 3. "TF3,Transmit buffer 3 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 2. "TF2,Transmit buffer 2 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "TF1,Transmit buffer 1 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x10 0. "TF0,Transmit buffer 0 x with x=[0-31]" "0,1"
|
|
line.long 0x14 "TXBAER,Tx Buffer Access Error Register"
|
|
bitfld.long 0x14 31. "TER31,Transmit error 31 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 30. "TER30,Transmit error 30 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 29. "TER29,Transmit error 29 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 28. "TER28,Transmit error 28 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 27. "TER27,Transmit error 27 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 26. "TER26,Transmit error 26 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. "TER25,Transmit error 25 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 24. "TER24,Transmit error 24 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 23. "TER23,Transmit error 23 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 22. "TER22,Transmit error 22 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 21. "TER21,Transmit error 21 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 20. "TER20,Transmit error 20 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. "TER19,Transmit error 19 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 18. "TER18,Transmit error 18 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 17. "TER17,Transmit error 17 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 16. "TER16,Transmit error 16 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 15. "TER15,Transmit error 15 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 14. "TER14,Transmit error 14 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "TER13,Transmit error 13 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 12. "TER12,Transmit error 12 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 11. "TER11,Transmit error 11 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 10. "TER10,Transmit error 10 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 9. "TER9,Transmit error 9 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 8. "TER8,Transmit error 8 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "TER7,Transmit error 7 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 6. "TER6,Transmit error 6 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 5. "TER5,Transmit error 5 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 4. "TER4,Transmit error 4 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 3. "TER3,Transmit error 3 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 2. "TER2,Transmit error 2 x with x=[0-31]" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "TER1,Transmit error 1 x with x=[0-31]" "0,1"
|
|
bitfld.long 0x14 0. "TER0,Transmit error 0 x with x=[0-31]" "0,1"
|
|
tree.end
|
|
tree "ITM (Instrumentation Trace Macrocell)"
|
|
base ad:0xE0000000
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "PORT_BYTE_MODE[$1],ITM Stimulus Port Registers"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PORT,"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "PORT_HWORD_MODE[$1],ITM Stimulus Port Registers"
|
|
hexmask.long.word 0x0 0.--15. 1. "PORT,"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "PORT_WORD_MODE[$1],ITM Stimulus Port Registers"
|
|
hexmask.long 0x0 0.--31. 1. "PORT,"
|
|
repeat.end
|
|
group.long 0xE00++0x3
|
|
line.long 0x0 "TER,ITM Trace Enable Register"
|
|
group.long 0xE40++0x3
|
|
line.long 0x0 "TPR,ITM Trace Privilege Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRIVMASK,"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "TCR,ITM Trace Control Register"
|
|
bitfld.long 0x0 23. "BUSY," "0,1"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TraceBusID,"
|
|
bitfld.long 0x0 10.--11. "GTSFREQ," "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "TSPrescale," "0,1,2,3"
|
|
bitfld.long 0x0 5. "STALLENA," "0,1"
|
|
bitfld.long 0x0 4. "SWOENA," "0,1"
|
|
bitfld.long 0x0 3. "DWTENA," "0,1"
|
|
bitfld.long 0x0 2. "SYNCENA," "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TSENA," "0,1"
|
|
bitfld.long 0x0 0. "ITMENA," "0,1"
|
|
tree.end
|
|
tree "LOCKBIT"
|
|
base ad:0x0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "LOCKBIT,Lock Bits"
|
|
bitfld.long 0x0 31. "LOCK_REGION_31,Lock Region 31" "0,1"
|
|
bitfld.long 0x0 30. "LOCK_REGION_30,Lock Region 30" "0,1"
|
|
bitfld.long 0x0 29. "LOCK_REGION_29,Lock Region 29" "0,1"
|
|
bitfld.long 0x0 28. "LOCK_REGION_28,Lock Region 28" "0,1"
|
|
bitfld.long 0x0 27. "LOCK_REGION_27,Lock Region 27" "0,1"
|
|
bitfld.long 0x0 26. "LOCK_REGION_26,Lock Region 26" "0,1"
|
|
bitfld.long 0x0 25. "LOCK_REGION_25,Lock Region 25" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LOCK_REGION_24,Lock Region 24" "0,1"
|
|
bitfld.long 0x0 23. "LOCK_REGION_23,Lock Region 23" "0,1"
|
|
bitfld.long 0x0 22. "LOCK_REGION_22,Lock Region 22" "0,1"
|
|
bitfld.long 0x0 21. "LOCK_REGION_21,Lock Region 21" "0,1"
|
|
bitfld.long 0x0 20. "LOCK_REGION_20,Lock Region 20" "0,1"
|
|
bitfld.long 0x0 19. "LOCK_REGION_19,Lock Region 19" "0,1"
|
|
bitfld.long 0x0 18. "LOCK_REGION_18,Lock Region 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "LOCK_REGION_17,Lock Region 17" "0,1"
|
|
bitfld.long 0x0 16. "LOCK_REGION_16,Lock Region 16" "0,1"
|
|
bitfld.long 0x0 15. "LOCK_REGION_15,Lock Region 15" "0,1"
|
|
bitfld.long 0x0 14. "LOCK_REGION_14,Lock Region 14" "0,1"
|
|
bitfld.long 0x0 13. "LOCK_REGION_13,Lock Region 13" "0,1"
|
|
bitfld.long 0x0 12. "LOCK_REGION_12,Lock Region 12" "0,1"
|
|
bitfld.long 0x0 11. "LOCK_REGION_11,Lock Region 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "LOCK_REGION_10,Lock Region 10" "0,1"
|
|
bitfld.long 0x0 9. "LOCK_REGION_9,Lock Region 9" "0,1"
|
|
bitfld.long 0x0 8. "LOCK_REGION_8,Lock Region 8" "0,1"
|
|
bitfld.long 0x0 7. "LOCK_REGION_7,Lock Region 7" "0,1"
|
|
bitfld.long 0x0 6. "LOCK_REGION_6,Lock Region 6" "0,1"
|
|
bitfld.long 0x0 5. "LOCK_REGION_5,Lock Region 5" "0,1"
|
|
bitfld.long 0x0 4. "LOCK_REGION_4,Lock Region 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LOCK_REGION_3,Lock Region 3" "0,1"
|
|
bitfld.long 0x0 2. "LOCK_REGION_2,Lock Region 2" "0,1"
|
|
bitfld.long 0x0 1. "LOCK_REGION_1,Lock Region 1" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_REGION_0,Lock Region 0" "0,1"
|
|
tree.end
|
|
tree "MATRIX (AHB Bus Matrix)"
|
|
base ad:0x0
|
|
tree "MATRIX0"
|
|
base ad:0x40000000
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MCFG[$1],Master Configuration Register"
|
|
bitfld.long 0x0 0.--2. "ULBT,Undefined Length Burst Type" "0: Unlimited Length Burst-No predicted end of burst..,1: Single Access-The undefined length burst is..,2: 4-beat Burst-The undefined length burst or..,3: 8-beat Burst-The undefined length burst or..,4: 16-beat Burst-The undefined length burst or..,5: 32-beat Burst-The undefined length burst or..,6: 64-beat Burst-The undefined length burst or..,7: 128-beat Burst-The undefined length burst or.."
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SCFG[$1],Slave Configuration Register"
|
|
hexmask.long.byte 0x0 18.--21. 1. "FIXED_DEFMSTR,Fixed Default Master"
|
|
bitfld.long 0x0 16.--17. "DEFMSTR_TYPE,Default Master Type" "0: No Default Master-At the end of the current..,1: Last Default Master-At the end of the current..,2: Fixed Default Master-At the end of the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLOT_CYCLE,Maximum Bus Grant Duration for Masters"
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40000080 ad:0x40000088 ad:0x40000090 ad:0x40000098 ad:0x400000A0 ad:0x400000A8 ad:0x400000B0 ad:0x400000B8 ad:0x400000C0 ad:0x400000C8 ad:0x400000D0 ad:0x400000D8 ad:0x400000E0 ad:0x400000E8 ad:0x400000F0 ad:0x400000F8)
|
|
tree "MATRIX_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PRAS,Priority Register A for Slave"
|
|
bitfld.long 0x0 30. "LQOSEN7,Latency Quality of Service Enable for Master 7" "0,1"
|
|
bitfld.long 0x0 28.--29. "M7PR,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 26. "LQOSEN6,Latency Quality of Service Enable for Master 6" "0,1"
|
|
bitfld.long 0x0 24.--25. "M6PR,Master 6 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 22. "LQOSEN5,Latency Quality of Service Enable for Master 5" "0,1"
|
|
bitfld.long 0x0 20.--21. "M5PR,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 18. "LQOSEN4,Latency Quality of Service Enable for Master 4" "0,1"
|
|
bitfld.long 0x0 16.--17. "M4PR,Master 4 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 14. "LQOSEN3,Latency Quality of Service Enable for Master 3" "0,1"
|
|
bitfld.long 0x0 12.--13. "M3PR,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 10. "LQOSEN2,Latency Quality of Service Enable for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "M2PR,Master 2 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 6. "LQOSEN1,Latency Quality of Service Enable for Master 1" "0,1"
|
|
bitfld.long 0x0 4.--5. "M1PR,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 2. "LQOSEN0,Latency Quality of Service Enable for Master 0" "0,1"
|
|
bitfld.long 0x0 0.--1. "M0PR,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x4 "PRBS,Priority Register B for Slave"
|
|
bitfld.long 0x4 30. "LQOSEN15,Latency Quality of Service Enable for Master 15" "0,1"
|
|
bitfld.long 0x4 28.--29. "M15PR,Master 15 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 26. "LQOSEN14,Latency Quality of Service Enable for Master 14" "0,1"
|
|
bitfld.long 0x4 24.--25. "M14PR,Master 14 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 22. "LQOSEN13,Latency Quality of Service Enable for Master 13" "0,1"
|
|
bitfld.long 0x4 20.--21. "M13PR,Master 13 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 18. "LQOSEN12,Latency Quality of Service Enable for Master 12" "0,1"
|
|
bitfld.long 0x4 16.--17. "M12PR,Master 12 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 14. "LQOSEN11,Latency Quality of Service Enable for Master 11" "0,1"
|
|
bitfld.long 0x4 12.--13. "M11PR,Master 11 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 10. "LQOSEN10,Latency Quality of Service Enable for Master 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "M10PR,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 6. "LQOSEN9,Latency Quality of Service Enable for Master 9" "0,1"
|
|
bitfld.long 0x4 4.--5. "M9PR,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 2. "LQOSEN8,Latency Quality of Service Enable for Master 8" "0,1"
|
|
bitfld.long 0x4 0.--1. "M8PR,Master 8 Priority" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40000000
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "MRCR,Master Remap Control Register"
|
|
bitfld.long 0x0 15. "RCB15,Remap Command Bit for Master 15" "0,1"
|
|
bitfld.long 0x0 14. "RCB14,Remap Command Bit for Master 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RCB13,Remap Command Bit for Master 13" "0,1"
|
|
bitfld.long 0x0 12. "RCB12,Remap Command Bit for Master 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RCB11,Remap Command Bit for Master 11" "0,1"
|
|
bitfld.long 0x0 10. "RCB10,Remap Command Bit for Master 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RCB9,Remap Command Bit for Master 9" "0,1"
|
|
bitfld.long 0x0 8. "RCB8,Remap Command Bit for Master 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RCB7,Remap Command Bit for Master 7" "0,1"
|
|
bitfld.long 0x0 6. "RCB6,Remap Command Bit for Master 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RCB5,Remap Command Bit for Master 5" "0,1"
|
|
bitfld.long 0x0 4. "RCB4,Remap Command Bit for Master 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RCB3,Remap Command Bit for Master 3" "0,1"
|
|
bitfld.long 0x0 2. "RCB2,Remap Command Bit for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCB1,Remap Command Bit for Master 1" "0,1"
|
|
bitfld.long 0x0 0. "RCB0,Remap Command Bit for Master 0" "0,1"
|
|
wgroup.long 0x150++0x7
|
|
line.long 0x0 "MEIER,Master Error Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MEIDR,Master Error Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
rgroup.long 0x158++0x7
|
|
line.long 0x0 "MEIMR,Master Error Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MESR,Master Error Status Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x160)++0x3
|
|
line.long 0x0 "MEAR[$1],Master 0 Error Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ERRADD,Master Error Address"
|
|
repeat.end
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "CFGFRZ," "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x1E8++0x3
|
|
line.long 0x0 "WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "PSR[$1],Protection Slave Register"
|
|
bitfld.long 0x0 31. "DPSOA7,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 30. "DPSOA6,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DPSOA5,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 28. "DPSOA4,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DPSOA3,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 26. "DPSOA2,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DPSOA1,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 24. "DPSOA0,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "WRUSERH7,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 22. "WRUSERH6,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "WRUSERH5,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 20. "WRUSERH4,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "WRUSERH3,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 18. "WRUSERH2,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "WRUSERH1,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 16. "WRUSERH0,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RDUSERH7,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 14. "RDUSERH6,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RDUSERH5,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 12. "RDUSERH4,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RDUSERH3,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 10. "RDUSERH2,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RDUSERH1,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 8. "RDUSERH0,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LAUSERH7,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 6. "LAUSERH6,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LAUSERH5,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 4. "LAUSERH4,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LAUSERH3,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 2. "LAUSERH2,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LAUSERH1,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 0. "LAUSERH0,Low Area USER in HSELx Protected Region" "0,1"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "PASSR[$1],Protected Areas Split Slave Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PASPLIT7,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PASPLIT6,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PASPLIT5,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PASPLIT4,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PASPLIT3,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PASPLIT2,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PASPLIT1,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PASPLIT0,Protected Areas Split for HSELx Protected Region"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x280)++0x3
|
|
line.long 0x0 "PRTSR[$1],Protected Region Top Slave Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PRTOP7,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PRTOP6,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PRTOP5,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PRTOP4,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PRTOP3,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRTOP2,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PRTOP1,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRTOP0,HSELx Protected Region Top"
|
|
repeat.end
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2C0)++0x3
|
|
line.long 0x0 "PPSELR[$1],Protected Peripheral Select Register"
|
|
bitfld.long 0x0 31. "USERP31,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 30. "USERP30,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "USERP29,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 28. "USERP28,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "USERP27,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 26. "USERP26,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "USERP25,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 24. "USERP24,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "USERP23,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 22. "USERP22,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "USERP21,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 20. "USERP20,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "USERP19,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 18. "USERP18,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "USERP17,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 16. "USERP16,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "USERP15,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 14. "USERP14,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "USERP13,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 12. "USERP12,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "USERP11,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 10. "USERP10,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "USERP9,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 8. "USERP8,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "USERP7,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 6. "USERP6,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "USERP5,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 4. "USERP4,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "USERP3,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 2. "USERP2,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "USERP1,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 0. "USERP0,User PSELy Peripheral" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "MCAN (Controller Area Network)"
|
|
base ad:0x0
|
|
tree "MCAN0"
|
|
base ad:0x40058000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CREL,Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day"
|
|
line.long 0x4 "ENDN,Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0x8++0x27
|
|
line.long 0x0 "CUST,Customer Register"
|
|
hexmask.long 0x0 0.--31. 1. "CSV,Customer-specific Value"
|
|
line.long 0x4 "DBTP,Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled.,1: Transmitter Delay Compensation enabled."
|
|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "DSJW,Data (Re) Synchronization Jump Width" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TEST,Test Register"
|
|
bitfld.long 0x8 7. "RX,Receive Pin (read-only)" "0,1"
|
|
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin (read/write)" "0: Reset value CANTX controlled by the CAN Core..,1: Sample Point can be monitored at pin CANTX.,2: Dominant ('0') level at pin CANTX.,3: Recessive ('1') at pin CANTX."
|
|
newline
|
|
bitfld.long 0x8 4. "LBCK,Loop Back Mode (read/write)" "0: Reset value. Loop Back mode is disabled.,1: Loop Back mode is enabled (see Section 1.5.1.9)."
|
|
line.long 0xC "RWD,RAM Watchdog Register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value (read-only)"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration (read/write)"
|
|
line.long 0x10 "CCCR,CC Control Register"
|
|
bitfld.long 0x10 15. "NISO,Non-ISO Operation" "0,1"
|
|
bitfld.long 0x10 14. "TXP,Transmit Pause (read/write write protection)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration (read/write write protection)" "0,1"
|
|
bitfld.long 0x10 12. "PXHD,Protocol Exception Event Handling (read/write write protection)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "BRSE,Bit Rate Switching Enable (read/write write protection)" "0: Bit rate switching for transmissions disabled.,1: Bit rate switching for transmissions enabled."
|
|
bitfld.long 0x10 8. "FDOE,CAN FD Operation Enable (read/write write protection)" "0: FD operation disabled.,1: FD operation enabled."
|
|
newline
|
|
bitfld.long 0x10 7. "TEST,Test Mode Enable (read/write write protection against '1')" "0: Normal operation MCAN_TEST register holds reset..,1: Test mode write access to MCAN_TEST register.."
|
|
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission (read/write write protection)" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled."
|
|
newline
|
|
bitfld.long 0x10 5. "MON,Bus Monitoring Mode (read/write write protection against '1')" "0: Bus Monitoring mode is disabled.,1: Bus Monitoring mode is enabled."
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request (read/write)" "0: No clock stop is requested.,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge (read-only)" "0,1"
|
|
bitfld.long 0x10 2. "ASM,Restricted Operation Mode (read/write write protection against '1')" "0: Normal CAN operation.,1: Restricted Operation mode active."
|
|
newline
|
|
bitfld.long 0x10 1. "CCE,Configuration Change Enable (read/write write protection)" "0: The processor has no write access to the..,1: The processor has write access to the protected.."
|
|
bitfld.long 0x10 0. "INIT,Initialization (read/write)" "0: Normal operation.,1: Initialization is started."
|
|
line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re) Synchronization Jump Width"
|
|
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
|
|
line.long 0x18 "TSCC,Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,?"
|
|
line.long 0x1C "TSCV,Timestamp Counter Value Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter (cleared on write)"
|
|
line.long 0x20 "TOCC,Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Receive FIFO 0,3: Timeout controlled by Receive FIFO 1"
|
|
newline
|
|
bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled.,1: Timeout Counter enabled."
|
|
line.long 0x24 "TOCV,Timeout Counter Value Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter (cleared on write)"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging (cleared on read)"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message (cleared on read)" "0,1"
|
|
bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message (cleared on read)" "0,1"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code (set to 111 on read)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code (set to 111 on read)" "0: No error occurred since LEC has been reset by..,1: More than 5 equal bits in a sequence have..,2: A fixed format part of a received frame has the..,3: The message transmitted by the MCAN was not..,4: During transmission of a message (with the..,5: During transmission of a message (or acknowledge..,6: The CRC check sum of a received message was..,7: Any read access to the Protocol Status Register.."
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "TDCR,Transmit Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Receive Buffer" "0,1"
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Transmission Completed" "0,1"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RF1L,Receive FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x0 6. "RF1F,Receive FIFO 1 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1W,Receive FIFO 1 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 4. "RF1N,Receive FIFO 1 New Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L,Receive FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 2. "RF0F,Receive FIFO 0 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Receive FIFO 0 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 0. "RF0N,Receive FIFO 0 New Message" "0,1"
|
|
line.long 0x4 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Receive Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Receive FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Receive FIFO 1 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Receive FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Receive FIFO 1 New Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Receive FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Receive FIFO 0 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Receive FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Receive FIFO 0 New Message Interrupt Enable" "0,1"
|
|
line.long 0x8 "ILS,Interrupt Line Select Register"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Receive Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Receive FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Receive FIFO 1 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Receive FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Receive FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Receive FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Receive FIFO 0 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Receive FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Receive FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs.,1: Reject all remote frames with 11-bit standard IDs."
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs.,1: Reject all remote frames with 29-bit extended IDs."
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration Register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask Register"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected.,1: FIFO message lost.,2: Message stored in FIFO 0.,3: Message stored in FIFO 1."
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1 Register"
|
|
bitfld.long 0x0 31. "ND31,New Data" "0,1"
|
|
bitfld.long 0x0 30. "ND30,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ND29,New Data" "0,1"
|
|
bitfld.long 0x0 28. "ND28,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "ND27,New Data" "0,1"
|
|
bitfld.long 0x0 26. "ND26,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "ND25,New Data" "0,1"
|
|
bitfld.long 0x0 24. "ND24,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "ND23,New Data" "0,1"
|
|
bitfld.long 0x0 22. "ND22,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ND21,New Data" "0,1"
|
|
bitfld.long 0x0 20. "ND20,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ND19,New Data" "0,1"
|
|
bitfld.long 0x0 18. "ND18,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ND17,New Data" "0,1"
|
|
bitfld.long 0x0 16. "ND16,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "ND15,New Data" "0,1"
|
|
bitfld.long 0x0 14. "ND14,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data" "0,1"
|
|
bitfld.long 0x0 12. "ND12,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ND11,New Data" "0,1"
|
|
bitfld.long 0x0 10. "ND10,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ND9,New Data" "0,1"
|
|
bitfld.long 0x0 8. "ND8,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ND7,New Data" "0,1"
|
|
bitfld.long 0x0 6. "ND6,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ND5,New Data" "0,1"
|
|
bitfld.long 0x0 4. "ND4,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ND3,New Data" "0,1"
|
|
bitfld.long 0x0 2. "ND2,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ND1,New Data" "0,1"
|
|
bitfld.long 0x0 0. "ND0,New Data" "0,1"
|
|
line.long 0x4 "NDAT2,New Data 2 Register"
|
|
bitfld.long 0x4 31. "ND63,New Data" "0,1"
|
|
bitfld.long 0x4 30. "ND62,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ND61,New Data" "0,1"
|
|
bitfld.long 0x4 28. "ND60,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data" "0,1"
|
|
bitfld.long 0x4 26. "ND58,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data" "0,1"
|
|
bitfld.long 0x4 24. "ND56,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data" "0,1"
|
|
bitfld.long 0x4 22. "ND54,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data" "0,1"
|
|
bitfld.long 0x4 20. "ND52,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data" "0,1"
|
|
bitfld.long 0x4 18. "ND50,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data" "0,1"
|
|
bitfld.long 0x4 16. "ND48,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data" "0,1"
|
|
bitfld.long 0x4 14. "ND46,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data" "0,1"
|
|
bitfld.long 0x4 12. "ND44,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data" "0,1"
|
|
bitfld.long 0x4 10. "ND42,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data" "0,1"
|
|
bitfld.long 0x4 8. "ND40,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data" "0,1"
|
|
bitfld.long 0x4 6. "ND38,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data" "0,1"
|
|
bitfld.long 0x4 4. "ND36,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data" "0,1"
|
|
bitfld.long 0x4 2. "ND34,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data" "0,1"
|
|
bitfld.long 0x4 0. "ND32,New Data" "0,1"
|
|
line.long 0x8 "RXF0C,Receive FIFO 0 Configuration Register"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Receive FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Receive FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Receive FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Receive FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,Receive FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F0F,Receive FIFO 0 Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Receive FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Receive FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Receive FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Receive FIFO 0 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Receive FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Receive Rx Buffer Configuration Register"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Receive Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Receive FIFO 1 Configuration Register"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Receive FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Receive FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Receive FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Receive FIFO 1 Status Register"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received.,2: Debug messages A B received.,3: Debug messages A B C received DMA request is set."
|
|
bitfld.long 0x0 25. "RF1L,Receive FIFO 1 Message Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Receive FIFO 1 Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Receive FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Receive FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Receive FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Receive FIFO 1 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Receive FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Receive Buffer / FIFO Element Size Configuration Register"
|
|
bitfld.long 0x4 8.--10. "RBDS,Receive Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Receive FIFO 1 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Receive FIFO 0 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
line.long 0x8 "TXBC,Transmit Buffer Configuration Register"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Transmit Buffer Element Size Configuration Register"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48- byte data field,7: 64-byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Transmit Buffer Request Pending Register"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending for Buffer 0" "0,1"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Transmit Buffer Add Request Register"
|
|
bitfld.long 0x0 31. "AR31,Add Request for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "AR30,Add Request for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "AR28,Add Request for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "AR26,Add Request for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "AR24,Add Request for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "AR22,Add Request for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "AR20,Add Request for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "AR18,Add Request for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "AR16,Add Request for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "AR14,Add Request for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "AR12,Add Request for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "AR10,Add Request for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "AR8,Add Request for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "AR6,Add Request for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "AR4,Add Request for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "AR2,Add Request for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "AR0,Add Request for Transmit Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCR,Transmit Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request for Transmit Buffer 0" "0,1"
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Transmit Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred for Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCF,Transmit Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CF15,Cancellation Finished for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CF11,Cancellation Finished for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CF9,Cancellation Finished for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CF7,Cancellation Finished for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CF5,Cancellation Finished for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CF3,Cancellation Finished for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CF1,Cancellation Finished for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished for Transmit Buffer 0" "0,1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Transmit Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable for Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCIE,Transmit Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable for Transmit Buffer 0" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "TXEFC,Transmit Event FIFO Configuration Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Transmit Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Transmit Event FIFO Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
tree "MCAN1"
|
|
base ad:0x4005C000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CREL,Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day"
|
|
line.long 0x4 "ENDN,Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0x8++0x27
|
|
line.long 0x0 "CUST,Customer Register"
|
|
hexmask.long 0x0 0.--31. 1. "CSV,Customer-specific Value"
|
|
line.long 0x4 "DBTP,Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x4 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled.,1: Transmitter Delay Compensation enabled."
|
|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data Time Segment After Sample Point"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "DSJW,Data (Re) Synchronization Jump Width" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "TEST,Test Register"
|
|
bitfld.long 0x8 7. "RX,Receive Pin (read-only)" "0,1"
|
|
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin (read/write)" "0: Reset value CANTX controlled by the CAN Core..,1: Sample Point can be monitored at pin CANTX.,2: Dominant ('0') level at pin CANTX.,3: Recessive ('1') at pin CANTX."
|
|
newline
|
|
bitfld.long 0x8 4. "LBCK,Loop Back Mode (read/write)" "0: Reset value. Loop Back mode is disabled.,1: Loop Back mode is enabled (see Section 1.5.1.9)."
|
|
line.long 0xC "RWD,RAM Watchdog Register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value (read-only)"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration (read/write)"
|
|
line.long 0x10 "CCCR,CC Control Register"
|
|
bitfld.long 0x10 15. "NISO,Non-ISO Operation" "0,1"
|
|
bitfld.long 0x10 14. "TXP,Transmit Pause (read/write write protection)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration (read/write write protection)" "0,1"
|
|
bitfld.long 0x10 12. "PXHD,Protocol Exception Event Handling (read/write write protection)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "BRSE,Bit Rate Switching Enable (read/write write protection)" "0: Bit rate switching for transmissions disabled.,1: Bit rate switching for transmissions enabled."
|
|
bitfld.long 0x10 8. "FDOE,CAN FD Operation Enable (read/write write protection)" "0: FD operation disabled.,1: FD operation enabled."
|
|
newline
|
|
bitfld.long 0x10 7. "TEST,Test Mode Enable (read/write write protection against '1')" "0: Normal operation MCAN_TEST register holds reset..,1: Test mode write access to MCAN_TEST register.."
|
|
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission (read/write write protection)" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled."
|
|
newline
|
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bitfld.long 0x10 5. "MON,Bus Monitoring Mode (read/write write protection against '1')" "0: Bus Monitoring mode is disabled.,1: Bus Monitoring mode is enabled."
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request (read/write)" "0: No clock stop is requested.,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge (read-only)" "0,1"
|
|
bitfld.long 0x10 2. "ASM,Restricted Operation Mode (read/write write protection against '1')" "0: Normal CAN operation.,1: Restricted Operation mode active."
|
|
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|
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bitfld.long 0x10 1. "CCE,Configuration Change Enable (read/write write protection)" "0: The processor has no write access to the..,1: The processor has write access to the protected.."
|
|
bitfld.long 0x10 0. "INIT,Initialization (read/write)" "0: Normal operation.,1: Initialization is started."
|
|
line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler Register"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re) Synchronization Jump Width"
|
|
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
|
|
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|
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hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time Segment Before Sample Point"
|
|
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time Segment After Sample Point"
|
|
line.long 0x18 "TSCC,Timestamp Counter Configuration Register"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter value used,?"
|
|
line.long 0x1C "TSCV,Timestamp Counter Value Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TSC,Timestamp Counter (cleared on write)"
|
|
line.long 0x20 "TOCC,Timeout Counter Configuration Register"
|
|
hexmask.long.word 0x20 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x20 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Receive FIFO 0,3: Timeout controlled by Receive FIFO 1"
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newline
|
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bitfld.long 0x20 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled.,1: Timeout Counter enabled."
|
|
line.long 0x24 "TOCV,Timeout Counter Value Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "TOC,Timeout Counter (cleared on write)"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging (cleared on read)"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1"
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|
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|
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hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status Register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event (cleared on read)" "0,1"
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|
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bitfld.long 0x4 13. "RFDF,Received a CAN FD Message (cleared on read)" "0,1"
|
|
bitfld.long 0x4 12. "RBRS,BRS Flag of Last Received CAN FD Message (cleared on read)" "0,1"
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bitfld.long 0x4 11. "RESI,ESI Flag of Last Received CAN FD Message (cleared on read)" "0,1"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code (set to 111 on read)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1"
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|
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
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bitfld.long 0x4 5. "EP,Error Passive" "0,1"
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bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
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bitfld.long 0x4 0.--2. "LEC,Last Error Code (set to 111 on read)" "0: No error occurred since LEC has been reset by..,1: More than 5 equal bits in a sequence have..,2: A fixed format part of a received frame has the..,3: The message transmitted by the MCAN was not..,4: During transmission of a message (with the..,5: During transmission of a message (or acknowledge..,6: The CRC check sum of a received message was..,7: Any read access to the Protocol Status Register.."
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|
group.long 0x48++0x3
|
|
line.long 0x0 "TDCR,Transmit Delay Compensation Register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
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hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter"
|
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group.long 0x50++0xF
|
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line.long 0x0 "IR,Interrupt Register"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1"
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bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0,1"
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newline
|
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bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1"
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bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1"
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bitfld.long 0x0 24. "EW,Warning Status" "0,1"
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bitfld.long 0x0 23. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1"
|
|
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|
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bitfld.long 0x0 19. "DRX,Message stored to Dedicated Receive Buffer" "0,1"
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1"
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|
newline
|
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bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1"
|
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bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1"
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newline
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bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
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|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1"
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bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
|
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bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1"
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newline
|
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bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1"
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newline
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bitfld.long 0x0 9. "TC,Transmission Completed" "0,1"
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|
bitfld.long 0x0 8. "HPM,High Priority Message" "0,1"
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newline
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bitfld.long 0x0 7. "RF1L,Receive FIFO 1 Message Lost" "0,1"
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bitfld.long 0x0 6. "RF1F,Receive FIFO 1 Full" "0,1"
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bitfld.long 0x0 5. "RF1W,Receive FIFO 1 Watermark Reached" "0,1"
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bitfld.long 0x0 4. "RF1N,Receive FIFO 1 New Message" "0,1"
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newline
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bitfld.long 0x0 3. "RF0L,Receive FIFO 0 Message Lost" "0,1"
|
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bitfld.long 0x0 2. "RF0F,Receive FIFO 0 Full" "0,1"
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newline
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bitfld.long 0x0 1. "RF0W,Receive FIFO 0 Watermark Reached" "0,1"
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bitfld.long 0x0 0. "RF0N,Receive FIFO 0 New Message" "0,1"
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line.long 0x4 "IE,Interrupt Enable Register"
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bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
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|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
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newline
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bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
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bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
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bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Receive Buffer Interrupt Enable" "0,1"
|
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bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
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bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
|
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bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
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bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
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bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
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bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 7. "RF1LE,Receive FIFO 1 Message Lost Interrupt Enable" "0,1"
|
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bitfld.long 0x4 6. "RF1FE,Receive FIFO 1 Full Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x4 5. "RF1WE,Receive FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
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bitfld.long 0x4 4. "RF1NE,Receive FIFO 1 New Message Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "RF0LE,Receive FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Receive FIFO 0 Full Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "RF0WE,Receive FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
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bitfld.long 0x4 0. "RF0NE,Receive FIFO 0 New Message Interrupt Enable" "0,1"
|
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line.long 0x8 "ILS,Interrupt Line Select Register"
|
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bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
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newline
|
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bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Receive Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 7. "RF1LL,Receive FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Receive FIFO 1 Full Interrupt Line" "0,1"
|
|
newline
|
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bitfld.long 0x8 5. "RF1WL,Receive FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Receive FIFO 1 New Message Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 3. "RF0LL,Receive FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Receive FIFO 0 Full Interrupt Line" "0,1"
|
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newline
|
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bitfld.long 0x8 1. "RF0WL,Receive FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Receive FIFO 0 New Message Interrupt Line" "0,1"
|
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line.long 0xC "ILE,Interrupt Line Enable Register"
|
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bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
|
|
newline
|
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bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs.,1: Reject all remote frames with 11-bit standard IDs."
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs.,1: Reject all remote frames with 29-bit extended IDs."
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration Register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask Register"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
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bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected.,1: FIFO message lost.,2: Message stored in FIFO 0.,3: Message stored in FIFO 1."
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1 Register"
|
|
bitfld.long 0x0 31. "ND31,New Data" "0,1"
|
|
bitfld.long 0x0 30. "ND30,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "ND29,New Data" "0,1"
|
|
bitfld.long 0x0 28. "ND28,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "ND27,New Data" "0,1"
|
|
bitfld.long 0x0 26. "ND26,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "ND25,New Data" "0,1"
|
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bitfld.long 0x0 24. "ND24,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 23. "ND23,New Data" "0,1"
|
|
bitfld.long 0x0 22. "ND22,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "ND21,New Data" "0,1"
|
|
bitfld.long 0x0 20. "ND20,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "ND19,New Data" "0,1"
|
|
bitfld.long 0x0 18. "ND18,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 17. "ND17,New Data" "0,1"
|
|
bitfld.long 0x0 16. "ND16,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "ND15,New Data" "0,1"
|
|
bitfld.long 0x0 14. "ND14,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "ND13,New Data" "0,1"
|
|
bitfld.long 0x0 12. "ND12,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "ND11,New Data" "0,1"
|
|
bitfld.long 0x0 10. "ND10,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "ND9,New Data" "0,1"
|
|
bitfld.long 0x0 8. "ND8,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "ND7,New Data" "0,1"
|
|
bitfld.long 0x0 6. "ND6,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "ND5,New Data" "0,1"
|
|
bitfld.long 0x0 4. "ND4,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "ND3,New Data" "0,1"
|
|
bitfld.long 0x0 2. "ND2,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "ND1,New Data" "0,1"
|
|
bitfld.long 0x0 0. "ND0,New Data" "0,1"
|
|
line.long 0x4 "NDAT2,New Data 2 Register"
|
|
bitfld.long 0x4 31. "ND63,New Data" "0,1"
|
|
bitfld.long 0x4 30. "ND62,New Data" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "ND61,New Data" "0,1"
|
|
bitfld.long 0x4 28. "ND60,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data" "0,1"
|
|
bitfld.long 0x4 26. "ND58,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data" "0,1"
|
|
bitfld.long 0x4 24. "ND56,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data" "0,1"
|
|
bitfld.long 0x4 22. "ND54,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data" "0,1"
|
|
bitfld.long 0x4 20. "ND52,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data" "0,1"
|
|
bitfld.long 0x4 18. "ND50,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data" "0,1"
|
|
bitfld.long 0x4 16. "ND48,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data" "0,1"
|
|
bitfld.long 0x4 14. "ND46,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data" "0,1"
|
|
bitfld.long 0x4 12. "ND44,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data" "0,1"
|
|
bitfld.long 0x4 10. "ND42,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data" "0,1"
|
|
bitfld.long 0x4 8. "ND40,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data" "0,1"
|
|
bitfld.long 0x4 6. "ND38,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data" "0,1"
|
|
bitfld.long 0x4 4. "ND36,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data" "0,1"
|
|
bitfld.long 0x4 2. "ND34,New Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data" "0,1"
|
|
bitfld.long 0x4 0. "ND32,New Data" "0,1"
|
|
line.long 0x8 "RXF0C,Receive FIFO 0 Configuration Register"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Receive FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Receive FIFO 0 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F0SA,Receive FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Receive FIFO 0 Status Register"
|
|
bitfld.long 0x0 25. "RF0L,Receive FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F0F,Receive FIFO 0 Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Receive FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Receive FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Receive FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Receive FIFO 0 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Receive FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Receive Rx Buffer Configuration Register"
|
|
hexmask.long.word 0x4 2.--15. 1. "RBSA,Receive Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Receive FIFO 1 Configuration Register"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Receive FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Receive FIFO 1 Size"
|
|
hexmask.long.word 0x8 2.--15. 1. "F1SA,Receive FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Receive FIFO 1 Status Register"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages..,1: Debug message A received.,2: Debug messages A B received.,3: Debug messages A B C received DMA request is set."
|
|
bitfld.long 0x0 25. "RF1L,Receive FIFO 1 Message Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Receive FIFO 1 Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Receive FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Receive FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Receive FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Receive FIFO 1 Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Receive FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Receive Buffer / FIFO Element Size Configuration Register"
|
|
bitfld.long 0x4 8.--10. "RBDS,Receive Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Receive FIFO 1 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Receive FIFO 0 Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48-byte data field,7: 64-byte data field"
|
|
line.long 0x8 "TXBC,Transmit Buffer Configuration Register"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Transmit FIFO/Queue Status Register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Transmit Buffer Element Size Configuration Register"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8-byte data field,1: 12-byte data field,2: 16-byte data field,3: 20-byte data field,4: 24-byte data field,5: 32-byte data field,6: 48- byte data field,7: 64-byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Transmit Buffer Request Pending Register"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending for Buffer 0" "0,1"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Transmit Buffer Add Request Register"
|
|
bitfld.long 0x0 31. "AR31,Add Request for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "AR30,Add Request for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "AR28,Add Request for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "AR26,Add Request for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "AR24,Add Request for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "AR22,Add Request for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "AR20,Add Request for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "AR18,Add Request for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "AR16,Add Request for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "AR14,Add Request for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "AR12,Add Request for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "AR10,Add Request for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "AR8,Add Request for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "AR6,Add Request for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "AR4,Add Request for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "AR2,Add Request for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "AR0,Add Request for Transmit Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCR,Transmit Buffer Cancellation Request Register"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request for Transmit Buffer 0" "0,1"
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Transmit Buffer Transmission Occurred Register"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred for Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCF,Transmit Buffer Cancellation Finished Register"
|
|
bitfld.long 0x4 31. "CF31,Cancellation Finished for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CF30,Cancellation Finished for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Cancellation Finished for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CF28,Cancellation Finished for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Cancellation Finished for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CF26,Cancellation Finished for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Cancellation Finished for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CF24,Cancellation Finished for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Cancellation Finished for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CF22,Cancellation Finished for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Cancellation Finished for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CF20,Cancellation Finished for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CF19,Cancellation Finished for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CF18,Cancellation Finished for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Cancellation Finished for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CF16,Cancellation Finished for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CF15,Cancellation Finished for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CF14,Cancellation Finished for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Cancellation Finished for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CF12,Cancellation Finished for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CF11,Cancellation Finished for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CF10,Cancellation Finished for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CF9,Cancellation Finished for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CF8,Cancellation Finished for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CF7,Cancellation Finished for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CF6,Cancellation Finished for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CF5,Cancellation Finished for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CF4,Cancellation Finished for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CF3,Cancellation Finished for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CF2,Cancellation Finished for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CF1,Cancellation Finished for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CF0,Cancellation Finished for Transmit Buffer 0" "0,1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Transmit Buffer Transmission Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable for Buffer 31" "0,1"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable for Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable for Buffer 29" "0,1"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable for Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable for Buffer 27" "0,1"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable for Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable for Buffer 25" "0,1"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable for Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable for Buffer 23" "0,1"
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable for Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable for Buffer 21" "0,1"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable for Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable for Buffer 19" "0,1"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable for Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable for Buffer 17" "0,1"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable for Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable for Buffer 15" "0,1"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable for Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable for Buffer 13" "0,1"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable for Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable for Buffer 11" "0,1"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable for Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable for Buffer 9" "0,1"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable for Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable for Buffer 7" "0,1"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable for Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable for Buffer 5" "0,1"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable for Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable for Buffer 3" "0,1"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable for Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable for Buffer 1" "0,1"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable for Buffer 0" "0,1"
|
|
line.long 0x4 "TXBCIE,Transmit Buffer Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable for Transmit Buffer 31" "0,1"
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable for Transmit Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable for Transmit Buffer 29" "0,1"
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable for Transmit Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable for Transmit Buffer 27" "0,1"
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable for Transmit Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable for Transmit Buffer 25" "0,1"
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable for Transmit Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable for Transmit Buffer 23" "0,1"
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable for Transmit Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable for Transmit Buffer 21" "0,1"
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable for Transmit Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable for Transmit Buffer 19" "0,1"
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable for Transmit Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable for Transmit Buffer 17" "0,1"
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable for Transmit Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable for Transmit Buffer 15" "0,1"
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable for Transmit Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable for Transmit Buffer 13" "0,1"
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable for Transmit Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable for Transmit Buffer 11" "0,1"
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable for Transmit Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable for Transmit Buffer 9" "0,1"
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable for Transmit Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable for Transmit Buffer 7" "0,1"
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable for Transmit Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable for Transmit Buffer 5" "0,1"
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable for Transmit Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable for Transmit Buffer 3" "0,1"
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable for Transmit Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable for Transmit Buffer 1" "0,1"
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable for Transmit Buffer 0" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "TXEFC,Transmit Event FIFO Configuration Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Transmit Event FIFO Status Register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Transmit Event FIFO Acknowledge Register"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
tree.end
|
|
tree.end
|
|
tree "MPU (Memory Protection Unit)"
|
|
base ad:0xE000ED90
|
|
group.long 0x0++0x2B
|
|
line.long 0x0 "TYPE,MPU Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "IREGION,Indicates the number of supported MPU data regions."
|
|
hexmask.long.byte 0x0 8.--15. 1. "DREGION,Indicates the number of supported MPU instruction regions."
|
|
bitfld.long 0x0 0. "SEPARATE,Indicates support for unified or separate instruction and date memory maps." "0,1"
|
|
line.long 0x4 "CTRL,MPU Control Register"
|
|
bitfld.long 0x4 2. "PRIVDEFENA,Enables privileged software access to the default memory map." "0,1"
|
|
bitfld.long 0x4 1. "HFNMIENA,Enables the operation of MPU during hard fault NMI and FAULTMASK handlers." "0,1"
|
|
bitfld.long 0x4 0. "ENABLE,Enables the MPU" "0,1"
|
|
line.long 0x8 "RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "REGION,Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers."
|
|
line.long 0xC "RBAR,MPU Region Base Address Register"
|
|
hexmask.long 0xC 5.--31. 1. "ADDR,Region base address field."
|
|
bitfld.long 0xC 4. "VALID,MPU Region Number valid bit." "0,1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "REGION,MPU region field."
|
|
line.long 0x10 "RASR,MPU Region Attribute and Size Register"
|
|
bitfld.long 0x10 28. "XN,Instruction access disable bit." "0,1"
|
|
bitfld.long 0x10 24.--26. "AP,Access permission field." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 19.--21. "TEX,MPU access permission attributes." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 18. "S,Shareable bit." "0,1"
|
|
bitfld.long 0x10 17. "C,MPU access permission attributes." "0,1"
|
|
bitfld.long 0x10 16. "B,MPU access permission attributes." "0,1"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SRD,Subregion disable bits."
|
|
hexmask.long.byte 0x10 1.--5. 1. "SIZE,Specifies the size of the MPU protection region."
|
|
newline
|
|
bitfld.long 0x10 0. "ENABLE,Region enable bit." "0,1"
|
|
line.long 0x14 "RBAR_A1,MPU Alias 1 Region Base Address Register"
|
|
line.long 0x18 "RASR_A1,MPU Alias 1 Region Attribute and Size Register"
|
|
line.long 0x1C "RBAR_A2,MPU Alias 2 Region Base Address Register"
|
|
line.long 0x20 "RASR_A2,MPU Alias 2 Region Attribute and Size Register"
|
|
line.long 0x24 "RBAR_A3,MPU Alias 3 Region Base Address Register"
|
|
line.long 0x28 "RASR_A3,MPU Alias 3 Region Attribute and Size Register"
|
|
tree.end
|
|
tree "NMIC (Non-maskable Interrupt Controller)"
|
|
base ad:0x400A8000
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 8. "NMI8,Non-maskable Interrupt 8 Enable" "0,1"
|
|
bitfld.long 0x0 7. "NMI7,Non-maskable Interrupt 7 Enable" "0,1"
|
|
bitfld.long 0x0 6. "NMI6,Non-maskable Interrupt 6 Enable" "0,1"
|
|
bitfld.long 0x0 5. "NMI5,Non-maskable Interrupt 5 Enable" "0,1"
|
|
bitfld.long 0x0 4. "NMI4,Non-maskable Interrupt 4 Enable" "0,1"
|
|
bitfld.long 0x0 3. "NMI3,Non-maskable Interrupt 3 Enable" "0,1"
|
|
bitfld.long 0x0 2. "NMI2,Non-maskable Interrupt 2 Enable" "0,1"
|
|
bitfld.long 0x0 1. "NMI1,Non-maskable Interrupt 1 Enable" "0,1"
|
|
bitfld.long 0x0 0. "NMI0,Non-maskable Interrupt 0 Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 8. "NMI8,Non-maskable Interrupt 8 Disable" "0,1"
|
|
bitfld.long 0x4 7. "NMI7,Non-maskable Interrupt 7 Disable" "0,1"
|
|
bitfld.long 0x4 6. "NMI6,Non-maskable Interrupt 6 Disable" "0,1"
|
|
bitfld.long 0x4 5. "NMI5,Non-maskable Interrupt 5 Disable" "0,1"
|
|
bitfld.long 0x4 4. "NMI4,Non-maskable Interrupt 4 Disable" "0,1"
|
|
bitfld.long 0x4 3. "NMI3,Non-maskable Interrupt 3 Disable" "0,1"
|
|
bitfld.long 0x4 2. "NMI2,Non-maskable Interrupt 2 Disable" "0,1"
|
|
bitfld.long 0x4 1. "NMI1,Non-maskable Interrupt 1 Disable" "0,1"
|
|
bitfld.long 0x4 0. "NMI0,Non-maskable Interrupt 0 Disable" "0,1"
|
|
rgroup.long 0x8++0xB
|
|
line.long 0x0 "IAR,Interrupt Active Register"
|
|
bitfld.long 0x0 8. "NMI8,Active Interrupt 8" "0,1"
|
|
bitfld.long 0x0 7. "NMI7,Active Interrupt 7" "0,1"
|
|
bitfld.long 0x0 6. "NMI6,Active Interrupt 6" "0,1"
|
|
bitfld.long 0x0 5. "NMI5,Active Interrupt 5" "0,1"
|
|
bitfld.long 0x0 4. "NMI4,Active Interrupt 4" "0,1"
|
|
bitfld.long 0x0 3. "NMI3,Active Interrupt 3" "0,1"
|
|
bitfld.long 0x0 2. "NMI2,Active Interrupt 2" "0,1"
|
|
bitfld.long 0x0 1. "NMI1,Active Interrupt 1" "0,1"
|
|
bitfld.long 0x0 0. "NMI0,Active Interrupt 0" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 8. "NMI8,Non-maskable Interrupt Source 8 Pending (cleared on read)" "0,1"
|
|
bitfld.long 0x4 7. "NMI7,Non-maskable Interrupt Source 7 Pending (cleared on read)" "0,1"
|
|
bitfld.long 0x4 6. "NMI6,Non-maskable Interrupt Source 6 Pending (cleared on read)" "0,1"
|
|
bitfld.long 0x4 5. "NMI5,Non-maskable Interrupt Source 5 Pending (cleared on read)" "0,1"
|
|
bitfld.long 0x4 4. "NMI4,Non-maskable Interrupt Source 4 Pending (cleared on read)" "0,1"
|
|
bitfld.long 0x4 3. "NMI3,Non-maskable Interrupt Source 3 Pending (cleared on read)" "0,1"
|
|
bitfld.long 0x4 2. "NMI2,Non-maskable Interrupt Source 2 Pending (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "NMI1,Non-maskable Interrupt Source 1 Pending (cleared on read)" "0,1"
|
|
bitfld.long 0x4 0. "NMI0,Non-maskable Interrupt Source 0 Pending (cleared on read)" "0,1"
|
|
line.long 0x8 "GFCS,Glitch Filter Configuration Status Register"
|
|
bitfld.long 0x8 8. "RDY8,Filter 8 Configuration Ready" "0,1"
|
|
bitfld.long 0x8 7. "RDY7,Filter 7 Configuration Ready" "0,1"
|
|
bitfld.long 0x8 6. "RDY6,Filter 6 Configuration Ready" "0,1"
|
|
bitfld.long 0x8 5. "RDY5,Filter 5 Configuration Ready" "0,1"
|
|
bitfld.long 0x8 4. "RDY4,Filter 4 Configuration Ready" "0,1"
|
|
bitfld.long 0x8 3. "RDY3,Filter 3 Configuration Ready" "0,1"
|
|
bitfld.long 0x8 2. "RDY2,Filter 2 Configuration Ready" "0,1"
|
|
bitfld.long 0x8 1. "RDY1,Filter 1 Configuration Ready" "0,1"
|
|
bitfld.long 0x8 0. "RDY0,Filter 0 Configuration Ready" "0,1"
|
|
group.long 0x14++0x23
|
|
line.long 0x0 "SCFG0R,Source Configuration Register 0"
|
|
bitfld.long 0x0 31. "FRZ,Interrupt Line Freeze" "0,1"
|
|
bitfld.long 0x0 16. "EN,Source Enable" "0,1"
|
|
bitfld.long 0x0 9. "LVL,Level Detection (LVL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x0 8. "POL,Polarity (POL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x0 4. "GFEN,Glitch Filter Enable (GFEN bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x0 0.--1. "GFSEL,Glitch Filter Selector (GFSEL field is read-only in NMIC_SCFG1 to 8)" "0,1,2,3"
|
|
line.long 0x4 "SCFG1R,Source Configuration Register 1"
|
|
bitfld.long 0x4 31. "FRZ,Interrupt Line Freeze" "0,1"
|
|
bitfld.long 0x4 16. "EN,Source Enable" "0,1"
|
|
bitfld.long 0x4 9. "LVL,Level Detection (LVL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x4 8. "POL,Polarity (POL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x4 4. "GFEN,Glitch Filter Enable (GFEN bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x4 0.--1. "GFSEL,Glitch Filter Selector (GFSEL field is read-only in NMIC_SCFG1 to 8)" "0,1,2,3"
|
|
line.long 0x8 "SCFG2R,Source Configuration Register 2"
|
|
bitfld.long 0x8 31. "FRZ,Interrupt Line Freeze" "0,1"
|
|
bitfld.long 0x8 16. "EN,Source Enable" "0,1"
|
|
bitfld.long 0x8 9. "LVL,Level Detection (LVL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x8 8. "POL,Polarity (POL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x8 4. "GFEN,Glitch Filter Enable (GFEN bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x8 0.--1. "GFSEL,Glitch Filter Selector (GFSEL field is read-only in NMIC_SCFG1 to 8)" "0,1,2,3"
|
|
line.long 0xC "SCFG3R,Source Configuration Register 3"
|
|
bitfld.long 0xC 31. "FRZ,Interrupt Line Freeze" "0,1"
|
|
bitfld.long 0xC 16. "EN,Source Enable" "0,1"
|
|
bitfld.long 0xC 9. "LVL,Level Detection (LVL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0xC 8. "POL,Polarity (POL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0xC 4. "GFEN,Glitch Filter Enable (GFEN bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0xC 0.--1. "GFSEL,Glitch Filter Selector (GFSEL field is read-only in NMIC_SCFG1 to 8)" "0,1,2,3"
|
|
line.long 0x10 "SCFG4R,Source Configuration Register 4"
|
|
bitfld.long 0x10 31. "FRZ,Interrupt Line Freeze" "0,1"
|
|
bitfld.long 0x10 16. "EN,Source Enable" "0,1"
|
|
bitfld.long 0x10 9. "LVL,Level Detection (LVL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x10 8. "POL,Polarity (POL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x10 4. "GFEN,Glitch Filter Enable (GFEN bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x10 0.--1. "GFSEL,Glitch Filter Selector (GFSEL field is read-only in NMIC_SCFG1 to 8)" "0,1,2,3"
|
|
line.long 0x14 "SCFG5R,Source Configuration Register 5"
|
|
bitfld.long 0x14 31. "FRZ,Interrupt Line Freeze" "0,1"
|
|
bitfld.long 0x14 16. "EN,Source Enable" "0,1"
|
|
bitfld.long 0x14 9. "LVL,Level Detection (LVL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x14 8. "POL,Polarity (POL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x14 4. "GFEN,Glitch Filter Enable (GFEN bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x14 0.--1. "GFSEL,Glitch Filter Selector (GFSEL field is read-only in NMIC_SCFG1 to 8)" "0,1,2,3"
|
|
line.long 0x18 "SCFG6R,Source Configuration Register 6"
|
|
bitfld.long 0x18 31. "FRZ,Interrupt Line Freeze" "0,1"
|
|
bitfld.long 0x18 16. "EN,Source Enable" "0,1"
|
|
bitfld.long 0x18 9. "LVL,Level Detection (LVL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x18 8. "POL,Polarity (POL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x18 4. "GFEN,Glitch Filter Enable (GFEN bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x18 0.--1. "GFSEL,Glitch Filter Selector (GFSEL field is read-only in NMIC_SCFG1 to 8)" "0,1,2,3"
|
|
line.long 0x1C "SCFG7R,Source Configuration Register 7"
|
|
bitfld.long 0x1C 31. "FRZ,Interrupt Line Freeze" "0,1"
|
|
bitfld.long 0x1C 16. "EN,Source Enable" "0,1"
|
|
bitfld.long 0x1C 9. "LVL,Level Detection (LVL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x1C 8. "POL,Polarity (POL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x1C 4. "GFEN,Glitch Filter Enable (GFEN bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x1C 0.--1. "GFSEL,Glitch Filter Selector (GFSEL field is read-only in NMIC_SCFG1 to 8)" "0,1,2,3"
|
|
line.long 0x20 "SCFG8R,Source Configuration Register 8"
|
|
bitfld.long 0x20 31. "FRZ,Interrupt Line Freeze" "0,1"
|
|
bitfld.long 0x20 16. "EN,Source Enable" "0,1"
|
|
bitfld.long 0x20 9. "LVL,Level Detection (LVL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x20 8. "POL,Polarity (POL bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x20 4. "GFEN,Glitch Filter Enable (GFEN bit is read-only in NMIC_SCFG1 to 8)" "0,1"
|
|
bitfld.long 0x20 0.--1. "GFSEL,Glitch Filter Selector (GFSEL field is read-only in NMIC_SCFG1 to 8)" "0,1,2,3"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPCFEN,Write Protection Configuration Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WVSRC,Write Violation Source"
|
|
bitfld.long 0x0 2. "BSWVS,Busy Register Write Violation Status" "0,1"
|
|
bitfld.long 0x0 1. "FZWVS,Frozen Register Write Violation Status" "0,1"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Register Violation Status" "0,1"
|
|
tree.end
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
base ad:0xE000E100
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "ISER[$1],Interrupt Set Enable Register n"
|
|
hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt set enable bits"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "ICER[$1],Interrupt Clear Enable Register n"
|
|
hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt clear-enable bits"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "ISPR[$1],Interrupt Set Pending Register n"
|
|
hexmask.long 0x0 0.--31. 1. "SETPEND,Interrupt set-pending bits"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x180)++0x3
|
|
line.long 0x0 "ICPR[$1],Interrupt Clear Pending Register n"
|
|
hexmask.long 0x0 0.--31. 1. "CLRPEND,Interrupt clear-pending bits"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "IABR[$1],Interrupt Active bit Register n"
|
|
hexmask.long 0x0 0.--31. 1. "ACTIVE,Interrupt active flags"
|
|
repeat.end
|
|
repeat 240. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x300)++0x0
|
|
line.byte 0x0 "IP[$1],Interrupt Priority Register (8Bit wide) n"
|
|
hexmask.byte 0x0 0.--7. 1. "PRI0,Priority of interrupt 0"
|
|
repeat.end
|
|
wgroup.long 0xE00++0x3
|
|
line.long 0x0 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x0 0.--8. 1. "INTID,Interrupt ID of the interrupt to trigger in the range 0-239. For example a value of 0x03 specifies interrupt IRQ3."
|
|
tree.end
|
|
tree "PCC (Parallel Capture Controller)"
|
|
base ad:0x4001C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 30.--31. "CID,Clear If Disabled" "0: Clear not enabled,1: Clear on falling edge on DEN1 enabled,2: Clear on falling edge on DEN2 enabled,3: Clear on falling edge on either DEN1 or DEN2.."
|
|
bitfld.long 0x0 16.--18. "ISIZE,Input Data Size" "0: Input data bus size is 8 bits,1: Input data bus size is 10 bits,2: Input data bus size is 12 bits,3: Input data bus size is 14 bits,4: Input data bus size is 16 bits,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 11. "FRSTS,First Sample" "0,1"
|
|
bitfld.long 0x0 10. "HALFS,Half Sampling" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ALWYS,Always Sampling" "0,1"
|
|
bitfld.long 0x0 8. "SCALE,Scale Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "DSIZE,Data Size" "0: 1 data is read in the PCC_RHR,1: 2 data are read in the PCC_RHR,2: 4 data are read in the PCC_RHR (only for 8 bits..,?"
|
|
bitfld.long 0x0 0. "PCEN,Parallele Capture Enable" "0,1"
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0xC++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error." "0,1"
|
|
bitfld.long 0x4 0. "DRDY,Data Ready" "0,1"
|
|
line.long 0x8 "RHR,Reception Holding Register"
|
|
hexmask.long 0x8 0.--31. 1. "RDATA,Reception Data."
|
|
group.long 0xE0++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key."
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "PIO (Parallel Input/Output Controller)"
|
|
base ad:0x40008000
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40008000 ad:0x40008040 ad:0x40008080 ad:0x400080C0)
|
|
tree "PIO_GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "MSKR,PIO Mask Register"
|
|
bitfld.long 0x0 31. "MSK31,PIO Line 31 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 30. "MSK30,PIO Line 30 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 29. "MSK29,PIO Line 29 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 28. "MSK28,PIO Line 28 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 27. "MSK27,PIO Line 27 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 26. "MSK26,PIO Line 26 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 25. "MSK25,PIO Line 25 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 24. "MSK24,PIO Line 24 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 23. "MSK23,PIO Line 23 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 22. "MSK22,PIO Line 22 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 21. "MSK21,PIO Line 21 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 20. "MSK20,PIO Line 20 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 19. "MSK19,PIO Line 19 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 18. "MSK18,PIO Line 18 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 17. "MSK17,PIO Line 17 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 16. "MSK16,PIO Line 16 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 15. "MSK15,PIO Line 15 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 14. "MSK14,PIO Line 14 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 13. "MSK13,PIO Line 13 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 12. "MSK12,PIO Line 12 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 11. "MSK11,PIO Line 11 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 10. "MSK10,PIO Line 10 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 9. "MSK9,PIO Line 9 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 8. "MSK8,PIO Line 8 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 7. "MSK7,PIO Line 7 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 6. "MSK6,PIO Line 6 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 5. "MSK5,PIO Line 5 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 4. "MSK4,PIO Line 4 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 3. "MSK3,PIO Line 3 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 2. "MSK2,PIO Line 2 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 1. "MSK1,PIO Line 1 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 0. "MSK0,PIO Line 0 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
line.long 0x4 "CFGR,PIO Configuration Register"
|
|
bitfld.long 0x4 30. "ICFS,Interrupt Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
|
|
bitfld.long 0x4 29. "PCFS,Physical Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
|
|
newline
|
|
bitfld.long 0x4 24.--26. "EVTSEL,Event Selection" "0: Event detection on input falling edge,1: Event detection on input rising edge,2: Event detection on input both edge,3: Event detection on low level input,4: Event detection on high level input,?,?,?"
|
|
bitfld.long 0x4 16.--18. "DRVSTR,Drive Strength" "0: Output drive is 2mA,1: Output drive is 4mA,2: Output drive is 8mA,3: Output drive is 16mA,4: Output drive is 24mA,5: Output drive is 32mA,6: Output drive is 40mA,7: Output drive is 48mA"
|
|
newline
|
|
bitfld.long 0x4 15. "SCHMITT,Schmitt Trigger" "0: Schmitt trigger is enabled for the selected I/O..,1: Schmitt trigger is disabled for the selected I/O.."
|
|
bitfld.long 0x4 14. "OPD,Open-Drain" "0: The open-drain is disabled for the selected I/O..,1: The open-drain is enabled for the selected I/O.."
|
|
newline
|
|
bitfld.long 0x4 10. "PDEN,Pull-Down Enable" "0: Pull-Down is disabled for the selected I/O lines.,1: Pull-Down is enabled for the selected I/O lines.."
|
|
bitfld.long 0x4 9. "PUEN,Pull-Up Enable" "0: Pull-Up is disabled for the selected I/O lines.,1: Pull-Up is enabled for the selected I/O lines."
|
|
newline
|
|
bitfld.long 0x4 8. "DIR,Direction" "0: The selected I/O lines are pure inputs.,1: The selected I/O lines are enabled in output."
|
|
bitfld.long 0x4 0.--2. "FUNC,I/O Line Function" "0: Select the PIO mode for the selected I/O lines.,1: Select the peripheral A for the selected I/O..,2: Select the peripheral B for the selected I/O..,3: Select the peripheral C for the selected I/O..,4: Select the peripheral D for the selected I/O..,5: Select the peripheral E for the selected I/O..,6: Select the peripheral F for the selected I/O..,7: Select the peripheral G for the selected I/O.."
|
|
rgroup.long ($2+0x8)++0x7
|
|
line.long 0x0 "PDSR,PIO Pin Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Input Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Data Status" "0,1"
|
|
line.long 0x4 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x4 31. "P31,Lock Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Lock Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Lock Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Lock Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Lock Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Lock Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Lock Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Lock Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Lock Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Lock Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Lock Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Lock Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Lock Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Lock Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Lock Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Lock Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Lock Status" "0,1"
|
|
wgroup.long ($2+0x10)++0x7
|
|
line.long 0x0 "SODR,PIO Set Output Data Register"
|
|
bitfld.long 0x0 31. "P31,Set Output Data" "0,1"
|
|
bitfld.long 0x0 30. "P30,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Set Output Data" "0,1"
|
|
bitfld.long 0x0 28. "P28,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Set Output Data" "0,1"
|
|
bitfld.long 0x0 26. "P26,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Set Output Data" "0,1"
|
|
bitfld.long 0x0 24. "P24,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Set Output Data" "0,1"
|
|
bitfld.long 0x0 22. "P22,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Set Output Data" "0,1"
|
|
bitfld.long 0x0 20. "P20,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Set Output Data" "0,1"
|
|
bitfld.long 0x0 18. "P18,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Set Output Data" "0,1"
|
|
bitfld.long 0x0 16. "P16,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Set Output Data" "0,1"
|
|
bitfld.long 0x0 14. "P14,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Set Output Data" "0,1"
|
|
bitfld.long 0x0 12. "P12,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Set Output Data" "0,1"
|
|
bitfld.long 0x0 10. "P10,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Set Output Data" "0,1"
|
|
bitfld.long 0x0 8. "P8,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set Output Data" "0,1"
|
|
bitfld.long 0x0 6. "P6,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Set Output Data" "0,1"
|
|
bitfld.long 0x0 4. "P4,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Set Output Data" "0,1"
|
|
bitfld.long 0x0 2. "P2,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Set Output Data" "0,1"
|
|
bitfld.long 0x0 0. "P0,Set Output Data" "0,1"
|
|
line.long 0x4 "CODR,PIO Clear Output Data Register"
|
|
bitfld.long 0x4 31. "P31,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 30. "P30,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 28. "P28,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 26. "P26,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 24. "P24,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 22. "P22,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 20. "P20,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 18. "P18,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 16. "P16,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 14. "P14,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 12. "P12,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 10. "P10,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 8. "P8,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 6. "P6,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 4. "P4,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 2. "P2,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 0. "P0,Clear Output Data" "0,1"
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "ODSR,PIO Output Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
wgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "IER,PIO Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,PIO Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0,1"
|
|
rgroup.long ($2+0x28)++0x7
|
|
line.long 0x0 "IMR,PIO Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,PIO Interrupt Status Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0,1"
|
|
wgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "IOFR,PIO I/O Freeze Configuration Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "FRZKEY,Freeze Key"
|
|
bitfld.long 0x0 1. "FINT,Freeze Interrupt Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FPHY,Freeze Physical Configuration" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40008000
|
|
group.long 0x500++0x3
|
|
line.long 0x0 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "DIV,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x5E0++0x3
|
|
line.long 0x0 "WPMR,PIO Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x5E4++0x3
|
|
line.long 0x0 "WPSR,PIO Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x4000C000
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "SCER,System Clock Enable Register"
|
|
bitfld.long 0x0 11. "PCK3,Programmable Clock 3 Output Enable" "0,1"
|
|
bitfld.long 0x0 10. "PCK2,Programmable Clock 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PCK1,Programmable Clock 1 Output Enable" "0,1"
|
|
bitfld.long 0x0 8. "PCK0,Programmable Clock 0 Output Enable" "0,1"
|
|
line.long 0x4 "SCDR,System Clock Disable Register"
|
|
bitfld.long 0x4 11. "PCK3,Programmable Clock 3 Output Disable" "0,1"
|
|
bitfld.long 0x4 10. "PCK2,Programmable Clock 2 Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PCK1,Programmable Clock 1 Output Disable" "0,1"
|
|
bitfld.long 0x4 8. "PCK0,Programmable Clock 0 Output Disable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SCSR,System Clock Status Register"
|
|
bitfld.long 0x0 11. "PCK3,Programmable Clock 3 Output Status" "0,1"
|
|
bitfld.long 0x0 10. "PCK2,Programmable Clock 2 Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PCK1,Programmable Clock 1 Output Status" "0,1"
|
|
bitfld.long 0x0 8. "PCK0,Programmable Clock 0 Output Status" "0,1"
|
|
group.long 0x20++0x13
|
|
line.long 0x0 "CKGR_MOR,Main Oscillator Register"
|
|
bitfld.long 0x0 28. "BCPUNMIC,Bad CPU Clock Interrupt to NMIC Enable" "0,1"
|
|
bitfld.long 0x0 27. "BCPURST,Bad CPU Clock Reset Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "EXT32KFME,32.768 kHz External Slow clock Frequency Monitoring Enable" "0,1"
|
|
bitfld.long 0x0 25. "CFDEN,Clock Failure Detector Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MOSCSEL,Main Clock Oscillator Selection" "0,1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "KEY,Write Access Password"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MOSCXTST,Main Crystal Oscillator Startup Time"
|
|
bitfld.long 0x0 4.--6. "MOSCRCF,Main RC Oscillator Frequency Selection" "0: The RC oscillator frequency is at 4 MHz,1: The RC oscillator frequency is at 8 MHz,2: The RC oscillator frequency is at 10 MHz,3: The RC oscillator frequency is at 12 MHz,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 3. "MOSCRCEN,Main RC Oscillator Enable" "0,1"
|
|
bitfld.long 0x0 1. "ZERO,Shall be always write at '0'" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MOSCXTEN,Main Crystal Oscillator Enable" "0,1"
|
|
line.long 0x4 "CKGR_MCFR,Main Clock Frequency Register"
|
|
bitfld.long 0x4 24. "CCSS,Counter Clock Source Selection" "0,1"
|
|
bitfld.long 0x4 20. "RCMEAS,RC Oscillator Frequency Measure (write-only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MAINFRDY,Main Clock Frequency Measure Ready" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "MAINF,Main Clock Frequency"
|
|
line.long 0x8 "CKGR_PLLAR,PLLA Register"
|
|
bitfld.long 0x8 29. "ONE,Must Be Set to 1" "0,1"
|
|
hexmask.long.word 0x8 16.--26. 1. "MULA,PLLA Multiplier"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "FREQ_VCO,VCO Frequency Configuratio" "0: Frequency range: 40-80 MHz,1: Frequency range: 70-150 MHz,2: Frequency range: 125-275 MHz,3: Frequency range: 250-450 MHz"
|
|
hexmask.long.byte 0x8 8.--13. 1. "PLLACOUNT,PLLA Counter"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "DIVA,PLLA Front End Divider"
|
|
line.long 0xC "CKGR_PLLBR,PLLB Register"
|
|
bitfld.long 0xC 29.--30. "SRCB,PLLB Source Clock Selection" "0: MAINCK is the source clock of PLLB.,?,2: RC2CK is the source clock of PLLB.,?"
|
|
hexmask.long.word 0xC 16.--26. 1. "MULB,PLLB Multiplier"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "FREQ_VCO,VCO Frequency Configuration" "0: Frequency range: 40-80 MHz,1: Frequency range: 70-150 MHz,2: Frequency range: 125-275 MHz,3: Frequency range: 250-450 MHz"
|
|
hexmask.long.byte 0xC 8.--13. 1. "PLLBCOUNT,PLLB Counter"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "DIVB,PLLB Front End Divider"
|
|
line.long 0x10 "MCKR,Master Clock Register"
|
|
bitfld.long 0x10 13. "ZERO,Shall be always write at '0'" "0,1"
|
|
bitfld.long 0x10 8. "MDIV,Master Clock Division" "0: MCK is FCLK divided by 1.,1: MCK is FCLK divided by 2."
|
|
newline
|
|
bitfld.long 0x10 4.--6. "PRES,Processor Clock Prescaler" "0: Selected clock,1: Selected clock divided by 2,2: Selected clock divided by 4,3: Selected clock divided by 8,4: Selected clock divided by 16,5: Selected clock divided by 32,6: Selected clock divided by 64,?"
|
|
bitfld.long 0x10 0.--1. "CSS,Master Clock Source Selection" "0: MD_SLCK is selected,1: MAINCK is selected,2: PLLACK is selected,?"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "PCK[$1],Programmable Clock Register"
|
|
hexmask.long.byte 0x0 4.--11. 1. "PRES,Programmable Clock Prescaler"
|
|
bitfld.long 0x0 0.--2. "CSS,Programmable Clock Source Selection" "0: MD_SLCK is selected,1: MAINCK is selected,2: PLLACK is selected,3: PLLBCKDIV is selected,4: MCK is selected,?,?,?"
|
|
repeat.end
|
|
wgroup.long 0x60++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 23. "CPUMON,CPU Clock Monitor Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "EXT32KERR,32.768 kHz external slow clock Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CFDEV,Clock Failure Detector Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "MOSCRCS,Main RC Oscillator Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "PCKRDY3,Programmable Clock Ready 3 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "MCKRDY,Master Clock Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LOCKB,PLLB Lock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "LOCKA,PLLA Lock Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 23. "CPUMON,CPU Clock Monitor Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 21. "EXT32KERR,32.768 kHz external slow clock Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "CFDEV,Clock Failure Detector Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "MOSCRCS,Main RC Status Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 11. "PCKRDY3,Programmable Clock Ready 3 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "MCKRDY,Master Clock Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "LOCKB,PLLB Lock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "LOCKA,PLLA Lock Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Disable" "0,1"
|
|
rgroup.long 0x68++0x7
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 23. "CPUMON,CPU Clock Monitor Error" "0,1"
|
|
bitfld.long 0x0 21. "EXT32KERR,External Slow Clock Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "FOS,Clock Failure Detector Fault Output Status" "0,1"
|
|
bitfld.long 0x0 19. "CFDS,Clock Failure Detector Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CFDEV,Clock Failure Detector Event" "0,1"
|
|
bitfld.long 0x0 17. "MOSCRCS,Main RC Oscillator Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MOSCSELS,Main Clock Source Oscillator Selection Status" "0,1"
|
|
bitfld.long 0x0 11. "PCKRDY3,Programmable Clock Ready Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PCKRDY2,Programmable Clock Ready Status" "0,1"
|
|
bitfld.long 0x0 9. "PCKRDY1,Programmable Clock Ready Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PCKRDY0,Programmable Clock Ready Status" "0,1"
|
|
bitfld.long 0x0 7. "OSCSELS,Monitoring Domain Slow Clock Source Oscillator Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MCKRDY,Master Clock Status" "0,1"
|
|
bitfld.long 0x0 2. "LOCKB,PLLB Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCKA,PLLA Lock Status" "0,1"
|
|
bitfld.long 0x0 0. "MOSCXTS,Main Crystal Oscillator Status" "0,1"
|
|
line.long 0x4 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x4 23. "CPUMON,CPU Clock Monitor Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 21. "EXT32KERR,32.768 kHz Slow Clock Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "CFDEV,Clock Failure Detector Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 17. "MOSCRCS,Main RC Status Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 11. "PCKRDY3,Programmable Clock Ready 3 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 3. "MCKRDY,Master Clock Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "LOCKB,PLLB Lock Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "LOCKA,PLLA Lock Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Mask" "0,1"
|
|
wgroup.long 0x78++0x3
|
|
line.long 0x0 "FOCR,Fault Output Clear Register"
|
|
bitfld.long 0x0 0. "FOCLR,Fault Output Clear" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PLL_CFG,PLL Configuration Register"
|
|
bitfld.long 0x0 30.--31. "SRB,Internal Filter PLL - Select Internal Resistor Value" "0: 24 Ohms,1: 6 Ohms,2: 3 Ohms,3: 12 Ohms"
|
|
bitfld.long 0x0 28.--29. "SCB,Internal Filter PLL - Select Internal Capaticance Value" "0: 20 pF,1: 40 pF,2: 30 pF,3: 60 pF"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "OUTCUR_PLLB,PLLB Output Current"
|
|
bitfld.long 0x0 14.--15. "SRA,Internal Filter PLL - Select Internal Resistor Value" "0: 24 Ohms,1: 6 Ohms,2: 3 Ohms,3: 12 Ohms"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "SCA,Internal Filter PLL - Select Internal Capaticance Value" "0: 20 pF,1: 40 pF,2: 30 pF,3: 60 pF"
|
|
hexmask.long.byte 0x0 0.--3. 1. "OUTCUR_PLLA,PLLA Output Current"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
group.long 0x10C++0x7
|
|
line.long 0x0 "PCR,Peripheral Control Register"
|
|
bitfld.long 0x0 29. "GCLKEN,Generic Clock Enable" "0,1"
|
|
bitfld.long 0x0 28. "EN,Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--27. 1. "GCLKDIV,Generic Clock Division Ratio"
|
|
bitfld.long 0x0 12. "CMD,Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "GCLKCSS,Generic Clock Source Selection" "0: MD_SLCK is selected,1: MAINCK is selected,2: PLLACK is selected,3: PLLBCK is selected,4: MCK is selected,5: RC2 is selected,?,?"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PID,Peripheral ID"
|
|
line.long 0x4 "OCR1,Oscillator Calibration Register"
|
|
bitfld.long 0x4 31. "SEL12,Selection of Main RC Oscillator Calibration Bits for 12 MHz" "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. "CAL10,Main RC Oscillator Calibration Bits for 10 MHz"
|
|
newline
|
|
bitfld.long 0x4 23. "SEL10,Selection of Main RC Oscillator Calibration Bits for 10 MHz" "0,1"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CAL12,Main RC Oscillator Calibration Bits for 12 MHz"
|
|
newline
|
|
bitfld.long 0x4 15. "SEL8,Selection of Main RC Oscillator Calibration Bits for 8 MHz" "0,1"
|
|
hexmask.long.byte 0x4 8.--14. 1. "CAL8,Main RC Oscillator Calibration Bits for 8 MHz"
|
|
newline
|
|
bitfld.long 0x4 7. "SEL4,Selection of Main RC Oscillator Calibration Bits for 4 MHz" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CAL4,Main RC Oscillator Calibration Bits for 4 MHz"
|
|
group.long 0x130++0x3
|
|
line.long 0x0 "PMMR,PLL Maximum Multiplier Value Register"
|
|
hexmask.long.word 0x0 16.--26. 1. "PLLB_MMAX,PLLB Maximum Allowed Multiplier Value"
|
|
hexmask.long.word 0x0 0.--10. 1. "PLLA_MMAX,PLLA Maximum Allowed Multiplier Value"
|
|
group.long 0x160++0x3
|
|
line.long 0x0 "CPULIM,CPU Monitor Limits Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CPU_HIGH_RES,CPU Monitoring High Reset Limit"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CPU_LOW_RES,CPU Monitoring Low RESET Limit"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "CPU_HIGH_IT,CPU Monitoring High IT Limit"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPU_LOW_IT,CPU Monitoring Low IT Limit"
|
|
rgroup.long 0x170++0xF
|
|
line.long 0x0 "CSR0,Peripheral Clock Status Register 0"
|
|
bitfld.long 0x0 31. "PID31,Peripheral Clock 31 Status" "0,1"
|
|
bitfld.long 0x0 30. "PID30,Peripheral Clock 30 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "PID29,Peripheral Clock 29 Status" "0,1"
|
|
bitfld.long 0x0 28. "PID28,Peripheral Clock 28 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PID27,Peripheral Clock 27 Status" "0,1"
|
|
bitfld.long 0x0 26. "PID26,Peripheral Clock 26 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "PID25,Peripheral Clock 25 Status" "0,1"
|
|
bitfld.long 0x0 24. "PID24,Peripheral Clock 24 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PID23,Peripheral Clock 23 Status" "0,1"
|
|
bitfld.long 0x0 22. "PID22,Peripheral Clock 22 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PID14,Peripheral Clock 14 Status" "0,1"
|
|
bitfld.long 0x0 13. "PID13,Peripheral Clock 13 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PID10,Peripheral Clock 10 Status" "0,1"
|
|
bitfld.long 0x0 9. "PID9,Peripheral Clock 9 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PID8,Peripheral Clock 8 Status" "0,1"
|
|
bitfld.long 0x0 7. "PID7,Peripheral Clock 7 Status" "0,1"
|
|
line.long 0x4 "CSR1,Peripheral Clock Status Register 1"
|
|
bitfld.long 0x4 31. "PID63,Peripheral Clock 63 Status" "0,1"
|
|
bitfld.long 0x4 27. "PID59,Peripheral Clock 59 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "PID55,Peripheral Clock 55 Status" "0,1"
|
|
bitfld.long 0x4 22. "PID54,Peripheral Clock 54 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PID53,Peripheral Clock 53 Status" "0,1"
|
|
bitfld.long 0x4 18. "PID50,Peripheral Clock 50 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PID45,Peripheral Clock 45 Status" "0,1"
|
|
bitfld.long 0x4 12. "PID44,Peripheral Clock 44 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "PID38,Peripheral Clock 38 Status" "0,1"
|
|
bitfld.long 0x4 4. "PID36,Peripheral Clock 36 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PID33,Peripheral Clock 33 Status" "0,1"
|
|
bitfld.long 0x4 0. "PID32,Peripheral Clock 32 Status" "0,1"
|
|
line.long 0x8 "CSR2,Peripheral Clock Status Register 2"
|
|
bitfld.long 0x8 4. "PID68,Peripheral Clock 68 Status" "0,1"
|
|
bitfld.long 0x8 2. "PID66,Peripheral Clock 66 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "PID65,Peripheral Clock 65 Status" "0,1"
|
|
bitfld.long 0x8 0. "PID64,Peripheral Clock 64 Status" "0,1"
|
|
line.long 0xC "CSR3,Peripheral Clock Status Register 3"
|
|
rgroup.long 0x190++0xF
|
|
line.long 0x0 "GCSR0,Generic Clock Status Register 0"
|
|
bitfld.long 0x0 28. "GPID28,Generic Clock 28 Status" "0,1"
|
|
bitfld.long 0x0 25. "GPID25,Generic Clock 25 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "GPID23,Generic Clock 23 Status" "0,1"
|
|
bitfld.long 0x0 14. "GPID14,Generic Clock 14 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "GPID13,Generic Clock 13 Status" "0,1"
|
|
bitfld.long 0x0 9. "GPID9,Generic Clock 9 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "GPID8,Generic Clock 8 Status" "0,1"
|
|
bitfld.long 0x0 7. "GPID7,Generic Clock 7 Status" "0,1"
|
|
line.long 0x4 "GCSR1,Generic Clock Status Register 1"
|
|
bitfld.long 0x4 21. "GPID53,Generic Clock 53 Status" "0,1"
|
|
bitfld.long 0x4 18. "GPID50,Generic Clock 50 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "GPID38,Generic Clock 38 Status" "0,1"
|
|
bitfld.long 0x4 4. "GPID36,Generic Clock 36 Status" "0,1"
|
|
line.long 0x8 "GCSR2,Generic Clock Status Register 2"
|
|
bitfld.long 0x8 4. "GPID68,Generic Clock 68 Status" "0,1"
|
|
bitfld.long 0x8 2. "GPID66,Generic Clock 66 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "GPID65,Generic Clock 65 Status" "0,1"
|
|
line.long 0xC "GCSR3,Generic Clock Status Register 3"
|
|
group.long 0x1B0++0x7
|
|
line.long 0x0 "OSC2,Oscillator Control Register 2"
|
|
hexmask.long.byte 0x0 16.--23. 1. "KEY,Register Write Access Password"
|
|
bitfld.long 0x0 8. "EN_WR_CALIB,Enable Calibration Register Write" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "OSCRCF,2nd Oscillator Frequency Selection" "0: The 2nd RC oscillator frequency is at 4 MHz,1: The 2nd RC oscillator frequency is at 8 MHz,2: The 2nd RC oscillator frequency is at 10 MHz,3: The 2nd RC oscillator frequency is at 12 MHz"
|
|
bitfld.long 0x0 0. "EN,Enable" "0,1"
|
|
line.long 0x4 "OCR2,Oscillator Calibration Register 2"
|
|
bitfld.long 0x4 31. "SEL10,Selection of Main RC Oscillator Calibration Bits for 10 MHz" "0,1"
|
|
hexmask.long.byte 0x4 24.--30. 1. "CAL10,Main RC Oscillator Calibration Bits for 10 MHz"
|
|
newline
|
|
bitfld.long 0x4 23. "SEL12,Selection of Main RC Oscillator Calibration Bits for 12 MHz" "0,1"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CAL12,Main RC Oscillator Calibration Bits for 12 MHz"
|
|
newline
|
|
bitfld.long 0x4 15. "SEL8,Selection of Main RC Oscillator Calibration Bits for 8 MHz" "0,1"
|
|
hexmask.long.byte 0x4 8.--14. 1. "CAL8,Main RC Oscillator Calibration Bits for 8 MHz"
|
|
newline
|
|
bitfld.long 0x4 7. "SEL4,Selection of Main RC Oscillator Calibration Bits for 4 MHz" "0,1"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CAL4,Main RC Oscillator Calibration Bits for 4 MHz"
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Controller)"
|
|
base ad:0x0
|
|
tree "PWM0"
|
|
base ad:0x40068000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CLK,PWM Clock Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PREB,CLKB Source Clock Selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DIVB,CLKB Divide Factor"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "PREA,CLKA Source Clock Selection"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIVA,CLKA Divide Factor"
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "ENA,PWM Enable Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
line.long 0x4 "DIS,PWM Disable Register"
|
|
bitfld.long 0x4 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Channel ID" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,PWM Status Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER1,PWM Interrupt Enable Register 1"
|
|
bitfld.long 0x0 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CHID3,Counter Event on Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Counter Event on Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Counter Event on Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Counter Event on Channel 0 Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR1,PWM Interrupt Disable Register 1"
|
|
bitfld.long 0x4 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CHID3,Counter Event on Channel 3 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Counter Event on Channel 2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Counter Event on Channel 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Counter Event on Channel 0 Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR1,PWM Interrupt Mask Register 1"
|
|
bitfld.long 0x0 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CHID3,Counter Event on Channel 3 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Counter Event on Channel 2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Counter Event on Channel 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Counter Event on Channel 0 Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR1,PWM Interrupt Status Register 1"
|
|
bitfld.long 0x4 19. "FCHID3,Fault Protection Trigger on Channel 3" "0,1"
|
|
bitfld.long 0x4 18. "FCHID2,Fault Protection Trigger on Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FCHID1,Fault Protection Trigger on Channel 1" "0,1"
|
|
bitfld.long 0x4 16. "FCHID0,Fault Protection Trigger on Channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CHID3,Counter Event on Channel 3" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Counter Event on Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Counter Event on Channel 1" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Counter Event on Channel 0" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x0 21.--23. "PTRCS,DMA Controller Transfer Request Comparison Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20. "PTRM,DMA Controller Transfer Request Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "UPDM,Synchronous Channels Update Mode" "0: Manual write of double buffer registers and..,1: Manual write of double buffer registers and..,2: Automatic write of duty-cycle update registers..,?"
|
|
bitfld.long 0x0 3. "SYNC3,Synchronous Channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SYNC2,Synchronous Channel 2" "0,1"
|
|
bitfld.long 0x0 1. "SYNC1,Synchronous Channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SYNC0,Synchronous Channel 0" "0,1"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "DMAR,PWM DMA Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DMADUTY,Duty-Cycle Holding Register for DMA Access"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SCUC,PWM Sync Channels Update Control Register"
|
|
bitfld.long 0x0 0. "UPDULOCK,Synchronous Channels Update Unlock" "0,1"
|
|
line.long 0x4 "SCUP,PWM Sync Channels Update Period Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "UPRCNT,Update Period Counter"
|
|
hexmask.long.byte 0x4 0.--3. 1. "UPR,Update Period"
|
|
wgroup.long 0x30++0xB
|
|
line.long 0x0 "SCUPUPD,PWM Sync Channels Update Period Update Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "UPRUPD,Update Period Update"
|
|
line.long 0x4 "IER2,PWM Interrupt Enable Register 2"
|
|
bitfld.long 0x4 23. "CMPU7,Comparison 7 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "CMPU6,Comparison 6 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CMPU5,Comparison 5 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "CMPU4,Comparison 4 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CMPU3,Comparison 3 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "CMPU2,Comparison 2 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CMPU1,Comparison 1 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "CMPU0,Comparison 0 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CMPM7,Comparison 7 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "CMPM6,Comparison 6 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CMPM5,Comparison 5 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "CMPM4,Comparison 4 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMPM3,Comparison 3 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "CMPM2,Comparison 2 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CMPM1,Comparison 1 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "CMPM0,Comparison 0 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Enable" "0,1"
|
|
line.long 0x8 "IDR2,PWM Interrupt Disable Register 2"
|
|
bitfld.long 0x8 23. "CMPU7,Comparison 7 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 22. "CMPU6,Comparison 6 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "CMPU5,Comparison 5 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 20. "CMPU4,Comparison 4 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "CMPU3,Comparison 3 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 18. "CMPU2,Comparison 2 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "CMPU1,Comparison 1 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 16. "CMPU0,Comparison 0 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "CMPM7,Comparison 7 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 14. "CMPM6,Comparison 6 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "CMPM5,Comparison 5 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 12. "CMPM4,Comparison 4 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "CMPM3,Comparison 3 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 10. "CMPM2,Comparison 2 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "CMPM1,Comparison 1 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 8. "CMPM0,Comparison 0 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Disable" "0,1"
|
|
rgroup.long 0x3C++0x7
|
|
line.long 0x0 "IMR2,PWM Interrupt Mask Register 2"
|
|
bitfld.long 0x0 23. "CMPU7,Comparison 7 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "CMPU6,Comparison 6 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CMPU5,Comparison 5 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "CMPU4,Comparison 4 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CMPU3,Comparison 3 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "CMPU2,Comparison 2 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMPU1,Comparison 1 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "CMPU0,Comparison 0 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CMPM7,Comparison 7 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "CMPM6,Comparison 6 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CMPM5,Comparison 5 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "CMPM4,Comparison 4 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMPM3,Comparison 3 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "CMPM2,Comparison 2 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CMPM1,Comparison 1 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "CMPM0,Comparison 0 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR2,PWM Interrupt Status Register 2"
|
|
bitfld.long 0x4 23. "CMPU7,Comparison 7 Update" "0,1"
|
|
bitfld.long 0x4 22. "CMPU6,Comparison 6 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CMPU5,Comparison 5 Update" "0,1"
|
|
bitfld.long 0x4 20. "CMPU4,Comparison 4 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CMPU3,Comparison 3 Update" "0,1"
|
|
bitfld.long 0x4 18. "CMPU2,Comparison 2 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CMPU1,Comparison 1 Update" "0,1"
|
|
bitfld.long 0x4 16. "CMPU0,Comparison 0 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CMPM7,Comparison 7 Match" "0,1"
|
|
bitfld.long 0x4 14. "CMPM6,Comparison 6 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CMPM5,Comparison 5 Match" "0,1"
|
|
bitfld.long 0x4 12. "CMPM4,Comparison 4 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMPM3,Comparison 3 Match" "0,1"
|
|
bitfld.long 0x4 10. "CMPM2,Comparison 2 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CMPM1,Comparison 1 Match" "0,1"
|
|
bitfld.long 0x4 8. "CMPM0,Comparison 0 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UNRE,Synchronous Channels Update Underrun Error" "0,1"
|
|
bitfld.long 0x4 0. "WRDY,Write Ready for Synchronous Channels Update" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "OOV,PWM Output Override Value Register"
|
|
bitfld.long 0x0 19. "OOVL3,Output Override Value for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x0 18. "OOVL2,Output Override Value for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "OOVL1,Output Override Value for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x0 16. "OOVL0,Output Override Value for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OOVH3,Output Override Value for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x0 2. "OOVH2,Output Override Value for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OOVH1,Output Override Value for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x0 0. "OOVH0,Output Override Value for PWMH output of the channel 0" "0,1"
|
|
line.long 0x4 "OS,PWM Output Selection Register"
|
|
bitfld.long 0x4 19. "OSL3,Output Selection for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x4 18. "OSL2,Output Selection for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "OSL1,Output Selection for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x4 16. "OSL0,Output Selection for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OSH3,Output Selection for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x4 2. "OSH2,Output Selection for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OSH1,Output Selection for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x4 0. "OSH0,Output Selection for PWMH output of the channel 0" "0,1"
|
|
wgroup.long 0x4C++0xF
|
|
line.long 0x0 "OSS,PWM Output Selection Set Register"
|
|
bitfld.long 0x0 19. "OSSL3,Output Selection Set for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x0 18. "OSSL2,Output Selection Set for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "OSSL1,Output Selection Set for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x0 16. "OSSL0,Output Selection Set for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OSSH3,Output Selection Set for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x0 2. "OSSH2,Output Selection Set for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OSSH1,Output Selection Set for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x0 0. "OSSH0,Output Selection Set for PWMH output of the channel 0" "0,1"
|
|
line.long 0x4 "OSC,PWM Output Selection Clear Register"
|
|
bitfld.long 0x4 19. "OSCL3,Output Selection Clear for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x4 18. "OSCL2,Output Selection Clear for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "OSCL1,Output Selection Clear for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x4 16. "OSCL0,Output Selection Clear for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OSCH3,Output Selection Clear for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x4 2. "OSCH2,Output Selection Clear for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OSCH1,Output Selection Clear for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x4 0. "OSCH0,Output Selection Clear for PWMH output of the channel 0" "0,1"
|
|
line.long 0x8 "OSSUPD,PWM Output Selection Set Update Register"
|
|
bitfld.long 0x8 19. "OSSUPL3,Output Selection Set for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x8 18. "OSSUPL2,Output Selection Set for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "OSSUPL1,Output Selection Set for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x8 16. "OSSUPL0,Output Selection Set for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OSSUPH3,Output Selection Set for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x8 2. "OSSUPH2,Output Selection Set for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OSSUPH1,Output Selection Set for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x8 0. "OSSUPH0,Output Selection Set for PWMH output of the channel 0" "0,1"
|
|
line.long 0xC "OSCUPD,PWM Output Selection Clear Update Register"
|
|
bitfld.long 0xC 19. "OSCUPL3,Output Selection Clear for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0xC 18. "OSCUPL2,Output Selection Clear for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "OSCUPL1,Output Selection Clear for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0xC 16. "OSCUPL0,Output Selection Clear for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OSCUPH3,Output Selection Clear for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0xC 2. "OSCUPH2,Output Selection Clear for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OSCUPH1,Output Selection Clear for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0xC 0. "OSCUPH0,Output Selection Clear for PWMH output of the channel 0" "0,1"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "FMR,PWM Fault Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FFIL,Fault Filtering"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FMOD,Fault Activation Mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "FPOL,Fault Polarity"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "FSR,PWM Fault Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FS,Fault Status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FIV,Fault Input Value"
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x0 "FCR,PWM Fault Clear Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FCLR,Fault Clear"
|
|
group.long 0x68++0x7
|
|
line.long 0x0 "FPV1,PWM Fault Protection Value Register 1"
|
|
bitfld.long 0x0 19. "FPVL3,Fault Protection Value for PWML output on channel 3" "0,1"
|
|
bitfld.long 0x0 18. "FPVL2,Fault Protection Value for PWML output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FPVL1,Fault Protection Value for PWML output on channel 1" "0,1"
|
|
bitfld.long 0x0 16. "FPVL0,Fault Protection Value for PWML output on channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FPVH3,Fault Protection Value for PWMH output on channel 3" "0,1"
|
|
bitfld.long 0x0 2. "FPVH2,Fault Protection Value for PWMH output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FPVH1,Fault Protection Value for PWMH output on channel 1" "0,1"
|
|
bitfld.long 0x0 0. "FPVH0,Fault Protection Value for PWMH output on channel 0" "0,1"
|
|
line.long 0x4 "FPE,PWM Fault Protection Enable Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "FPE3,Fault Protection Enable for channel 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FPE2,Fault Protection Enable for channel 2"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "FPE1,Fault Protection Enable for channel 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "FPE0,Fault Protection Enable for channel 0"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x7C)++0x3
|
|
line.long 0x0 "ELMR[$1],PWM Event Line 0 Mode Register"
|
|
bitfld.long 0x0 7. "CSEL7,Comparison 7 Selection" "0,1"
|
|
bitfld.long 0x0 6. "CSEL6,Comparison 6 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CSEL5,Comparison 5 Selection" "0,1"
|
|
bitfld.long 0x0 4. "CSEL4,Comparison 4 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CSEL3,Comparison 3 Selection" "0,1"
|
|
bitfld.long 0x0 2. "CSEL2,Comparison 2 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CSEL1,Comparison 1 Selection" "0,1"
|
|
bitfld.long 0x0 0. "CSEL0,Comparison 0 Selection" "0,1"
|
|
repeat.end
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "SSPR,PWM Spread Spectrum Register"
|
|
bitfld.long 0x0 24. "SPRDM,Spread Spectrum Counter Mode" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "SPRD,Spread Spectrum Limit Value"
|
|
wgroup.long 0xA4++0x3
|
|
line.long 0x0 "SSPUP,PWM Spread Spectrum Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "SPRDUP,Spread Spectrum Limit Value Update"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "SMMR,PWM Stepper Motor Mode Register"
|
|
bitfld.long 0x0 17. "DOWN1,Down Count" "0,1"
|
|
bitfld.long 0x0 16. "DOWN0,Down Count" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GCEN1,Gray Count Enable" "0,1"
|
|
bitfld.long 0x0 0. "GCEN0,Gray Count Enable" "0,1"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FPV2,PWM Fault Protection Value 2 Register"
|
|
bitfld.long 0x0 19. "FPZL3,Fault Protection to Hi-Z for PWML output on channel 3" "0,1"
|
|
bitfld.long 0x0 18. "FPZL2,Fault Protection to Hi-Z for PWML output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FPZL1,Fault Protection to Hi-Z for PWML output on channel 1" "0,1"
|
|
bitfld.long 0x0 16. "FPZL0,Fault Protection to Hi-Z for PWML output on channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FPZH3,Fault Protection to Hi-Z for PWMH output on channel 3" "0,1"
|
|
bitfld.long 0x0 2. "FPZH2,Fault Protection to Hi-Z for PWMH output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FPZH1,Fault Protection to Hi-Z for PWMH output on channel 1" "0,1"
|
|
bitfld.long 0x0 0. "FPZH0,Fault Protection to Hi-Z for PWMH output on channel 0" "0,1"
|
|
wgroup.long 0xE4++0x3
|
|
line.long 0x0 "WPCR,PWM Write Protection Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "WPRG5,Write Protection Register Group 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "WPRG4,Write Protection Register Group 4" "0,1"
|
|
bitfld.long 0x0 5. "WPRG3,Write Protection Register Group 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "WPRG2,Write Protection Register Group 2" "0,1"
|
|
bitfld.long 0x0 3. "WPRG1,Write Protection Register Group 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WPRG0,Write Protection Register Group 0" "0,1"
|
|
bitfld.long 0x0 0.--1. "WPCMD,Write Protection Command" "0: Disables the software write protection of the..,1: Enables the software write protection of the..,2: Enables the hardware write protection of the..,?"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,PWM Write Protection Status Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WPVSRC,Write Protect Violation Source"
|
|
bitfld.long 0x0 13. "WPHWS5,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "WPHWS4,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 11. "WPHWS3,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WPHWS2,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 9. "WPHWS1,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "WPHWS0,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 7. "WPVS,Write Protect Violation Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WPSWS5,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 4. "WPSWS4,Write Protect SW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "WPSWS3,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 2. "WPSWS2,Write Protect SW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPSWS1,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 0. "WPSWS0,Write Protect SW Status" "0,1"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40068130 ad:0x40068140 ad:0x40068150 ad:0x40068160 ad:0x40068170 ad:0x40068180 ad:0x40068190 ad:0x400681A0)
|
|
tree "PWM_CMP[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CMPV,PWM Comparison Value Register"
|
|
bitfld.long 0x0 24. "CVM,Comparison x Value Mode" "0: Compare when counter is incrementing,1: Compare when counter is decrementing"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CV,Comparison x Value"
|
|
wgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMPVUPD,PWM Comparison Value Update Register"
|
|
bitfld.long 0x0 24. "CVMUPD,Comparison x Value Mode Update" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CVUPD,Comparison x Value Update"
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "CMPM,PWM Comparison Mode Register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CUPRCNT,Comparison x Update Period Counter"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CUPR,Comparison x Update Period"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CPRCNT,Comparison x Period Counter"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CPR,Comparison x Period"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CTR,Comparison x Trigger"
|
|
bitfld.long 0x0 0. "CEN,Comparison x Enable" "0,1"
|
|
wgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "CMPMUPD,PWM Comparison Mode Update Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CUPRUPD,Comparison x Update Period Update"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CPRUPD,Comparison x Period Update"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CTRUPD,Comparison x Trigger Update"
|
|
bitfld.long 0x0 0. "CENUPD,Comparison x Enable Update" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40068200 ad:0x40068220 ad:0x40068240 ad:0x40068260)
|
|
tree "PWM_CH_NUM[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "CMR,PWM Channel Mode Register"
|
|
bitfld.long 0x0 19. "PPM,Push-Pull Mode" "0,1"
|
|
bitfld.long 0x0 18. "DTLI,Dead-Time PWMLx Output Inverted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DTHI,Dead-Time PWMHx Output Inverted" "0,1"
|
|
bitfld.long 0x0 16. "DTE,Dead-Time Generator Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCTS,Timer Counter Trigger Selection" "0,1"
|
|
bitfld.long 0x0 12. "DPOLI,Disabled Polarity Inverted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "UPDS,Update Selection" "0: At the next end of PWM period,1: At the next end of Half PWM period"
|
|
bitfld.long 0x0 10. "CES,Counter Event Selection" "0: At the end of PWM period,1: At half of PWM period AND at the end of PWM period"
|
|
newline
|
|
bitfld.long 0x0 9. "CPOL,Channel Polarity" "0: Waveform starts at low level,1: Waveform starts at high level"
|
|
bitfld.long 0x0 8. "CALG,Channel Alignment" "0: Left aligned,1: Center aligned"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CPRE,Channel Prescaler"
|
|
line.long 0x4 "CDTY,PWM Channel Duty Cycle Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CDTY,Channel Duty-Cycle"
|
|
wgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "CDTYUPD,PWM Channel Duty Cycle Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CDTYUPD,Channel Duty-Cycle Update"
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "CPRD,PWM Channel Period Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CPRD,Channel Period"
|
|
wgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "CPRDUPD,PWM Channel Period Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CPRDUPD,Channel Period Update"
|
|
rgroup.long ($2+0x14)++0x3
|
|
line.long 0x0 "CCNT,PWM Channel Counter Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Channel Counter Register"
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "DT,PWM Channel Dead Time Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DTL,Dead-Time Value for PWMLx Output"
|
|
hexmask.long.word 0x0 0.--15. 1. "DTH,Dead-Time Value for PWMHx Output"
|
|
wgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "DTUPD,PWM Channel Dead Time Update Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DTLUPD,Dead-Time Value Update for PWMLx Output"
|
|
hexmask.long.word 0x0 0.--15. 1. "DTHUPD,Dead-Time Value Update for PWMHx Output"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40068000
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "CMUPD0,PWM Channel Mode Update Register (ch_num = 0)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
wgroup.long 0x420++0x3
|
|
line.long 0x0 "CMUPD1,PWM Channel Mode Update Register (ch_num = 1)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
group.long 0x42C++0x7
|
|
line.long 0x0 "ETRG1,PWM External Trigger Register (trg_num = 1)"
|
|
bitfld.long 0x0 31. "RFEN,Recoverable Fault Enable" "0,1"
|
|
bitfld.long 0x0 30. "TRGSRC,Trigger Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRGFILT,Filtered input" "0,1"
|
|
bitfld.long 0x0 28. "TRGEDGE,Edge Selection" "0: TRGMODE = 1: TRGINx event detection on falling..,1: TRGMODE = 1: TRGINx event detection on rising.."
|
|
newline
|
|
bitfld.long 0x0 24.--25. "TRGMODE,External Trigger Mode" "0: External trigger is not enabled.,1: External PWM Reset Mode,2: External PWM Start Mode,3: Cycle-by-cycle Duty Mode"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "MAXCNT,Maximum Counter value"
|
|
line.long 0x4 "LEBR1,PWM Leading-Edge Blanking Register (trg_num = 1)"
|
|
bitfld.long 0x4 19. "PWMHREN,PWMH Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 18. "PWMHFEN,PWMH Falling Edge Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PWMLREN,PWML Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 16. "PWMLFEN,PWML Falling Edge Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "LEBDELAY,Leading-Edge Blanking Delay for TRGINx"
|
|
wgroup.long 0x440++0x3
|
|
line.long 0x0 "CMUPD2,PWM Channel Mode Update Register (ch_num = 2)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
group.long 0x44C++0x7
|
|
line.long 0x0 "ETRG2,PWM External Trigger Register (trg_num = 2)"
|
|
bitfld.long 0x0 31. "RFEN,Recoverable Fault Enable" "0,1"
|
|
bitfld.long 0x0 30. "TRGSRC,Trigger Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRGFILT,Filtered input" "0,1"
|
|
bitfld.long 0x0 28. "TRGEDGE,Edge Selection" "0: TRGMODE = 1: TRGINx event detection on falling..,1: TRGMODE = 1: TRGINx event detection on rising.."
|
|
newline
|
|
bitfld.long 0x0 24.--25. "TRGMODE,External Trigger Mode" "0: External trigger is not enabled.,1: External PWM Reset Mode,2: External PWM Start Mode,3: Cycle-by-cycle Duty Mode"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "MAXCNT,Maximum Counter value"
|
|
line.long 0x4 "LEBR2,PWM Leading-Edge Blanking Register (trg_num = 2)"
|
|
bitfld.long 0x4 19. "PWMHREN,PWMH Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 18. "PWMHFEN,PWMH Falling Edge Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PWMLREN,PWML Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 16. "PWMLFEN,PWML Falling Edge Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "LEBDELAY,Leading-Edge Blanking Delay for TRGINx"
|
|
wgroup.long 0x460++0x3
|
|
line.long 0x0 "CMUPD3,PWM Channel Mode Update Register (ch_num = 3)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
tree.end
|
|
tree "PWM1"
|
|
base ad:0x4006C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CLK,PWM Clock Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PREB,CLKB Source Clock Selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DIVB,CLKB Divide Factor"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "PREA,CLKA Source Clock Selection"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIVA,CLKA Divide Factor"
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "ENA,PWM Enable Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
line.long 0x4 "DIS,PWM Disable Register"
|
|
bitfld.long 0x4 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Channel ID" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,PWM Status Register"
|
|
bitfld.long 0x0 3. "CHID3,Channel ID" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER1,PWM Interrupt Enable Register 1"
|
|
bitfld.long 0x0 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CHID3,Counter Event on Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Counter Event on Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Counter Event on Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Counter Event on Channel 0 Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR1,PWM Interrupt Disable Register 1"
|
|
bitfld.long 0x4 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CHID3,Counter Event on Channel 3 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Counter Event on Channel 2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Counter Event on Channel 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Counter Event on Channel 0 Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR1,PWM Interrupt Mask Register 1"
|
|
bitfld.long 0x0 19. "FCHID3,Fault Protection Trigger on Channel 3 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CHID3,Counter Event on Channel 3 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Counter Event on Channel 2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Counter Event on Channel 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Counter Event on Channel 0 Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR1,PWM Interrupt Status Register 1"
|
|
bitfld.long 0x4 19. "FCHID3,Fault Protection Trigger on Channel 3" "0,1"
|
|
bitfld.long 0x4 18. "FCHID2,Fault Protection Trigger on Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "FCHID1,Fault Protection Trigger on Channel 1" "0,1"
|
|
bitfld.long 0x4 16. "FCHID0,Fault Protection Trigger on Channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CHID3,Counter Event on Channel 3" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Counter Event on Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Counter Event on Channel 1" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Counter Event on Channel 0" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x0 21.--23. "PTRCS,DMA Controller Transfer Request Comparison Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20. "PTRM,DMA Controller Transfer Request Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "UPDM,Synchronous Channels Update Mode" "0: Manual write of double buffer registers and..,1: Manual write of double buffer registers and..,2: Automatic write of duty-cycle update registers..,?"
|
|
bitfld.long 0x0 3. "SYNC3,Synchronous Channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SYNC2,Synchronous Channel 2" "0,1"
|
|
bitfld.long 0x0 1. "SYNC1,Synchronous Channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SYNC0,Synchronous Channel 0" "0,1"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "DMAR,PWM DMA Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "DMADUTY,Duty-Cycle Holding Register for DMA Access"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SCUC,PWM Sync Channels Update Control Register"
|
|
bitfld.long 0x0 0. "UPDULOCK,Synchronous Channels Update Unlock" "0,1"
|
|
line.long 0x4 "SCUP,PWM Sync Channels Update Period Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "UPRCNT,Update Period Counter"
|
|
hexmask.long.byte 0x4 0.--3. 1. "UPR,Update Period"
|
|
wgroup.long 0x30++0xB
|
|
line.long 0x0 "SCUPUPD,PWM Sync Channels Update Period Update Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "UPRUPD,Update Period Update"
|
|
line.long 0x4 "IER2,PWM Interrupt Enable Register 2"
|
|
bitfld.long 0x4 23. "CMPU7,Comparison 7 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "CMPU6,Comparison 6 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CMPU5,Comparison 5 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "CMPU4,Comparison 4 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CMPU3,Comparison 3 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "CMPU2,Comparison 2 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CMPU1,Comparison 1 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "CMPU0,Comparison 0 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CMPM7,Comparison 7 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "CMPM6,Comparison 6 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CMPM5,Comparison 5 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "CMPM4,Comparison 4 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMPM3,Comparison 3 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "CMPM2,Comparison 2 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CMPM1,Comparison 1 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "CMPM0,Comparison 0 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Enable" "0,1"
|
|
line.long 0x8 "IDR2,PWM Interrupt Disable Register 2"
|
|
bitfld.long 0x8 23. "CMPU7,Comparison 7 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 22. "CMPU6,Comparison 6 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "CMPU5,Comparison 5 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 20. "CMPU4,Comparison 4 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "CMPU3,Comparison 3 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 18. "CMPU2,Comparison 2 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "CMPU1,Comparison 1 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 16. "CMPU0,Comparison 0 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "CMPM7,Comparison 7 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 14. "CMPM6,Comparison 6 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "CMPM5,Comparison 5 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 12. "CMPM4,Comparison 4 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "CMPM3,Comparison 3 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 10. "CMPM2,Comparison 2 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "CMPM1,Comparison 1 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 8. "CMPM0,Comparison 0 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Disable" "0,1"
|
|
rgroup.long 0x3C++0x7
|
|
line.long 0x0 "IMR2,PWM Interrupt Mask Register 2"
|
|
bitfld.long 0x0 23. "CMPU7,Comparison 7 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "CMPU6,Comparison 6 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CMPU5,Comparison 5 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "CMPU4,Comparison 4 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CMPU3,Comparison 3 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "CMPU2,Comparison 2 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMPU1,Comparison 1 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "CMPU0,Comparison 0 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CMPM7,Comparison 7 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "CMPM6,Comparison 6 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CMPM5,Comparison 5 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "CMPM4,Comparison 4 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMPM3,Comparison 3 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "CMPM2,Comparison 2 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CMPM1,Comparison 1 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "CMPM0,Comparison 0 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR2,PWM Interrupt Status Register 2"
|
|
bitfld.long 0x4 23. "CMPU7,Comparison 7 Update" "0,1"
|
|
bitfld.long 0x4 22. "CMPU6,Comparison 6 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CMPU5,Comparison 5 Update" "0,1"
|
|
bitfld.long 0x4 20. "CMPU4,Comparison 4 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CMPU3,Comparison 3 Update" "0,1"
|
|
bitfld.long 0x4 18. "CMPU2,Comparison 2 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CMPU1,Comparison 1 Update" "0,1"
|
|
bitfld.long 0x4 16. "CMPU0,Comparison 0 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CMPM7,Comparison 7 Match" "0,1"
|
|
bitfld.long 0x4 14. "CMPM6,Comparison 6 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CMPM5,Comparison 5 Match" "0,1"
|
|
bitfld.long 0x4 12. "CMPM4,Comparison 4 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMPM3,Comparison 3 Match" "0,1"
|
|
bitfld.long 0x4 10. "CMPM2,Comparison 2 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CMPM1,Comparison 1 Match" "0,1"
|
|
bitfld.long 0x4 8. "CMPM0,Comparison 0 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UNRE,Synchronous Channels Update Underrun Error" "0,1"
|
|
bitfld.long 0x4 0. "WRDY,Write Ready for Synchronous Channels Update" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "OOV,PWM Output Override Value Register"
|
|
bitfld.long 0x0 19. "OOVL3,Output Override Value for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x0 18. "OOVL2,Output Override Value for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "OOVL1,Output Override Value for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x0 16. "OOVL0,Output Override Value for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OOVH3,Output Override Value for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x0 2. "OOVH2,Output Override Value for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OOVH1,Output Override Value for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x0 0. "OOVH0,Output Override Value for PWMH output of the channel 0" "0,1"
|
|
line.long 0x4 "OS,PWM Output Selection Register"
|
|
bitfld.long 0x4 19. "OSL3,Output Selection for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x4 18. "OSL2,Output Selection for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "OSL1,Output Selection for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x4 16. "OSL0,Output Selection for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OSH3,Output Selection for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x4 2. "OSH2,Output Selection for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OSH1,Output Selection for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x4 0. "OSH0,Output Selection for PWMH output of the channel 0" "0,1"
|
|
wgroup.long 0x4C++0xF
|
|
line.long 0x0 "OSS,PWM Output Selection Set Register"
|
|
bitfld.long 0x0 19. "OSSL3,Output Selection Set for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x0 18. "OSSL2,Output Selection Set for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "OSSL1,Output Selection Set for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x0 16. "OSSL0,Output Selection Set for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OSSH3,Output Selection Set for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x0 2. "OSSH2,Output Selection Set for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OSSH1,Output Selection Set for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x0 0. "OSSH0,Output Selection Set for PWMH output of the channel 0" "0,1"
|
|
line.long 0x4 "OSC,PWM Output Selection Clear Register"
|
|
bitfld.long 0x4 19. "OSCL3,Output Selection Clear for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x4 18. "OSCL2,Output Selection Clear for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "OSCL1,Output Selection Clear for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x4 16. "OSCL0,Output Selection Clear for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OSCH3,Output Selection Clear for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x4 2. "OSCH2,Output Selection Clear for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OSCH1,Output Selection Clear for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x4 0. "OSCH0,Output Selection Clear for PWMH output of the channel 0" "0,1"
|
|
line.long 0x8 "OSSUPD,PWM Output Selection Set Update Register"
|
|
bitfld.long 0x8 19. "OSSUPL3,Output Selection Set for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0x8 18. "OSSUPL2,Output Selection Set for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "OSSUPL1,Output Selection Set for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0x8 16. "OSSUPL0,Output Selection Set for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "OSSUPH3,Output Selection Set for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0x8 2. "OSSUPH2,Output Selection Set for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OSSUPH1,Output Selection Set for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x8 0. "OSSUPH0,Output Selection Set for PWMH output of the channel 0" "0,1"
|
|
line.long 0xC "OSCUPD,PWM Output Selection Clear Update Register"
|
|
bitfld.long 0xC 19. "OSCUPL3,Output Selection Clear for PWML output of the channel 3" "0,1"
|
|
bitfld.long 0xC 18. "OSCUPL2,Output Selection Clear for PWML output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "OSCUPL1,Output Selection Clear for PWML output of the channel 1" "0,1"
|
|
bitfld.long 0xC 16. "OSCUPL0,Output Selection Clear for PWML output of the channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "OSCUPH3,Output Selection Clear for PWMH output of the channel 3" "0,1"
|
|
bitfld.long 0xC 2. "OSCUPH2,Output Selection Clear for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OSCUPH1,Output Selection Clear for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0xC 0. "OSCUPH0,Output Selection Clear for PWMH output of the channel 0" "0,1"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "FMR,PWM Fault Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FFIL,Fault Filtering"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FMOD,Fault Activation Mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "FPOL,Fault Polarity"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "FSR,PWM Fault Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FS,Fault Status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FIV,Fault Input Value"
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x0 "FCR,PWM Fault Clear Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FCLR,Fault Clear"
|
|
group.long 0x68++0x7
|
|
line.long 0x0 "FPV1,PWM Fault Protection Value Register 1"
|
|
bitfld.long 0x0 19. "FPVL3,Fault Protection Value for PWML output on channel 3" "0,1"
|
|
bitfld.long 0x0 18. "FPVL2,Fault Protection Value for PWML output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FPVL1,Fault Protection Value for PWML output on channel 1" "0,1"
|
|
bitfld.long 0x0 16. "FPVL0,Fault Protection Value for PWML output on channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FPVH3,Fault Protection Value for PWMH output on channel 3" "0,1"
|
|
bitfld.long 0x0 2. "FPVH2,Fault Protection Value for PWMH output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FPVH1,Fault Protection Value for PWMH output on channel 1" "0,1"
|
|
bitfld.long 0x0 0. "FPVH0,Fault Protection Value for PWMH output on channel 0" "0,1"
|
|
line.long 0x4 "FPE,PWM Fault Protection Enable Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "FPE3,Fault Protection Enable for channel 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FPE2,Fault Protection Enable for channel 2"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "FPE1,Fault Protection Enable for channel 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "FPE0,Fault Protection Enable for channel 0"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x7C)++0x3
|
|
line.long 0x0 "ELMR[$1],PWM Event Line 0 Mode Register"
|
|
bitfld.long 0x0 7. "CSEL7,Comparison 7 Selection" "0,1"
|
|
bitfld.long 0x0 6. "CSEL6,Comparison 6 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CSEL5,Comparison 5 Selection" "0,1"
|
|
bitfld.long 0x0 4. "CSEL4,Comparison 4 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CSEL3,Comparison 3 Selection" "0,1"
|
|
bitfld.long 0x0 2. "CSEL2,Comparison 2 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CSEL1,Comparison 1 Selection" "0,1"
|
|
bitfld.long 0x0 0. "CSEL0,Comparison 0 Selection" "0,1"
|
|
repeat.end
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "SSPR,PWM Spread Spectrum Register"
|
|
bitfld.long 0x0 24. "SPRDM,Spread Spectrum Counter Mode" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "SPRD,Spread Spectrum Limit Value"
|
|
wgroup.long 0xA4++0x3
|
|
line.long 0x0 "SSPUP,PWM Spread Spectrum Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "SPRDUP,Spread Spectrum Limit Value Update"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "SMMR,PWM Stepper Motor Mode Register"
|
|
bitfld.long 0x0 17. "DOWN1,Down Count" "0,1"
|
|
bitfld.long 0x0 16. "DOWN0,Down Count" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GCEN1,Gray Count Enable" "0,1"
|
|
bitfld.long 0x0 0. "GCEN0,Gray Count Enable" "0,1"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FPV2,PWM Fault Protection Value 2 Register"
|
|
bitfld.long 0x0 19. "FPZL3,Fault Protection to Hi-Z for PWML output on channel 3" "0,1"
|
|
bitfld.long 0x0 18. "FPZL2,Fault Protection to Hi-Z for PWML output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "FPZL1,Fault Protection to Hi-Z for PWML output on channel 1" "0,1"
|
|
bitfld.long 0x0 16. "FPZL0,Fault Protection to Hi-Z for PWML output on channel 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FPZH3,Fault Protection to Hi-Z for PWMH output on channel 3" "0,1"
|
|
bitfld.long 0x0 2. "FPZH2,Fault Protection to Hi-Z for PWMH output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FPZH1,Fault Protection to Hi-Z for PWMH output on channel 1" "0,1"
|
|
bitfld.long 0x0 0. "FPZH0,Fault Protection to Hi-Z for PWMH output on channel 0" "0,1"
|
|
wgroup.long 0xE4++0x3
|
|
line.long 0x0 "WPCR,PWM Write Protection Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "WPRG5,Write Protection Register Group 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "WPRG4,Write Protection Register Group 4" "0,1"
|
|
bitfld.long 0x0 5. "WPRG3,Write Protection Register Group 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "WPRG2,Write Protection Register Group 2" "0,1"
|
|
bitfld.long 0x0 3. "WPRG1,Write Protection Register Group 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WPRG0,Write Protection Register Group 0" "0,1"
|
|
bitfld.long 0x0 0.--1. "WPCMD,Write Protection Command" "0: Disables the software write protection of the..,1: Enables the software write protection of the..,2: Enables the hardware write protection of the..,?"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,PWM Write Protection Status Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WPVSRC,Write Protect Violation Source"
|
|
bitfld.long 0x0 13. "WPHWS5,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "WPHWS4,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 11. "WPHWS3,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WPHWS2,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 9. "WPHWS1,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "WPHWS0,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 7. "WPVS,Write Protect Violation Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WPSWS5,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 4. "WPSWS4,Write Protect SW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "WPSWS3,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 2. "WPSWS2,Write Protect SW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPSWS1,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 0. "WPSWS0,Write Protect SW Status" "0,1"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x4006C130 ad:0x4006C140 ad:0x4006C150 ad:0x4006C160 ad:0x4006C170 ad:0x4006C180 ad:0x4006C190 ad:0x4006C1A0)
|
|
tree "PWM_CMP[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CMPV,PWM Comparison Value Register"
|
|
bitfld.long 0x0 24. "CVM,Comparison x Value Mode" "0: Compare when counter is incrementing,1: Compare when counter is decrementing"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CV,Comparison x Value"
|
|
wgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMPVUPD,PWM Comparison Value Update Register"
|
|
bitfld.long 0x0 24. "CVMUPD,Comparison x Value Mode Update" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CVUPD,Comparison x Value Update"
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "CMPM,PWM Comparison Mode Register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CUPRCNT,Comparison x Update Period Counter"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CUPR,Comparison x Update Period"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CPRCNT,Comparison x Period Counter"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CPR,Comparison x Period"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CTR,Comparison x Trigger"
|
|
bitfld.long 0x0 0. "CEN,Comparison x Enable" "0,1"
|
|
wgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "CMPMUPD,PWM Comparison Mode Update Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CUPRUPD,Comparison x Update Period Update"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CPRUPD,Comparison x Period Update"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CTRUPD,Comparison x Trigger Update"
|
|
bitfld.long 0x0 0. "CENUPD,Comparison x Enable Update" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4006C200 ad:0x4006C220 ad:0x4006C240 ad:0x4006C260)
|
|
tree "PWM_CH_NUM[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "CMR,PWM Channel Mode Register"
|
|
bitfld.long 0x0 19. "PPM,Push-Pull Mode" "0,1"
|
|
bitfld.long 0x0 18. "DTLI,Dead-Time PWMLx Output Inverted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DTHI,Dead-Time PWMHx Output Inverted" "0,1"
|
|
bitfld.long 0x0 16. "DTE,Dead-Time Generator Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCTS,Timer Counter Trigger Selection" "0,1"
|
|
bitfld.long 0x0 12. "DPOLI,Disabled Polarity Inverted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "UPDS,Update Selection" "0: At the next end of PWM period,1: At the next end of Half PWM period"
|
|
bitfld.long 0x0 10. "CES,Counter Event Selection" "0: At the end of PWM period,1: At half of PWM period AND at the end of PWM period"
|
|
newline
|
|
bitfld.long 0x0 9. "CPOL,Channel Polarity" "0: Waveform starts at low level,1: Waveform starts at high level"
|
|
bitfld.long 0x0 8. "CALG,Channel Alignment" "0: Left aligned,1: Center aligned"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CPRE,Channel Prescaler"
|
|
line.long 0x4 "CDTY,PWM Channel Duty Cycle Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CDTY,Channel Duty-Cycle"
|
|
wgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "CDTYUPD,PWM Channel Duty Cycle Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CDTYUPD,Channel Duty-Cycle Update"
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "CPRD,PWM Channel Period Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CPRD,Channel Period"
|
|
wgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "CPRDUPD,PWM Channel Period Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CPRDUPD,Channel Period Update"
|
|
rgroup.long ($2+0x14)++0x3
|
|
line.long 0x0 "CCNT,PWM Channel Counter Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Channel Counter Register"
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "DT,PWM Channel Dead Time Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DTL,Dead-Time Value for PWMLx Output"
|
|
hexmask.long.word 0x0 0.--15. 1. "DTH,Dead-Time Value for PWMHx Output"
|
|
wgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "DTUPD,PWM Channel Dead Time Update Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DTLUPD,Dead-Time Value Update for PWMLx Output"
|
|
hexmask.long.word 0x0 0.--15. 1. "DTHUPD,Dead-Time Value Update for PWMHx Output"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x4006C000
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "CMUPD0,PWM Channel Mode Update Register (ch_num = 0)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
wgroup.long 0x420++0x3
|
|
line.long 0x0 "CMUPD1,PWM Channel Mode Update Register (ch_num = 1)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
group.long 0x42C++0x7
|
|
line.long 0x0 "ETRG1,PWM External Trigger Register (trg_num = 1)"
|
|
bitfld.long 0x0 31. "RFEN,Recoverable Fault Enable" "0,1"
|
|
bitfld.long 0x0 30. "TRGSRC,Trigger Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRGFILT,Filtered input" "0,1"
|
|
bitfld.long 0x0 28. "TRGEDGE,Edge Selection" "0: TRGMODE = 1: TRGINx event detection on falling..,1: TRGMODE = 1: TRGINx event detection on rising.."
|
|
newline
|
|
bitfld.long 0x0 24.--25. "TRGMODE,External Trigger Mode" "0: External trigger is not enabled.,1: External PWM Reset Mode,2: External PWM Start Mode,3: Cycle-by-cycle Duty Mode"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "MAXCNT,Maximum Counter value"
|
|
line.long 0x4 "LEBR1,PWM Leading-Edge Blanking Register (trg_num = 1)"
|
|
bitfld.long 0x4 19. "PWMHREN,PWMH Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 18. "PWMHFEN,PWMH Falling Edge Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PWMLREN,PWML Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 16. "PWMLFEN,PWML Falling Edge Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "LEBDELAY,Leading-Edge Blanking Delay for TRGINx"
|
|
wgroup.long 0x440++0x3
|
|
line.long 0x0 "CMUPD2,PWM Channel Mode Update Register (ch_num = 2)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
group.long 0x44C++0x7
|
|
line.long 0x0 "ETRG2,PWM External Trigger Register (trg_num = 2)"
|
|
bitfld.long 0x0 31. "RFEN,Recoverable Fault Enable" "0,1"
|
|
bitfld.long 0x0 30. "TRGSRC,Trigger Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRGFILT,Filtered input" "0,1"
|
|
bitfld.long 0x0 28. "TRGEDGE,Edge Selection" "0: TRGMODE = 1: TRGINx event detection on falling..,1: TRGMODE = 1: TRGINx event detection on rising.."
|
|
newline
|
|
bitfld.long 0x0 24.--25. "TRGMODE,External Trigger Mode" "0: External trigger is not enabled.,1: External PWM Reset Mode,2: External PWM Start Mode,3: Cycle-by-cycle Duty Mode"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "MAXCNT,Maximum Counter value"
|
|
line.long 0x4 "LEBR2,PWM Leading-Edge Blanking Register (trg_num = 2)"
|
|
bitfld.long 0x4 19. "PWMHREN,PWMH Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 18. "PWMHFEN,PWMH Falling Edge Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PWMLREN,PWML Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 16. "PWMLFEN,PWML Falling Edge Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "LEBDELAY,Leading-Edge Blanking Delay for TRGINx"
|
|
wgroup.long 0x460++0x3
|
|
line.long 0x0 "CMUPD3,PWM Channel Mode Update Register (ch_num = 3)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0x40100200
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,System Reset Key"
|
|
hexmask.long.byte 0x0 8.--15. 1. "PERIID,Peripheral Identifier"
|
|
bitfld.long 0x0 4. "PERIIDON,External Reset" "0,1"
|
|
bitfld.long 0x0 3. "EXTRST,External Reset" "0,1"
|
|
bitfld.long 0x0 0. "PROCRST,Processor Reset" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 17. "SRCMP,Software Reset Command in Progress" "0,1"
|
|
bitfld.long 0x0 16. "NRSTL,NRST Pin Level" "0,1"
|
|
bitfld.long 0x0 8.--10. "RSTTYP,Reset Type" "0: First powerup reset,?,2: Watchdog fault occurred,3: Processor reset required by the software,?,?,6: CPU clock failure detection occurred,7: 32.768 kHz crystal failure detection fault.."
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Write Access Password"
|
|
bitfld.long 0x0 3. "CPUFEN,CPU Fail Enable" "0,1"
|
|
bitfld.long 0x0 1. "SCKSW,Slow Clock Switching" "0,1"
|
|
tree.end
|
|
tree "RSWDT (Reinforced Safety Watchdog Timer)"
|
|
base ad:0x40100300
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 0. "WDRSTT,Watchdog Restart" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 29. "WDIDLEHLT,Watchdog Idle Halt" "0,1"
|
|
bitfld.long 0x0 28. "WDDBGHLT,Watchdog Debug Halt" "0,1"
|
|
hexmask.long.word 0x0 16.--27. 1. "ALLONES,Must Always Be Written with 0xFFF"
|
|
bitfld.long 0x0 15. "WDDIS,Watchdog Disable" "0,1"
|
|
bitfld.long 0x0 13. "WDRSTEN,Watchdog Reset Enable" "0,1"
|
|
bitfld.long 0x0 12. "WDFIEN,Watchdog Fault Interrupt Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "WDV,Watchdog Counter Value"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 0. "WDUNF,Watchdog Underflow" "0,1"
|
|
tree.end
|
|
tree "RTC (Real-time Clock)"
|
|
base ad:0x40100260
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 16.--17. "CALEVSEL,Calendar Event Selection" "0: Week change (every Monday at time 00:00:00),1: Month change (every 01 of each month at time..,2: Year change (every January 1 at time 00:00:00),?"
|
|
bitfld.long 0x0 8.--9. "TIMEVSEL,Time Event Selection" "0: Minute change,1: Hour change,2: Every day at midnight,3: Every day at noon"
|
|
newline
|
|
bitfld.long 0x0 1. "UPDCAL,Update Request Calendar Register" "0,1"
|
|
bitfld.long 0x0 0. "UPDTIM,Update Request Time Register" "0,1"
|
|
line.long 0x4 "MR,Mode Register"
|
|
bitfld.long 0x4 28.--29. "TPERIOD,Period of the Output Pulse" "0: 1 second,1: 500 ms,2: 250 ms,3: 125 ms"
|
|
bitfld.long 0x4 24.--26. "THIGH,High Duration of the Output Pulse" "0: 31.2 ms,1: 15.6 ms,2: 3.91 ms,3: 976 us,4: 488 us,5: 122 us,6: 30.5 us,7: 15.2 us"
|
|
newline
|
|
bitfld.long 0x4 23. "EN1,PIO Line Enable" "0,1"
|
|
bitfld.long 0x4 20.--22. "OUT1,RTCOUT1 Output Source Selection" "0: No waveform stuck at '0',1: 1 Hz square wave,2: 32 Hz square wave,3: 64 Hz square wave,4: 512 Hz square wave,5: Output toggles when alarm flag rises,6: Output is a copy of the alarm flag,7: Duty cycle programmable pulse"
|
|
newline
|
|
bitfld.long 0x4 19. "EN0,PIO Line Enable" "0,1"
|
|
bitfld.long 0x4 16.--18. "OUT0,RTCOUT0 OutputSource Selection" "0: No waveform stuck at '0',1: 1 Hz square wave,2: 32 Hz square wave,3: 64 Hz square wave,4: 512 Hz square wave,5: Output toggles when alarm flag rises,6: Output is a copy of the alarm flag,7: Duty cycle programmable pulse"
|
|
newline
|
|
bitfld.long 0x4 15. "HIGHPPM,HIGH PPM Correction" "0,1"
|
|
hexmask.long.byte 0x4 8.--14. 1. "CORRECTION,Slow Clock Correction"
|
|
newline
|
|
bitfld.long 0x4 4. "NEGPPM,NEGative PPM Correction" "0,1"
|
|
bitfld.long 0x4 1. "PERSIAN,PERSIAN Calendar" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "HRMOD,12-/24-hour Mode" "0,1"
|
|
line.long 0x8 "TIMR,Time Register"
|
|
bitfld.long 0x8 22. "AMPM,Ante Meridiem Post Meridiem Indicator" "0,1"
|
|
hexmask.long.byte 0x8 16.--21. 1. "HOUR,Current Hour"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 1. "MIN,Current Minute"
|
|
hexmask.long.byte 0x8 0.--6. 1. "SEC,Current Second"
|
|
line.long 0xC "CALR,Calendar Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "DATE,Current Day in Current Month"
|
|
bitfld.long 0xC 21.--23. "DAY,Current Day in Current Week" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--20. 1. "MONTH,Current Month"
|
|
hexmask.long.byte 0xC 8.--15. 1. "YEAR,Current Year"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--6. 1. "CENT,Current Century"
|
|
line.long 0x10 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x10 23. "HOUREN,Hour Alarm Enable" "0,1"
|
|
bitfld.long 0x10 22. "AMPM,AM/PM Indicator" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--21. 1. "HOUR,Hour Alarm"
|
|
bitfld.long 0x10 15. "MINEN,Minute Alarm Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--14. 1. "MIN,Minute Alarm"
|
|
bitfld.long 0x10 7. "SECEN,Second Alarm Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--6. 1. "SEC,Second Alarm"
|
|
line.long 0x14 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x14 31. "DATEEN,Date Alarm Enable" "0,1"
|
|
hexmask.long.byte 0x14 24.--29. 1. "DATE,Date Alarm"
|
|
newline
|
|
bitfld.long 0x14 23. "MTHEN,Month Alarm Enable" "0,1"
|
|
hexmask.long.byte 0x14 16.--20. 1. "MONTH,Month Alarm"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 5. "TDERR,Time and/or Date Free Running Error" "0: The internal free running counters are carrying..,1: The internal free running counters have been.."
|
|
bitfld.long 0x0 4. "CALEV,Calendar Event" "0: No calendar event has occurred since the last..,1: At least one calendar event has occurred since.."
|
|
newline
|
|
bitfld.long 0x0 3. "TIMEV,Time Event" "0: No time event has occurred since the last clear.,1: At least one time event has occurred since the.."
|
|
bitfld.long 0x0 2. "SEC,Second Event" "0: No second event has occurred since the last clear.,1: At least one second event has occurred since the.."
|
|
newline
|
|
bitfld.long 0x0 1. "ALARM,Alarm Flag" "0: No alarm matching condition occurred.,1: An alarm matching condition has occurred."
|
|
bitfld.long 0x0 0. "ACKUPD,Acknowledge for Update" "0: Time and calendar registers cannot be updated.,1: Time and calendar registers can be updated."
|
|
wgroup.long 0x1C++0xB
|
|
line.long 0x0 "SCCR,Status Clear Command Register"
|
|
bitfld.long 0x0 5. "TDERRCLR,Time and/or Date Free Running Error Clear" "0,1"
|
|
bitfld.long 0x0 4. "CALCLR,Calendar Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIMCLR,Time Clear" "0,1"
|
|
bitfld.long 0x0 2. "SECCLR,Second Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRCLR,Alarm Clear" "0,1"
|
|
bitfld.long 0x0 0. "ACKCLR,Acknowledge Clear" "0,1"
|
|
line.long 0x4 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x4 5. "TDERREN,Time and/or Date Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "CALEN,Calendar Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TIMEN,Time Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "SECEN,Second Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALREN,Alarm Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "ACKEN,Acknowledge Update Interrupt Enable" "0,1"
|
|
line.long 0x8 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x8 5. "TDERRDIS,Time and/or Date Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 4. "CALDIS,Calendar Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TIMDIS,Time Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 2. "SECDIS,Second Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ALRDIS,Alarm Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 0. "ACKDIS,Acknowledge Update Interrupt Disable" "0,1"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 5. "TDERR,Time and/or Date Error Mask" "0,1"
|
|
bitfld.long 0x0 4. "CAL,Calendar Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIM,Time Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "SEC,Second Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALR,Alarm Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "ACK,Acknowledge Update Interrupt Mask" "0,1"
|
|
line.long 0x4 "VER,Valid Entry Register"
|
|
bitfld.long 0x4 3. "NVCALALR,Non-valid Calendar Alarm" "0,1"
|
|
bitfld.long 0x4 2. "NVTIMALR,Non-valid Time Alarm" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NVCAL,Non-valid Calendar" "0,1"
|
|
bitfld.long 0x4 0. "NVTIM,Non-valid Time" "0,1"
|
|
rgroup.long 0xD0++0x3
|
|
line.long 0x0 "MSR,Milliseconds Register"
|
|
hexmask.long.word 0x0 0.--9. 1. "MS,Number of 1/1024 seconds elapsed within 1 second"
|
|
tree.end
|
|
tree "RTT (Real-time Timer)"
|
|
base ad:0x40100230
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 24. "RTC1HZ,Real-Time Clock 1Hz Clock Selection" "0,1"
|
|
bitfld.long 0x0 20. "RTTDIS,Real-time Timer Disable" "0,1"
|
|
bitfld.long 0x0 18. "RTTRST,Real-time Timer Restart" "0,1"
|
|
bitfld.long 0x0 17. "RTTINCIEN,Real-time Timer Increment Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "ALMIEN,Alarm Interrupt Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "RTPRES,Real-time Timer Prescaler Value"
|
|
line.long 0x4 "AR,Alarm Register"
|
|
hexmask.long 0x4 0.--31. 1. "ALMV,Alarm Value"
|
|
rgroup.long 0x8++0x7
|
|
line.long 0x0 "VR,Value Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRTV,Current Real-time Value"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 1. "RTTINC,Prescaler Roll-over Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 0. "ALMS,Real-time Alarm Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "SCB (System Control Block)"
|
|
base ad:0xE000ED00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CPUID,CPUID Base Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 1. "VARIANT,Indicates processor revision: 0x2 = Revision 2"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "ARCHITECTURE,Indicates architecture. Reads as 0xF"
|
|
hexmask.long.word 0x0 4.--15. 1. "PARTNO,Indicates part number"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Indicates patch release: 0x0 = Patch 0"
|
|
group.long 0x4++0x3B
|
|
line.long 0x0 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x0 31. "NMIPENDSET,Makes the NMI exception active or reads the state of the exception" "0: write: no effect; read: NMI exception is not..,1: write: changes NMI exception state to pending;.."
|
|
bitfld.long 0x0 28. "PENDSVSET,Sets the PendSV exception as pending or reads the current state of the exception" "0: write: no effect; read: PendSV exception is not..,1: write: changes PendSV exception state to.."
|
|
newline
|
|
bitfld.long 0x0 27. "PENDSVCLR,Removes the pending status of the PendSV exception" "0: no effect,1: removes the pending state from the PendSV.."
|
|
bitfld.long 0x0 26. "PENDSTSET,Sets the SysTick exception as pending or reads the current state of the exception" "0: write: no effect; read: SysTick exception is not..,1: write: changes SysTick exception state to.."
|
|
newline
|
|
bitfld.long 0x0 25. "PENDSTCLR,Removes the pending status of the SysTick exception" "0: no effect,1: removes the pending state from the SysTick.."
|
|
bitfld.long 0x0 23. "ISRPREEMPT,Indicates whether a pending exception will be serviced on exit from debug halt state" "0: Will not service,1: Will service a pending exception"
|
|
newline
|
|
bitfld.long 0x0 22. "ISRPENDING,Is external interrupt generated by the NVIC pending" "0,1"
|
|
hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Exception number of the highest priority pending enabled exception"
|
|
newline
|
|
bitfld.long 0x0 11. "RETTOBASE,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "0: there are preempted active exceptions to execute,1: there are no active exceptions or the.."
|
|
hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Active exception number"
|
|
line.long 0x4 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x4 7.--31. 1. "TBLOFF,Bits[31:7] of the vector table address"
|
|
line.long 0x8 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "VECTKEY,Vector key"
|
|
bitfld.long 0x8 15. "ENDIANNESS,Memory system endianness" "0: Little-endian,1: Big-endian"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "PRIGROUP,Interrupt priority grouping field. This field determines the split of group priority from subpriority." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 2. "SYSRESETREQ,System Reset Request" "0: no system reset request,1: asserts a signal to the outer system that.."
|
|
newline
|
|
bitfld.long 0x8 1. "VECTCLRACTIVE,Clears all active state information for fixed and configurable exceptions" "0,1"
|
|
bitfld.long 0x8 0. "VECTRESET,Writing 1 to this bit causes a local system reset" "0,1"
|
|
line.long 0xC "SCR,System Control Register"
|
|
bitfld.long 0xC 4. "SEVONPEND,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "0: only enabled interrupts or events can wakeup the..,1: enabled events and all interrupts including.."
|
|
bitfld.long 0xC 2. "SLEEPDEEP,Provides a qualifying hint indicating that waking from sleep might take longer" "0: sleep,1: deep sleep"
|
|
newline
|
|
bitfld.long 0xC 1. "SLEEPONEXIT,Determines whether on an exit from an ISR that returns to the base level of execution priority the processor enters a sleep state" "0: o not sleep when returning to Thread mode,1: enter sleep or deep sleep on return from an ISR"
|
|
line.long 0x10 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x10 18. "BP,Branch prediction enable bi" "0,1"
|
|
bitfld.long 0x10 17. "IC,Instruction cache enable bi" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "DC,Cache enable bit" "0,1"
|
|
bitfld.long 0x10 9. "STKALIGN,Indicates stack alignment on exception entry" "0: 4-byte aligned,1: 8-byte aligned"
|
|
newline
|
|
bitfld.long 0x10 8. "BFHFNMIGN,Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions." "0: data bus faults caused by load and store..,1: handlers running at priority -1 and -2 ignore.."
|
|
bitfld.long 0x10 4. "DIV_0_TRP,Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0" "0: do not trap divide by 0,1: trap divide by 0"
|
|
newline
|
|
bitfld.long 0x10 3. "UNALIGN_TRP,Enables unaligned access traps" "0: do not trap unaligned halfword and word accesses,1: trap unaligned halfword and word accesses"
|
|
bitfld.long 0x10 1. "USERSETMPEND,Enables unprivileged software access to the STIR" "0: disable,1: enable"
|
|
newline
|
|
bitfld.long 0x10 0. "NONBASETHRDENA,Controls whether the processor can enter Thread mode with exceptions active" "0: processor can enter Thread mode only when no..,1: processor can enter Thread mode from any level.."
|
|
line.long 0x14 "SHPR1,System Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault"
|
|
hexmask.long.byte 0x14 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. "PRI_11,Priority of system handler 11 SVCall"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "PRI_15,Priority of system handler 15 SysTick exception"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "PRI_14,Priority of system handler 14 PendSV"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PRI_12,Priority of system handler 12 SysTick"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 18. "USGFAULTENA," "0: disable the exception,1: enable the exception"
|
|
bitfld.long 0x20 17. "BUSFAULTENA," "0: disable the exception,1: enable the exception"
|
|
newline
|
|
bitfld.long 0x20 16. "MEMFAULTENA," "0: disable the exception,1: enable the exception"
|
|
bitfld.long 0x20 15. "SVCALLPENDED," "0: exception is not pending,1: exception is pending"
|
|
newline
|
|
bitfld.long 0x20 14. "BUSFAULTPENDED," "0: exception is not pending,1: exception is pending"
|
|
bitfld.long 0x20 13. "MEMFAULTPENDED," "0: exception is not pending,1: exception is pending"
|
|
newline
|
|
bitfld.long 0x20 12. "USGFAULTPENDED," "0: exception is not pending,1: exception is pending"
|
|
bitfld.long 0x20 11. "SYSTICKACT," "0: exception is not active,1: exception is active"
|
|
newline
|
|
bitfld.long 0x20 10. "PENDSVACT," "0: exception is not active,1: exception is active"
|
|
bitfld.long 0x20 8. "MONITORACT," "0: exception is not active,1: exception is active"
|
|
newline
|
|
bitfld.long 0x20 7. "SVCALLACT," "0: exception is not active,1: exception is active"
|
|
bitfld.long 0x20 3. "USGFAULTACT," "0: exception is not active,1: exception is active"
|
|
newline
|
|
bitfld.long 0x20 1. "BUSFAULTACT," "0: exception is not active,1: exception is active"
|
|
bitfld.long 0x20 0. "MEMFAULTACT," "0: exception is not active,1: exception is active"
|
|
line.long 0x24 "CFSR,Configurable Fault Status Registers"
|
|
bitfld.long 0x24 25. "DIVBYZERO," "0: no divide by zero fault or divide by zero..,1: the processor has executed an SDIV or UDIV.."
|
|
bitfld.long 0x24 24. "UNALIGNED," "0: no unaligned access fault or unaligned access..,1: the processor has made an unaligned memory access"
|
|
newline
|
|
bitfld.long 0x24 19. "NOCP," "0: no UsageFault caused by attempting to access a..,1: the processor has attempted to access a.."
|
|
bitfld.long 0x24 18. "INVPC," "0: no invalid PC load UsageFault,1: the processor has attempted an illegal load of.."
|
|
newline
|
|
bitfld.long 0x24 17. "INVSTATE," "0: no invalid state UsageFault,1: the processor has attempted to execute an.."
|
|
bitfld.long 0x24 16. "UNDEFINSTR," "0: no undefined instruction UsageFault,1: the processor has attempted to execute an.."
|
|
newline
|
|
bitfld.long 0x24 15. "BFARVALID," "0: value in BFAR is not a valid fault address,1: BFAR holds a valid fault address"
|
|
bitfld.long 0x24 13. "LSPERR," "0: No bus fault occurred during floating-point lazy..,1: A bus fault occurred during floating-point lazy.."
|
|
newline
|
|
bitfld.long 0x24 12. "STKERR," "0: no stacking fault,1: stacking for an exception entry has caused one.."
|
|
bitfld.long 0x24 11. "UNSTKERR," "0: no unstacking fault,1: unstack for an exception return has caused one.."
|
|
newline
|
|
bitfld.long 0x24 10. "IMPRECISERR," "0: no imprecise data bus error,1: a data bus error has occurred but the return.."
|
|
bitfld.long 0x24 9. "PRECISERR," "0: no precise data bus error,1: a data bus error has occurred and the PC value.."
|
|
newline
|
|
bitfld.long 0x24 8. "IBUSERR," "0: no instruction bus error,1: instruction bus error"
|
|
bitfld.long 0x24 7. "MMARVALID," "0: value in MMAR is not a valid fault address,1: MMAR holds a valid fault address"
|
|
newline
|
|
bitfld.long 0x24 5. "MLSPERR," "0: No MemManage fault occurred during..,1: A MemManage fault occurred during floating-point.."
|
|
bitfld.long 0x24 4. "MSTKERR," "0: no stacking fault,1: stacking for an exception entry has caused one.."
|
|
newline
|
|
bitfld.long 0x24 3. "MUNSTKERR," "0: no unstacking fault,1: unstack for an exception return has caused one.."
|
|
bitfld.long 0x24 1. "DACCVIOL," "0: no data access violation fault,1: the processor attempted a load or store at a.."
|
|
newline
|
|
bitfld.long 0x24 0. "IACCVIOL," "0: no instruction access violation fault,1: the processor attempted an instruction fetch.."
|
|
line.long 0x28 "HFSR,HardFault Status register"
|
|
bitfld.long 0x28 31. "DEBUGEVT,Indicates when a Debug event has occurred" "0,1"
|
|
bitfld.long 0x28 30. "FORCED,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "0: no forced HardFault,1: forced HardFault"
|
|
newline
|
|
bitfld.long 0x28 1. "VECTTBL,Indicates when a fault has occurred because of a vector table read error on exception processing" "0: no BusFault on vector table read,1: BusFault on vector table read"
|
|
line.long 0x2C "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x2C 4. "EXTERNAL,debug event generated because of the assertion of an external debug request" "0: No EDBGRQ debug event,1: EDBGRQ debug event"
|
|
bitfld.long 0x2C 3. "VCATCH,triggering of a Vector catch" "0: No Vector catch triggered,1: Vector catch triggered"
|
|
newline
|
|
bitfld.long 0x2C 2. "DWTTRAP,debug event generated by the DWT" "0: No current debug events generated by the DWT,1: At least one current debug event generated by.."
|
|
bitfld.long 0x2C 1. "BKPT,debug event generated by BKPT instruction execution or a breakpoint match in FPB" "0: No current breakpoint debug event,1: At least one current breakpoint debug event"
|
|
newline
|
|
bitfld.long 0x2C 0. "HALTED,debug event generated by" "0: No active halt request debug event,1: Halt request debug event active"
|
|
line.long 0x30 "MMFAR,MemManage Fault Address Register"
|
|
hexmask.long 0x30 0.--31. 1. "ADDRESS,Data address for an MPU fault"
|
|
line.long 0x34 "BFAR,BusFault Address Register"
|
|
hexmask.long 0x34 0.--31. 1. "ADDRESS,Data address for a precise bus fault"
|
|
line.long 0x38 "AFSR,Auxiliary Fault Status Register"
|
|
rgroup.long 0x78++0xB
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x0 27.--29. "LoU,Level of Unification" "0: if neither instruction nor data cache is..,1: if either cache is implemented,?,?,?,?,?,?"
|
|
bitfld.long 0x0 24.--26. "LoC,Level of Coherency" "0: if neither instruction nor data cache is..,1: if either cache is implemented,?,?,?,?,?,?"
|
|
line.long 0x4 "CTR,Cache Type Register"
|
|
bitfld.long 0x4 29.--31. "FORMAT,Register format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 24.--27. 1. "CWG,Cache Writeback Granule"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "ERG,Exclusives Reservation Granule"
|
|
hexmask.long.byte 0x4 16.--19. 1. "DMINLINE,Smallest cache line of all the data and unified caches under the core control"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "IMINLINE,Smallest cache line of all the instruction caches under the control of the processor"
|
|
line.long 0x8 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x8 31. "WT,Write-Through support" "0,1"
|
|
bitfld.long 0x8 30. "WB,Write-Back support" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "RA,Read allocation support" "0,1"
|
|
bitfld.long 0x8 28. "WA,Write allocation support" "0,1"
|
|
newline
|
|
hexmask.long.word 0x8 12.--27. 1. "NumSets,number of sets"
|
|
hexmask.long.word 0x8 3.--11. 1. "Associativity,number of ways"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "LineSize,number of words in each cache line" "0,1,2,3,4,5,6,7"
|
|
group.long 0x84++0x7
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x0 1.--3. "LEVEL,cache level selected" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "IND,selection of instruction or data cache" "0: Data cache,1: Instruction cache"
|
|
line.long 0x4 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x4 22.--23. "CP11,Access privileges for coprocessor 11." "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "CP10,Access privileges for coprocessor 10." "0,1,2,3"
|
|
wgroup.long 0x150++0x3
|
|
line.long 0x0 "ICIALLU,I-cache invalidate all to PoU"
|
|
wgroup.long 0x158++0x23
|
|
line.long 0x0 "ICIMVAU,I-cache invalidate by MVA to PoU"
|
|
line.long 0x4 "DCIMVAC,D-cache invalidate by MVA to PoC"
|
|
line.long 0x8 "DCISW,D-cache invalidate by set-way"
|
|
line.long 0xC "DCCMVAU,D-cache clean by MVA to PoU"
|
|
line.long 0x10 "DCCMVAC,D-cache clean by MVA to PoC"
|
|
line.long 0x14 "DCCSW,D-cache clean by set-way"
|
|
line.long 0x18 "DCCIMVAC,D-cache clean and invalidate by MVA to PoC"
|
|
line.long 0x1C "DCCISW,D-cache clean and invalidate by set-way"
|
|
line.long 0x20 "BPIALL,Branch predictor invalidate all"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x0 0.--8. 1. "INTID,Interrupt ID of the interrupt to trigger in the range 0-239. For example a value of 0x03 specifies interrupt IRQ3."
|
|
rgroup.long 0x240++0xB
|
|
line.long 0x0 "MVFR0,Media and VFP Feature Register 0"
|
|
line.long 0x4 "MVFR1,Media and VFP Feature Register 1"
|
|
line.long 0x8 "MVFR2,Media and VFP Feature Register 2"
|
|
tree.end
|
|
tree "SCNSCB (System Control)"
|
|
base ad:0xE000E000
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "ICTR,Interrupt Controller Type Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTLINESNUM,Total number of interrupt lines supported by an implementation defined in groups of 32"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x0 28. "DISFPUISSOPT,Disables dynamic allocation of ADD and SUB instructions" "0,1"
|
|
bitfld.long 0x0 27. "DISCRITAXIRUW,Disable critical AXI read-under-write" "0,1"
|
|
bitfld.long 0x0 26. "DISDYNADD,Disables dynamic allocation of ADD and SUB instructions" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DISISSCH1,"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DISDI,"
|
|
bitfld.long 0x0 15. "DISCRITAXIRUR," "0,1"
|
|
bitfld.long 0x0 14. "DISBTACALLOC," "0,1"
|
|
bitfld.long 0x0 13. "DISBTACREAD," "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "DISITMATBFLUSH,Disables ITM and DWT ATB flush" "0,1"
|
|
bitfld.long 0x0 11. "DISRAMODE,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "0,1"
|
|
bitfld.long 0x0 10. "FPEXCODIS,Disables FPU exception outputs" "0,1"
|
|
bitfld.long 0x0 2. "DISFOLD,Disables folding of IT instructions" "0,1"
|
|
tree.end
|
|
tree "SFR (Special Function Registers)"
|
|
base ad:0x400A0000
|
|
repeat 40. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "ROMCODE_DBG[$1],ROM code debug"
|
|
hexmask.long 0x0 0.--31. 1. "ROM_CODE_DEBUG,Rom code debug step"
|
|
repeat.end
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "CAN0,CAN0 MSB Base Address"
|
|
hexmask.long.word 0x0 16.--31. 1. "EXT_MEM_ADDR,MSB Base Address"
|
|
line.long 0x4 "CAN1,CAN1 MSB Base Address"
|
|
hexmask.long.word 0x4 16.--31. 1. "EXT_MEM_ADDR,MSB Base Address"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "BOOT_CFG,BOOT Configuration"
|
|
bitfld.long 0x0 0.--2. "BOOT_SEL,BOOT_MODE selected" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "SHA (Secure Hash Algorithm)"
|
|
base ad:0x40094000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 13. "WUIEHV,Write User Initial or Expected Hash Values" "0,1"
|
|
bitfld.long 0x0 12. "WUIHV,Write User Initial Hash Values" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 4. "FIRST,First Block of a Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Start Processing" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CHKCNT,Check Counter"
|
|
bitfld.long 0x0 24.--25. "CHECK,Hash Check" "0: No check is performed,1: Check is performed with expected hash stored in..,2: Check is performed with expected hash provided..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "DUALBUFF,Dual Input Buffer" "0: SHA_IDATARx and SHA_IODATARx cannot be written..,1: SHA_IDATARx and SHA_IODATARx can be written.."
|
|
hexmask.long.byte 0x0 8.--11. 1. "ALGO,SHA Algorithm"
|
|
newline
|
|
bitfld.long 0x0 6. "UIEHV,User Initial or Expected Hash Value Registers" "0,1"
|
|
bitfld.long 0x0 5. "UIHV,User Initial Hash Value Registers" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SMOD,Start Mode" "0: Manual mode,1: Auto mode,2: SHA_IDATAR0 access only mode (mandatory when DMA..,?"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "SECE,Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "CHECKF,Check Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "SECE,Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "CHECKF,Check Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "SECE,Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "CHECKF,Check Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 24. "SECE,Security and/or Safety Event" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "CHKST,Check Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx)"
|
|
newline
|
|
bitfld.long 0x4 16. "CHECKF,Check Done Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx)" "0,1"
|
|
bitfld.long 0x4 12.--14. "URAT,Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by writing a 1 to SWRST bit in SHA_CR)" "0,1"
|
|
bitfld.long 0x4 4. "WRDY,Input Data Register Write Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR or by reading SHA_IODATARx)" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "MSR,Message Size Register"
|
|
hexmask.long 0x0 0.--31. 1. "MSGSIZE,Message Size"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "BCR,Bytes Count Register"
|
|
hexmask.long 0x0 0.--31. 1. "BYTCNT,Remaining Byte Count Before Auto Padding"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "IODATAR[$1],Input/Output Data 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IODATA,Input/Output Data"
|
|
repeat.end
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "SPW (SpaceWire)"
|
|
base ad:0x40040000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ROUTER_STS,SpW Router Status"
|
|
hexmask.long.byte 0x0 24.--31. 1. "COUNT,Packet Count"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BYTE,Router byte"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "SOURCE,Source address"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DEST,Destination addr"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "ROUTER_CFG,SpW Router Config"
|
|
bitfld.long 0x0 2. "DISTIMEOUT,Disable Timeout" "0,1"
|
|
bitfld.long 0x0 1. "FALLBACK,Fallback Routing" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LAENA,LA Routing Enable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "ROUTER_TIMEOUT,SpW Router Timeout"
|
|
bitfld.long 0x0 31. "LOCKED,Locked" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "ADDR,Physical Address"
|
|
repeat 224. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "ROUTER_TABLE[$1],SpW Router Table (Logical addresses 32 to 255. index 0 for logical address 32)"
|
|
bitfld.long 0x0 8. "DELHEAD,Delete Header Byte" "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "ADDR,Address"
|
|
repeat.end
|
|
rgroup.long 0x400++0x3
|
|
line.long 0x0 "LINK1_PI_RM,SpW Link 1 Pending Read Masked Interrupt"
|
|
bitfld.long 0x0 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x0 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x0 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x0 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x0 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x0 0. "DISERR,DisErr" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "LINK1_PI_R,SpW Link 1 Pending Read Interrupt"
|
|
bitfld.long 0x0 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x0 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x0 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x0 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x0 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x0 0. "DISERR,DisErr" "0,1"
|
|
group.long 0x40C++0x7
|
|
line.long 0x0 "LINK1_PI_RCS,SpW Link 1 Pending Read. Clear and Enabed Interrupt"
|
|
bitfld.long 0x0 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x0 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x0 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x0 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x0 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x0 0. "DISERR,DisErr" "0,1"
|
|
line.long 0x4 "LINK1_IM,SpW Link 1 Interrupt Mask"
|
|
bitfld.long 0x4 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x4 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x4 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x4 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x4 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x4 0. "DISERR,DisErr" "0,1"
|
|
wgroup.long 0x414++0xB
|
|
line.long 0x0 "LINK1_PI_C,SpW Link 1 Clear Pending Interrupt"
|
|
bitfld.long 0x0 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x0 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x0 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x0 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x0 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x0 0. "DISERR,DisErr" "0,1"
|
|
line.long 0x4 "LINK1_IM_S,SpW Link 1 Interrupt Set Mask"
|
|
bitfld.long 0x4 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x4 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x4 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x4 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x4 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x4 0. "DISERR,DisErr" "0,1"
|
|
line.long 0x8 "LINK1_IM_C,SpW Link 1 Interrupt Clear Mask"
|
|
bitfld.long 0x8 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x8 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x8 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x8 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x8 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x8 0. "DISERR,DisErr" "0,1"
|
|
group.long 0x420++0x7
|
|
line.long 0x0 "LINK1_CFG,SpW Link 1 Config"
|
|
bitfld.long 0x0 0.--1. "COMMAND,Command" "0: The link proceeds directly to the ErrorReset..,1: State is not actively changed.,2: The Codec will wait in state Ready until the..,3: SpaceWire link can proceed to Started state."
|
|
line.long 0x4 "LINK1_CLKDIV,SpW Link 1 Clock Division"
|
|
hexmask.long.byte 0x4 16.--20. 1. "TXINITDIV,TxInitDiv"
|
|
hexmask.long.byte 0x4 0.--4. 1. "TXOPERDIV,TxOperDiv"
|
|
rgroup.long 0x428++0x3
|
|
line.long 0x0 "LINK1_STATUS,SpW Link 1 Status"
|
|
bitfld.long 0x0 25. "SEEN5,SEEN5" "0,1"
|
|
bitfld.long 0x0 24. "SEEN4,SEEN4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SEEN3,SEEN3" "0,1"
|
|
bitfld.long 0x0 22. "SEEN2,SEEN2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SEEN1,SEEN1" "0,1"
|
|
bitfld.long 0x0 20. "SEEN0,SEEN0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GOTNCHAR,GotNChar" "0,1"
|
|
bitfld.long 0x0 18. "GOTFCT,GotFCT" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "GOTNULL,GotNull" "0,1"
|
|
bitfld.long 0x0 16. "TXEMPTY,TxEmpty" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--8. 1. "TXDEFDIV,TxDefDiv"
|
|
bitfld.long 0x0 0.--2. "LINKSTATE,LinkState" "0: CODEC link state machine in ErrorReset state,1: CODEC link state machine in ErrorWait state,2: CODEC link state machine in Ready state,3: CODEC link state machine in Started state,4: CODEC link state machine in Connecting state,5: CODEC link state machine in Run state,?,?"
|
|
group.long 0x42C++0x3
|
|
line.long 0x0 "LINK1_SWRESET,SpW Link 1 Software Reset"
|
|
hexmask.long 0x0 0.--31. 1. "PATTERN,Pattern"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "LINK1_ESCCHAREVENT[$1],SpW Link 1 Escape Character Event"
|
|
bitfld.long 0x0 17. "HWEVENT,HwEvent" "0,1"
|
|
bitfld.long 0x0 16. "ACTIVE,Active" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MASK,Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "VALUE,Value"
|
|
repeat.end
|
|
rgroup.long 0x438++0x3
|
|
line.long 0x0 "LINK1_ESCCHARSTS,SpW Link 1 Escape Character Status"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHAR2,Esc Char 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CHAR1,Esc Char 1"
|
|
group.long 0x43C++0x3
|
|
line.long 0x0 "LINK1_TRANSESC,SpW Link 1 Transmit Escape Character"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CHAR,Character"
|
|
rgroup.long 0x440++0xB
|
|
line.long 0x0 "LINK1_DISTINTPI_RM,SpW Link 1 Distributed Interrupt Pending Read Masked Interrupt"
|
|
bitfld.long 0x0 31. "DI31,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 30. "DI30,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DI29,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 28. "DI28,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DI27,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 26. "DI26,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DI25,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 24. "DI24,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DI23,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 22. "DI22,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DI21,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 20. "DI20,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DI19,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 18. "DI18,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DI17,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 16. "DI16,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DI15,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "DI14,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DI13,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 12. "DI12,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DI11,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 10. "DI10,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DI9,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 8. "DI8,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DI7,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "DI6,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DI5,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "DI4,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DI3,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "DI2,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DI1,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "DI0,Distributed Interrupt" "0,1"
|
|
line.long 0x4 "LINK1_DISTINTPI_RCM,SpW Link 1 Distributed Interrupt Pending Read and Clear Masked Interrupt"
|
|
bitfld.long 0x4 31. "DI31,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 30. "DI30,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DI29,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 28. "DI28,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DI27,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 26. "DI26,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DI25,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 24. "DI24,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DI23,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 22. "DI22,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DI21,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 20. "DI20,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DI19,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 18. "DI18,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DI17,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 16. "DI16,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DI15,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 14. "DI14,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DI13,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 12. "DI12,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DI11,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 10. "DI10,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DI9,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 8. "DI8,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DI7,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 6. "DI6,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DI5,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 4. "DI4,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DI3,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 2. "DI2,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DI1,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 0. "DI0,Distributed Interrupt" "0,1"
|
|
line.long 0x8 "LINK1_DISTINTPI_R,SpW Link 1 Distributed Interrupt Pending Read Interrupt"
|
|
bitfld.long 0x8 31. "DI31,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 30. "DI30,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "DI29,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 28. "DI28,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "DI27,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 26. "DI26,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "DI25,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 24. "DI24,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "DI23,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 22. "DI22,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "DI21,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 20. "DI20,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DI19,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 18. "DI18,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "DI17,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 16. "DI16,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "DI15,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 14. "DI14,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DI13,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 12. "DI12,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DI11,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 10. "DI10,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DI9,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 8. "DI8,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DI7,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 6. "DI6,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DI5,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 4. "DI4,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DI3,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 2. "DI2,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DI1,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 0. "DI0,Distributed Interrupt" "0,1"
|
|
group.long 0x44C++0x7
|
|
line.long 0x0 "LINK1_DISTINTPI_RCS,SpW Link 1 Distributed Interrupt Pending Read and Clear Interrupt"
|
|
bitfld.long 0x0 31. "DI31,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 30. "DI30,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DI29,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 28. "DI28,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DI27,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 26. "DI26,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DI25,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 24. "DI24,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DI23,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 22. "DI22,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DI21,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 20. "DI20,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DI19,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 18. "DI18,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DI17,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 16. "DI16,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DI15,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "DI14,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DI13,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 12. "DI12,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DI11,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 10. "DI10,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DI9,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 8. "DI8,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DI7,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "DI6,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DI5,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "DI4,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DI3,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "DI2,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DI1,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "DI0,Distributed Interrupt" "0,1"
|
|
line.long 0x4 "LINK1_DISTINTIM,SpW Link 1 Distributed Interrupt Mask"
|
|
bitfld.long 0x4 31. "DI31,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 30. "DI30,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DI29,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 28. "DI28,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DI27,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 26. "DI26,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DI25,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 24. "DI24,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DI23,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 22. "DI22,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DI21,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 20. "DI20,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DI19,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 18. "DI18,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DI17,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 16. "DI16,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DI15,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 14. "DI14,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DI13,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 12. "DI12,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DI11,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 10. "DI10,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DI9,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 8. "DI8,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DI7,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 6. "DI6,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DI5,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 4. "DI4,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DI3,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 2. "DI2,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DI1,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 0. "DI0,Distributed Interrupt mask" "0,1"
|
|
wgroup.long 0x454++0xB
|
|
line.long 0x0 "LINK1_DISTINTPI_C,SpW Link 1 Distributed Interrupt Clear Pending Interrupt"
|
|
bitfld.long 0x0 31. "DI31,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 30. "DI30,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DI29,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 28. "DI28,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DI27,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 26. "DI26,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DI25,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 24. "DI24,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DI23,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 22. "DI22,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DI21,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 20. "DI20,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DI19,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 18. "DI18,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DI17,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 16. "DI16,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DI15,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "DI14,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DI13,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 12. "DI12,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DI11,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 10. "DI10,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DI9,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 8. "DI8,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DI7,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "DI6,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DI5,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "DI4,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DI3,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "DI2,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DI1,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "DI0,Distributed Interrupt" "0,1"
|
|
line.long 0x4 "LINK1_DISTINTIM_S,SpW Link 1 Distributed Interrupt Set Mask"
|
|
bitfld.long 0x4 31. "DI31,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 30. "DI30,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DI29,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 28. "DI28,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DI27,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 26. "DI26,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DI25,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 24. "DI24,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DI23,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 22. "DI22,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DI21,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 20. "DI20,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DI19,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 18. "DI18,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DI17,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 16. "DI16,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DI15,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 14. "DI14,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DI13,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 12. "DI12,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DI11,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 10. "DI10,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DI9,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 8. "DI8,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DI7,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 6. "DI6,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DI5,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 4. "DI4,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DI3,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 2. "DI2,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DI1,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 0. "DI0,Distributed Interrupt mask" "0,1"
|
|
line.long 0x8 "LINK1_DISTINTIM_C,SpW Link 1 Distributed Interrupt Clear Mask"
|
|
bitfld.long 0x8 31. "DI31,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 30. "DI30,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "DI29,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 28. "DI28,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "DI27,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 26. "DI26,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "DI25,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 24. "DI24,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "DI23,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 22. "DI22,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "DI21,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 20. "DI20,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DI19,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 18. "DI18,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "DI17,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 16. "DI16,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "DI15,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 14. "DI14,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DI13,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 12. "DI12,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DI11,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 10. "DI10,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DI9,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 8. "DI8,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DI7,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 6. "DI6,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DI5,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 4. "DI4,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DI3,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 2. "DI2,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DI1,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 0. "DI0,Distributed Interrupt mask" "0,1"
|
|
rgroup.long 0x460++0xB
|
|
line.long 0x0 "LINK1_DISTACKPI_RM,SpW Link 1 Distributed Interrupt Acknowledge Pending Read Masked Interrupt"
|
|
bitfld.long 0x0 31. "DA31,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 30. "DA30,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DA29,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 28. "DA28,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DA27,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 26. "DA26,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DA25,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 24. "DA24,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DA23,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 22. "DA22,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DA21,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 20. "DA20,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DA19,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 18. "DA18,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DA17,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 16. "DA16,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DA15,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 14. "DA14,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DA13,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 12. "DA12,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DA11,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 10. "DA10,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DA9,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 8. "DA8,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DA7,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 6. "DA6,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DA5,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 4. "DA4,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DA3,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 2. "DA2,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DA1,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 0. "DA0,Distributed Acknowledge" "0,1"
|
|
line.long 0x4 "LINK1_DISTACKPI_RCM,SpW Link 1 Distributed Interrupt Acknowledge Pending Read and Clear Masked Interrupt"
|
|
bitfld.long 0x4 31. "DA31,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 30. "DA30,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DA29,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 28. "DA28,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DA27,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 26. "DA26,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DA25,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 24. "DA24,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DA23,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 22. "DA22,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DA21,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 20. "DA20,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DA19,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 18. "DA18,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DA17,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 16. "DA16,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DA15,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 14. "DA14,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DA13,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 12. "DA12,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DA11,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 10. "DA10,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DA9,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 8. "DA8,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DA7,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 6. "DA6,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DA5,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 4. "DA4,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DA3,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 2. "DA2,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DA1,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 0. "DA0,Distributed Acknowledge" "0,1"
|
|
line.long 0x8 "LINK1_DISTACKPI_R,SpW Link 1 Distributed Interrupt Acknowledge Pending Read Interrupt"
|
|
bitfld.long 0x8 31. "DA31,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 30. "DA30,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "DA29,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 28. "DA28,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "DA27,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 26. "DA26,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "DA25,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 24. "DA24,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "DA23,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 22. "DA22,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "DA21,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 20. "DA20,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DA19,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 18. "DA18,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "DA17,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 16. "DA16,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "DA15,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 14. "DA14,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DA13,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 12. "DA12,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DA11,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 10. "DA10,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DA9,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 8. "DA8,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DA7,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 6. "DA6,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DA5,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 4. "DA4,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DA3,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 2. "DA2,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DA1,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 0. "DA0,Distributed Acknowledge" "0,1"
|
|
group.long 0x46C++0x7
|
|
line.long 0x0 "LINK1_DISTACKPI_RCS,SpW Link 1 Distributed Interrupt Acknowledge Pending Read and Clear Interrupt"
|
|
bitfld.long 0x0 31. "DA31,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 30. "DA30,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DA29,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 28. "DA28,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DA27,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 26. "DA26,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DA25,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 24. "DA24,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DA23,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 22. "DA22,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DA21,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 20. "DA20,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DA19,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 18. "DA18,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DA17,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 16. "DA16,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DA15,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 14. "DA14,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DA13,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 12. "DA12,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DA11,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 10. "DA10,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DA9,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 8. "DA8,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DA7,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 6. "DA6,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DA5,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 4. "DA4,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DA3,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 2. "DA2,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DA1,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 0. "DA0,Distributed Acknowledge" "0,1"
|
|
line.long 0x4 "LINK1_DISTACKIM,SpW Link 1 Distributed Interrupt Acknowledge Mask"
|
|
bitfld.long 0x4 31. "DA31,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 30. "DA30,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DA29,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 28. "DA28,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DA27,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 26. "DA26,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DA25,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 24. "DA24,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DA23,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 22. "DA22,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DA21,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 20. "DA20,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DA19,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 18. "DA18,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DA17,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 16. "DA16,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DA15,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 14. "DA14,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DA13,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 12. "DA12,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DA11,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 10. "DA10,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DA9,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 8. "DA8,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DA7,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 6. "DA6,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DA5,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 4. "DA4,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DA3,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 2. "DA2,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DA1,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 0. "DA0,Distributed Acknowledge mask" "0,1"
|
|
wgroup.long 0x474++0xB
|
|
line.long 0x0 "LINK1_DISTACKPI_C,SpW Link 1 Distributed Interrupt Acknowledge Clear Pending Interrupt"
|
|
bitfld.long 0x0 31. "DA31,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 30. "DA30,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DA29,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 28. "DA28,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DA27,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 26. "DA26,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DA25,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 24. "DA24,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DA23,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 22. "DA22,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DA21,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 20. "DA20,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DA19,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 18. "DA18,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DA17,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 16. "DA16,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DA15,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 14. "DA14,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DA13,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 12. "DA12,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DA11,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 10. "DA10,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DA9,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 8. "DA8,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DA7,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 6. "DA6,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DA5,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 4. "DA4,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DA3,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 2. "DA2,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DA1,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 0. "DA0,Distributed Acknowledge" "0,1"
|
|
line.long 0x4 "LINK1_DISTACKIM_S,SpW Link 1 Distributed Interrupt Acknowledge Set Mask"
|
|
bitfld.long 0x4 31. "DA31,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 30. "DA30,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DA29,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 28. "DA28,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DA27,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 26. "DA26,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DA25,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 24. "DA24,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DA23,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 22. "DA22,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DA21,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 20. "DA20,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DA19,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 18. "DA18,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DA17,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 16. "DA16,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DA15,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 14. "DA14,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DA13,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 12. "DA12,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DA11,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 10. "DA10,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DA9,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 8. "DA8,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DA7,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 6. "DA6,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DA5,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 4. "DA4,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DA3,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 2. "DA2,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DA1,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 0. "DA0,Distributed Acknowledge mask" "0,1"
|
|
line.long 0x8 "LINK1_DISTACKIM_C,SpW Link 1 Distributed Interrupt Acknowledge Clear Mask"
|
|
bitfld.long 0x8 31. "DA31,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 30. "DA30,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "DA29,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 28. "DA28,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "DA27,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 26. "DA26,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "DA25,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 24. "DA24,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "DA23,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 22. "DA22,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "DA21,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 20. "DA20,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DA19,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 18. "DA18,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "DA17,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 16. "DA16,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "DA15,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 14. "DA14,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DA13,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 12. "DA12,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DA11,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 10. "DA10,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DA9,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 8. "DA8,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DA7,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 6. "DA6,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DA5,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 4. "DA4,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DA3,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 2. "DA2,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DA1,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 0. "DA0,Distributed Acknowledge mask" "0,1"
|
|
rgroup.long 0x480++0x3
|
|
line.long 0x0 "LINK2_PI_RM,SpW Link 2 Pending Read Masked Interrupt"
|
|
bitfld.long 0x0 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x0 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x0 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x0 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x0 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x0 0. "DISERR,DisErr" "0,1"
|
|
rgroup.long 0x488++0x3
|
|
line.long 0x0 "LINK2_PI_R,SpW Link 2 Pending Read Interrupt"
|
|
bitfld.long 0x0 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x0 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x0 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x0 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x0 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x0 0. "DISERR,DisErr" "0,1"
|
|
group.long 0x48C++0x7
|
|
line.long 0x0 "LINK2_PI_RCS,SpW Link 2 Pending Read. Clear and Enabled Interrupt"
|
|
bitfld.long 0x0 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x0 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x0 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x0 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x0 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x0 0. "DISERR,DisErr" "0,1"
|
|
line.long 0x4 "LINK2_IM,SpW Link 2 Interrupt Mask"
|
|
bitfld.long 0x4 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x4 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x4 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x4 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x4 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x4 0. "DISERR,DisErr" "0,1"
|
|
wgroup.long 0x494++0xB
|
|
line.long 0x0 "LINK2_PI_C,SpW Link 2 Clear Pending Interrupt"
|
|
bitfld.long 0x0 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x0 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x0 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x0 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x0 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x0 0. "DISERR,DisErr" "0,1"
|
|
line.long 0x4 "LINK2_IM_S,SpW Link 2 Interrupt Set Mask"
|
|
bitfld.long 0x4 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x4 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x4 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x4 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x4 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x4 0. "DISERR,DisErr" "0,1"
|
|
line.long 0x8 "LINK2_IM_C,SpW Link 2 Interrupt Clear Mask"
|
|
bitfld.long 0x8 9. "ESCEVENT1,Escape Event 1" "0,1"
|
|
bitfld.long 0x8 8. "ESCEVENT2,Escape Event 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DISCARD,Discard" "0,1"
|
|
bitfld.long 0x8 6. "EEPREC,EEP received" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "EEPTRANS,EEP transmitted" "0,1"
|
|
bitfld.long 0x8 4. "LINKABORT,LinkAbort" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CRERR,CrErr" "0,1"
|
|
bitfld.long 0x8 2. "ESCERR,ESCErr" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "PARERR,ParErr" "0,1"
|
|
bitfld.long 0x8 0. "DISERR,DisErr" "0,1"
|
|
group.long 0x4A0++0x7
|
|
line.long 0x0 "LINK2_CFG,SpW Link 2 Config"
|
|
bitfld.long 0x0 0.--1. "COMMAND,Command" "0: The link proceeds directly to the ErrorReset..,1: State is not actively changed.,2: The Codec will wait in state Ready until the..,3: SpaceWire link can proceed to Started state."
|
|
line.long 0x4 "LINK2_CLKDIV,SpW Link 2 Clock Division"
|
|
hexmask.long.byte 0x4 16.--20. 1. "TXINITDIV,TxInitDiv"
|
|
hexmask.long.byte 0x4 0.--4. 1. "TXOPERDIV,TxOperDiv"
|
|
rgroup.long 0x4A8++0x3
|
|
line.long 0x0 "LINK2_STATUS,SpW Link 2 Status"
|
|
bitfld.long 0x0 25. "SEEN5,SEEN5" "0,1"
|
|
bitfld.long 0x0 24. "SEEN4,SEEN4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "SEEN3,SEEN3" "0,1"
|
|
bitfld.long 0x0 22. "SEEN2,SEEN2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SEEN1,SEEN1" "0,1"
|
|
bitfld.long 0x0 20. "SEEN0,SEEN0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GOTNCHAR,GotNChar" "0,1"
|
|
bitfld.long 0x0 18. "GOTFCT,GotFCT" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "GOTNULL,GotNull" "0,1"
|
|
bitfld.long 0x0 16. "TXEMPTY,TxEmpty" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--8. 1. "TXDEFDIV,TxDefDiv"
|
|
bitfld.long 0x0 0.--2. "LINKSTATE,LinkState" "0: CODEC link state machine in ErrorReset state,1: CODEC link state machine in ErrorWait state,2: CODEC link state machine in Ready state,3: CODEC link state machine in Started state,4: CODEC link state machine in Connecting state,5: CODEC link state machine in Run state,?,?"
|
|
group.long 0x4AC++0x3
|
|
line.long 0x0 "LINK2_SWRESET,SpW Link 2 Software Reset"
|
|
hexmask.long 0x0 0.--31. 1. "PATTERN,Pattern"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x4B0)++0x3
|
|
line.long 0x0 "LINK2_ESCCHAREVENT[$1],SpW Link 2 Escape Character Event"
|
|
bitfld.long 0x0 17. "HWEVENT,HwEvent" "0,1"
|
|
bitfld.long 0x0 16. "ACTIVE,Active" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MASK,Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "VALUE,Value"
|
|
repeat.end
|
|
rgroup.long 0x4B8++0x3
|
|
line.long 0x0 "LINK2_ESCCHARSTS,SpW Link 2 Escape Character Status"
|
|
hexmask.long.byte 0x0 8.--15. 1. "CHAR2,Esc Char 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CHAR1,Esc Char 1"
|
|
group.long 0x4BC++0x3
|
|
line.long 0x0 "LINK2_TRANSESC,SpW Link 2 Transmit Escape Character"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CHAR,Character"
|
|
rgroup.long 0x4C0++0xB
|
|
line.long 0x0 "LINK2_DISTINTPI_RM,SpW Link 2 Distributed Interrupt Pending Read Masked Interrupt"
|
|
bitfld.long 0x0 31. "DI31,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 30. "DI30,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DI29,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 28. "DI28,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DI27,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 26. "DI26,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DI25,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 24. "DI24,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DI23,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 22. "DI22,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DI21,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 20. "DI20,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DI19,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 18. "DI18,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DI17,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 16. "DI16,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DI15,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "DI14,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DI13,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 12. "DI12,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DI11,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 10. "DI10,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DI9,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 8. "DI8,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DI7,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "DI6,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DI5,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "DI4,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DI3,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "DI2,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DI1,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "DI0,Distributed Interrupt" "0,1"
|
|
line.long 0x4 "LINK2_DISTINTPI_RCM,SpW Link 2 Distributed Interrupt Pending Read and Clear Masked Interrupt"
|
|
bitfld.long 0x4 31. "DI31,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 30. "DI30,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DI29,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 28. "DI28,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DI27,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 26. "DI26,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DI25,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 24. "DI24,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DI23,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 22. "DI22,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DI21,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 20. "DI20,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DI19,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 18. "DI18,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DI17,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 16. "DI16,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DI15,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 14. "DI14,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DI13,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 12. "DI12,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DI11,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 10. "DI10,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DI9,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 8. "DI8,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DI7,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 6. "DI6,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DI5,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 4. "DI4,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DI3,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 2. "DI2,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DI1,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x4 0. "DI0,Distributed Interrupt" "0,1"
|
|
line.long 0x8 "LINK2_DISTINTPI_R,SpW Link 2 Distributed Interrupt Pending Read Interrupt"
|
|
bitfld.long 0x8 31. "DI31,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 30. "DI30,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "DI29,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 28. "DI28,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "DI27,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 26. "DI26,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "DI25,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 24. "DI24,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "DI23,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 22. "DI22,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "DI21,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 20. "DI20,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DI19,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 18. "DI18,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "DI17,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 16. "DI16,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "DI15,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 14. "DI14,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DI13,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 12. "DI12,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DI11,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 10. "DI10,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DI9,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 8. "DI8,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DI7,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 6. "DI6,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DI5,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 4. "DI4,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DI3,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 2. "DI2,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DI1,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x8 0. "DI0,Distributed Interrupt" "0,1"
|
|
group.long 0x4CC++0x7
|
|
line.long 0x0 "LINK2_DISTINTPI_RCS,SpW Link 2 Distributed Interrupt Pending Read and Clear Interrupt"
|
|
bitfld.long 0x0 31. "DI31,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 30. "DI30,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DI29,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 28. "DI28,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DI27,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 26. "DI26,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DI25,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 24. "DI24,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DI23,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 22. "DI22,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DI21,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 20. "DI20,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DI19,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 18. "DI18,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DI17,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 16. "DI16,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DI15,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "DI14,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DI13,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 12. "DI12,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DI11,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 10. "DI10,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DI9,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 8. "DI8,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DI7,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "DI6,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DI5,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "DI4,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DI3,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "DI2,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DI1,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "DI0,Distributed Interrupt" "0,1"
|
|
line.long 0x4 "LINK2_DISTINTIM,SpW Link 2 Distributed Interrupt Mask"
|
|
bitfld.long 0x4 31. "DI31,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 30. "DI30,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DI29,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 28. "DI28,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DI27,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 26. "DI26,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DI25,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 24. "DI24,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DI23,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 22. "DI22,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DI21,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 20. "DI20,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DI19,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 18. "DI18,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DI17,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 16. "DI16,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DI15,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 14. "DI14,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DI13,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 12. "DI12,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DI11,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 10. "DI10,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DI9,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 8. "DI8,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DI7,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 6. "DI6,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DI5,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 4. "DI4,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DI3,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 2. "DI2,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DI1,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 0. "DI0,Distributed Interrupt mask" "0,1"
|
|
wgroup.long 0x4D4++0xB
|
|
line.long 0x0 "LINK2_DISTINTPI_C,SpW Link 2 Distributed Interrupt Clear Pending Interrupt"
|
|
bitfld.long 0x0 31. "DI31,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 30. "DI30,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DI29,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 28. "DI28,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DI27,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 26. "DI26,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DI25,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 24. "DI24,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DI23,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 22. "DI22,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DI21,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 20. "DI20,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DI19,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 18. "DI18,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DI17,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 16. "DI16,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DI15,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "DI14,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DI13,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 12. "DI12,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DI11,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 10. "DI10,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DI9,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 8. "DI8,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DI7,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "DI6,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DI5,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "DI4,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DI3,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "DI2,Distributed Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DI1,Distributed Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "DI0,Distributed Interrupt" "0,1"
|
|
line.long 0x4 "LINK2_DISTINTIM_S,SpW Link 2 Distributed Interrupt Set Mask"
|
|
bitfld.long 0x4 31. "DI31,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 30. "DI30,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DI29,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 28. "DI28,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DI27,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 26. "DI26,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DI25,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 24. "DI24,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DI23,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 22. "DI22,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DI21,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 20. "DI20,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DI19,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 18. "DI18,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DI17,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 16. "DI16,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DI15,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 14. "DI14,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DI13,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 12. "DI12,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DI11,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 10. "DI10,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DI9,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 8. "DI8,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DI7,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 6. "DI6,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DI5,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 4. "DI4,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DI3,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 2. "DI2,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DI1,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x4 0. "DI0,Distributed Interrupt mask" "0,1"
|
|
line.long 0x8 "LINK2_DISTINTIM_C,SpW Link 2 Distributed Interrupt Clear Mask"
|
|
bitfld.long 0x8 31. "DI31,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 30. "DI30,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "DI29,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 28. "DI28,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "DI27,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 26. "DI26,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "DI25,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 24. "DI24,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "DI23,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 22. "DI22,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "DI21,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 20. "DI20,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DI19,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 18. "DI18,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "DI17,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 16. "DI16,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "DI15,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 14. "DI14,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DI13,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 12. "DI12,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DI11,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 10. "DI10,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DI9,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 8. "DI8,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DI7,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 6. "DI6,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DI5,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 4. "DI4,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DI3,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 2. "DI2,Distributed Interrupt mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DI1,Distributed Interrupt mask" "0,1"
|
|
bitfld.long 0x8 0. "DI0,Distributed Interrupt mask" "0,1"
|
|
rgroup.long 0x4E0++0xB
|
|
line.long 0x0 "LINK2_DISTACKPI_RM,SpW Link 2 Distributed Interrupt Acknowledge Pending Read Masked Interrupt"
|
|
bitfld.long 0x0 31. "DA31,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 30. "DA30,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DA29,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 28. "DA28,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DA27,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 26. "DA26,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DA25,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 24. "DA24,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DA23,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 22. "DA22,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DA21,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 20. "DA20,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DA19,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 18. "DA18,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DA17,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 16. "DA16,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DA15,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 14. "DA14,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DA13,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 12. "DA12,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DA11,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 10. "DA10,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DA9,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 8. "DA8,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DA7,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 6. "DA6,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DA5,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 4. "DA4,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DA3,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 2. "DA2,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DA1,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 0. "DA0,Distributed Acknowledge" "0,1"
|
|
line.long 0x4 "LINK2_DISTACKPI_RCM,SpW Link 2 Distributed Interrupt Acknowledge Pending Read and Clear Masked Interrupt"
|
|
bitfld.long 0x4 31. "DA31,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 30. "DA30,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DA29,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 28. "DA28,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DA27,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 26. "DA26,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DA25,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 24. "DA24,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DA23,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 22. "DA22,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DA21,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 20. "DA20,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DA19,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 18. "DA18,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DA17,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 16. "DA16,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DA15,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 14. "DA14,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DA13,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 12. "DA12,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DA11,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 10. "DA10,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DA9,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 8. "DA8,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DA7,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 6. "DA6,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DA5,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 4. "DA4,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DA3,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 2. "DA2,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DA1,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x4 0. "DA0,Distributed Acknowledge" "0,1"
|
|
line.long 0x8 "LINK2_DISTACKPI_R,SpW Link 2 Distributed Interrupt Acknowledge Pending Read Interrupt"
|
|
bitfld.long 0x8 31. "DA31,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 30. "DA30,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "DA29,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 28. "DA28,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "DA27,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 26. "DA26,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "DA25,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 24. "DA24,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "DA23,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 22. "DA22,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "DA21,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 20. "DA20,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DA19,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 18. "DA18,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "DA17,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 16. "DA16,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "DA15,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 14. "DA14,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DA13,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 12. "DA12,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DA11,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 10. "DA10,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DA9,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 8. "DA8,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DA7,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 6. "DA6,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DA5,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 4. "DA4,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DA3,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 2. "DA2,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DA1,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x8 0. "DA0,Distributed Acknowledge" "0,1"
|
|
group.long 0x4EC++0x7
|
|
line.long 0x0 "LINK2_DISTACKPI_RCS,SpW Link 2 Distributed Interrupt Acknowledge Pending Read and Clear Interrupt"
|
|
bitfld.long 0x0 31. "DA31,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 30. "DA30,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DA29,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 28. "DA28,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DA27,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 26. "DA26,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DA25,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 24. "DA24,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DA23,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 22. "DA22,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DA21,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 20. "DA20,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DA19,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 18. "DA18,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DA17,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 16. "DA16,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DA15,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 14. "DA14,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DA13,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 12. "DA12,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DA11,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 10. "DA10,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DA9,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 8. "DA8,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DA7,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 6. "DA6,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DA5,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 4. "DA4,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DA3,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 2. "DA2,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DA1,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 0. "DA0,Distributed Acknowledge" "0,1"
|
|
line.long 0x4 "LINK2_DISTACKIM,SpW Link 2 Distributed Interrupt Acknowledge Mask"
|
|
bitfld.long 0x4 31. "DA31,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 30. "DA30,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DA29,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 28. "DA28,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DA27,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 26. "DA26,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DA25,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 24. "DA24,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DA23,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 22. "DA22,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DA21,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 20. "DA20,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DA19,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 18. "DA18,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DA17,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 16. "DA16,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DA15,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 14. "DA14,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DA13,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 12. "DA12,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DA11,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 10. "DA10,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DA9,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 8. "DA8,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DA7,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 6. "DA6,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DA5,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 4. "DA4,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DA3,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 2. "DA2,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DA1,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 0. "DA0,Distributed Acknowledge mask" "0,1"
|
|
wgroup.long 0x4F4++0xB
|
|
line.long 0x0 "LINK2_DISTACKPI_C,SpW Link 2 Distributed Interrupt Acknowledge Clear Pending Interrupt"
|
|
bitfld.long 0x0 31. "DA31,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 30. "DA30,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DA29,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 28. "DA28,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DA27,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 26. "DA26,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DA25,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 24. "DA24,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DA23,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 22. "DA22,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DA21,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 20. "DA20,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DA19,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 18. "DA18,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DA17,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 16. "DA16,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "DA15,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 14. "DA14,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DA13,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 12. "DA12,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DA11,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 10. "DA10,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DA9,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 8. "DA8,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "DA7,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 6. "DA6,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DA5,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 4. "DA4,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DA3,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 2. "DA2,Distributed Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DA1,Distributed Acknowledge" "0,1"
|
|
bitfld.long 0x0 0. "DA0,Distributed Acknowledge" "0,1"
|
|
line.long 0x4 "LINK2_DISTACKIM_S,SpW Link 2 Distributed Interrupt Acknowledge Set Mask"
|
|
bitfld.long 0x4 31. "DA31,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 30. "DA30,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "DA29,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 28. "DA28,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "DA27,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 26. "DA26,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DA25,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 24. "DA24,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "DA23,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 22. "DA22,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DA21,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 20. "DA20,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DA19,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 18. "DA18,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "DA17,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 16. "DA16,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "DA15,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 14. "DA14,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DA13,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 12. "DA12,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DA11,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 10. "DA10,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DA9,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 8. "DA8,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DA7,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 6. "DA6,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DA5,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 4. "DA4,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "DA3,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 2. "DA2,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DA1,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x4 0. "DA0,Distributed Acknowledge mask" "0,1"
|
|
line.long 0x8 "LINK2_DISTACKIM_C,SpW Link 2 Distributed Interrupt Acknowledge Clear Mask"
|
|
bitfld.long 0x8 31. "DA31,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 30. "DA30,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "DA29,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 28. "DA28,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "DA27,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 26. "DA26,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "DA25,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 24. "DA24,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "DA23,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 22. "DA22,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "DA21,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 20. "DA20,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DA19,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 18. "DA18,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "DA17,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 16. "DA16,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "DA15,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 14. "DA14,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "DA13,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 12. "DA12,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DA11,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 10. "DA10,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DA9,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 8. "DA8,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "DA7,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 6. "DA6,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DA5,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 4. "DA4,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "DA3,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 2. "DA2,Distributed Acknowledge mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "DA1,Distributed Acknowledge mask" "0,1"
|
|
bitfld.long 0x8 0. "DA0,Distributed Acknowledge mask" "0,1"
|
|
rgroup.long 0x800++0x3
|
|
line.long 0x0 "PKTRX1_PI_RM,PktRx Pending Read Masked Interrupt"
|
|
bitfld.long 0x0 4. "ACT,Activated" "0,1"
|
|
bitfld.long 0x0 3. "DISCARD,Packet Discard" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EEP,EEP seen" "0,1"
|
|
bitfld.long 0x0 1. "EOP,EOP seen" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DEACT,Deactivated" "0,1"
|
|
rgroup.long 0x808++0x3
|
|
line.long 0x0 "PKTRX1_PI_R,PktRx Pending Read Interrupt"
|
|
bitfld.long 0x0 4. "ACT,Activated" "0,1"
|
|
bitfld.long 0x0 3. "DISCARD,Packet Discard" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EEP,EEP seen" "0,1"
|
|
bitfld.long 0x0 1. "EOP,EOP seen" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DEACT,Deactivated" "0,1"
|
|
group.long 0x80C++0x7
|
|
line.long 0x0 "PKTRX1_PI_RCS,PktRx Pending Read. Clear and Enabled Interrupt"
|
|
bitfld.long 0x0 4. "ACT,Activated" "0,1"
|
|
bitfld.long 0x0 3. "DISCARD,Packet Discard" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EEP,EEP seen" "0,1"
|
|
bitfld.long 0x0 1. "EOP,EOP seen" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DEACT,Deactivated" "0,1"
|
|
line.long 0x4 "PKTRX1_IM,PktRx Interrupt Mask"
|
|
bitfld.long 0x4 4. "ACT,Activated" "0,1"
|
|
bitfld.long 0x4 3. "DISCARD,Packet Discard" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EEP,EEP seen" "0,1"
|
|
bitfld.long 0x4 1. "EOP,EOP seen" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DEACT,Deactivated" "0,1"
|
|
wgroup.long 0x814++0xB
|
|
line.long 0x0 "PKTRX1_PI_C,PktRx Clear Pending Interrupt"
|
|
bitfld.long 0x0 4. "ACT,Activated" "0,1"
|
|
bitfld.long 0x0 3. "DISCARD,Packet Discard" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EEP,EEP seen" "0,1"
|
|
bitfld.long 0x0 1. "EOP,EOP seen" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DEACT,Deactivated" "0,1"
|
|
line.long 0x4 "PKTRX1_IM_S,PktRx Interrupt Set Mask"
|
|
bitfld.long 0x4 4. "ACT,Activated" "0,1"
|
|
bitfld.long 0x4 3. "DISCARD,Packet Discard" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EEP,EEP seen" "0,1"
|
|
bitfld.long 0x4 1. "EOP,EOP seen" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DEACT,Deactivated" "0,1"
|
|
line.long 0x8 "PKTRX1_IM_C,PktRx Interrupt Clear Mask"
|
|
bitfld.long 0x8 4. "ACT,Activated" "0,1"
|
|
bitfld.long 0x8 3. "DISCARD,Packet Discard" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "EEP,EEP seen" "0,1"
|
|
bitfld.long 0x8 1. "EOP,EOP seen" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "DEACT,Deactivated" "0,1"
|
|
group.long 0x820++0x3
|
|
line.long 0x0 "PKTRX1_CFG,PktRx Config"
|
|
bitfld.long 0x0 0. "DISCARD,Discard" "0,1"
|
|
rgroup.long 0x824++0x3
|
|
line.long 0x0 "PKTRX1_STATUS,PktRx Status"
|
|
bitfld.long 0x0 21. "DEACT,Deactivating" "0,1"
|
|
bitfld.long 0x0 20. "PENDING,Pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ACT,Active" "0,1"
|
|
bitfld.long 0x0 18. "ARM,Armed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "LOCKED,Locked" "0,1"
|
|
bitfld.long 0x0 16. "PACKET,Packet" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "COUNT,Packet Count"
|
|
group.long 0x830++0xF
|
|
line.long 0x0 "PKTRX1_NXTBUFDATAADDR,PktRx Next Buffer Data Address"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address"
|
|
line.long 0x4 "PKTRX1_NXTBUFDATALEN,PktRx Next Buffer Data Length"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "LEN,Length"
|
|
line.long 0x8 "PKTRX1_NXTBUFPKTADDR,PktRx Next Buffer Packet Address"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Address"
|
|
line.long 0xC "PKTRX1_NXTBUFCFG,PktRx Next Buffer Config"
|
|
bitfld.long 0xC 30. "SPLIT,Split Pkt" "0,1"
|
|
bitfld.long 0xC 22.--24. "START,Start Mode" "0: Start if any bit in Start Value matches an..,1: Start immediately. Request a deactivation on..,2: Start if Start Value matches an incoming Time..,?,4: Start when Current Buffer is deactivated e.g. by..,?,?,?"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--21. 1. "VALUE,Start Value"
|
|
hexmask.long.word 0xC 0.--15. 1. "MAXCNT,Max Count"
|
|
rgroup.long 0x840++0xB
|
|
line.long 0x0 "PKTRX1_CURBUFDATAADDR,PktRx Current Buffer Data Address"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address"
|
|
line.long 0x4 "PKTRX1_CURBUFDATALEN,PktRx Current Buffer Data Length"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "LEN,Length"
|
|
line.long 0x8 "PKTRX1_CURBUFPKTADDR,PktRx Current Buffer Packet Address"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Address"
|
|
group.long 0x84C++0x3
|
|
line.long 0x0 "PKTRX1_CURBUFCFG,PktRx Current Buffer Config"
|
|
bitfld.long 0x0 31. "ABORT,Abort" "0,1"
|
|
bitfld.long 0x0 30. "SPLIT,Split" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "MAXCNT,Max Count"
|
|
rgroup.long 0x850++0x7
|
|
line.long 0x0 "PKTRX1_PREVBUFDATALEN,PktRx Previous Buffer Data Length"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "LEN,Length"
|
|
line.long 0x4 "PKTRX1_PREVBUFSTS,PktRx Previous Buffer Status"
|
|
bitfld.long 0x4 31. "LOCKED,Locked" "0,1"
|
|
bitfld.long 0x4 19. "DMAERR,DMA Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "FULLD,Buffer Data Full" "0,1"
|
|
bitfld.long 0x4 17. "FULLI,Buffer Info Full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "EEP,EEP seen" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,Count"
|
|
group.long 0x87C++0x3
|
|
line.long 0x0 "PKTRX1_SWRESET,PktRx Software Reset"
|
|
hexmask.long 0x0 0.--31. 1. "PATTERN,Pattern"
|
|
rgroup.long 0xC00++0x3
|
|
line.long 0x0 "PKTTX1_PI_RM,PktTx Pending Read Masked Interrupt"
|
|
bitfld.long 0x0 3. "EEP,EEP sent" "0,1"
|
|
bitfld.long 0x0 2. "EOP,EOP sent" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ACT,Activated" "0,1"
|
|
bitfld.long 0x0 0. "DEACT,Deactivated" "0,1"
|
|
rgroup.long 0xC08++0x3
|
|
line.long 0x0 "PKTTX1_PI_R,PktTx Pending Read Interrupt"
|
|
bitfld.long 0x0 3. "EEP,EEP sent" "0,1"
|
|
bitfld.long 0x0 2. "EOP,EOP sent" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ACT,Activated" "0,1"
|
|
bitfld.long 0x0 0. "DEACT,Deactivated" "0,1"
|
|
group.long 0xC0C++0x7
|
|
line.long 0x0 "PKTTX1_PI_RCS,PktTx Pending Read. Clear and Enabled Interrupt"
|
|
bitfld.long 0x0 3. "EEP,EEP sent" "0,1"
|
|
bitfld.long 0x0 2. "EOP,EOP sent" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ACT,Activated" "0,1"
|
|
bitfld.long 0x0 0. "DEACT,Deactivated" "0,1"
|
|
line.long 0x4 "PKTTX1_IM,PktTx Interrupt Mask"
|
|
bitfld.long 0x4 3. "EEP,EEP sent" "0,1"
|
|
bitfld.long 0x4 2. "EOP,EOP sent" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ACT,Activated" "0,1"
|
|
bitfld.long 0x4 0. "DEACT,Deactivated" "0,1"
|
|
wgroup.long 0xC14++0xB
|
|
line.long 0x0 "PKTTX1_PI_C,PktTx Clear Pending Interrupt"
|
|
bitfld.long 0x0 3. "EEP,EEP sent" "0,1"
|
|
bitfld.long 0x0 2. "EOP,EOP sent" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ACT,Activated" "0,1"
|
|
bitfld.long 0x0 0. "DEACT,Deactivated" "0,1"
|
|
line.long 0x4 "PKTTX1_IM_S,PktTx Interrupt Set Mask"
|
|
bitfld.long 0x4 3. "EEP,EEP sent" "0,1"
|
|
bitfld.long 0x4 2. "EOP,EOP sent" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ACT,Activated" "0,1"
|
|
bitfld.long 0x4 0. "DEACT,Deactivated" "0,1"
|
|
line.long 0x8 "PKTTX1_IM_C,PktTx Interrupt Clear Mask"
|
|
bitfld.long 0x8 3. "EEP,EEP sent" "0,1"
|
|
bitfld.long 0x8 2. "EOP,EOP sent" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ACT,Activated" "0,1"
|
|
bitfld.long 0x8 0. "DEACT,Deactivated" "0,1"
|
|
group.long 0xC20++0xF
|
|
line.long 0x0 "PKTTX1_STATUS,PktTx Status"
|
|
bitfld.long 0x0 16.--18. "PREV,Previous" "0: No information. Field not locked.,1: Last send list fully done,2: Aborted due to memory access error.,3: Aborted by new send list.,4: Aborted by direct user command.,5: Aborted by timeout.,?,?"
|
|
bitfld.long 0x0 3. "DEACT,Deactivating" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "PENDING,Pending" "0,1"
|
|
bitfld.long 0x0 1. "ACT,Active" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ARM,Armed" "0,1"
|
|
line.long 0x4 "PKTTX1_NXTSENDROUT,PktTx Next Send List Router Bytes"
|
|
hexmask.long.byte 0x4 24.--31. 1. "BYTE1,Byte1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BYTE2,Byte2"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "BYTE3,Byte3"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BYTE4,Byte4"
|
|
line.long 0x8 "PKTTX1_NXTSENDADDR,PktTx Next Send List Address"
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,Address"
|
|
line.long 0xC "PKTTX1_NXTSENDCFG,PktTx Next Send List Config"
|
|
bitfld.long 0xC 29. "ABORT,Abort" "0,1"
|
|
bitfld.long 0xC 22.--23. "START,Start Mode" "0: Start if any bit in Start Value matches an..,1: Start immediately if possible,2: Start if Start Value matches an incoming Time..,?"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--21. 1. "VALUE,Start Value"
|
|
hexmask.long.word 0xC 0.--15. 1. "LEN,Length"
|
|
rgroup.long 0xC30++0x7
|
|
line.long 0x0 "PKTTX1_CURSENDROUT,PktTx Current Send List Router Bytes"
|
|
hexmask.long.byte 0x0 24.--31. 1. "BYTE1,Byte1"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BYTE2,Byte2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BYTE3,Byte3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BYTE4,Byte4"
|
|
line.long 0x4 "PKTTX1_CURSENDADDR,PktTx Current Send List Address"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Address"
|
|
group.long 0xC38++0x7
|
|
line.long 0x0 "PKTTX1_CURSENDCFG,PktTx Current Send List Config"
|
|
bitfld.long 0x0 31. "ABORT,Abort" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LEN,Length"
|
|
line.long 0x4 "PKTTX1_SWRESET,PktTx Software Reset"
|
|
hexmask.long 0x4 0.--31. 1. "PATTERN,Pattern"
|
|
group.long 0xE00++0x3
|
|
line.long 0x0 "RMAP1_CFG,SpW RMAP 1 Config"
|
|
bitfld.long 0x0 16. "RMAPENA,RMAP Enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLA,Address"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DESTKEY,DestKey"
|
|
rgroup.long 0xE04++0x7
|
|
line.long 0x0 "RMAP1_STS_RC,SpW RMAP 1 Read and Clear Status"
|
|
bitfld.long 0x0 8. "VALID,Valid" "0,1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ERRCODE,Error Code"
|
|
line.long 0x4 "RMAP1_STS,SpW RMAP 1 Read Status"
|
|
bitfld.long 0x4 8. "VALID,Valid" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ERRCODE,Error Code"
|
|
rgroup.long 0xE80++0x3
|
|
line.long 0x0 "TCH_PI_RM,SpW Tch Pending Read Masked Interrupt"
|
|
bitfld.long 0x0 4. "EARLYWD,Early Watchdog" "0,1"
|
|
bitfld.long 0x0 3. "LATEWD,Late Watchdog" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ANYTIMECODE,Any Time Code" "0,1"
|
|
bitfld.long 0x0 1. "TIMECODE,Time Code" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TCEVENT,TcEvent" "0,1"
|
|
rgroup.long 0xE88++0x3
|
|
line.long 0x0 "TCH_PI_R,SpW Tch Pending Read Interrupt"
|
|
bitfld.long 0x0 4. "EARLYWD,Early Watchdog" "0,1"
|
|
bitfld.long 0x0 3. "LATEWD,Late Watchdog" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ANYTIMECODE,Any Time Code" "0,1"
|
|
bitfld.long 0x0 1. "TIMECODE,Time Code" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TCEVENT,TcEvent" "0,1"
|
|
group.long 0xE8C++0x7
|
|
line.long 0x0 "TCH_PI_RCS,SpW Tch Pending Read. Clear and Enabled Interrupt"
|
|
bitfld.long 0x0 4. "EARLYWD,Early Watchdog" "0,1"
|
|
bitfld.long 0x0 3. "LATEWD,Late Watchdog" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ANYTIMECODE,Any Time Code" "0,1"
|
|
bitfld.long 0x0 1. "TIMECODE,Time Code" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TCEVENT,TcEvent" "0,1"
|
|
line.long 0x4 "TCH_IM,SpW Tch Interrupt Mask"
|
|
bitfld.long 0x4 4. "EARLYWD,Early Watchdog" "0,1"
|
|
bitfld.long 0x4 3. "LATEWD,Late Watchdog" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "ANYTIMECODE,Any Time Code" "0,1"
|
|
bitfld.long 0x4 1. "TIMECODE,Time Code" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TCEVENT,TcEvent" "0,1"
|
|
wgroup.long 0xE94++0xB
|
|
line.long 0x0 "TCH_PI_C,SpW Tch Clear Pending Interrupt"
|
|
bitfld.long 0x0 4. "EARLYWD,Early Watchdog" "0,1"
|
|
bitfld.long 0x0 3. "LATEWD,Late Watchdog" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ANYTIMECODE,Any Time Code" "0,1"
|
|
bitfld.long 0x0 1. "TIMECODE,Time Code" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TCEVENT,TcEvent" "0,1"
|
|
line.long 0x4 "TCH_IM_S,SpW Tch Interrupt Set Mask"
|
|
bitfld.long 0x4 4. "EARLYWD,Early Watchdog" "0,1"
|
|
bitfld.long 0x4 3. "LATEWD,Late Watchdog" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "ANYTIMECODE,Any Time Code" "0,1"
|
|
bitfld.long 0x4 1. "TIMECODE,Time Code" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TCEVENT,TcEvent" "0,1"
|
|
line.long 0x8 "TCH_IM_C,SpW Tch Interrupt Clear Mask"
|
|
bitfld.long 0x8 4. "EARLYWD,Early Watchdog" "0,1"
|
|
bitfld.long 0x8 3. "LATEWD,Late Watchdog" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ANYTIMECODE,Any Time Code" "0,1"
|
|
bitfld.long 0x8 1. "TIMECODE,Time Code" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "TCEVENT,TcEvent" "0,1"
|
|
group.long 0xEA0++0x1F
|
|
line.long 0x0 "TCH_CFGLISTEN,SpW Tch Config Listener"
|
|
bitfld.long 0x0 1. "L2,Listen link 2" "0,1"
|
|
bitfld.long 0x0 0. "L1,Listen link 1" "0,1"
|
|
line.long 0x4 "TCH_CFGSEND,SpW Tch Config Sender"
|
|
bitfld.long 0x4 1. "S2,Send link 2" "0,1"
|
|
bitfld.long 0x4 0. "S1,Send link 1" "0,1"
|
|
line.long 0x8 "TCH_CFG,SpW Tch Config"
|
|
hexmask.long.byte 0x8 0.--5. 1. "EVENT,Event"
|
|
line.long 0xC "TCH_CFGRESTART,SpW Tch Config Restart"
|
|
bitfld.long 0xC 15. "ONESHOT,One Shot" "0,1"
|
|
bitfld.long 0xC 14. "PPS,Pps" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--13. 1. "EVENT,Event"
|
|
hexmask.long.byte 0xC 0.--5. 1. "VALUE,Value"
|
|
line.long 0x10 "TCH_CFGTCEVENT,SpW Tch Config Tc Event"
|
|
hexmask.long.byte 0x10 8.--13. 1. "MASK,Mask"
|
|
hexmask.long.byte 0x10 0.--5. 1. "VALUE,Value"
|
|
line.long 0x14 "TCH_CFGWD,SpW Tch Config Watchdog"
|
|
hexmask.long.word 0x14 16.--31. 1. "EARLY,Early"
|
|
hexmask.long.word 0x14 0.--15. 1. "LATE,Late"
|
|
line.long 0x18 "TCH_LASTTIMECODE,SpW Tch Last Time Code"
|
|
bitfld.long 0x18 8. "SEND,Send Now" "0,1"
|
|
hexmask.long.byte 0x18 0.--5. 1. "VALUE,Value"
|
|
line.long 0x1C "TCH_SWRESET,SpW Tch Software Reset"
|
|
hexmask.long 0x1C 0.--31. 1. "PATTERN,Pattern"
|
|
rgroup.long 0xF00++0x7
|
|
line.long 0x0 "GROUP_IRQSTS1,SpW Group Interrupt status 1"
|
|
bitfld.long 0x0 16. "TCH,Time Code Handler" "0,1"
|
|
bitfld.long 0x0 15. "RX1,Rx 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TX1,Tx 1" "0,1"
|
|
line.long 0x4 "GROUP_IRQSTS2,SpW Group Interrupt status 2"
|
|
bitfld.long 0x4 23. "Di1,Distributed Interrupt 1" "0,1"
|
|
bitfld.long 0x4 22. "Dia1,Distributed Interrupt Acknowledge Link 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "Link1,Link 1" "0,1"
|
|
bitfld.long 0x4 20. "Di2,Distributed Interrupt 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "Dia2,Distributed Interrupt Acknowledge Link 2" "0,1"
|
|
bitfld.long 0x4 18. "Link2,Link 2" "0,1"
|
|
rgroup.long 0xF0C++0x3
|
|
line.long 0x0 "GROUP_EDACSTS,SpW Group Interrupt status"
|
|
hexmask.long.byte 0x0 8.--15. 1. "UNCORR,Uncorrectable Error"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CORR,Correction Count"
|
|
tree.end
|
|
tree "SUPC (Supply Controller)"
|
|
base ad:0x40100210
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Supply Controller Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 5. "MDRCSEL,Monitoring Domain RC Oscillator Select" "0: No effect.,1: If KEY is correct XTALSEL switches the slow.."
|
|
newline
|
|
bitfld.long 0x0 3. "TDXTALSEL,Timing Domain Crystal Oscillator Select" "0: No effect.,1: If KEY is correct XTALSEL switches the slow.."
|
|
bitfld.long 0x0 2. "ZERO,Shall be always write at '0'" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "SMMR,Supply Controller Supply Monitor Mode Register"
|
|
bitfld.long 0x0 23. "CORESMUSEL,Core Supply Monitor User Selection" "0,1"
|
|
line.long 0x4 "MR,Supply Controller Mode Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "KEY,Password Key"
|
|
bitfld.long 0x4 22. "FXTALSTUP,Fast Startup 32.768 kHz Crystal Oscillator" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "ZERO,Shall be always write at '0'" "0,1"
|
|
bitfld.long 0x4 13. "CORSMDIS,VDDCORE Supply Monitor Disable" "0: The VDDCORE supply monitor is enabled.,1: The VDDCORE supply monitor is disabled."
|
|
newline
|
|
bitfld.long 0x4 12. "CORSMRSTEN,VDDCORE Supply Monitor Reset Enable" "0: The core reset signal vddcore_nreset is not..,1: The core reset signal vddcore_nreset is asserted.."
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SR,Supply Controller Status Register"
|
|
bitfld.long 0x0 7. "TDOSCSEL,32 kHz Oscillator Selection Status" "0: The timing domain slow clock TD_SLCK is..,1: The timing domain slow clock TD_SLCK is.."
|
|
bitfld.long 0x0 3. "CORSMRSTS,VDDCORE Supply Monitor Reset Status (cleared on read)" "0: No VDDCORE Supply Monitor reset event has been..,1: At least one VDDCORE Supply Monitor reset event.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "PWR,Supply Controller Power Register"
|
|
bitfld.long 0x0 18. "ZERO,MD_SLCK always generated by the slow RC oscillator" "0,1"
|
|
group.long 0xD4++0x3
|
|
line.long 0x0 "SYSC_WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key."
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "SYSTICK (System Timer)"
|
|
base ad:0xE000E010
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CSR,Control and Status Register"
|
|
bitfld.long 0x0 16. "COUNTFLAG,Returns 1 if timer counted to 0 since last time this was read" "0,1"
|
|
bitfld.long 0x0 2. "CLKSOURCE,Indicates the clock source" "0: external clock,1: processor clock"
|
|
newline
|
|
bitfld.long 0x0 1. "TICKINT,Enables SysTick exception request" "0: counting down to 0 does not assert the SysTick..,1: counting down to 0 asserts the SysTick exception.."
|
|
bitfld.long 0x0 0. "ENABLE,Enables the counter" "0: counter disabled,1: counter enabled"
|
|
line.long 0x4 "RVR,Reload Value Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,Value to load into the SysTick Current Value Register when the counter reaches 0"
|
|
line.long 0x8 "CVR,Current Value Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,Current value at the time the register is accessed"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CALIB,Calibration Value Register"
|
|
bitfld.long 0x0 31. "NOREF,Indicates whether the device provides a reference clock to the processor" "0: The reference clock is provided,1: The reference clock is not provided"
|
|
bitfld.long 0x0 30. "SKEW,Indicates whether the TENMS value is exact" "0: 10ms calibration value is exact,1: 10ms calibration value is inexact because of the.."
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Reload value to use for 10ms timing"
|
|
tree.end
|
|
tree "TC (Timer/Counter)"
|
|
base ad:0x0
|
|
tree "TC0"
|
|
base ad:0x40070000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40070000 ad:0x40070040 ad:0x40070080)
|
|
tree "TC_CHANNEL[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0,1"
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0,1"
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
|
|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK clock signal (from..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal SLCK clock signal (from..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
|
|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK clock signal (from..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal SLCK clock signal (from..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0,1"
|
|
rgroup.long ($2+0xC)++0x7
|
|
line.long 0x0 "RAB,Register AB"
|
|
hexmask.long 0x0 0.--31. 1. "RAB,Register A or Register B"
|
|
line.long 0x4 "CV,Counter Value"
|
|
hexmask.long 0x4 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0,1"
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "ETRGS," "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0,1"
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: The trigger/capture input B is driven internally..,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40070000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0,1"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0,1"
|
|
bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0,1"
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0,1"
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0,1"
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0,1"
|
|
bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0,1"
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0,1"
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "TC1"
|
|
base ad:0x40074000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40074000 ad:0x40074040 ad:0x40074080)
|
|
tree "TC_CHANNEL[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0,1"
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0,1"
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
|
|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK clock signal (from..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal SLCK clock signal (from..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
|
|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK clock signal (from..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal SLCK clock signal (from..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0,1"
|
|
rgroup.long ($2+0xC)++0x7
|
|
line.long 0x0 "RAB,Register AB"
|
|
hexmask.long 0x0 0.--31. 1. "RAB,Register A or Register B"
|
|
line.long 0x4 "CV,Counter Value"
|
|
hexmask.long 0x4 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0,1"
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "ETRGS," "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0,1"
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: The trigger/capture input B is driven internally..,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40074000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0,1"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0,1"
|
|
bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0,1"
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0,1"
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0,1"
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0,1"
|
|
bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0,1"
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0,1"
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "TC2"
|
|
base ad:0x40078000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40078000 ad:0x40078040 ad:0x40078080)
|
|
tree "TC_CHANNEL[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0,1"
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0,1"
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
|
|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK clock signal (from..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal SLCK clock signal (from..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
|
|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK clock signal (from..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal SLCK clock signal (from..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0,1"
|
|
rgroup.long ($2+0xC)++0x7
|
|
line.long 0x0 "RAB,Register AB"
|
|
hexmask.long 0x0 0.--31. 1. "RAB,Register A or Register B"
|
|
line.long 0x4 "CV,Counter Value"
|
|
hexmask.long 0x4 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0,1"
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "ETRGS," "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0,1"
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: The trigger/capture input B is driven internally..,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40078000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0,1"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0,1"
|
|
bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0,1"
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0,1"
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0,1"
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0,1"
|
|
bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0,1"
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0,1"
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "TCMECC (TCM RAM-HECC)"
|
|
base ad:0x40100400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,TCMECC Control Register"
|
|
bitfld.long 0x0 5. "RST_NOFIX_CPT,reset the un-fixable error counter" "0,1"
|
|
bitfld.long 0x0 4. "RST_FIX_CPT,reset the fixable error counter" "0,1"
|
|
bitfld.long 0x0 2. "TEST_MODE_WR,test mode of ECC protection - write mode" "0,1"
|
|
bitfld.long 0x0 1. "TEST_MODE_RD,test mode of ECC protection - read mode" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,ECC protection enable" "0,1"
|
|
line.long 0x4 "TESTCB1,TCMECC Test mode register 1"
|
|
hexmask.long.byte 0x4 8.--15. 1. "TCB2,test check bit (8 bit)"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TCB1,test check bit (8 bit)"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,TCMECC Status register"
|
|
bitfld.long 0x0 29. "MEM_ID_D,memory identification number" "0,1"
|
|
bitfld.long 0x0 28. "MEM_ID_I,memory identification number" "0,1"
|
|
bitfld.long 0x0 27. "ONE,one" "0,1"
|
|
bitfld.long 0x0 24.--26. "HES,Hardware Error Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 15. "OVER_NOFIX,counter overflow" "0,1"
|
|
hexmask.long.byte 0x0 10.--14. 1. "CPT_NOFIX,5 bits counter"
|
|
bitfld.long 0x0 9. "MEM_NOFIX_D,Un-fixable error status in data memory" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MEM_NOFIX_I,Un-fixable error status in instruction memory" "0,1"
|
|
bitfld.long 0x0 7. "OVER_FIX,counter overflow" "0,1"
|
|
hexmask.long.byte 0x0 2.--6. 1. "CPT_FIX,5 bits counter"
|
|
bitfld.long 0x0 1. "MEM_FIX_D,Fixable error status in data memory" "0,1"
|
|
bitfld.long 0x0 0. "MEM_FIX_I,Fixable error status in instruction memory" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,TCMECC Interrupt Enable Register"
|
|
bitfld.long 0x0 3. "MEM_NOFIX_D,Un-fixable error on data" "0,1"
|
|
bitfld.long 0x0 2. "MEM_FIX_D,Fixable error on data" "0,1"
|
|
bitfld.long 0x0 1. "MEM_NOFIX_I,Un-fixable error on instruction" "0,1"
|
|
bitfld.long 0x0 0. "MEM_FIX_I,Fixable error on instruction" "0,1"
|
|
line.long 0x4 "IDR,TCMECC Interrupt Disable Register"
|
|
bitfld.long 0x4 3. "MEM_NOFIX_D,un-fixable error on data" "0,1"
|
|
bitfld.long 0x4 2. "MEM_FIX_D,fixable error on data" "0,1"
|
|
bitfld.long 0x4 1. "MEM_NOFIX_I,un-fixable error on instruction" "0,1"
|
|
bitfld.long 0x4 0. "MEM_FIX_I,fixable error on instruction" "0,1"
|
|
rgroup.long 0x18++0x13
|
|
line.long 0x0 "IMR,TCMECC Interrupt Mask Register"
|
|
bitfld.long 0x0 3. "MEM_NOFIX_D,un-fixable error on data" "0,1"
|
|
bitfld.long 0x0 2. "MEM_FIX_D,fixable error on data" "0,1"
|
|
bitfld.long 0x0 1. "MEM_NOFIX_I,un-fixable error on instruction" "0,1"
|
|
bitfld.long 0x0 0. "MEM_FIX_I,fixable error on instruction" "0,1"
|
|
line.long 0x4 "FAILAR,TCMECC Fail address register"
|
|
hexmask.long 0x4 0.--31. 1. "ADDRESS,address of the error detected (refers to instruction memory)"
|
|
line.long 0x8 "FAILARD,TCMECC Fail address register data"
|
|
hexmask.long 0x8 0.--31. 1. "ADDRESS,address of the error detected"
|
|
line.long 0xC "FAILDR,TCMECC Fail data register"
|
|
hexmask.long 0xC 0.--31. 1. "DATA,data of the error detected (refers to instruction memory)"
|
|
line.long 0x10 "FAILDRD,TCMECC Fail data register data"
|
|
hexmask.long 0x10 0.--31. 1. "DATA,data of the error detected (refers to instruction memory)"
|
|
tree.end
|
|
tree "TPIU (Trace Port Interface Register)"
|
|
base ad:0xE0040000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SSPSR,Supported Parallel Port Size Register"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CSPSR,Current Parallel Port Size Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "ACPR,Asynchronous Clock Prescaler Register"
|
|
hexmask.long.word 0x0 0.--12. 1. "PRESCALER,"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "SPPR,Selected Pin Protocol Register"
|
|
bitfld.long 0x0 0.--1. "TXMODE," "0,1,2,3"
|
|
rgroup.long 0x300++0x3
|
|
line.long 0x0 "FFSR,Formatter and Flush Status Register"
|
|
bitfld.long 0x0 3. "FtNonStop," "0,1"
|
|
bitfld.long 0x0 2. "TCPresent," "0,1"
|
|
bitfld.long 0x0 1. "FtStopped," "0,1"
|
|
bitfld.long 0x0 0. "FlInProg," "0,1"
|
|
group.long 0x304++0x3
|
|
line.long 0x0 "FFCR,Formatter and Flush Control Register"
|
|
bitfld.long 0x0 8. "TrigIn," "0,1"
|
|
bitfld.long 0x0 1. "EnFCont," "0,1"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "FSCR,Formatter Synchronization Counter Register"
|
|
rgroup.long 0xEE8++0xB
|
|
line.long 0x0 "TRIGGER,TRIGGER"
|
|
bitfld.long 0x0 0. "TRIGGER," "0,1"
|
|
line.long 0x4 "FIFO0,Integration ETM Data"
|
|
bitfld.long 0x4 29. "ITM_ATVALID," "0,1"
|
|
bitfld.long 0x4 27.--28. "ITM_bytecount," "0,1,2,3"
|
|
bitfld.long 0x4 26. "ETM_ATVALID," "0,1"
|
|
bitfld.long 0x4 24.--25. "ETM_bytecount," "0,1,2,3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "ETM2,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "ETM1,"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ETM0,"
|
|
line.long 0x8 "ITATBCTR2,ITATBCTR2"
|
|
bitfld.long 0x8 0. "ATREADY," "0,1"
|
|
rgroup.long 0xEF8++0x7
|
|
line.long 0x0 "ITATBCTR0,ITATBCTR0"
|
|
bitfld.long 0x0 0. "ATREADY," "0,1"
|
|
line.long 0x4 "FIFO1,Integration ITM Data"
|
|
bitfld.long 0x4 29. "ITM_ATVALID," "0,1"
|
|
bitfld.long 0x4 27.--28. "ITM_bytecount," "0,1,2,3"
|
|
bitfld.long 0x4 26. "ETM_ATVALID," "0,1"
|
|
bitfld.long 0x4 24.--25. "ETM_bytecount," "0,1,2,3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "ITM2,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "ITM1,"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ITM0,"
|
|
group.long 0xF00++0x3
|
|
line.long 0x0 "ITCTRL,Integration Mode Control"
|
|
bitfld.long 0x0 0. "Mode," "0,1"
|
|
group.long 0xFA0++0x7
|
|
line.long 0x0 "CLAIMSET,Claim tag set"
|
|
line.long 0x4 "CLAIMCLR,Claim tag clear"
|
|
rgroup.long 0xFC8++0x7
|
|
line.long 0x0 "DEVID,TPIU_DEVID"
|
|
bitfld.long 0x0 11. "NRZVALID," "0,1"
|
|
bitfld.long 0x0 10. "MANCVALID," "0,1"
|
|
bitfld.long 0x0 9. "PTINVALID," "0,1"
|
|
bitfld.long 0x0 6.--8. "MinBufSz," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 5. "AsynClkIn," "0,1"
|
|
bitfld.long 0x0 0. "NrTraceInput," "0,1"
|
|
line.long 0x4 "DEVTYPE,TPIU_DEVTYPE"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MajorType,"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SubType,"
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x40090000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WAKEY,Register Write Access Key"
|
|
bitfld.long 0x0 0. "ENABLE,Enables the TRNG to Provide Random Values" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared on read)" "0,1"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "ODATA,Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40100250
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 4. "LOCKMR,Lock Mode Register Write Access" "0,1"
|
|
bitfld.long 0x0 0. "WDRSTT,Watchdog Restart" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 29. "WDIDLEHLT,Watchdog Idle Halt" "0,1"
|
|
bitfld.long 0x0 28. "WDDBGHLT,Watchdog Debug Halt" "0,1"
|
|
hexmask.long.word 0x0 16.--27. 1. "WDD,Watchdog Delta Value"
|
|
bitfld.long 0x0 15. "WDDIS,Watchdog Disable" "0,1"
|
|
bitfld.long 0x0 14. "WDRPROC,Watchdog Reset Processor" "0,1"
|
|
bitfld.long 0x0 13. "WDRSTEN,Watchdog Reset Enable" "0,1"
|
|
bitfld.long 0x0 12. "WDFIEN,Watchdog Fault Interrupt Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "WDV,Watchdog Counter Value"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 1. "WDERR,Watchdog Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "WDUNF,Watchdog Underflow (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "XDMAC (Extensible DMA Controller)"
|
|
base ad:0x40098000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "GTYPE,Global Type Register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "NB_REQ,Number of Peripheral Requests Minus One"
|
|
hexmask.long.word 0x0 5.--15. 1. "FIFO_SZ,Number of Bytes"
|
|
hexmask.long.byte 0x0 0.--4. 1. "NB_CH,Number of Channels Minus One"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "GCFG,Global Configuration Register"
|
|
bitfld.long 0x0 8. "BXKBEN,Boundary X Kilobyte Enable" "0,1"
|
|
bitfld.long 0x0 3. "CGDISIF,Bus Interface Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 2. "CGDISFIFO,FIFO Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 1. "CGDISPIPE,Pipeline Clock Gating Disable" "0,1"
|
|
bitfld.long 0x0 0. "CGDISREG,Configuration Registers Clock Gating Disable" "0,1"
|
|
line.long 0x4 "GWAC,Global Weighted Arbiter Configuration Register"
|
|
hexmask.long.byte 0x4 12.--15. 1. "PW3,Pool Weight 3"
|
|
hexmask.long.byte 0x4 8.--11. 1. "PW2,Pool Weight 2"
|
|
hexmask.long.byte 0x4 4.--7. 1. "PW1,Pool Weight 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PW0,Pool Weight 0"
|
|
wgroup.long 0xC++0x7
|
|
line.long 0x0 "GIE,Global Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "IE31,XDMAC Channel 31 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 30. "IE30,XDMAC Channel 30 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 29. "IE29,XDMAC Channel 29 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 28. "IE28,XDMAC Channel 28 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 27. "IE27,XDMAC Channel 27 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 26. "IE26,XDMAC Channel 26 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 25. "IE25,XDMAC Channel 25 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 24. "IE24,XDMAC Channel 24 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 23. "IE23,XDMAC Channel 23 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 22. "IE22,XDMAC Channel 22 Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "IE21,XDMAC Channel 21 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 20. "IE20,XDMAC Channel 20 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 19. "IE19,XDMAC Channel 19 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 18. "IE18,XDMAC Channel 18 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 17. "IE17,XDMAC Channel 17 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 16. "IE16,XDMAC Channel 16 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 15. "IE15,XDMAC Channel 15 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "IE14,XDMAC Channel 14 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "IE13,XDMAC Channel 13 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 12. "IE12,XDMAC Channel 12 Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "IE11,XDMAC Channel 11 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 10. "IE10,XDMAC Channel 10 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 9. "IE9,XDMAC Channel 9 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 8. "IE8,XDMAC Channel 8 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 7. "IE7,XDMAC Channel 7 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 6. "IE6,XDMAC Channel 6 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 5. "IE5,XDMAC Channel 5 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 4. "IE4,XDMAC Channel 4 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 3. "IE3,XDMAC Channel 3 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 2. "IE2,XDMAC Channel 2 Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IE1,XDMAC Channel 1 Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 0. "IE0,XDMAC Channel 0 Interrupt Enable Bit" "0,1"
|
|
line.long 0x4 "GID,Global Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "ID31,XDMAC Channel 31 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 30. "ID30,XDMAC Channel 30 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 29. "ID29,XDMAC Channel 29 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 28. "ID28,XDMAC Channel 28 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 27. "ID27,XDMAC Channel 27 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 26. "ID26,XDMAC Channel 26 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 25. "ID25,XDMAC Channel 25 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 24. "ID24,XDMAC Channel 24 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 23. "ID23,XDMAC Channel 23 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 22. "ID22,XDMAC Channel 22 Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "ID21,XDMAC Channel 21 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 20. "ID20,XDMAC Channel 20 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 19. "ID19,XDMAC Channel 19 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 18. "ID18,XDMAC Channel 18 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 17. "ID17,XDMAC Channel 17 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 16. "ID16,XDMAC Channel 16 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 15. "ID15,XDMAC Channel 15 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 14. "ID14,XDMAC Channel 14 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 13. "ID13,XDMAC Channel 13 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 12. "ID12,XDMAC Channel 12 Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ID11,XDMAC Channel 11 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 10. "ID10,XDMAC Channel 10 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 9. "ID9,XDMAC Channel 9 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 8. "ID8,XDMAC Channel 8 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 7. "ID7,XDMAC Channel 7 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 6. "ID6,XDMAC Channel 6 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 5. "ID5,XDMAC Channel 5 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 4. "ID4,XDMAC Channel 4 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 3. "ID3,XDMAC Channel 3 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 2. "ID2,XDMAC Channel 2 Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ID1,XDMAC Channel 1 Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 0. "ID0,XDMAC Channel 0 Interrupt Disable Bit" "0,1"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "GIM,Global Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "IM31,XDMAC Channel 31 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 30. "IM30,XDMAC Channel 30 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 29. "IM29,XDMAC Channel 29 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 28. "IM28,XDMAC Channel 28 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 27. "IM27,XDMAC Channel 27 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 26. "IM26,XDMAC Channel 26 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 25. "IM25,XDMAC Channel 25 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 24. "IM24,XDMAC Channel 24 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 23. "IM23,XDMAC Channel 23 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 22. "IM22,XDMAC Channel 22 Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "IM21,XDMAC Channel 21 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 20. "IM20,XDMAC Channel 20 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 19. "IM19,XDMAC Channel 19 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 18. "IM18,XDMAC Channel 18 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 17. "IM17,XDMAC Channel 17 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 16. "IM16,XDMAC Channel 16 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 15. "IM15,XDMAC Channel 15 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 14. "IM14,XDMAC Channel 14 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 13. "IM13,XDMAC Channel 13 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 12. "IM12,XDMAC Channel 12 Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "IM11,XDMAC Channel 11 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 10. "IM10,XDMAC Channel 10 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 9. "IM9,XDMAC Channel 9 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 8. "IM8,XDMAC Channel 8 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 7. "IM7,XDMAC Channel 7 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 6. "IM6,XDMAC Channel 6 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 5. "IM5,XDMAC Channel 5 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 4. "IM4,XDMAC Channel 4 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 3. "IM3,XDMAC Channel 3 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 2. "IM2,XDMAC Channel 2 Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IM1,XDMAC Channel 1 Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 0. "IM0,XDMAC Channel 0 Interrupt Mask Bit" "0,1"
|
|
line.long 0x4 "GIS,Global Interrupt Status Register"
|
|
bitfld.long 0x4 31. "IS31,XDMAC Channel 31 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 30. "IS30,XDMAC Channel 30 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 29. "IS29,XDMAC Channel 29 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 28. "IS28,XDMAC Channel 28 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 27. "IS27,XDMAC Channel 27 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 26. "IS26,XDMAC Channel 26 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 25. "IS25,XDMAC Channel 25 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 24. "IS24,XDMAC Channel 24 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 23. "IS23,XDMAC Channel 23 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 22. "IS22,XDMAC Channel 22 Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "IS21,XDMAC Channel 21 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 20. "IS20,XDMAC Channel 20 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 19. "IS19,XDMAC Channel 19 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 18. "IS18,XDMAC Channel 18 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 17. "IS17,XDMAC Channel 17 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 16. "IS16,XDMAC Channel 16 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 15. "IS15,XDMAC Channel 15 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 14. "IS14,XDMAC Channel 14 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 13. "IS13,XDMAC Channel 13 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 12. "IS12,XDMAC Channel 12 Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "IS11,XDMAC Channel 11 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 10. "IS10,XDMAC Channel 10 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 9. "IS9,XDMAC Channel 9 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 8. "IS8,XDMAC Channel 8 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 7. "IS7,XDMAC Channel 7 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 6. "IS6,XDMAC Channel 6 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 5. "IS5,XDMAC Channel 5 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 4. "IS4,XDMAC Channel 4 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 3. "IS3,XDMAC Channel 3 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 2. "IS2,XDMAC Channel 2 Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "IS1,XDMAC Channel 1 Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 0. "IS0,XDMAC Channel 0 Interrupt Status Bit" "0,1"
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "GE,Global Channel Enable Register"
|
|
bitfld.long 0x0 31. "EN31,XDMAC Channel 31 Enable Bit" "0,1"
|
|
bitfld.long 0x0 30. "EN30,XDMAC Channel 30 Enable Bit" "0,1"
|
|
bitfld.long 0x0 29. "EN29,XDMAC Channel 29 Enable Bit" "0,1"
|
|
bitfld.long 0x0 28. "EN28,XDMAC Channel 28 Enable Bit" "0,1"
|
|
bitfld.long 0x0 27. "EN27,XDMAC Channel 27 Enable Bit" "0,1"
|
|
bitfld.long 0x0 26. "EN26,XDMAC Channel 26 Enable Bit" "0,1"
|
|
bitfld.long 0x0 25. "EN25,XDMAC Channel 25 Enable Bit" "0,1"
|
|
bitfld.long 0x0 24. "EN24,XDMAC Channel 24 Enable Bit" "0,1"
|
|
bitfld.long 0x0 23. "EN23,XDMAC Channel 23 Enable Bit" "0,1"
|
|
bitfld.long 0x0 22. "EN22,XDMAC Channel 22 Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "EN21,XDMAC Channel 21 Enable Bit" "0,1"
|
|
bitfld.long 0x0 20. "EN20,XDMAC Channel 20 Enable Bit" "0,1"
|
|
bitfld.long 0x0 19. "EN19,XDMAC Channel 19 Enable Bit" "0,1"
|
|
bitfld.long 0x0 18. "EN18,XDMAC Channel 18 Enable Bit" "0,1"
|
|
bitfld.long 0x0 17. "EN17,XDMAC Channel 17 Enable Bit" "0,1"
|
|
bitfld.long 0x0 16. "EN16,XDMAC Channel 16 Enable Bit" "0,1"
|
|
bitfld.long 0x0 15. "EN15,XDMAC Channel 15 Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "EN14,XDMAC Channel 14 Enable Bit" "0,1"
|
|
bitfld.long 0x0 13. "EN13,XDMAC Channel 13 Enable Bit" "0,1"
|
|
bitfld.long 0x0 12. "EN12,XDMAC Channel 12 Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EN11,XDMAC Channel 11 Enable Bit" "0,1"
|
|
bitfld.long 0x0 10. "EN10,XDMAC Channel 10 Enable Bit" "0,1"
|
|
bitfld.long 0x0 9. "EN9,XDMAC Channel 9 Enable Bit" "0,1"
|
|
bitfld.long 0x0 8. "EN8,XDMAC Channel 8 Enable Bit" "0,1"
|
|
bitfld.long 0x0 7. "EN7,XDMAC Channel 7 Enable Bit" "0,1"
|
|
bitfld.long 0x0 6. "EN6,XDMAC Channel 6 Enable Bit" "0,1"
|
|
bitfld.long 0x0 5. "EN5,XDMAC Channel 5 Enable Bit" "0,1"
|
|
bitfld.long 0x0 4. "EN4,XDMAC Channel 4 Enable Bit" "0,1"
|
|
bitfld.long 0x0 3. "EN3,XDMAC Channel 3 Enable Bit" "0,1"
|
|
bitfld.long 0x0 2. "EN2,XDMAC Channel 2 Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EN1,XDMAC Channel 1 Enable Bit" "0,1"
|
|
bitfld.long 0x0 0. "EN0,XDMAC Channel 0 Enable Bit" "0,1"
|
|
line.long 0x4 "GD,Global Channel Disable Register"
|
|
bitfld.long 0x4 31. "DI31,XDMAC Channel 31 Disable Bit" "0,1"
|
|
bitfld.long 0x4 30. "DI30,XDMAC Channel 30 Disable Bit" "0,1"
|
|
bitfld.long 0x4 29. "DI29,XDMAC Channel 29 Disable Bit" "0,1"
|
|
bitfld.long 0x4 28. "DI28,XDMAC Channel 28 Disable Bit" "0,1"
|
|
bitfld.long 0x4 27. "DI27,XDMAC Channel 27 Disable Bit" "0,1"
|
|
bitfld.long 0x4 26. "DI26,XDMAC Channel 26 Disable Bit" "0,1"
|
|
bitfld.long 0x4 25. "DI25,XDMAC Channel 25 Disable Bit" "0,1"
|
|
bitfld.long 0x4 24. "DI24,XDMAC Channel 24 Disable Bit" "0,1"
|
|
bitfld.long 0x4 23. "DI23,XDMAC Channel 23 Disable Bit" "0,1"
|
|
bitfld.long 0x4 22. "DI22,XDMAC Channel 22 Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DI21,XDMAC Channel 21 Disable Bit" "0,1"
|
|
bitfld.long 0x4 20. "DI20,XDMAC Channel 20 Disable Bit" "0,1"
|
|
bitfld.long 0x4 19. "DI19,XDMAC Channel 19 Disable Bit" "0,1"
|
|
bitfld.long 0x4 18. "DI18,XDMAC Channel 18 Disable Bit" "0,1"
|
|
bitfld.long 0x4 17. "DI17,XDMAC Channel 17 Disable Bit" "0,1"
|
|
bitfld.long 0x4 16. "DI16,XDMAC Channel 16 Disable Bit" "0,1"
|
|
bitfld.long 0x4 15. "DI15,XDMAC Channel 15 Disable Bit" "0,1"
|
|
bitfld.long 0x4 14. "DI14,XDMAC Channel 14 Disable Bit" "0,1"
|
|
bitfld.long 0x4 13. "DI13,XDMAC Channel 13 Disable Bit" "0,1"
|
|
bitfld.long 0x4 12. "DI12,XDMAC Channel 12 Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DI11,XDMAC Channel 11 Disable Bit" "0,1"
|
|
bitfld.long 0x4 10. "DI10,XDMAC Channel 10 Disable Bit" "0,1"
|
|
bitfld.long 0x4 9. "DI9,XDMAC Channel 9 Disable Bit" "0,1"
|
|
bitfld.long 0x4 8. "DI8,XDMAC Channel 8 Disable Bit" "0,1"
|
|
bitfld.long 0x4 7. "DI7,XDMAC Channel 7 Disable Bit" "0,1"
|
|
bitfld.long 0x4 6. "DI6,XDMAC Channel 6 Disable Bit" "0,1"
|
|
bitfld.long 0x4 5. "DI5,XDMAC Channel 5 Disable Bit" "0,1"
|
|
bitfld.long 0x4 4. "DI4,XDMAC Channel 4 Disable Bit" "0,1"
|
|
bitfld.long 0x4 3. "DI3,XDMAC Channel 3 Disable Bit" "0,1"
|
|
bitfld.long 0x4 2. "DI2,XDMAC Channel 2 Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DI1,XDMAC Channel 1 Disable Bit" "0,1"
|
|
bitfld.long 0x4 0. "DI0,XDMAC Channel 0 Disable Bit" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "GS,Global Channel Status Register"
|
|
bitfld.long 0x0 31. "ST31,XDMAC Channel 31 Status Bit" "0,1"
|
|
bitfld.long 0x0 30. "ST30,XDMAC Channel 30 Status Bit" "0,1"
|
|
bitfld.long 0x0 29. "ST29,XDMAC Channel 29 Status Bit" "0,1"
|
|
bitfld.long 0x0 28. "ST28,XDMAC Channel 28 Status Bit" "0,1"
|
|
bitfld.long 0x0 27. "ST27,XDMAC Channel 27 Status Bit" "0,1"
|
|
bitfld.long 0x0 26. "ST26,XDMAC Channel 26 Status Bit" "0,1"
|
|
bitfld.long 0x0 25. "ST25,XDMAC Channel 25 Status Bit" "0,1"
|
|
bitfld.long 0x0 24. "ST24,XDMAC Channel 24 Status Bit" "0,1"
|
|
bitfld.long 0x0 23. "ST23,XDMAC Channel 23 Status Bit" "0,1"
|
|
bitfld.long 0x0 22. "ST22,XDMAC Channel 22 Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ST21,XDMAC Channel 21 Status Bit" "0,1"
|
|
bitfld.long 0x0 20. "ST20,XDMAC Channel 20 Status Bit" "0,1"
|
|
bitfld.long 0x0 19. "ST19,XDMAC Channel 19 Status Bit" "0,1"
|
|
bitfld.long 0x0 18. "ST18,XDMAC Channel 18 Status Bit" "0,1"
|
|
bitfld.long 0x0 17. "ST17,XDMAC Channel 17 Status Bit" "0,1"
|
|
bitfld.long 0x0 16. "ST16,XDMAC Channel 16 Status Bit" "0,1"
|
|
bitfld.long 0x0 15. "ST15,XDMAC Channel 15 Status Bit" "0,1"
|
|
bitfld.long 0x0 14. "ST14,XDMAC Channel 14 Status Bit" "0,1"
|
|
bitfld.long 0x0 13. "ST13,XDMAC Channel 13 Status Bit" "0,1"
|
|
bitfld.long 0x0 12. "ST12,XDMAC Channel 12 Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ST11,XDMAC Channel 11 Status Bit" "0,1"
|
|
bitfld.long 0x0 10. "ST10,XDMAC Channel 10 Status Bit" "0,1"
|
|
bitfld.long 0x0 9. "ST9,XDMAC Channel 9 Status Bit" "0,1"
|
|
bitfld.long 0x0 8. "ST8,XDMAC Channel 8 Status Bit" "0,1"
|
|
bitfld.long 0x0 7. "ST7,XDMAC Channel 7 Status Bit" "0,1"
|
|
bitfld.long 0x0 6. "ST6,XDMAC Channel 6 Status Bit" "0,1"
|
|
bitfld.long 0x0 5. "ST5,XDMAC Channel 5 Status Bit" "0,1"
|
|
bitfld.long 0x0 4. "ST4,XDMAC Channel 4 Status Bit" "0,1"
|
|
bitfld.long 0x0 3. "ST3,XDMAC Channel 3 Status Bit" "0,1"
|
|
bitfld.long 0x0 2. "ST2,XDMAC Channel 2 Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ST1,XDMAC Channel 1 Status Bit" "0,1"
|
|
bitfld.long 0x0 0. "ST0,XDMAC Channel 0 Status Bit" "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "GRS,Global Channel Read Suspend Register"
|
|
bitfld.long 0x0 31. "RS31,XDMAC Channel 31 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 30. "RS30,XDMAC Channel 30 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 29. "RS29,XDMAC Channel 29 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 28. "RS28,XDMAC Channel 28 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 27. "RS27,XDMAC Channel 27 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 26. "RS26,XDMAC Channel 26 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 25. "RS25,XDMAC Channel 25 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 24. "RS24,XDMAC Channel 24 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 23. "RS23,XDMAC Channel 23 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 22. "RS22,XDMAC Channel 22 Read Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RS21,XDMAC Channel 21 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 20. "RS20,XDMAC Channel 20 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 19. "RS19,XDMAC Channel 19 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 18. "RS18,XDMAC Channel 18 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 17. "RS17,XDMAC Channel 17 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 16. "RS16,XDMAC Channel 16 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 15. "RS15,XDMAC Channel 15 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 14. "RS14,XDMAC Channel 14 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 13. "RS13,XDMAC Channel 13 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 12. "RS12,XDMAC Channel 12 Read Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RS11,XDMAC Channel 11 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 10. "RS10,XDMAC Channel 10 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 9. "RS9,XDMAC Channel 9 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 8. "RS8,XDMAC Channel 8 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 7. "RS7,XDMAC Channel 7 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 6. "RS6,XDMAC Channel 6 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 5. "RS5,XDMAC Channel 5 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 4. "RS4,XDMAC Channel 4 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 3. "RS3,XDMAC Channel 3 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 2. "RS2,XDMAC Channel 2 Read Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RS1,XDMAC Channel 1 Read Suspend Bit" "0,1"
|
|
bitfld.long 0x0 0. "RS0,XDMAC Channel 0 Read Suspend Bit" "0,1"
|
|
line.long 0x4 "GWS,Global Channel Write Suspend Register"
|
|
bitfld.long 0x4 31. "WS31,XDMAC Channel 31 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 30. "WS30,XDMAC Channel 30 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 29. "WS29,XDMAC Channel 29 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 28. "WS28,XDMAC Channel 28 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 27. "WS27,XDMAC Channel 27 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 26. "WS26,XDMAC Channel 26 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 25. "WS25,XDMAC Channel 25 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 24. "WS24,XDMAC Channel 24 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 23. "WS23,XDMAC Channel 23 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 22. "WS22,XDMAC Channel 22 Write Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "WS21,XDMAC Channel 21 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 20. "WS20,XDMAC Channel 20 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 19. "WS19,XDMAC Channel 19 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 18. "WS18,XDMAC Channel 18 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 17. "WS17,XDMAC Channel 17 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 16. "WS16,XDMAC Channel 16 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 15. "WS15,XDMAC Channel 15 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 14. "WS14,XDMAC Channel 14 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 13. "WS13,XDMAC Channel 13 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 12. "WS12,XDMAC Channel 12 Write Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "WS11,XDMAC Channel 11 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 10. "WS10,XDMAC Channel 10 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 9. "WS9,XDMAC Channel 9 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 8. "WS8,XDMAC Channel 8 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 7. "WS7,XDMAC Channel 7 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 6. "WS6,XDMAC Channel 6 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 5. "WS5,XDMAC Channel 5 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 4. "WS4,XDMAC Channel 4 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 3. "WS3,XDMAC Channel 3 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 2. "WS2,XDMAC Channel 2 Write Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "WS1,XDMAC Channel 1 Write Suspend Bit" "0,1"
|
|
bitfld.long 0x4 0. "WS0,XDMAC Channel 0 Write Suspend Bit" "0,1"
|
|
wgroup.long 0x30++0xB
|
|
line.long 0x0 "GRWS,Global Channel Read Write Suspend Register"
|
|
bitfld.long 0x0 31. "RWS31,XDMAC Channel 31 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 30. "RWS30,XDMAC Channel 30 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 29. "RWS29,XDMAC Channel 29 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 28. "RWS28,XDMAC Channel 28 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 27. "RWS27,XDMAC Channel 27 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 26. "RWS26,XDMAC Channel 26 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 25. "RWS25,XDMAC Channel 25 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 24. "RWS24,XDMAC Channel 24 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 23. "RWS23,XDMAC Channel 23 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 22. "RWS22,XDMAC Channel 22 Read Write Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "RWS21,XDMAC Channel 21 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 20. "RWS20,XDMAC Channel 20 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 19. "RWS19,XDMAC Channel 19 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 18. "RWS18,XDMAC Channel 18 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 17. "RWS17,XDMAC Channel 17 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 16. "RWS16,XDMAC Channel 16 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 15. "RWS15,XDMAC Channel 15 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 14. "RWS14,XDMAC Channel 14 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 13. "RWS13,XDMAC Channel 13 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 12. "RWS12,XDMAC Channel 12 Read Write Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RWS11,XDMAC Channel 11 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 10. "RWS10,XDMAC Channel 10 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 9. "RWS9,XDMAC Channel 9 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 8. "RWS8,XDMAC Channel 8 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 7. "RWS7,XDMAC Channel 7 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 6. "RWS6,XDMAC Channel 6 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 5. "RWS5,XDMAC Channel 5 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 4. "RWS4,XDMAC Channel 4 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 3. "RWS3,XDMAC Channel 3 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 2. "RWS2,XDMAC Channel 2 Read Write Suspend Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RWS1,XDMAC Channel 1 Read Write Suspend Bit" "0,1"
|
|
bitfld.long 0x0 0. "RWS0,XDMAC Channel 0 Read Write Suspend Bit" "0,1"
|
|
line.long 0x4 "GRWR,Global Channel Read Write Resume Register"
|
|
bitfld.long 0x4 31. "RWR31,XDMAC Channel 31 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 30. "RWR30,XDMAC Channel 30 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 29. "RWR29,XDMAC Channel 29 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 28. "RWR28,XDMAC Channel 28 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 27. "RWR27,XDMAC Channel 27 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 26. "RWR26,XDMAC Channel 26 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 25. "RWR25,XDMAC Channel 25 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 24. "RWR24,XDMAC Channel 24 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 23. "RWR23,XDMAC Channel 23 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 22. "RWR22,XDMAC Channel 22 Read Write Resume Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "RWR21,XDMAC Channel 21 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 20. "RWR20,XDMAC Channel 20 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 19. "RWR19,XDMAC Channel 19 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 18. "RWR18,XDMAC Channel 18 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 17. "RWR17,XDMAC Channel 17 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 16. "RWR16,XDMAC Channel 16 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 15. "RWR15,XDMAC Channel 15 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 14. "RWR14,XDMAC Channel 14 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 13. "RWR13,XDMAC Channel 13 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 12. "RWR12,XDMAC Channel 12 Read Write Resume Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RWR11,XDMAC Channel 11 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 10. "RWR10,XDMAC Channel 10 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 9. "RWR9,XDMAC Channel 9 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 8. "RWR8,XDMAC Channel 8 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 7. "RWR7,XDMAC Channel 7 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 6. "RWR6,XDMAC Channel 6 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 5. "RWR5,XDMAC Channel 5 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 4. "RWR4,XDMAC Channel 4 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 3. "RWR3,XDMAC Channel 3 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 2. "RWR2,XDMAC Channel 2 Read Write Resume Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RWR1,XDMAC Channel 1 Read Write Resume Bit" "0,1"
|
|
bitfld.long 0x4 0. "RWR0,XDMAC Channel 0 Read Write Resume Bit" "0,1"
|
|
line.long 0x8 "GSWR,Global Channel Software Request Register"
|
|
bitfld.long 0x8 31. "SWREQ31,XDMAC Channel 31 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 30. "SWREQ30,XDMAC Channel 30 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 29. "SWREQ29,XDMAC Channel 29 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 28. "SWREQ28,XDMAC Channel 28 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 27. "SWREQ27,XDMAC Channel 27 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 26. "SWREQ26,XDMAC Channel 26 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 25. "SWREQ25,XDMAC Channel 25 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 24. "SWREQ24,XDMAC Channel 24 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 23. "SWREQ23,XDMAC Channel 23 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 22. "SWREQ22,XDMAC Channel 22 Software Request Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "SWREQ21,XDMAC Channel 21 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 20. "SWREQ20,XDMAC Channel 20 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 19. "SWREQ19,XDMAC Channel 19 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 18. "SWREQ18,XDMAC Channel 18 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 17. "SWREQ17,XDMAC Channel 17 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 16. "SWREQ16,XDMAC Channel 16 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 15. "SWREQ15,XDMAC Channel 15 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 14. "SWREQ14,XDMAC Channel 14 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 13. "SWREQ13,XDMAC Channel 13 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 12. "SWREQ12,XDMAC Channel 12 Software Request Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "SWREQ11,XDMAC Channel 11 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 10. "SWREQ10,XDMAC Channel 10 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 9. "SWREQ9,XDMAC Channel 9 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 8. "SWREQ8,XDMAC Channel 8 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 7. "SWREQ7,XDMAC Channel 7 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 6. "SWREQ6,XDMAC Channel 6 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 5. "SWREQ5,XDMAC Channel 5 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 4. "SWREQ4,XDMAC Channel 4 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 3. "SWREQ3,XDMAC Channel 3 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 2. "SWREQ2,XDMAC Channel 2 Software Request Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "SWREQ1,XDMAC Channel 1 Software Request Bit" "0,1"
|
|
bitfld.long 0x8 0. "SWREQ0,XDMAC Channel 0 Software Request Bit" "0,1"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "GSWS,Global Channel Software Request Status Register"
|
|
bitfld.long 0x0 31. "SWRS31,XDMAC Channel 31 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 30. "SWRS30,XDMAC Channel 30 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 29. "SWRS29,XDMAC Channel 29 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 28. "SWRS28,XDMAC Channel 28 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 27. "SWRS27,XDMAC Channel 27 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 26. "SWRS26,XDMAC Channel 26 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 25. "SWRS25,XDMAC Channel 25 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 24. "SWRS24,XDMAC Channel 24 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 23. "SWRS23,XDMAC Channel 23 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 22. "SWRS22,XDMAC Channel 22 Software Request Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SWRS21,XDMAC Channel 21 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 20. "SWRS20,XDMAC Channel 20 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 19. "SWRS19,XDMAC Channel 19 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 18. "SWRS18,XDMAC Channel 18 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 17. "SWRS17,XDMAC Channel 17 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 16. "SWRS16,XDMAC Channel 16 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 15. "SWRS15,XDMAC Channel 15 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 14. "SWRS14,XDMAC Channel 14 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 13. "SWRS13,XDMAC Channel 13 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 12. "SWRS12,XDMAC Channel 12 Software Request Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SWRS11,XDMAC Channel 11 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 10. "SWRS10,XDMAC Channel 10 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 9. "SWRS9,XDMAC Channel 9 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 8. "SWRS8,XDMAC Channel 8 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 7. "SWRS7,XDMAC Channel 7 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 6. "SWRS6,XDMAC Channel 6 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 5. "SWRS5,XDMAC Channel 5 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 4. "SWRS4,XDMAC Channel 4 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 3. "SWRS3,XDMAC Channel 3 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 2. "SWRS2,XDMAC Channel 2 Software Request Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SWRS1,XDMAC Channel 1 Software Request Status Bit" "0,1"
|
|
bitfld.long 0x0 0. "SWRS0,XDMAC Channel 0 Software Request Status Bit" "0,1"
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "GSWF,Global Channel Software Flush Request Register"
|
|
bitfld.long 0x0 31. "SWF31,XDMAC Channel 31 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 30. "SWF30,XDMAC Channel 30 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 29. "SWF29,XDMAC Channel 29 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 28. "SWF28,XDMAC Channel 28 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 27. "SWF27,XDMAC Channel 27 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 26. "SWF26,XDMAC Channel 26 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 25. "SWF25,XDMAC Channel 25 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 24. "SWF24,XDMAC Channel 24 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 23. "SWF23,XDMAC Channel 23 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 22. "SWF22,XDMAC Channel 22 Software Flush Request Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SWF21,XDMAC Channel 21 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 20. "SWF20,XDMAC Channel 20 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 19. "SWF19,XDMAC Channel 19 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 18. "SWF18,XDMAC Channel 18 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 17. "SWF17,XDMAC Channel 17 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 16. "SWF16,XDMAC Channel 16 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 15. "SWF15,XDMAC Channel 15 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 14. "SWF14,XDMAC Channel 14 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 13. "SWF13,XDMAC Channel 13 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 12. "SWF12,XDMAC Channel 12 Software Flush Request Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SWF11,XDMAC Channel 11 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 10. "SWF10,XDMAC Channel 10 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 9. "SWF9,XDMAC Channel 9 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 8. "SWF8,XDMAC Channel 8 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 7. "SWF7,XDMAC Channel 7 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 6. "SWF6,XDMAC Channel 6 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 5. "SWF5,XDMAC Channel 5 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 4. "SWF4,XDMAC Channel 4 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 3. "SWF3,XDMAC Channel 3 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 2. "SWF2,XDMAC Channel 2 Software Flush Request Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SWF1,XDMAC Channel 1 Software Flush Request Bit" "0,1"
|
|
bitfld.long 0x0 0. "SWF0,XDMAC Channel 0 Software Flush Request Bit" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40098050 ad:0x40098090 ad:0x400980D0 ad:0x40098110 ad:0x40098150 ad:0x40098190 ad:0x400981D0 ad:0x40098210 ad:0x40098250 ad:0x40098290 ad:0x400982D0 ad:0x40098310 ad:0x40098350 ad:0x40098390 ad:0x400983D0 ad:0x40098410)
|
|
tree "XDMAC_CHID[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x7
|
|
line.long 0x0 "CIE,Channel Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "ROIE,Request Overflow Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 5. "WBIE,Write Bus Error Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RBIE,Read Bus Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 3. "FIE,End of Flush Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DIE,End of Disable Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 1. "LIE,End of Linked List Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BIE,End of Block Interrupt Enable Bit" "0,1"
|
|
line.long 0x4 "CID,Channel Interrupt Disable Register"
|
|
bitfld.long 0x4 6. "ROID,Request Overflow Error Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 5. "WBEID,Write Bus Error Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RBEID,Read Bus Error Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 3. "FID,End of Flush Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DID,End of Disable Interrupt Disable Bit" "0,1"
|
|
bitfld.long 0x4 1. "LID,End of Linked List Interrupt Disable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "BID,End of Block Interrupt Disable Bit" "0,1"
|
|
rgroup.long ($2+0x8)++0x7
|
|
line.long 0x0 "CIM,Channel Interrupt Mask Register"
|
|
bitfld.long 0x0 6. "ROIM,Request Overflow Error Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 5. "WBEIM,Write Bus Error Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RBEIM,Read Bus Error Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 3. "FIM,End of Flush Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DIM,End of Disable Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 1. "LIM,End of Linked List Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BIM,End of Block Interrupt Mask Bit" "0,1"
|
|
line.long 0x4 "CIS,Channel Interrupt Status Register"
|
|
bitfld.long 0x4 6. "ROIS,Request Overflow Error Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 5. "WBEIS,Write Bus Error Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RBEIS,Read Bus Error Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 3. "FIS,End of Flush Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DIS,End of Disable Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 1. "LIS,End of Linked List Interrupt Status Bit" "0,1"
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newline
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bitfld.long 0x4 0. "BIS,End of Block Interrupt Status Bit" "0,1"
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|
group.long ($2+0x10)++0x27
|
|
line.long 0x0 "CSA,Channel Source Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "SA,Channel x Source Address"
|
|
line.long 0x4 "CDA,Channel Destination Address Register"
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|
hexmask.long 0x4 0.--31. 1. "DA,Channel x Destination Address"
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|
line.long 0x8 "CNDA,Channel Next Descriptor Address Register"
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|
hexmask.long 0x8 2.--31. 1. "NDA,Channel x Next Descriptor Address"
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bitfld.long 0x8 0. "NDAIF,Channel x Next Descriptor Interface" "0,1"
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line.long 0xC "CNDC,Channel Next Descriptor Control Register"
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bitfld.long 0xC 3.--4. "NDVIEW,Channel x Next Descriptor View" "0: Next Descriptor View 0,1: Next Descriptor View 1,2: Next Descriptor View 2,3: Next Descriptor View 3"
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bitfld.long 0xC 2. "NDDUP,Channel x Next Descriptor Destination Update" "0: Destination parameters remain unchanged.,1: Destination parameters are updated when the.."
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newline
|
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bitfld.long 0xC 1. "NDSUP,Channel x Next Descriptor Source Update" "0: Source parameters remain unchanged.,1: Source parameters are updated when the.."
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bitfld.long 0xC 0. "NDE,Channel x Next Descriptor Enable" "0: Descriptor fetch is disabled.,1: Descriptor fetch is enabled."
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|
line.long 0x10 "CUBC,Channel Microblock Control Register"
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hexmask.long.tbyte 0x10 0.--23. 1. "UBLEN,Channel x Microblock Length"
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line.long 0x14 "CBC,Channel Block Control Register"
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hexmask.long.word 0x14 0.--11. 1. "BLEN,Channel x Block Length"
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line.long 0x18 "CC,Channel Configuration Register"
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hexmask.long.byte 0x18 24.--30. 1. "PERID,Channel x Peripheral Hardware Request Line Identifier"
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bitfld.long 0x18 23. "WRIP,Write in Progress (this bit is read-only)" "0: No active write transaction on the bus.,1: A write transaction is in progress."
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|
newline
|
|
bitfld.long 0x18 22. "RDIP,Read in Progress (this bit is read-only)" "0: No active read transaction on the bus.,1: A read transaction is in progress."
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bitfld.long 0x18 21. "INITD,Channel Initialization Done (this bit is read-only)" "0: Channel initialization is in progress.,1: Channel initialization is completed."
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newline
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bitfld.long 0x18 18.--19. "DAM,Channel x Destination Addressing Mode" "0: The address remains unchanged.,1: The addressing mode is incremented (the..,2: The microblock stride is added at the microblock..,3: The microblock stride is added at the microblock.."
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bitfld.long 0x18 16.--17. "SAM,Channel x Source Addressing Mode" "0: The address remains unchanged.,1: The addressing mode is incremented (the..,2: The microblock stride is added at the microblock..,3: The microblock stride is added at the microblock.."
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|
newline
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bitfld.long 0x18 14. "DIF,Channel x Destination Interface Identifier" "0: The data is written through system bus interface..,1: The data is written though system bus interface 1."
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bitfld.long 0x18 13. "SIF,Channel x Source Interface Identifier" "0: The data is read through system bus interface 0.,1: The data is read through system bus interface 1."
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newline
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bitfld.long 0x18 11.--12. "DWIDTH,Channel x Data Width" "0: The data size is set to 8 bits,1: The data size is set to 16 bits,2: The data size is set to 32 bits,?"
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bitfld.long 0x18 8.--10. "CSIZE,Channel x Chunk Size" "0: 1 data transferred,1: 2 data transferred,2: 4 data transferred,3: 8 data transferred,4: 16 data transferred,?,?,?"
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newline
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bitfld.long 0x18 7. "MEMSET,Channel x Fill Block of Memory" "0: Memset is not activated.,1: Sets the block of memory pointed by DA field to.."
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bitfld.long 0x18 6. "SWREQ,Channel x Software Request Trigger" "0: Hardware request line is connected to the..,1: Software request is connected to the peripheral.."
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newline
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bitfld.long 0x18 5. "PROT,Channel x Protection" "0: Channel uses Privileged mode.,1: Channel uses User mode."
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bitfld.long 0x18 4. "DSYNC,Channel x Synchronization" "0: Peripheral-to-memory transfer.,1: Memory-to-peripheral transfer."
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newline
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bitfld.long 0x18 1.--2. "MBSIZE,Channel x Memory Burst Size" "0: The memory burst size is set to one.,1: The memory burst size is set to four.,2: The memory burst size is set to eight.,3: The memory burst size is set to sixteen."
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bitfld.long 0x18 0. "TYPE,Channel x Transfer Type" "0: Self-triggered mode (memory-to-memory transfer).,1: Synchronized mode (peripheral-to-memory or.."
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line.long 0x1C "CDS_MSP,Channel Data Stride Memory Set Pattern"
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hexmask.long.word 0x1C 16.--31. 1. "DDS_MSP,Channel x Destination Data Stride or Memory Set Pattern"
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hexmask.long.word 0x1C 0.--15. 1. "SDS_MSP,Channel x Source Data stride or Memory Set Pattern"
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line.long 0x20 "CSUS,Channel Source Microblock Stride"
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hexmask.long.tbyte 0x20 0.--23. 1. "SUBS,Channel x Source Microblock Stride"
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line.long 0x24 "CDUS,Channel Destination Microblock Stride"
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hexmask.long.tbyte 0x24 0.--23. 1. "DUBS,Channel x Destination Microblock Stride"
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tree.end
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repeat.end
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repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x40098450 ad:0x40098490 ad:0x400984D0 ad:0x40098510 ad:0x40098550 ad:0x40098590 ad:0x400985D0 ad:0x40098610 ad:0x40098650 ad:0x40098690 ad:0x400986D0 ad:0x40098710 ad:0x40098750 ad:0x40098790 ad:0x400987D0 ad:0x40098810)
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tree "XDMAC_CHID[$1]"
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base $2
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wgroup.long ($2)++0x7
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line.long 0x0 "CIE,Channel Interrupt Enable Register"
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bitfld.long 0x0 6. "ROIE,Request Overflow Error Interrupt Enable Bit" "0,1"
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bitfld.long 0x0 5. "WBIE,Write Bus Error Interrupt Enable Bit" "0,1"
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newline
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bitfld.long 0x0 4. "RBIE,Read Bus Error Interrupt Enable Bit" "0,1"
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bitfld.long 0x0 3. "FIE,End of Flush Interrupt Enable Bit" "0,1"
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newline
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bitfld.long 0x0 2. "DIE,End of Disable Interrupt Enable Bit" "0,1"
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bitfld.long 0x0 1. "LIE,End of Linked List Interrupt Enable Bit" "0,1"
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newline
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bitfld.long 0x0 0. "BIE,End of Block Interrupt Enable Bit" "0,1"
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line.long 0x4 "CID,Channel Interrupt Disable Register"
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bitfld.long 0x4 6. "ROID,Request Overflow Error Interrupt Disable Bit" "0,1"
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bitfld.long 0x4 5. "WBEID,Write Bus Error Interrupt Disable Bit" "0,1"
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|
newline
|
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bitfld.long 0x4 4. "RBEID,Read Bus Error Interrupt Disable Bit" "0,1"
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bitfld.long 0x4 3. "FID,End of Flush Interrupt Disable Bit" "0,1"
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|
newline
|
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bitfld.long 0x4 2. "DID,End of Disable Interrupt Disable Bit" "0,1"
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|
bitfld.long 0x4 1. "LID,End of Linked List Interrupt Disable Bit" "0,1"
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|
newline
|
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bitfld.long 0x4 0. "BID,End of Block Interrupt Disable Bit" "0,1"
|
|
rgroup.long ($2+0x8)++0x7
|
|
line.long 0x0 "CIM,Channel Interrupt Mask Register"
|
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bitfld.long 0x0 6. "ROIM,Request Overflow Error Interrupt Mask Bit" "0,1"
|
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bitfld.long 0x0 5. "WBEIM,Write Bus Error Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RBEIM,Read Bus Error Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 3. "FIM,End of Flush Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DIM,End of Disable Interrupt Mask Bit" "0,1"
|
|
bitfld.long 0x0 1. "LIM,End of Linked List Interrupt Mask Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BIM,End of Block Interrupt Mask Bit" "0,1"
|
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line.long 0x4 "CIS,Channel Interrupt Status Register"
|
|
bitfld.long 0x4 6. "ROIS,Request Overflow Error Interrupt Status Bit" "0,1"
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|
bitfld.long 0x4 5. "WBEIS,Write Bus Error Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RBEIS,Read Bus Error Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 3. "FIS,End of Flush Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DIS,End of Disable Interrupt Status Bit" "0,1"
|
|
bitfld.long 0x4 1. "LIS,End of Linked List Interrupt Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "BIS,End of Block Interrupt Status Bit" "0,1"
|
|
group.long ($2+0x10)++0x27
|
|
line.long 0x0 "CSA,Channel Source Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "SA,Channel x Source Address"
|
|
line.long 0x4 "CDA,Channel Destination Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "DA,Channel x Destination Address"
|
|
line.long 0x8 "CNDA,Channel Next Descriptor Address Register"
|
|
hexmask.long 0x8 2.--31. 1. "NDA,Channel x Next Descriptor Address"
|
|
bitfld.long 0x8 0. "NDAIF,Channel x Next Descriptor Interface" "0,1"
|
|
line.long 0xC "CNDC,Channel Next Descriptor Control Register"
|
|
bitfld.long 0xC 3.--4. "NDVIEW,Channel x Next Descriptor View" "0: Next Descriptor View 0,1: Next Descriptor View 1,2: Next Descriptor View 2,3: Next Descriptor View 3"
|
|
bitfld.long 0xC 2. "NDDUP,Channel x Next Descriptor Destination Update" "0: Destination parameters remain unchanged.,1: Destination parameters are updated when the.."
|
|
newline
|
|
bitfld.long 0xC 1. "NDSUP,Channel x Next Descriptor Source Update" "0: Source parameters remain unchanged.,1: Source parameters are updated when the.."
|
|
bitfld.long 0xC 0. "NDE,Channel x Next Descriptor Enable" "0: Descriptor fetch is disabled.,1: Descriptor fetch is enabled."
|
|
line.long 0x10 "CUBC,Channel Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "UBLEN,Channel x Microblock Length"
|
|
line.long 0x14 "CBC,Channel Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. "BLEN,Channel x Block Length"
|
|
line.long 0x18 "CC,Channel Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. "PERID,Channel x Peripheral Hardware Request Line Identifier"
|
|
bitfld.long 0x18 23. "WRIP,Write in Progress (this bit is read-only)" "0: No active write transaction on the bus.,1: A write transaction is in progress."
|
|
newline
|
|
bitfld.long 0x18 22. "RDIP,Read in Progress (this bit is read-only)" "0: No active read transaction on the bus.,1: A read transaction is in progress."
|
|
bitfld.long 0x18 21. "INITD,Channel Initialization Done (this bit is read-only)" "0: Channel initialization is in progress.,1: Channel initialization is completed."
|
|
newline
|
|
bitfld.long 0x18 18.--19. "DAM,Channel x Destination Addressing Mode" "0: The address remains unchanged.,1: The addressing mode is incremented (the..,2: The microblock stride is added at the microblock..,3: The microblock stride is added at the microblock.."
|
|
bitfld.long 0x18 16.--17. "SAM,Channel x Source Addressing Mode" "0: The address remains unchanged.,1: The addressing mode is incremented (the..,2: The microblock stride is added at the microblock..,3: The microblock stride is added at the microblock.."
|
|
newline
|
|
bitfld.long 0x18 14. "DIF,Channel x Destination Interface Identifier" "0: The data is written through system bus interface..,1: The data is written though system bus interface 1."
|
|
bitfld.long 0x18 13. "SIF,Channel x Source Interface Identifier" "0: The data is read through system bus interface 0.,1: The data is read through system bus interface 1."
|
|
newline
|
|
bitfld.long 0x18 11.--12. "DWIDTH,Channel x Data Width" "0: The data size is set to 8 bits,1: The data size is set to 16 bits,2: The data size is set to 32 bits,?"
|
|
bitfld.long 0x18 8.--10. "CSIZE,Channel x Chunk Size" "0: 1 data transferred,1: 2 data transferred,2: 4 data transferred,3: 8 data transferred,4: 16 data transferred,?,?,?"
|
|
newline
|
|
bitfld.long 0x18 7. "MEMSET,Channel x Fill Block of Memory" "0: Memset is not activated.,1: Sets the block of memory pointed by DA field to.."
|
|
bitfld.long 0x18 6. "SWREQ,Channel x Software Request Trigger" "0: Hardware request line is connected to the..,1: Software request is connected to the peripheral.."
|
|
newline
|
|
bitfld.long 0x18 5. "PROT,Channel x Protection" "0: Channel uses Privileged mode.,1: Channel uses User mode."
|
|
bitfld.long 0x18 4. "DSYNC,Channel x Synchronization" "0: Peripheral-to-memory transfer.,1: Memory-to-peripheral transfer."
|
|
newline
|
|
bitfld.long 0x18 1.--2. "MBSIZE,Channel x Memory Burst Size" "0: The memory burst size is set to one.,1: The memory burst size is set to four.,2: The memory burst size is set to eight.,3: The memory burst size is set to sixteen."
|
|
bitfld.long 0x18 0. "TYPE,Channel x Transfer Type" "0: Self-triggered mode (memory-to-memory transfer).,1: Synchronized mode (peripheral-to-memory or.."
|
|
line.long 0x1C "CDS_MSP,Channel Data Stride Memory Set Pattern"
|
|
hexmask.long.word 0x1C 16.--31. 1. "DDS_MSP,Channel x Destination Data Stride or Memory Set Pattern"
|
|
hexmask.long.word 0x1C 0.--15. 1. "SDS_MSP,Channel x Source Data stride or Memory Set Pattern"
|
|
line.long 0x20 "CSUS,Channel Source Microblock Stride"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. "SUBS,Channel x Source Microblock Stride"
|
|
line.long 0x24 "CDUS,Channel Destination Microblock Stride"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. "DUBS,Channel x Destination Microblock Stride"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
AUTOINDENT.OFF
|