1745 lines
125 KiB
Plaintext
1745 lines
125 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: S3F401F On-Chip Peripherals
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; @Props: Released
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; @Author: PSS
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; @Changelog: 2011-07-12 PSS
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; @Manufacturer: SAMSUNG - Samsung Semiconductor
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; @Doc: 467435um_s3f401f_rev10.pdf
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; @Core: ARM7TDMI-S
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; @Chip: S3F401F
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pers3f401.per 12528 2020-11-12 13:57:39Z bschroefel $
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; Known problems:
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; in 467435um_s3f401f_rev10.pdf there are many errors concerning described bits (some of the shown bits are undescribed and some of described bits do not exist).
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config 16. 8.
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width 0x0b
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base ad:0x3ff0000
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tree "ICEBreaker"
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width 8.
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group ice:0x8--0x0d "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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group ice:0x10--0x15 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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tree.end
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tree "ADC (A/D Converter)"
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base ad:0xFF040000
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width 12.
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group.long 0x00++0x03
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line.long 0x00 "ADCCON,ADC Control Register"
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bitfld.long 0x00 20.--23. " SHA3SEL ,ADC Input Selection Field for SHA3" "AIN0,AIN1,AIN2,AIN3,AIN4,AIN5,AIN6,AIN7,AIN8,AIN9,AIN10,AIN11,AIN12,AIN13,AIN14,AIN15"
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bitfld.long 0x00 16.--19. " SHA2SEL ,ADC Input Selection Field for SHA2" "AIN0,AIN1,AIN2,AIN3,AIN4,AIN5,AIN6,AIN7,AIN8,AIN9,AIN10,AIN11,AIN12,AIN13,AIN14,AIN15"
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bitfld.long 0x00 12.--15. " SHA1SEL ,ADC Input Selection Field for SHA1" "AIN0,AIN1,AIN2,AIN3,AIN4,AIN5,AIN6,AIN7,AIN8,AIN9,AIN10,AIN11,AIN12,AIN13,AIN14,AIN15"
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bitfld.long 0x00 8.--9. " MODESEL ,ADC Mode Selection Field" "3-point simultaneous sampling,1-point sampling,2-point simultaneous sampling,?..."
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textline " "
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bitfld.long 0x00 6. " TRIGEDGESEL ,ADC Trigger Edge Selection Bit for ADTRG pin" "Falling edge,Rising edge"
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bitfld.long 0x00 4.--5. " CLKSEL ,ADC Clock (ADCCLK) Selection Field" "Fin,Fin/2,Fin/4,Fin/8"
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bitfld.long 0x00 2.--3. " TRIGSEL ,ADC Start Trigger Signal Selection Field" "Software,Inverter block,ADCTRG pin,ADCTRG pin"
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bitfld.long 0x00 1. " EN ,ADC Block Enable Bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 0. " START ,ADC Conversion Start Bit" "No effect,Start"
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rgroup.long 0x04++0x0F
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line.long 0x00 "ADCSTATUS,ADC Status Register"
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bitfld.long 0x00 0. " STATUS ,ADC Status Monitoring Bit" "Not operating,Operating"
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line.long 0x04 "ADCRESULT1,ADC Converter Data1 Register"
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hexmask.long.word 0x04 0.--11. 1. " DATA1 ,A/D Converted Output Data Value"
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line.long 0x08 "ADCRESULT2,ADC Converter Data2 Register"
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hexmask.long.word 0x08 0.--11. 1. " DATA2 ,A/D Converted Output Data Value"
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line.long 0x0C "ADCRESULT3,ADC Converter Data3 Register"
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hexmask.long.word 0x0C 0.--11. 1. " DATA3 ,A/D Converted Output Data Value"
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width 11.
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tree.end
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tree "BT/WDT (Basic Timer & Watchdog Timer)"
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base ad:0xFF004000
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width 7.
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group.long 0x00++0x03
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line.long 0x00 "BTCON,Basic Timer Control Register"
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hexmask.long.byte 0x00 8.--15. 1. " WDTE ,Watchdog Timer Enable Bit"
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bitfld.long 0x00 2.--3. " CS ,Clock Source Select Field" "Fin / 2^12,Fin / 2^10,Fin / 2^6,Fin / 2^5"
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bitfld.long 0x00 1. " BTC ,Basic Timer Clear Bit" "No effect,Clear"
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bitfld.long 0x00 0. " WDTC ,Watch-Dog Timer Clear Bit" "No effect,Clear"
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rgroup.long 0x04++0x03
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line.long 0x00 "BTCNT,Basic Timer Count Register"
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bitfld.long 0x00 8.--10. " WCV ,Watchdog Timer Count Value Field" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x00 0.--7. 1. " BCV ,Basic Timer Count Value Field"
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width 11.
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tree.end
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tree.open "ENC (Encoder Counter)"
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tree "ENC0"
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base ad:0xFF028000
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width 11.
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group.long 0x00++0x2B
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line.long 0x00 "ENCCON0,Encoder Counter Control Register 0"
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bitfld.long 0x00 11. " DBGEN ,Debug Enable Bit" "Halted,Not halted"
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bitfld.long 0x00 8.--10. " ENCCLKSEL ,Encoder Counter Clock (DECCLK) Selection Field" "ENCCLK,ENCCLK/2,ENCCLK/4,ENCCLK/8,ENCCLK/16,ENCCLK/32,ENCCLK/64,ENCCLK/128"
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bitfld.long 0x00 7. " PZCLEN ,PCNT Clear Enable by Phase Z" "Enabled,Disabled"
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bitfld.long 0x00 4.--6. " ENCFILTER ,Filter Clock Selection Field of Encoder Counter" "ENCCLK,ENCCLK/2,ENCCLK/4,ENCCLK/8,ENCCLK/16,ENCCLK/32,ENCCLK/64,ENCCLK/128"
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textline " "
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bitfld.long 0x00 3. " ESELZ ,Phase Z Edge Type Selection Field" "Falling edge,Rising edge"
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bitfld.long 0x00 2. " ENCEN ,Encoder Counter Block Enable Bit" "Disabled,Enabled"
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bitfld.long 0x00 1. " SCNTCL ,Speed Counter (SCNT) Clear Bit" "No effect,Clear"
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bitfld.long 0x00 0. " PCNTCL ,Position Counter (PCNT) Clear Bit" "No effect,Clear"
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line.long 0x04 "ENCCON1,Encoder Counter Control Register 1"
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bitfld.long 0x04 11. " DBGEN ,Debug Enable Bit" "Halted,Not halted"
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bitfld.long 0x04 8.--10. " ENCCLKSEL ,Encoder Counter Clock (DECCLK) Selection Field" "ENCCLK,ENCCLK/2,ENCCLK/4,ENCCLK/8,ENCCLK/16,ENCCLK/32,ENCCLK/64,ENCCLK/128"
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bitfld.long 0x04 7. " PZCLEN ,PCNT Clear Enable by Phase Z" "Enabled,Disabled"
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bitfld.long 0x04 4.--6. " ENCFILTER ,Filter Clock Selection Field of Encoder Counter" "ENCCLK,ENCCLK/2,ENCCLK/4,ENCCLK/8,ENCCLK/16,ENCCLK/32,ENCCLK/64,ENCCLK/128"
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textline " "
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bitfld.long 0x04 3. " ESELZ ,Phase Z Edge Type Selection Field" "Falling edge,Rising edge"
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bitfld.long 0x04 2. " ENCEN ,Encoder Counter Block Enable Bit" "Disabled,Enabled"
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bitfld.long 0x04 1. " SCNTCL ,Speed Counter (SCNT) Clear Bit" "No effect,Cleared"
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bitfld.long 0x04 0. " PCNTCL ,Position Counter (PCNT) Clear Bit" "No effect,Cleared"
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line.long 0x08 "ENCSTATUS,Encoder Counter Status Register"
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bitfld.long 0x08 3. " PASTAT ,Phase A Status Bit" "Low,High"
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bitfld.long 0x08 2. " PBSTAT ,Phase B Status Bit" "Low,High"
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bitfld.long 0x08 1. " GLITCH ,Glitch Detection Field of Phase A, Phase B and Phase Z" "Not occurred,Occurred"
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bitfld.long 0x08 0. " DIRECTION ,Direction of Motor Rotation Bit" "PCNT increased,PCNT decreased"
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line.long 0x0C "PCNT,16 Bit Position Counter Register"
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hexmask.long.word 0x0C 0.--15. 1. " PCV ,The Current Position Counter Value Field"
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line.long 0x10 "PREF,16 Bit Position Reference Register"
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hexmask.long.word 0x10 0.--15. 1. " PREFDAT ,The Reference Value for Position Counter"
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line.long 0x14 "SCNT,16 Bit Speed Counter Register"
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hexmask.long.word 0x14 0.--15. 1. " SCV ,The Current Speed Counter Value Field"
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line.long 0x18 "SREF,16 Bit Speed Reference Register"
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hexmask.long.word 0x18 0.--15. 1. " SREFDAT ,The Reference Value for Speed Counter"
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line.long 0x1C "PACNT,16 Bit Phase A Capture Counter Register"
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hexmask.long.word 0x1C 0.--15. 1. " PACV ,The Phase A Capture Counter Value Field"
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line.long 0x20 "PACAP,16 Bit Phase A Capture Data Register"
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hexmask.long.word 0x20 0.--15. 1. " PACAPDAT ,The Phase A Captured Value Field"
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line.long 0x24 "PBCNT,16 Bit t Phase B Capture Counter Register"
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hexmask.long.word 0x24 0.--15. 1. " PBCV ,The Phase B Capture Counter Value Field"
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line.long 0x28 "PBCAP,16 Bit Phase B Capture Data Register"
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hexmask.long.word 0x28 0.--15. 1. " PBCAPDAT ,The Phase B Captured Value Field"
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width 11.
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tree.end
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tree "ENC1"
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base ad:0xFF02C000
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width 11.
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group.long 0x00++0x2B
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line.long 0x00 "ENCCON0,Encoder Counter Control Register 0"
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bitfld.long 0x00 11. " DBGEN ,Debug Enable Bit" "Halted,Not halted"
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bitfld.long 0x00 8.--10. " ENCCLKSEL ,Encoder Counter Clock (DECCLK) Selection Field" "ENCCLK,ENCCLK/2,ENCCLK/4,ENCCLK/8,ENCCLK/16,ENCCLK/32,ENCCLK/64,ENCCLK/128"
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bitfld.long 0x00 7. " PZCLEN ,PCNT Clear Enable by Phase Z" "Enabled,Disabled"
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bitfld.long 0x00 4.--6. " ENCFILTER ,Filter Clock Selection Field of Encoder Counter" "ENCCLK,ENCCLK/2,ENCCLK/4,ENCCLK/8,ENCCLK/16,ENCCLK/32,ENCCLK/64,ENCCLK/128"
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textline " "
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bitfld.long 0x00 3. " ESELZ ,Phase Z Edge Type Selection Field" "Falling edge,Rising edge"
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bitfld.long 0x00 2. " ENCEN ,Encoder Counter Block Enable Bit" "Disabled,Enabled"
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bitfld.long 0x00 1. " SCNTCL ,Speed Counter (SCNT) Clear Bit" "No effect,Clear"
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bitfld.long 0x00 0. " PCNTCL ,Position Counter (PCNT) Clear Bit" "No effect,Clear"
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line.long 0x04 "ENCCON1,Encoder Counter Control Register 1"
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bitfld.long 0x04 11. " DBGEN ,Debug Enable Bit" "Halted,Not halted"
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bitfld.long 0x04 8.--10. " ENCCLKSEL ,Encoder Counter Clock (DECCLK) Selection Field" "ENCCLK,ENCCLK/2,ENCCLK/4,ENCCLK/8,ENCCLK/16,ENCCLK/32,ENCCLK/64,ENCCLK/128"
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bitfld.long 0x04 7. " PZCLEN ,PCNT Clear Enable by Phase Z" "Enabled,Disabled"
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bitfld.long 0x04 4.--6. " ENCFILTER ,Filter Clock Selection Field of Encoder Counter" "ENCCLK,ENCCLK/2,ENCCLK/4,ENCCLK/8,ENCCLK/16,ENCCLK/32,ENCCLK/64,ENCCLK/128"
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textline " "
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bitfld.long 0x04 3. " ESELZ ,Phase Z Edge Type Selection Field" "Falling edge,Rising edge"
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bitfld.long 0x04 2. " ENCEN ,Encoder Counter Block Enable Bit" "Disabled,Enabled"
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bitfld.long 0x04 1. " SCNTCL ,Speed Counter (SCNT) Clear Bit" "No effect,Cleared"
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bitfld.long 0x04 0. " PCNTCL ,Position Counter (PCNT) Clear Bit" "No effect,Cleared"
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line.long 0x08 "ENCSTATUS,Encoder Counter Status Register"
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bitfld.long 0x08 3. " PASTAT ,Phase A Status Bit" "Low,High"
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bitfld.long 0x08 2. " PBSTAT ,Phase B Status Bit" "Low,High"
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bitfld.long 0x08 1. " GLITCH ,Glitch Detection Field of Phase A, Phase B and Phase Z" "Not occurred,Occurred"
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bitfld.long 0x08 0. " DIRECTION ,Direction of Motor Rotation Bit" "PCNT increased,PCNT decreased"
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line.long 0x0C "PCNT,16 Bit Position Counter Register"
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hexmask.long.word 0x0C 0.--15. 1. " PCV ,The Current Position Counter Value Field"
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line.long 0x10 "PREF,16 Bit Position Reference Register"
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hexmask.long.word 0x10 0.--15. 1. " PREFDAT ,The Reference Value for Position Counter"
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line.long 0x14 "SCNT,16 Bit Speed Counter Register"
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hexmask.long.word 0x14 0.--15. 1. " SCV ,The Current Speed Counter Value Field"
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line.long 0x18 "SREF,16 Bit Speed Reference Register"
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hexmask.long.word 0x18 0.--15. 1. " SREFDAT ,The Reference Value for Speed Counter"
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line.long 0x1C "PACNT,16 Bit Phase A Capture Counter Register"
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hexmask.long.word 0x1C 0.--15. 1. " PACV ,The Phase A Capture Counter Value Field"
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line.long 0x20 "PACAP,16 Bit Phase A Capture Data Register"
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hexmask.long.word 0x20 0.--15. 1. " PACAPDAT ,The Phase A Captured Value Field"
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line.long 0x24 "PBCNT,16 Bit t Phase B Capture Counter Register"
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hexmask.long.word 0x24 0.--15. 1. " PBCV ,The Phase B Capture Counter Value Field"
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line.long 0x28 "PBCAP,16 Bit Phase B Capture Data Register"
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hexmask.long.word 0x28 0.--15. 1. " PBCAPDAT ,The Phase B Captured Value Field"
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width 11.
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tree.end
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tree.end
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tree "IFC (Internal Flash ROM)"
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base ad:0xFFF00000
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width 8.
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wgroup.long 0x00++0x03
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line.long 0x00 "FMKEY,Flash Memory Key Register"
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hexmask.long 0x00 0.--31. 1. " FMKEYDAT ,Flash Memory Key"
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group.long 0x04++0x0B
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line.long 0x00 "FMADDR,Flash Memory Address Register"
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hexmask.long 0x00 0.--31. 1. " FMADDRDAT ,Flash Memory Address"
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line.long 0x04 "FMDATA,Flash Memory Data Register"
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hexmask.long 0x04 0.--31. 1. " FMDATADAT ,Flash Memory Data"
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line.long 0x08 "FMUCON,Flash Memory Control Register"
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bitfld.long 0x08 8. " INTERLEAVE ,Flash Memory Operation Mode Bit" "Not interleave mode,Interleave mode"
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bitfld.long 0x08 7. " UOSCEN ,Count Clock Enable Bit" "Disabled,Enabled"
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bitfld.long 0x08 6. " USTRSTPT ,Operation Start Bit" "Stop,Start"
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bitfld.long 0x08 5. " UOPGMR ,Option Program Enable Bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x08 3. " UCPUH ,CPU Hold Control Bit" "Work,Hold"
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bitfld.long 0x08 2. " UPGMR ,Normal Program Enable Bit" "Disabled,Enabled"
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bitfld.long 0x08 1. " USERSR ,Sector Erase Enable Bit" "Disabled,Enabled"
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bitfld.long 0x08 0. " UCERSR ,Chip Erase Enable Bit" "Disabled,Enabled"
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rgroup.long 0x10++0x07
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line.long 0x00 "FSO,Smart Option Bits Read Register"
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hexmask.long 0x00 0.--31. 1. " FSODAT ,Smart Option"
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line.long 0x04 "FPO,Protection Option Bits Read Register"
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hexmask.long 0x04 0.--31. 1. " FPODAT ,Smart Option"
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width 11.
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tree.end
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tree.open "IMC (Inverter Motor Controller)"
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tree "IMC0"
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base ad:0xFF020000
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width 13.
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group.long 0x00++0x0F
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line.long 0x00 "IMCON0,Inverter Motor Control Register 0"
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bitfld.long 0x00 28. " DBGEN ,Debug Enable Bit" "Halted,Not halted"
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bitfld.long 0x00 26.--27. " SYNCSEL ,Synchronous Write Time Selection Field" "ZERO and TOPCMP,ZERO,TOPCMP,?..."
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bitfld.long 0x00 20.--24. " NUMSKIP ,Numbers of Skip for Motor Match Interrupt Field" "No skip,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--18. " IMCLKSEL ,Inverter Clock (IMCLK) Selection Field" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,PCLK/128"
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textline " "
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bitfld.long 0x00 14. " PWMOUTEN ,PWM Output Enable Bit" "Enabled,Disabled"
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bitfld.long 0x00 13. " PWMOUTOFFEN ,PWM Output Disable by PWMxOFF" "Disabled,Enabled"
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bitfld.long 0x00 12. " PWMOFFEN ,PWMxOFF Enable Bit" "Disabled,Enabled"
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bitfld.long 0x00 8.--10. " IMFILTER ,Filter Clock Selection of PWMxOFF pin" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,PCLK/128"
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textline " "
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bitfld.long 0x00 6.--7. " ESELPWMOFF ,PWMxOFF Active Type Selection Field" "Falling edge,Rising edge,Low level,High level"
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bitfld.long 0x00 5. " PWMPOLD ,PWMxD0/1/2s Polarity Selection Bit" "Low start,High start"
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bitfld.long 0x00 4. " PWMPOLU ,PWMxU0/1/ 2s Polarity Selection Bit" "Low start,High start"
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bitfld.long 0x00 3. " PWMSWAP ,Swapping of PWMxUx and PWMxDx" "No swap,Swap"
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textline " "
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bitfld.long 0x00 2. " WMODE ,Write Mode Selection of Compare Register" "Immediate,Synchronous"
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bitfld.long 0x00 1. " IMMODE ,Inverter Motor Mode Selection Bit" "Tri-angular shape,Saw-tooth shape"
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bitfld.long 0x00 0. " IMEN ,Inverter Motor Block Enable/Disable Control Bit" "Disabled,Enabled"
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line.long 0x04 "IMCON1,Inverter Motor Control Register 1"
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bitfld.long 0x04 21. " PWMxU0DT ,PWMxU0 Dead-time Insert Bit: before PWM output disable by setting PWMxU0EN" "No insertion,Insertion"
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bitfld.long 0x04 20. " PWMxU1DT ,PWMxU1 Dead-time Insert Bit: before PWM output disable by setting PWMxU1EN" "No insertion,Insertion"
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bitfld.long 0x04 19. " PWMxU2DT ,PWMxU2 Dead-time Insert Bit: before PWM output disable by setting PWMxU2EN" "No insertion,Insertion"
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bitfld.long 0x04 18. " PWMxD0DT ,PWMxD0 Dead-time Insert Bit: before PWM output disable by setting PWMxD0EN" "No insertion,Insertion"
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textline " "
|
|
bitfld.long 0x04 17. " PWMxD1DT ,PWMxD1 Dead-time Insert Bit: before PWM output disable by setting PWMxD1EN" "No insertion,Insertion"
|
|
bitfld.long 0x04 16. " PWMxD2DT ,PWMxD2 Dead-time Insert Bit: before PWM output disable by setting PWMxD2EN" "No insertion,Insertion"
|
|
bitfld.long 0x04 13. " PWMxU0LEVEL ,PWMxU0 Output Level Selection Bit" "Low level,High level"
|
|
bitfld.long 0x04 12. " PWMxU1LEVEL ,PWMxU1 Output Level Selection Bit" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PWMxU2LEVEL ,PWMxU2 Output Level Selection Bit" "Low level,High level"
|
|
bitfld.long 0x04 10. " PWMxD0LEVEL ,PWMxD0 Output Level Selection Bit" "Low level,High level"
|
|
bitfld.long 0x04 9. " PWMxD1LEVEL ,PWMxD1 Output Level Selection Bit" "Low level,High level"
|
|
bitfld.long 0x04 8. " PWMxD2LEVEL ,PWMxD2 Output Level Selection Bit" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PWMxU0EN ,PWMxU0 PWM Output Enable Bit" "Enabled,Disabled"
|
|
bitfld.long 0x04 4. " PWMxU1EN ,PWMxU1 PWM Output Enable Bit" "Enabled,Disabled"
|
|
bitfld.long 0x04 3. " PWMxU2EN ,PWMxU2 PWM Output Enable Bit" "Enabled,Disabled"
|
|
bitfld.long 0x04 2. " PWMxD0EN ,PWMxD0 PWM Output Enable Bit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PWMxD1EN ,PWMxD1 PWM Output Enable Bit" "Enabled,Disabled"
|
|
bitfld.long 0x04 0. " PWMxD2EN ,PWMxD2 PWM Output Enable Bit" "Enabled,Disabled"
|
|
line.long 0x08 "IMSTATUS,Inverter Motor Status Register"
|
|
bitfld.long 0x08 1. " UPDOWNSTAT ,Status of PWM Counter" "Up counting,Down counting"
|
|
bitfld.long 0x08 0. " FAULTSTAT ,Status of PWM Output Signal" "Normal,High-Z"
|
|
line.long 0x0C "ADCSTARETSEL,ADC Start Signal Select Register"
|
|
bitfld.long 0x0C 3. " ADCCMPF0SEL ,Enable ADC Start Trigger Signal by ADCCMPF0 Match" "Not selected,Selected"
|
|
bitfld.long 0x0C 2. " ADCCMPR0SEL ,Enable ADC Start Trigger Signal by ADCCMPR0 Match" "Not selected,Selected"
|
|
bitfld.long 0x0C 1. " 0SEL ,Enable ADC Start Trigger Signal by Counter Zero Match" "Not selected,Selected"
|
|
bitfld.long 0x0C 0. " TOPCMPSEL ,Enable ADC Start Trigger Signal by TOPCMP Match" "Not selected,Selected"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IMCNT,16-Bit Inverter Motor Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,The Current IMC Count Value"
|
|
group.long 0x14++0x3B
|
|
line.long 0x00 "TOPCMP,16-Bit Top Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TOPCMPDAT ,Determine the TOP Compare Register Value"
|
|
line.long 0x08 "PACMPR,16-Bit Phase A Compare Register of Rising"
|
|
hexmask.long.word 0x08 0.--15. 1. " PACMPRDAT ,Determine the Phase A Compare Register Value at Rising"
|
|
line.long 0x0C "PACMPF,16-Bit Phase A Compare Register of Falling"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PACMPFDAT ,Determine the Phase A Compare Register Value at Falling"
|
|
line.long 0x10 "PBCMPR,16-Bit Phase B Compare Register of Rising"
|
|
hexmask.long.word 0x10 0.--15. 1. " PBCMPRDAT ,Determine the Phase B Compare Register Value at Rising"
|
|
line.long 0x14 "PBCMPR,16-Bit Phase B Compare Register of Falling"
|
|
hexmask.long.word 0x14 0.--15. 1. " PBCMPFDAT ,Determine the Phase B Compare Register Value at Falling"
|
|
line.long 0x18 "PCCMPR,16-Bit Phase C Compare Register of Rising"
|
|
hexmask.long.word 0x18 0.--15. 1. " PCCMPRDAT ,Determine the Phase C Compare Register Value at Rising"
|
|
line.long 0x1C "PCCMPR,16-Bit Phase C Compare Register of Falling"
|
|
hexmask.long.word 0x1C 0.--15. 1. " PCCMPRDAT ,Determine the Phase C Compare Register Value at Falling"
|
|
line.long 0x20 "ADCCMPR0,16-Bit ADC Start Compare Register of Rising 0"
|
|
hexmask.long.word 0x20 0.--15. 1. " ADCCMPR0DAT ,Determine the ADC0 Compare Register Value at Rising"
|
|
line.long 0x24 "ADCCMPF0,16-Bit ADC Start Compare Register of Falling 0"
|
|
hexmask.long.word 0x24 0.--15. 1. " ADCCMPF0DAT ,Determine the ADC0 Compare Register Value at Falling"
|
|
line.long 0x28 "ADCCMPR1,16-Bit ADC Start Compare Register of Rising 1"
|
|
hexmask.long.word 0x28 0.--15. 1. " ADCCMPR1DAT ,Determine the ADC1 Compare Register Value at Rising"
|
|
line.long 0x2C "ADCCMPF1,16-Bit ADC Start Compare Register of Falling 1"
|
|
hexmask.long.word 0x2C 0.--15. 1. " ADCCMPF1DAT ,Determine the ADC1 Compare Register Value at Falling"
|
|
line.long 0x30 "ADCCMPR2DAT,16-Bit ADC Start Compare Register of Rising 2"
|
|
hexmask.long.word 0x30 0.--15. 1. " ADCCMPR2DAT ,Determine the ADC2 Compare Register Value at Rising"
|
|
line.long 0x34 "ADCCMPF2DAT,16-Bit ADC Start Compare Register of Falling 2"
|
|
hexmask.long.word 0x34 0.--15. 1. " ADCCMPF2DAT ,Determine the ADC2 Compare Register Value at Falling"
|
|
line.long 0x38 "DTCMPDAT,16-Bit Dead-time Compare Register"
|
|
hexmask.long.word 0x38 0.--15. 1. " DTCMPDAT ,Determine the Dead-time Compare Register Value"
|
|
width 11.
|
|
tree.end
|
|
tree "IMC1"
|
|
base ad:0xFF024000
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "IMCON0,Inverter Motor Control Register 0"
|
|
bitfld.long 0x00 28. " DBGEN ,Debug Enable Bit" "Halted,Not halted"
|
|
bitfld.long 0x00 26.--27. " SYNCSEL ,Synchronous Write Time Selection Field" "ZERO and TOPCMP,ZERO,TOPCMP,?..."
|
|
bitfld.long 0x00 20.--24. " NUMSKIP ,Numbers of Skip for Motor Match Interrupt Field" "No skip,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--18. " IMCLKSEL ,Inverter Clock (IMCLK) Selection Field" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,PCLK/128"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PWMOUTEN ,PWM Output Enable Bit" "Enabled,Disabled"
|
|
bitfld.long 0x00 13. " PWMOUTOFFEN ,PWM Output Disable by PWMxOFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PWMOFFEN ,PWMxOFF Enable Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " IMFILTER ,Filter Clock Selection of PWMxOFF pin" "PCLK,PCLK/2,PCLK/4,PCLK/8,PCLK/16,PCLK/32,PCLK/64,PCLK/128"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ESELPWMOFF ,PWMxOFF Active Type Selection Field" "Falling edge,Rising edge,Low level,High level"
|
|
bitfld.long 0x00 5. " PWMPOLD ,PWMxD0/1/2s Polarity Selection Bit" "Low start,High start"
|
|
bitfld.long 0x00 4. " PWMPOLU ,PWMxU0/1/ 2s Polarity Selection Bit" "Low start,High start"
|
|
bitfld.long 0x00 3. " PWMSWAP ,Swapping of PWMxUx and PWMxDx" "No swap,Swap"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WMODE ,Write Mode Selection of Compare Register" "Immediate,Synchronous"
|
|
bitfld.long 0x00 1. " IMMODE ,Inverter Motor Mode Selection Bit" "Tri-angular shape,Saw-tooth shape"
|
|
bitfld.long 0x00 0. " IMEN ,Inverter Motor Block Enable/Disable Control Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IMCON1,Inverter Motor Control Register 1"
|
|
bitfld.long 0x04 21. " PWMxU0DT ,PWMxU0 Dead-time Insert Bit: before PWM output disable by setting PWMxU0EN" "No insertion,Insertion"
|
|
bitfld.long 0x04 20. " PWMxU1DT ,PWMxU1 Dead-time Insert Bit: before PWM output disable by setting PWMxU1EN" "No insertion,Insertion"
|
|
bitfld.long 0x04 19. " PWMxU2DT ,PWMxU2 Dead-time Insert Bit: before PWM output disable by setting PWMxU2EN" "No insertion,Insertion"
|
|
bitfld.long 0x04 18. " PWMxD0DT ,PWMxD0 Dead-time Insert Bit: before PWM output disable by setting PWMxD0EN" "No insertion,Insertion"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PWMxD1DT ,PWMxD1 Dead-time Insert Bit: before PWM output disable by setting PWMxD1EN" "No insertion,Insertion"
|
|
bitfld.long 0x04 16. " PWMxD2DT ,PWMxD2 Dead-time Insert Bit: before PWM output disable by setting PWMxD2EN" "No insertion,Insertion"
|
|
bitfld.long 0x04 13. " PWMxU0LEVEL ,PWMxU0 Output Level Selection Bit" "Low level,High level"
|
|
bitfld.long 0x04 12. " PWMxU1LEVEL ,PWMxU1 Output Level Selection Bit" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PWMxU2LEVEL ,PWMxU2 Output Level Selection Bit" "Low level,High level"
|
|
bitfld.long 0x04 10. " PWMxD0LEVEL ,PWMxD0 Output Level Selection Bit" "Low level,High level"
|
|
bitfld.long 0x04 9. " PWMxD1LEVEL ,PWMxD1 Output Level Selection Bit" "Low level,High level"
|
|
bitfld.long 0x04 8. " PWMxD2LEVEL ,PWMxD2 Output Level Selection Bit" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PWMxU0EN ,PWMxU0 PWM Output Enable Bit" "Enabled,Disabled"
|
|
bitfld.long 0x04 4. " PWMxU1EN ,PWMxU1 PWM Output Enable Bit" "Enabled,Disabled"
|
|
bitfld.long 0x04 3. " PWMxU2EN ,PWMxU2 PWM Output Enable Bit" "Enabled,Disabled"
|
|
bitfld.long 0x04 2. " PWMxD0EN ,PWMxD0 PWM Output Enable Bit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PWMxD1EN ,PWMxD1 PWM Output Enable Bit" "Enabled,Disabled"
|
|
bitfld.long 0x04 0. " PWMxD2EN ,PWMxD2 PWM Output Enable Bit" "Enabled,Disabled"
|
|
line.long 0x08 "IMSTATUS,Inverter Motor Status Register"
|
|
bitfld.long 0x08 1. " UPDOWNSTAT ,Status of PWM Counter" "Up counting,Down counting"
|
|
bitfld.long 0x08 0. " FAULTSTAT ,Status of PWM Output Signal" "Normal,High-Z"
|
|
line.long 0x0C "ADCSTARETSEL,ADC Start Signal Select Register"
|
|
bitfld.long 0x0C 3. " ADCCMPF0SEL ,Enable ADC Start Trigger Signal by ADCCMPF0 Match" "Not selected,Selected"
|
|
bitfld.long 0x0C 2. " ADCCMPR0SEL ,Enable ADC Start Trigger Signal by ADCCMPR0 Match" "Not selected,Selected"
|
|
bitfld.long 0x0C 1. " 0SEL ,Enable ADC Start Trigger Signal by Counter Zero Match" "Not selected,Selected"
|
|
bitfld.long 0x0C 0. " TOPCMPSEL ,Enable ADC Start Trigger Signal by TOPCMP Match" "Not selected,Selected"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IMCNT,16-Bit Inverter Motor Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,The Current IMC Count Value"
|
|
group.long 0x14++0x3B
|
|
line.long 0x00 "TOPCMP,16-Bit Top Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TOPCMPDAT ,Determine the TOP Compare Register Value"
|
|
line.long 0x08 "PACMPR,16-Bit Phase A Compare Register of Rising"
|
|
hexmask.long.word 0x08 0.--15. 1. " PACMPRDAT ,Determine the Phase A Compare Register Value at Rising"
|
|
line.long 0x0C "PACMPF,16-Bit Phase A Compare Register of Falling"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PACMPFDAT ,Determine the Phase A Compare Register Value at Falling"
|
|
line.long 0x10 "PBCMPR,16-Bit Phase B Compare Register of Rising"
|
|
hexmask.long.word 0x10 0.--15. 1. " PBCMPRDAT ,Determine the Phase B Compare Register Value at Rising"
|
|
line.long 0x14 "PBCMPR,16-Bit Phase B Compare Register of Falling"
|
|
hexmask.long.word 0x14 0.--15. 1. " PBCMPFDAT ,Determine the Phase B Compare Register Value at Falling"
|
|
line.long 0x18 "PCCMPR,16-Bit Phase C Compare Register of Rising"
|
|
hexmask.long.word 0x18 0.--15. 1. " PCCMPRDAT ,Determine the Phase C Compare Register Value at Rising"
|
|
line.long 0x1C "PCCMPR,16-Bit Phase C Compare Register of Falling"
|
|
hexmask.long.word 0x1C 0.--15. 1. " PCCMPRDAT ,Determine the Phase C Compare Register Value at Falling"
|
|
line.long 0x20 "ADCCMPR0,16-Bit ADC Start Compare Register of Rising 0"
|
|
hexmask.long.word 0x20 0.--15. 1. " ADCCMPR0DAT ,Determine the ADC0 Compare Register Value at Rising"
|
|
line.long 0x24 "ADCCMPF0,16-Bit ADC Start Compare Register of Falling 0"
|
|
hexmask.long.word 0x24 0.--15. 1. " ADCCMPF0DAT ,Determine the ADC0 Compare Register Value at Falling"
|
|
line.long 0x28 "ADCCMPR1,16-Bit ADC Start Compare Register of Rising 1"
|
|
hexmask.long.word 0x28 0.--15. 1. " ADCCMPR1DAT ,Determine the ADC1 Compare Register Value at Rising"
|
|
line.long 0x2C "ADCCMPF1,16-Bit ADC Start Compare Register of Falling 1"
|
|
hexmask.long.word 0x2C 0.--15. 1. " ADCCMPF1DAT ,Determine the ADC1 Compare Register Value at Falling"
|
|
line.long 0x30 "ADCCMPR2DAT,16-Bit ADC Start Compare Register of Rising 2"
|
|
hexmask.long.word 0x30 0.--15. 1. " ADCCMPR2DAT ,Determine the ADC2 Compare Register Value at Rising"
|
|
line.long 0x34 "ADCCMPF2DAT,16-Bit ADC Start Compare Register of Falling 2"
|
|
hexmask.long.word 0x34 0.--15. 1. " ADCCMPF2DAT ,Determine the ADC2 Compare Register Value at Falling"
|
|
line.long 0x38 "DTCMPDAT,16-Bit Dead-time Compare Register"
|
|
hexmask.long.word 0x38 0.--15. 1. " DTCMPDAT ,Determine the Dead-time Compare Register Value"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree "VIC (Interrupt Controller)"
|
|
base ad:0xFFFFFF00
|
|
width 12.
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "INTMOD0,INTERRUPT MODE0 Register"
|
|
bitfld.long 0x00 31. " INT31_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 30. " INT30_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 29. " INT29_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 28. " INT28_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INT27_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 26. " INT26_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 25. " INT25_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 24. " INT24_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INT23_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 22. " INT22_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 21. " INT21_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 20. " INT20_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INT19_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 18. " INT18_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 17. " INT17_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 16. " INT16_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INT15_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 14. " INT14_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 13. " INT13_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 12. " INT12_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INT11_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 10. " INT10_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 9. " INT9_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 8. " INT8_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INT7_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 6. " INT6_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 5. " INT5_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 4. " INT4_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT3_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " INT2_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 1. " INT1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x00 0. " INT0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
line.long 0x04 "INTMOD1,INTERRUPT MODE1 Register"
|
|
bitfld.long 0x04 31. " PHASEZ1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 30. " MAT_S1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 29. " MAT_P1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 28. " CAP_B1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OVF_B1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 26. " CAP_A1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 25. " OVF_A1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 24. " FAULT1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x04 23. " ZERO1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 22. " TOPCMP1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 21. " ADCCMPF12_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 20. " ADCCMPR12_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ADCCMPF11_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 18. " ADCCMPR11_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 17. " ADCCMPF10_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 16. " ADCCMPR10_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PHASEZ0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 14. " MAT_S0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 13. " MAT_P0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 12. " CAP_B0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OVF_B0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 10. " CAP_A0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 9. " OVF_A0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 8. " FAULT0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ZERO0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 6. " TOPCMP0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 5. " ADCCMPF02_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 4. " ADCCMPR02_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ADCCMPF01_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 2. " ADCCMPR01_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 1. " ADCCMPF00_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x04 0. " ADCCMPR00_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
line.long 0x08 "INTMOD2,INTERRUPT MODE2 Register"
|
|
bitfld.long 0x08 25. " SW0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 24. " BT_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 23. " SSP_ERR1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 22. " SSP_RX1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SSP_TX1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 20. " SSP_ERR0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 19. " SSP_RX0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 18. " SSP_TX0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 17. " TMC5_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 16. " TOF5_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 15. " TMC4_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 14. " TOF4_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 13. " TMC3_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 12. " TOF3_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 11. " TMC2_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 10. " TOF2_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 9. " TMC1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 8. " TOF1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 7. " TMC0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 6. " TOF0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 5. " UERR1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 4. " UTX1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 3. " URX1_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 2. " UERR0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x08 1. " UTX0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
bitfld.long 0x08 0. " URX0_MOD ,Interrupt Type Selection Bit" "IRQ,FIQ"
|
|
line.long 0x0C "INTPND0,INTERRUPT PENDING0 Register"
|
|
eventfld.long 0x0C 31. " INT31_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 30. " INT30_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 29. " INT29_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 28. " INT28_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 27. " INT27_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 26. " INT26_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 25. " INT25_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 24. " INT24_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " INT23_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 22. " INT22_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 21. " INT21_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 20. " INT20_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " INT19_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 18. " INT18_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 17. " INT17_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 16. " INT16_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 15. " INT15_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 14. " INT14_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 13. " INT13_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 12. " INT12_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 11. " INT11_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 10. " INT10_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 9. " INT9_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 8. " INT8_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " INT7_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 6. " INT6_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 5. " INT5_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 4. " INT4_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x0C 3. " INT3_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 2. " INT2_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 1. " INT1_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
eventfld.long 0x0C 0. " INT0_PND ,Interrupt Type Selection Bit" "Not pending,Pending"
|
|
line.long 0x10 "INTPND1,INTERRUPT PENDING1 Register"
|
|
eventfld.long 0x10 31. " PHASEZ1_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 30. " MAT_S1_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 29. " MAT_P1_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 28. " CAP_B1_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x10 27. " OVF_B1_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 26. " CAP_A1_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 25. " OVF_A1_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 24. " FAULT1_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x10 23. " ZERO1_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 22. " TOPCMP1_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 21. " ADCCMPF12_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 20. " ADCCMPR12_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x10 19. " ADCCMPF11_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 18. " ADCCMPR11_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 17. " ADCCMPF10_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 16. " ADCCMPR10_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x10 15. " PHASEZ0_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 14. " MAT_S0_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 13. " MAT_P0_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 12. " CAP_B0_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x10 11. " OVF_B0_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 10. " CAP_A0_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 9. " OVF_A0_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 8. " FAULT0_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x10 7. " ZERO0_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 6. " TOPCMP0_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 5. " ADCCMPF02_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 4. " ADCCMPR02_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x10 3. " ADCCMPF01_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 2. " ADCCMPR01_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 1. " ADCCMPF00_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
eventfld.long 0x10 0. " ADCCMPR00_PND ,Interrupt Pending Register 1" "Not pending,Pending"
|
|
line.long 0x14 "INTPND2,INTERRUPT PENDING2 Register"
|
|
eventfld.long 0x14 25. " SW0_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 24. " BT_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 23. " SSP_ERR1_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 22. " SSP_RX1_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 21. " SSP_TX1_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 20. " SSP_ERR0_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 19. " SSP_RX0_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 18. " SSP_TX0_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 17. " TMC5_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 16. " TOF5_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 15. " TMC4_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 14. " TOF4_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 13. " TMC3_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 12. " TOF3_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 11. " TMC2_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 10. " TOF2_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 9. " TMC1_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 8. " TOF1_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 7. " TMC0_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 6. " TOF0_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 5. " UERR1_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 4. " UTX1_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 3. " URX1_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 2. " UERR0_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 1. " UTX0_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
eventfld.long 0x14 0. " URX0_PND ,Interrupt Pending Register 2" "Not pending,Pending"
|
|
line.long 0x18 "INTMSK0,INTERRUPT MASK0 Register"
|
|
bitfld.long 0x18 31. " INT31_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " INT30_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " INT29_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 28. " INT28_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 27. " INT27_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " INT26_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 25. " INT25_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " INT24_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 23. " INT23_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 22. " INT22_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " INT21_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " INT20_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 19. " INT19_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " INT18_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " INT17_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " INT16_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 15. " INT15_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " INT14_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 13. " INT13_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " INT12_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " INT11_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " INT10_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " INT9_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " INT8_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " INT7_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " INT6_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " INT5_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " INT4_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " INT3_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " INT2_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " INT1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " INT0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
line.long 0x1C "INTMSK1,INTERRUPT MASK1 Register"
|
|
bitfld.long 0x1C 31. " PHASEZ1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " MAT_S1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " MAT_P1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 28. " CAP_B1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " OVF_B1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 26. " CAP_A1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 25. " OVF_A1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 24. " FAULT1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " ZERO1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 22. " TOPCMP1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 21. " ADCCMPF12_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 20. " ADCCMPR12_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " ADCCMPF11_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 18. " ADCCMPR11_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " ADCCMPF10_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16. " ADCCMPR10_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " PHASEZ0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " MAT_S0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 13. " MAT_P0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 12. " CAP_B0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " OVF_B0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 10. " CAP_A0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " OVF_A0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 8. " FAULT0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " ZERO0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " TOPCMP0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " ADCCMPF02_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 4. " ADCCMPR02_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " ADCCMPF01_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " ADCCMPR01_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " ADCCMPF00_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " ADCCMPR00_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
line.long 0x20 "INTMSK2,INTERRUPT MASK 2 Register"
|
|
bitfld.long 0x20 25. " SW0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 24. " BT_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 23. " SSP_ERR1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 22. " SSP_RX1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 21. " SSP_TX1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 20. " SSP_ERR0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 19. " SSP_RX0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 18. " SSP_TX0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 17. " TMC5_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " TOF5_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 15. " TMC4_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 14. " TOF4_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 13. " TMC3_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 12. " TOF3_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 11. " TMC2_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 10. " TOF2_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 9. " TMC1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 8. " TOF1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 7. " TMC0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 6. " TOF0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 5. " UERR1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 4. " UTX1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 3. " URX1_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " UERR0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 1. " UTX0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " URX0_MSK ,Enable the corresponding interrupt request" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x0F
|
|
line.long 0x00 "INTOFFSIRQ,INTERRUPT OFFSET Register for IRQ"
|
|
hexmask.long.byte 0x00 0.--6. 1. " INTOFFSIRQDAT ,Interrupt Type Selection Bit"
|
|
line.long 0x04 "INTOFFSFIQ,INTERRUPT OFFSET Register for FIQ"
|
|
hexmask.long.byte 0x04 0.--6. 1. " INTOFFSFIQDAT ,Interrupt Type Selection Bit"
|
|
line.long 0x08 "INTIRQADDR,INTERRUPT VECTOR ADDRESS Register for IRQ"
|
|
hexmask.long 0x08 0.--31. 1. " INTIRQADDR ,Interrupt Type Selection Bit"
|
|
line.long 0x0C "INTFIQADDR,INTERRUPT VECTOR ADDRESS Register for FIQ"
|
|
hexmask.long 0x0C 0.--31. 1. " INTFIQADDR ,The interrupt vector address value of FIQ"
|
|
group.long 0x34++0x0F
|
|
line.long 0x00 "INTVECBASE,INTERRUPT VECTOR BASE ADDRESS Register"
|
|
hexmask.long 0x00 0.--31. 1. " INTVECBASEDAT ,The Interrupt Vector Base Address"
|
|
line.long 0x04 "INTCNON,INTERRUPT CONTROL Register"
|
|
bitfld.long 0x04 2. " FIQ ,FQI Interrupt Global Mask Bit" "Serviced,Not serviced"
|
|
bitfld.long 0x04 1. " IRQ ,IRQ Interrupt Global Mask Bit" "Serviced,Not serviced"
|
|
bitfld.long 0x04 0. " VEC ,Interrupt mode" "Standard,Vectored"
|
|
line.long 0x08 "INTPRI,INTERRUPT PRIORITY Register"
|
|
bitfld.long 0x08 12.--14. " PRIO_3 ,The Order of Interrupt Group3 Priority Selection Field" "G>H>I,G>I>H,H>G>I,H>I>G,I>G>H,I>H>G,?..."
|
|
bitfld.long 0x08 8.--10. " PRIO_2 ,The Order of Interrupt Group2 Priority Selection Field" "D>E>F,D>F>E,E>D>F,E>F>D,F>D>E,F>E>D,?..."
|
|
bitfld.long 0x08 4.--6. " PRIO_1 ,The Order of Interrupt Group1 Priority Selection Field" "A>B>C,A>C>B,B>A>C,B>C>A,C>A>B,C>B>A,?..."
|
|
bitfld.long 0x08 0.--2. " PRIO_0 ,The Order of Interrupt Group Priority Selection Field" "A|B|C>D|E|F>G|H|I,A|B|C>G|H|I>D|E|F,D|E|F>A|B|C>G|H|I,D|E|F>G|H|I>A|B|C,G|H|I>A|B|C>D|E|F,G|H|I>D|E|F>A|B|C,?..."
|
|
line.long 0x0C "SWINT,SOFTWARE INTERRUPT Register"
|
|
bitfld.long 0x0C 0. " SW0 ,Software Interrupt Request Bit" "No effect,Set to 1"
|
|
width 11.
|
|
tree.end
|
|
tree "IOPORT (I/O ports)"
|
|
base ad:0xFF044000
|
|
width 11.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "PCON0H,PORT0 Control Register"
|
|
bitfld.long 0x00 4.--5. " P0.18 ,PORT 0.18" "Input mode,Output mode,PWM0D2,?..."
|
|
bitfld.long 0x00 2.--3. " P0.17 ,PORT 0.17" "Input mode,Output mode,PWM0U2,?..."
|
|
bitfld.long 0x00 0.--1. " P0.16 ,PORT 0.16" "Input mode,Output mode,PWM0D1,?..."
|
|
line.long 0x04 "PCON0L,PORT0 Control Register"
|
|
bitfld.long 0x04 30.--31. " P0.15 ,PORT 0.15" "Input Mode,Output mode,PWM0U1,?..."
|
|
bitfld.long 0x04 28.--29. " P0.14 ,PORT 0.14" "Input Mode,Output mode,PWM0D0,?..."
|
|
bitfld.long 0x04 26.--27. " P0.13 ,PORT 0.13" "Input Mode,Output mode,PWM0U0,?..."
|
|
bitfld.long 0x04 24.--25. " P0.12 ,PORT 0.12" "Input Mode,Output mode,PWM0OFF,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " P0.11 ,PORT 0.11" "Input Mode,Output mode,PHASEZ0,?..."
|
|
bitfld.long 0x04 20.--21. " P0.10 ,PORT 0.10" "Input Mode,Output mode,PHASEB0,?..."
|
|
bitfld.long 0x04 18.--19. " P0.9 ,PORT 0.9" "Input Mode,Output mode,PHASEA0,?..."
|
|
bitfld.long 0x04 16.--17. " P0.8 ,PORT 0.8" "Input Mode,Output mode,T2PWM,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " P0.7 ,PORT 0.7" "Input Mode,Output mode,T2CAP,?..."
|
|
bitfld.long 0x04 12.--13. " P0.6 ,PORT 0.6" "Input Mode,Output mode,T2CLK,?..."
|
|
bitfld.long 0x04 10.--11. " P0.5 ,PORT 0.5" "Input Mode,Output mode,T1PWM,?..."
|
|
bitfld.long 0x04 8.--9. " P0.4 ,PORT 0.4" "Input Mode,Output mode,T1CAP,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " P0.3 ,PORT 0.3" "Input Mode,Output mode,T1CLK,?..."
|
|
bitfld.long 0x04 4.--5. " P0.2 ,PORT 0.2" "Input Mode,Output mode,T0PWM,?..."
|
|
bitfld.long 0x04 2.--3. " P0.1 ,PORT 0.1" "Input Mode,Output mode,T0CAP,?..."
|
|
bitfld.long 0x04 0.--1. " P0.0 ,PORT 0.0" "Input Mode,Output mode,T0CLK,?..."
|
|
line.long 0x08 "PCON1H,PORT1 Control Register"
|
|
bitfld.long 0x08 28.--29. " P1.30 ,PORT 1.30" "Input Mode,Output mode,PWM1D2,INT30"
|
|
bitfld.long 0x08 26.--27. " P1.29 ,PORT 1.29" "Input Mode,Output mode,PWM1U2,INT29"
|
|
bitfld.long 0x08 24.--25. " P1.28 ,PORT 1.28" "Input Mode,Output mode,PWM1D1,INT28"
|
|
bitfld.long 0x08 22.--23. " P1.27 ,PORT 1.27" "Input Mode,Output mode,PWM1U1,INT27"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " P1.26 ,PORT 1.26" "Input Mode,Output mode,PWM1D0,INT26"
|
|
bitfld.long 0x08 18.--19. " P1.25 ,PORT 1.25" "Input Mode,Output mode,PWM1U0,INT25"
|
|
bitfld.long 0x08 16.--17. " P1.24 ,PORT 1.24" "Input Mode,Output mode,PWM1OFF,INT24"
|
|
bitfld.long 0x08 14.--15. " P1.23 ,PORT 1.23" "Input Mode,Output mode,PHAZEZ1,INT23"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " P1.22 ,PORT 1.22" "Input Mode,Output mode,PHAZEB1,INT22"
|
|
bitfld.long 0x08 10.--11. " P1.21 ,PORT 1.21" "Input Mode,Output mode,PHAZEA1,INT21"
|
|
bitfld.long 0x08 8.--9. " P1.20 ,PORT 1.20" "Input Mode,Output mode,SSPFSS1,INT20"
|
|
bitfld.long 0x08 6.--7. " P1.19 ,PORT 1.19" "Input Mode,Output mode,SSPCLK1,INT19"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " P1.18 ,PORT 1.18" "Input Mode,Output mode,SSPRXD1,INT18"
|
|
bitfld.long 0x08 2.--3. " P1.17 ,PORT 1.17" "Input Mode,Output mode,SSPTXD1,INT17"
|
|
bitfld.long 0x08 0.--1. " P1.16 ,PORT 1.16" "Input Mode,Output mode,SSPFSS0,INT16"
|
|
line.long 0x0C "PCON1L,PORT1 Control Register"
|
|
bitfld.long 0x0C 30.--31. " P1.15 ,PORT 1.15" "Input Mode,Output mode,SSPCLK0,INT15"
|
|
bitfld.long 0x0C 28.--29. " P1.14 ,PORT 1.14" "Input Mode,Output mode,SSPRXD0,INT14"
|
|
bitfld.long 0x0C 26.--27. " P1.13 ,PORT 1.13" "Input Mode,Output mode,SSPTXD0,INT13"
|
|
bitfld.long 0x0C 24.--25. " P1.12 ,PORT 1.12" "Input Mode,Output mode,T5PWM,INT12"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " P1.11 ,PORT 1.11" "Input Mode,Output mode,T5CAP,INT11"
|
|
bitfld.long 0x0C 20.--21. " P1.10 ,PORT 1.10" "Input Mode,Output mode,T5CLK,INT10"
|
|
bitfld.long 0x0C 18.--19. " P1.9 ,PORT 1.9" "Input Mode,Output mode,T4PWM,INT9"
|
|
bitfld.long 0x0C 16.--17. " P1.8 ,PORT 1.8" "Input Mode,Output mode,T4CAP,INT8"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " P1.7 ,PORT 1.7" "Input Mode,Output mode,T4CLK,INT7"
|
|
bitfld.long 0x0C 12.--13. " P1.6 ,PORT 1.6" "Input Mode,Output mode,T3PWM,INT6"
|
|
bitfld.long 0x0C 10.--11. " P1.5 ,PORT 1.5" "Input Mode,Output mode,T3CAP,INT5"
|
|
bitfld.long 0x0C 8.--9. " P1.4 ,PORT 1.4" "Input Mode,Output mode,T3CLK,INT4"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " P1.3 ,PORT 2.3" "Input Mode,Output mode,UARTTX1,INT3"
|
|
bitfld.long 0x0C 4.--5. " P1.2 ,PORT 2.2" "Input Mode,Output mode,UARTRX1,INT2"
|
|
bitfld.long 0x0C 2.--3. " P1.1 ,PORT 2.1" "Input Mode,Output mode,UARTTX0,INT1"
|
|
bitfld.long 0x0C 0.--1. " P1.0 ,PORT 2.0" "Input Mode,Output mode,UARTRX0,INT0"
|
|
line.long 0x10 "PCON2,PORT2 Control Register"
|
|
bitfld.long 0x10 28.--29. " P2.14 ,PORT 2.14" "Input Mode,Output mode,AIN14,?..."
|
|
bitfld.long 0x10 26.--27. " P2.13 ,PORT 2.13" "Input Mode,Output mode,AIN13,?..."
|
|
bitfld.long 0x10 24.--25. " P2.12 ,PORT 2.12" "Input Mode,Output mode,AIN12,?..."
|
|
textline " "
|
|
bitfld.long 0x10 22.--23. " P2.11 ,PORT 2.11" "Input Mode,Output mode,AIN11,?..."
|
|
bitfld.long 0x10 20.--21. " P2.10 ,PORT 2.10" "Input Mode,Output mode,AIN10,?..."
|
|
bitfld.long 0x10 18.--19. " P2.9 ,PORT 2.9" "Input Mode,Output mode,AIN9,?..."
|
|
bitfld.long 0x10 16.--17. " P2.8 ,PORT 2.8" "Input Mode,Output mode,AIN8,?..."
|
|
textline " "
|
|
bitfld.long 0x10 14.--15. " P2.7 ,PORT 2.7" "Input Mode,Output mode,AIN7,?..."
|
|
bitfld.long 0x10 12.--13. " P2.6 ,PORT 2.6" "Input Mode,Output mode,AIN6,?..."
|
|
bitfld.long 0x10 10.--11. " P2.5 ,PORT 2.5" "Input Mode,Output mode,AIN5,?..."
|
|
bitfld.long 0x10 8.--9. " P2.4 ,PORT 2.4" "Input Mode,Output mode,AIN4,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6.--7. " P2.3 ,PORT 2.3" "Input Mode,Output mode,AIN3,?..."
|
|
bitfld.long 0x10 4.--5. " P2.2 ,PORT 2.2" "Input Mode,Output mode,AIN2,?..."
|
|
bitfld.long 0x10 2.--3. " P2.1 ,PORT 2.1" "Input Mode,Output mode,AIN1,?..."
|
|
bitfld.long 0x10 0.--1. " P2.0 ,PORT 2.0" "Input Mode,Output mode,AIN0,?..."
|
|
line.long 0x14 "PUR0,PORT0 Pull-Up Control Register"
|
|
bitfld.long 0x14 18. " P0.18 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " P0.17 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " P0.16 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " P0.15 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 14. " P0.14 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " P0.13 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " P0.12 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " P0.11 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " P0.10 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " P0.9 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " P0.8 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 7. " P0.7 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " P0.6 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " P0.5 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " P0.4 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " P0.3 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " P0.2 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " P0.1 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " P0.0 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
line.long 0x18 "PUR1,PORT1 Pull-Up Control Register"
|
|
bitfld.long 0x18 30. " P1.30 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " P1.29 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 28. " P1.28 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " P1.27 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 26. " P1.26 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 25. " P1.25 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " P1.24 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " P1.23 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 22. " P1.22 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " P1.21 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " P1.20 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 19. " P1.19 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 18. " P1.18 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " P1.17 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " P1.16 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 15. " P1.15 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 14. " P1.14 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 13. " P1.13 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " P1.12 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " P1.11 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 10. " P1.10 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " P1.9 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " P1.8 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " P1.7 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 6. " P1.6 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " P1.5 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " P1.4 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " P1.3 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " P1.2 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " P1.1 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " P1.0 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
line.long 0x1C "PUR2,PORT2 Pull-Up Control Register"
|
|
bitfld.long 0x1C 14. " P2.14 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 13. " P2.13 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 12. " P2.12 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " P2.11 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " P2.10 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " P2.9 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 8. " P2.8 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 7. " P2.7 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " P2.6 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " P2.5 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 4. " P2.4 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 3. " P2.3 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " P2.2 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " P2.1 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " P2.0 ,Pull-up Resistor Selection Bit" "Disabled,Enabled"
|
|
line.long 0x20 "OD0,PORT0 Open-Drain Control Register"
|
|
bitfld.long 0x20 18. " P0.18 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " P0.17 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " P0.16 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 15. " P0.15 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 14. " P0.14 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 13. " P0.13 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 12. " P0.12 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 11. " P0.11 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 10. " P0.10 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 9. " P0.9 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 8. " P0.8 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 7. " P0.7 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 6. " P0.6 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " P0.5 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 4. " P0.4 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 3. " P0.3 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 2. " P0.2 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 1. " P0.1 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " P0.0 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
line.long 0x24 "OD1,PORT1 Open-Drain Control Register"
|
|
bitfld.long 0x24 30. " P1.30 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " P1.29 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 28. " P1.28 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 27. " P1.27 ,Open-Drain Selection Bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x24 26. " P1.26 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 25. " P1.25 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 24. " P1.24 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 23. " P1.23 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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textline " "
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bitfld.long 0x24 22. " P1.22 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 21. " P1.21 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 20. " P1.20 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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bitfld.long 0x24 19. " P1.19 ,Open-Drain Selection Bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x24 18. " P1.18 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 17. " P1.17 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 16. " P1.16 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 15. " P1.15 ,Open-Drain Selection Bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x24 14. " P1.14 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 13. " P1.13 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 12. " P1.12 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 11. " P1.11 ,Open-Drain Selection Bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x24 10. " P1.10 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 9. " P1.9 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 8. " P1.8 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 7. " P1.7 ,Open-Drain Selection Bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x24 6. " P1.6 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 5. " P1.5 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 4. " P1.4 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 3. " P1.3 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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textline " "
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bitfld.long 0x24 2. " P1.2 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 1. " P1.1 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x24 0. " P1.0 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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line.long 0x28 "OD2,PORT2 Open-Drain Control Register"
|
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bitfld.long 0x28 14. " P2.14 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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bitfld.long 0x28 13. " P2.13 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x28 12. " P2.12 ,Open-Drain Selection Bit" "Disabled,Enabled"
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bitfld.long 0x28 11. " P2.11 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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textline " "
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bitfld.long 0x28 10. " P2.10 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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bitfld.long 0x28 9. " P2.9 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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bitfld.long 0x28 8. " P2.8 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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bitfld.long 0x28 7. " P2.7 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
textline " "
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bitfld.long 0x28 6. " P2.6 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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bitfld.long 0x28 5. " P2.5 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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bitfld.long 0x28 4. " P2.4 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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bitfld.long 0x28 3. " P2.3 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
textline " "
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bitfld.long 0x28 2. " P2.2 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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bitfld.long 0x28 1. " P2.1 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
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bitfld.long 0x28 0. " P2.0 ,Open-Drain Selection Bit" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
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line.long 0x00 "PDATSTAT0,PORT0 Data Status Register"
|
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setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P0.18 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
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setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P0.17 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
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setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P0.16 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
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setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P0.15 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
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textline " "
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setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P0.14 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
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setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P0.13 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
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setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P0.12 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
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setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P0.11 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
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setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P0.10 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
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setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P0.9 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
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setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P0.8 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
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setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P0.7 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
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setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P0.6 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
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setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P0.5 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
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setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P0.4 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P0.3 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
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setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P0.2 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P0.1 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0.0 ,Port 0 Output Data Status Bit" "Logic 0,Logic 1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PDATSTAT1,PORT1 Data Status Register"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P1.30 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P1.29 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P1.28 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P1.27 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
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setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P1.26 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P1.25 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P1.24 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P1.23 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P1.22 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P1.21 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P1.20 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P1.19 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
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setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P1.18 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
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|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P1.17 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P1.16 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
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|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P1.15 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
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setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P1.14 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
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|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P1.13 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
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setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P1.12 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
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|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P1.11 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
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setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P1.10 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
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setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P1.9 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
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setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P1.8 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P1.7 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P1.6 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P1.5 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P1.4 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P1.3 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P1.2 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1.1 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P1.0 ,Port 1 Output Data Status Bit" "Logic 0,Logic 1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PDATSTAT2,PORT2 Data Status Register"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P2.14 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P2.13 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P2.12 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P2.11 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P2.10 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P2.9 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P2.8 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P2.7 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P2.6 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P2.5 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P2.4 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P2.3 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
textline " "
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2.2 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P2.1 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P2.0 ,Port 2 Output Data Status Bit" "Logic 0,Logic 1"
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "EXTINTH,External Interrupt Control Register"
|
|
bitfld.long 0x00 28.--29. " P1.30 ,EXTINT 1.30 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x00 26.--27. " P1.29 ,EXTINT 1.29 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x00 24.--25. " P1.28 ,EXTINT 1.28 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x00 22.--23. " P1.27 ,EXTINT 1.27 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " P1.26 ,EXTINT 1.26 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x00 18.--19. " P1.25 ,EXTINT 1.25 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x00 16.--17. " P1.24 ,EXTINT 1.24 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x00 14.--15. " P1.23 ,EXTINT 1.23 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " P1.22 ,EXTINT 1.22 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x00 10.--11. " P1.21 ,EXTINT 1.21 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x00 8.--9. " P1.20 ,EXTINT 1.20 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x00 6.--7. " P1.19 ,EXTINT 1.19 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P1.18 ,EXTINT 1.18 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x00 2.--3. " P1.17 ,EXTINT 1.17 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x00 0.--1. " P1.16 ,EXTINT 1.16 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
line.long 0x04 "EXTINTL,External Interrupt Control Register"
|
|
bitfld.long 0x04 30.--31. " P1.15 ,EXTINT 1.15 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 28.--29. " P1.14 ,EXTINT 1.14 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 26.--27. " P1.13 ,EXTINT 1.13 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 24.--25. " P1.12 ,EXTINT 1.12 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " P1.11 ,EXTINT 1.11 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 20.--21. " P1.10 ,EXTINT 1.10 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 18.--19. " P1.9 ,EXTINT 1.9 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 16.--17. " P1.8 ,EXTINT 1.8 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " P1.7 ,EXTINT 1.7 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 12.--13. " P1.6 ,EXTINT 1.6 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 10.--11. " P1.5 ,EXTINT 1.5 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 8.--9. " P1.4 ,EXTINT 1.4 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " P1.3 ,EXTINT 1.3 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 4.--5. " P1.2 ,EXTINT 1.2 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 2.--3. " P1.1 ,EXTINT 1.1 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
bitfld.long 0x04 0.--1. " P1.0 ,EXTINT 1.0 Edge Selection Field" "Falling edge,Rising edge,Both,?..."
|
|
line.long 0x08 "EXTINTF0,External Interrupt Filter Control Register"
|
|
bitfld.long 0x08 29. " EXTINTF3EN ,External Interrupt Filter" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--28. " EXTINT3SEL ,External Interrupt with Filter Selection Field" "INT0,INT1,INT2,INT3,INT4,INT5,INT6,INT7,INT8,INT9,INT10,INT11,INT12,INT13,INT14,INT15,INT16,INT17,INT18,INT19,INT20,INT21,INT22,INT23,INT24,INT25,INT26,INT27,INT28,INT29,INT30,?..."
|
|
bitfld.long 0x08 21. " EXTINTF2EN ,External Interrupt Filter Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--20. " EXTINT2SEL ,External Interrupt with Filter Selection Field" "INT0,INT1,INT2,INT3,INT4,INT5,INT6,INT7,INT8,INT9,INT10,INT11,INT12,INT13,INT14,INT15,INT16,INT17,INT18,INT19,INT20,INT21,INT22,INT23,INT24,INT25,INT26,INT27,INT28,INT29,INT30,?..."
|
|
textline " "
|
|
bitfld.long 0x08 13. " EXTINTF1EN ,External Interrupt Filter Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x08 8.--12. " EXTINT1SEL ,External Interrupt with Filter Selection Field" "INT0,INT1,INT2,INT3,INT4,INT5,INT6,INT7,INT8,INT9,INT10,INT11,INT12,INT13,INT14,INT15,INT16,INT17,INT18,INT19,INT20,INT21,INT22,INT23,INT24,INT25,INT26,INT27,INT28,INT29,INT30,?..."
|
|
bitfld.long 0x08 5. " EXTINTF0EN ,External Interrupt Filter Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x08 0.--4. " EXTINT0SEL ,External Interrupt with Filter Selection Field" "INT0,INT1,INT2,INT3,INT4,INT5,INT6,INT7,INT8,INT9,INT10,INT11,INT12,INT13,INT14,INT15,INT16,INT17,INT18,INT19,INT20,INT21,INT22,INT23,INT24,INT25,INT26,INT27,INT28,INT29,INT30,?..."
|
|
line.long 0x0C "EXTINTF1,External Interrupt Filter Control Register"
|
|
bitfld.long 0x0C 29. " EXTINTF7EN ,External Interrupt Filter" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--28. " EXTINT7SEL ,External Interrupt with Filter Selection Field" "INT0,INT1,INT2,INT3,INT4,INT5,INT6,INT7,INT8,INT9,INT10,INT11,INT12,INT13,INT14,INT15,INT16,INT17,INT18,INT19,INT20,INT21,INT22,INT23,INT24,INT25,INT26,INT27,INT28,INT29,INT30,?..."
|
|
bitfld.long 0x0C 21. " EXTINTF6EN ,External Interrupt Filter Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--20. " EXTINT6SEL ,External Interrupt with Filter Selection Field" "INT0,INT1,INT2,INT3,INT4,INT5,INT6,INT7,INT8,INT9,INT10,INT11,INT12,INT13,INT14,INT15,INT16,INT17,INT18,INT19,INT20,INT21,INT22,INT23,INT24,INT25,INT26,INT27,INT28,INT29,INT30,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 13. " EXTINTF5EN ,External Interrupt Filter Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8.--12. " EXTINT5SEL ,External Interrupt with Filter Selection Field" "INT0,INT1,INT2,INT3,INT4,INT5,INT6,INT7,INT8,INT9,INT10,INT11,INT12,INT13,INT14,INT15,INT16,INT17,INT18,INT19,INT20,INT21,INT22,INT23,INT24,INT25,INT26,INT27,INT28,INT29,INT30,?..."
|
|
bitfld.long 0x0C 5. " EXTINTF4EN ,External Interrupt Filter Selection Bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--4. " EXTINT4SEL ,External Interrupt with Filter Selection Field" "INT0,INT1,INT2,INT3,INT4,INT5,INT6,INT7,INT8,INT9,INT10,INT11,INT12,INT13,INT14,INT15,INT16,INT17,INT18,INT19,INT20,INT21,INT22,INT23,INT24,INT25,INT26,INT27,INT28,INT29,INT30,?..."
|
|
width 11.
|
|
tree.end
|
|
tree "CM (Clock & Power Management)"
|
|
base ad:0xFF000000
|
|
width 9.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "SYSCON,System Control Register"
|
|
bitfld.long 0x00 8.--9. " PCLKDIV ,PCLK Clock Selection Field" "SCLK/8,SCLK/4,SCLK/2,SCLK"
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset Bit" "No effect,Reset"
|
|
bitfld.long 0x00 6. " IOSCON ,Internal Oscillator ON/OFF Control Bit" "Off,On"
|
|
bitfld.long 0x00 5. " PLLON ,PLL (Phase Locked Loop) ON/OFF Control Bit" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLKSRC ,Clock Source Select Bit" "EXTCLK,PLL output"
|
|
bitfld.long 0x00 2.--3. " MCLKDIV ,MCLK Clock Selection Field" "SCLK/8,SCLK/4,SCLK/2,SCLK"
|
|
bitfld.long 0x00 1. " IDLE ,IDLE Control Bit" "Normal,IDLE mode"
|
|
bitfld.long 0x00 0. " STOP ,STOP Control Bit" "Normal,STOP mode"
|
|
line.long 0x04 "PLLCON,PLL Control Register"
|
|
hexmask.long.byte 0x04 12.--19. 1. " MDIV ,Main Divider Control Field"
|
|
hexmask.long.byte 0x04 2.--9. 1. " PDIV ,Pre Divider Control Field"
|
|
bitfld.long 0x04 0.--1. " SDIV ,Post Divider Control Field" "0,1,2,3"
|
|
line.long 0x08 "PLLLOCK,PLL Locking Timer Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PLLLOCKIND ,PLL Locking Time End Compare Value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PMSTAT,Power Management Status Register"
|
|
bitfld.long 0x00 6. " IOSCSTAT ,Internal oscillator stabilization status bit" "Not stabilized,Stabilized"
|
|
bitfld.long 0x00 5. " PLLSTAT ,PLL stabilization status bit" "Not matched,Matched"
|
|
bitfld.long 0x00 4. " CMSTAT ,External oscillator status bit" "Not failed,Failed"
|
|
bitfld.long 0x00 3. " WDTRST ,Reset Source by Watchdog time" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PORRST ,Reset Source by POR" "Not caused,Caused"
|
|
bitfld.long 0x00 1. " PINRST ,Reset Source by External Reset Pin" "Not caused,Caused"
|
|
bitfld.long 0x00 0. " CMRST ,Reset Source by Clock Monitor Bit" "Not caused,Caused"
|
|
tree.end
|
|
tree.open "SSP (SYNCHRONOUS SERIAL PORT)"
|
|
tree "SSP0"
|
|
base ad:0xFF030000
|
|
width 14.
|
|
group.long 0x000++0x3
|
|
line.long 0x00 "SSPCR0,Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR[15:8] ,Serial Clock Rate Field"
|
|
bitfld.long 0x00 7. " SPH ,SSPCLK Phase Selection" "First clock,Second clock"
|
|
bitfld.long 0x00 6. " SPO ,SSPCLK Polarity" "First clock,Second clock"
|
|
bitfld.long 0x00 4.--5. " FRF[5:4] ,Frame Format Selection Field" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DSS[3:0] ,Data Size Selection Field" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
group.long 0x004++0x3
|
|
line.long 0x00 "SSPCR1,Control Register 1"
|
|
bitfld.long 0x00 4.--6. " RXIFLSEL[6:4] ,Receive Interrupt FIFO Level Selection Field" "Reserved,1/8,1/4,Reserved,1/2,?..."
|
|
bitfld.long 0x00 3. " SOD ,Slave-mode Output Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " MS ,Master or Slave Mode Selection" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,Synchronous Serial Port Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop-Back Mode" "Disabled,Enabled"
|
|
group.long 0x008++0x3
|
|
line.long 0x00 "SSPDR,Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA[15:0] ,Transmit/Receive FIFO"
|
|
rgroup.long 0x00c++0x3
|
|
line.long 0x00 "SSPSR,Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Prime-Cell SSP Busy Flag" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO Full Status" "Full,Not full"
|
|
bitfld.long 0x00 2. " RNE ,Receive Empty Status" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO Full Status" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO Empty Status" "Not empty,Empty"
|
|
group.long 0x010++0x3
|
|
line.long 0x00 "SSPCPSR,Clock Prescale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR[7:0] ,Clock Pre-scale Divisor Field"
|
|
group.long 0x014++0x3
|
|
line.long 0x00 "SSPIMSC,Interrupt Mask Set /Clear Register"
|
|
bitfld.long 0x00 3. " TXIM ,Transmit FIFO Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " RXIM ,Receive FIFO Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " RTIM ,Receive Timeout Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " RORIM ,Receive Overrun Interrupt Mask" "Not masked,Masked"
|
|
rgroup.long 0x018++0x3
|
|
line.long 0x00 "SSPRIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Gives the raw interrupt state(prior to masking) of the SSPTXINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXRIS ,Gives the raw interrupt state(prior to masking) of the SSPRXINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTRIS ,Gives the raw interrupt state(prior to masking) of the SSPRTINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RORRIS ,Gives the raw interrupt state(prior to masking) of the SSPRORINTR interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x01c++0x3
|
|
line.long 0x00 "SSPMIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Gives the transmit FIFO masked interrupt state(after masking) of the SSPTXINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXRIS ,Gives the receive FIFO masked interrupt state(after masking) of the SSPRXINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTRIS ,Gives the receive timeout masked interrupt state(after masking) of the SSPRTINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RORRIS ,Gives the receive over run masked interrupt status(after masking) of the SSPRORINTR interrupt" "Disabled,Enabled"
|
|
wgroup.long 0x020++0x3
|
|
line.long 0x00 "SSPICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " RTIC ,Clears the SSPRTINTR interrupt" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RORIC ,Clears the SSPRORINTR interrupt" "No effect,Clear"
|
|
rgroup.long 0xFE0++0xf
|
|
line.long 0x00 "SSPPeriphID0,Peripheral identification register bits7:0"
|
|
line.long 0x04 "SSPPeriphID1,Peripheral identification register bits15:8"
|
|
line.long 0x08 "SSPPeriphID2,Peripheral identification register bits23:16"
|
|
line.long 0x0c "SSPPeriphID3,Peripheral identification register bits31:24"
|
|
rgroup.long 0xFF0++0xf
|
|
line.long 0x00 "SSPPCellID0,PrimeCell identification register bits7:0"
|
|
line.long 0x04 "SSPPCellID1,PrimeCell identification register bits15:8"
|
|
line.long 0x08 "SSPPCellID2,PrimeCell identification register bits23:16"
|
|
line.long 0x0c "SSPPCellID3,PrimeCell identification register bits31:24"
|
|
width 0xb
|
|
tree.end
|
|
tree "SSP1"
|
|
base ad:0xFF034000
|
|
width 14.
|
|
group.long 0x000++0x3
|
|
line.long 0x00 "SSPCR0,Control Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCR[15:8] ,Serial Clock Rate Field"
|
|
bitfld.long 0x00 7. " SPH ,SSPCLK Phase Selection" "First clock,Second clock"
|
|
bitfld.long 0x00 6. " SPO ,SSPCLK Polarity" "First clock,Second clock"
|
|
bitfld.long 0x00 4.--5. " FRF[5:4] ,Frame Format Selection Field" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DSS[3:0] ,Data Size Selection Field" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
group.long 0x004++0x3
|
|
line.long 0x00 "SSPCR1,Control Register 1"
|
|
bitfld.long 0x00 4.--6. " RXIFLSEL[6:4] ,Receive Interrupt FIFO Level Selection Field" "Reserved,1/8,1/4,Reserved,1/2,?..."
|
|
bitfld.long 0x00 3. " SOD ,Slave-mode Output Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " MS ,Master or Slave Mode Selection" "Master,Slave"
|
|
bitfld.long 0x00 1. " SSE ,Synchronous Serial Port Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LBM ,Loop-Back Mode" "Disabled,Enabled"
|
|
group.long 0x008++0x3
|
|
line.long 0x00 "SSPDR,Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA[15:0] ,Transmit/Receive FIFO"
|
|
rgroup.long 0x00c++0x3
|
|
line.long 0x00 "SSPSR,Status Register"
|
|
bitfld.long 0x00 4. " BSY ,Prime-Cell SSP Busy Flag" "Idle,Busy"
|
|
bitfld.long 0x00 3. " RFF ,Receive FIFO Full Status" "Full,Not full"
|
|
bitfld.long 0x00 2. " RNE ,Receive Empty Status" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " TNF ,Transmit FIFO Full Status" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TFE ,Transmit FIFO Empty Status" "Not empty,Empty"
|
|
group.long 0x010++0x3
|
|
line.long 0x00 "SSPCPSR,Clock Prescale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR[7:0] ,Clock Pre-scale Divisor Field"
|
|
group.long 0x014++0x3
|
|
line.long 0x00 "SSPIMSC,Interrupt Mask Set /Clear Register"
|
|
bitfld.long 0x00 3. " TXIM ,Transmit FIFO Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " RXIM ,Receive FIFO Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " RTIM ,Receive Timeout Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " RORIM ,Receive Overrun Interrupt Mask" "Not masked,Masked"
|
|
rgroup.long 0x018++0x3
|
|
line.long 0x00 "SSPRIS,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Gives the raw interrupt state(prior to masking) of the SSPTXINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXRIS ,Gives the raw interrupt state(prior to masking) of the SSPRXINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTRIS ,Gives the raw interrupt state(prior to masking) of the SSPRTINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RORRIS ,Gives the raw interrupt state(prior to masking) of the SSPRORINTR interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x01c++0x3
|
|
line.long 0x00 "SSPMIS,Masked Interrupt Status Register"
|
|
bitfld.long 0x00 3. " TXRIS ,Gives the transmit FIFO masked interrupt state(after masking) of the SSPTXINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXRIS ,Gives the receive FIFO masked interrupt state(after masking) of the SSPRXINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RTRIS ,Gives the receive timeout masked interrupt state(after masking) of the SSPRTINTR interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RORRIS ,Gives the receive over run masked interrupt status(after masking) of the SSPRORINTR interrupt" "Disabled,Enabled"
|
|
wgroup.long 0x020++0x3
|
|
line.long 0x00 "SSPICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " RTIC ,Clears the SSPRTINTR interrupt" "No effect,Clear"
|
|
bitfld.long 0x00 0. " RORIC ,Clears the SSPRORINTR interrupt" "No effect,Clear"
|
|
rgroup.long 0xFE0++0xf
|
|
line.long 0x00 "SSPPeriphID0,Peripheral identification register bits7:0"
|
|
line.long 0x04 "SSPPeriphID1,Peripheral identification register bits15:8"
|
|
line.long 0x08 "SSPPeriphID2,Peripheral identification register bits23:16"
|
|
line.long 0x0c "SSPPeriphID3,Peripheral identification register bits31:24"
|
|
rgroup.long 0xFF0++0xf
|
|
line.long 0x00 "SSPPCellID0,PrimeCell identification register bits7:0"
|
|
line.long 0x04 "SSPPCellID1,PrimeCell identification register bits15:8"
|
|
line.long 0x08 "SSPPCellID2,PrimeCell identification register bits23:16"
|
|
line.long 0x0c "SSPPCellID3,PrimeCell identification register bits31:24"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "TC (16-bit timers)"
|
|
tree "TC 0"
|
|
base ad:0xFF008000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TCON,Timer Control Register"
|
|
bitfld.long 0x00 9. " T_CLKFTON ,Filter Enable Bit on for TCLK Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " T_CAPFTON ,Filter Enable Bit on for TCAP Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEN ,Timer Enable Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CL ,Timer Counter Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " OMS ,Timer Operating Mode Selection Field" "Interval,Match & overflow,PWM continuous,Capture on falling edge,Capture on rising edge,Capture on both edges,PWM one shot,?..."
|
|
bitfld.long 0x00 2. " ICS ,Timer Input Clock Selection Bit" "Internal,External"
|
|
bitfld.long 0x00 1. " IVT ,Phase Inverting Selection for PWMn" "Normal,Invert"
|
|
bitfld.long 0x00 0. " DBGEN ,Debug Enable" "Halted,Not halted"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TPRE,Timer Pre-Scale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRESCALE[7:0] ,Pre-scale Value for Timer"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TDAT,Timer Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA[15:0] ,Data"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "TPDAT,Timer Data Register for PWM"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDATA[15:0] ,Data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCNT,Timer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV[15:0] ,The current timer's count value during the normal operation"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC 1"
|
|
base ad:0xFF00C000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TCON,Timer Control Register"
|
|
bitfld.long 0x00 9. " T_CLKFTON ,Filter Enable Bit on for TCLK Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " T_CAPFTON ,Filter Enable Bit on for TCAP Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEN ,Timer Enable Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CL ,Timer Counter Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " OMS ,Timer Operating Mode Selection Field" "Interval,Match & overflow,PWM continuous,Capture on falling edge,Capture on rising edge,Capture on both edges,PWM one shot,?..."
|
|
bitfld.long 0x00 2. " ICS ,Timer Input Clock Selection Bit" "Internal,External"
|
|
bitfld.long 0x00 1. " IVT ,Phase Inverting Selection for PWMn" "Normal,Invert"
|
|
bitfld.long 0x00 0. " DBGEN ,Debug Enable" "Halted,Not halted"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TPRE,Timer Pre-Scale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRESCALE[7:0] ,Pre-scale Value for Timer"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TDAT,Timer Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA[15:0] ,Data"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "TPDAT,Timer Data Register for PWM"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDATA[15:0] ,Data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCNT,Timer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV[15:0] ,The current timer's count value during the normal operation"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC 2"
|
|
base ad:0xFF010000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TCON,Timer Control Register"
|
|
bitfld.long 0x00 9. " T_CLKFTON ,Filter Enable Bit on for TCLK Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " T_CAPFTON ,Filter Enable Bit on for TCAP Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEN ,Timer Enable Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CL ,Timer Counter Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " OMS ,Timer Operating Mode Selection Field" "Interval,Match & overflow,PWM continuous,Capture on falling edge,Capture on rising edge,Capture on both edges,PWM one shot,?..."
|
|
bitfld.long 0x00 2. " ICS ,Timer Input Clock Selection Bit" "Internal,External"
|
|
bitfld.long 0x00 1. " IVT ,Phase Inverting Selection for PWMn" "Normal,Invert"
|
|
bitfld.long 0x00 0. " DBGEN ,Debug Enable" "Halted,Not halted"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TPRE,Timer Pre-Scale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRESCALE[7:0] ,Pre-scale Value for Timer"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TDAT,Timer Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA[15:0] ,Data"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "TPDAT,Timer Data Register for PWM"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDATA[15:0] ,Data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCNT,Timer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV[15:0] ,The current timer's count value during the normal operation"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC 3"
|
|
base ad:0xFF014000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TCON,Timer Control Register"
|
|
bitfld.long 0x00 9. " T_CLKFTON ,Filter Enable Bit on for TCLK Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " T_CAPFTON ,Filter Enable Bit on for TCAP Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEN ,Timer Enable Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CL ,Timer Counter Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " OMS ,Timer Operating Mode Selection Field" "Interval,Match & overflow,PWM continuous,Capture on falling edge,Capture on rising edge,Capture on both edges,PWM one shot,?..."
|
|
bitfld.long 0x00 2. " ICS ,Timer Input Clock Selection Bit" "Internal,External"
|
|
bitfld.long 0x00 1. " IVT ,Phase Inverting Selection for PWMn" "Normal,Invert"
|
|
bitfld.long 0x00 0. " DBGEN ,Debug Enable" "Halted,Not halted"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TPRE,Timer Pre-Scale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRESCALE[7:0] ,Pre-scale Value for Timer"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TDAT,Timer Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA[15:0] ,Data"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "TPDAT,Timer Data Register for PWM"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDATA[15:0] ,Data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCNT,Timer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV[15:0] ,The current timer's count value during the normal operation"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC 4"
|
|
base ad:0xFF018000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TCON,Timer Control Register"
|
|
bitfld.long 0x00 9. " T_CLKFTON ,Filter Enable Bit on for TCLK Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " T_CAPFTON ,Filter Enable Bit on for TCAP Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEN ,Timer Enable Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CL ,Timer Counter Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " OMS ,Timer Operating Mode Selection Field" "Interval,Match & overflow,PWM continuous,Capture on falling edge,Capture on rising edge,Capture on both edges,PWM one shot,?..."
|
|
bitfld.long 0x00 2. " ICS ,Timer Input Clock Selection Bit" "Internal,External"
|
|
bitfld.long 0x00 1. " IVT ,Phase Inverting Selection for PWMn" "Normal,Invert"
|
|
bitfld.long 0x00 0. " DBGEN ,Debug Enable" "Halted,Not halted"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TPRE,Timer Pre-Scale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRESCALE[7:0] ,Pre-scale Value for Timer"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TDAT,Timer Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA[15:0] ,Data"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "TPDAT,Timer Data Register for PWM"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDATA[15:0] ,Data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCNT,Timer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV[15:0] ,The current timer's count value during the normal operation"
|
|
width 0xb
|
|
tree.end
|
|
tree "TC 5"
|
|
base ad:0xFF01C000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TCON,Timer Control Register"
|
|
bitfld.long 0x00 9. " T_CLKFTON ,Filter Enable Bit on for TCLK Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " T_CAPFTON ,Filter Enable Bit on for TCAP Input Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEN ,Timer Enable Bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CL ,Timer Counter Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " OMS ,Timer Operating Mode Selection Field" "Interval,Match & overflow,PWM continuous,Capture on falling edge,Capture on rising edge,Capture on both edges,PWM one shot,?..."
|
|
bitfld.long 0x00 2. " ICS ,Timer Input Clock Selection Bit" "Internal,External"
|
|
bitfld.long 0x00 1. " IVT ,Phase Inverting Selection for PWMn" "Normal,Invert"
|
|
bitfld.long 0x00 0. " DBGEN ,Debug Enable" "Halted,Not halted"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TPRE,Timer Pre-Scale Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRESCALE[7:0] ,Pre-scale Value for Timer"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TDAT,Timer Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA[15:0] ,Data"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "TPDAT,Timer Data Register for PWM"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDATA[15:0] ,Data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TCNT,Timer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV[15:0] ,The current timer's count value during the normal operation"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "UART"
|
|
tree "UART0"
|
|
base ad:0xFF038000
|
|
width 15.
|
|
group.long 0x000++0x03
|
|
line.long 0x00 "UARTDR,Data register"
|
|
bitfld.long 0x00 11. " OE_DR ," "No error,Error"
|
|
bitfld.long 0x00 10. " BE_DR ,Break Error" "No break receive,Break receive"
|
|
bitfld.long 0x00 9. " PE_DR ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 8. " FE_DR ,Frame Error" "No error,Error"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA[7:0] ,Data Value Field"
|
|
group.long 0x004++0x03
|
|
line.long 0x00 "UARTRSR,Receive status register/error clear register"
|
|
bitfld.long 0x00 3. " OE_RSR ,Overrun Error" "No error,Error"
|
|
bitfld.long 0x00 2. " BE_RSR ,Break Error" "No error,Error"
|
|
bitfld.long 0x00 1. " PE_RSR ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 0. " FE_RSR ,Frame Error" "No error,Error"
|
|
rgroup.long 0x018++0x03
|
|
line.long 0x00 "UARTFR,Flag register"
|
|
bitfld.long 0x00 31. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " RXFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 5. " TXFF ,Transmit FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXFE ,Receive FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 3. " BUSY ,UART Busy" "Not Busy,Busy"
|
|
group.long 0x020++0x03
|
|
line.long 0x00 "UARTILPR,IrDA low power counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ILPDVSR[7:0] ,Low Power Divisor Value"
|
|
group.long 0x024++0x03
|
|
line.long 0x00 "UARTIBRD,Integer baud rate register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIVINT[15:0] ,Baud Rate Setting Bits"
|
|
group.long 0x028++0x03
|
|
line.long 0x00 "UARTFBRD,Funcational baud rate register"
|
|
hexmask.long.byte 0x00 0.--5. 1. " DIVFRAC[5:0] ,Baud Rate Selection Field"
|
|
group.long 0x02c++0x03
|
|
line.long 0x00 "UARTLCR_H,Line control register"
|
|
bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " WLEN[6:5] ,Word Length" "5,6,7,8"
|
|
bitfld.long 0x00 4. " FEN ,Enable FIFO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "One,Two"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BRK ,Send Break" "Cleared,Set"
|
|
group.long 0x030++0x03
|
|
line.long 0x00 "UARTCR,Control register"
|
|
bitfld.long 0x00 9. " RXE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIRLP ,IrDA SIR Low Power Mode" "Non-IrDA,IrDA"
|
|
bitfld.long 0x00 1. " SIREN ,SIR Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled"
|
|
group.long 0x034++0x03
|
|
line.long 0x00 "UARTIFLS,Interrupt FIFO level select register"
|
|
bitfld.long 0x00 3.--5. " RXIFLSEL[5:3] ,Receive Interrupt FIFO Level Select" "1/8,1/4,1/2,3/4,7/8,?..."
|
|
bitfld.long 0x00 0.--2. " TXIFLSEL[2:0] ,Transmit Interrupt FIFO Level Select" "1/8,1/4,1/2,3/4,7/8,?..."
|
|
group.long 0x038++0x03
|
|
line.long 0x00 "UARTIMSC,Interrupt mask set / clear register"
|
|
bitfld.long 0x00 10. " OEIM ,Overrun error interrupt mask set/clear" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BEIM ,Break error interrupt mask set/clear" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PEIM ,Parity error interrupt mask set/clear" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FEIM ,Framing error interrupt mask set/clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTIM ,Receive timeout interrupt mask set/clear" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TXIM ,Transmit interrupt mask set/clear" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXIM ,Receive interrupt mask set/clear" "Disabled,Enabled"
|
|
rgroup.long 0x03c++0x03
|
|
line.long 0x00 "UARTRIS,Raw interrupt status register"
|
|
bitfld.long 0x00 10. " OERIS ,Overrun Error Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BERIS ,Break Error Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PERIS ,Parity Error Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FERIS ,Framing Error Interrupt Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTRIS ,Receive Timeout Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TXRIS ,Transmit Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXRIS ,Receive Interrupt Status" "Disabled,Enabled"
|
|
rgroup.long 0x040++0x03
|
|
line.long 0x00 "UARTMIS,Masked interrupt status register"
|
|
bitfld.long 0x00 10. " OEMIS ,Overrun Error Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BEMIS ,Break Error Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PEMIS ,Parity Error Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FEMIS ,Framing Error Masked Interrupt Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTMIS ,Receive Timeout Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TXMIS ,Transmit Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXMIS ,Receive Masked Interrupt Status" "Disabled,Enabled"
|
|
wgroup.long 0x044++0x03
|
|
line.long 0x00 "UARTICR,Interrupt clear register"
|
|
bitfld.long 0x00 10. " OEIC ,Overrun error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " BEIC ,Break error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " PEIC ,Parity error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " FEIC ,Framing error interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTIC ,Receive timeout interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXIC ,Transmit interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " RXIC ,Receive interrupt clear" "No effect,Clear"
|
|
rgroup.long 0xfe0++0x03
|
|
line.long 0x00 "UARTPeriphID0,Peripheral ID register bits7:0"
|
|
rgroup.long 0xfe4++0x03
|
|
line.long 0x00 "UARTPeriphID1,Peripheral ID register bits15:8"
|
|
rgroup.long 0xfe8++0x03
|
|
line.long 0x00 "UARTPeriphID2,Peripheral ID register bits23:16"
|
|
rgroup.long 0xfec++0x03
|
|
line.long 0x00 "UARTPeriphID3,Peripheral ID register bits31:24"
|
|
rgroup.long 0xff0++0x03
|
|
line.long 0x00 "UARTPCellID0,PrimeCell ID register bits7:0"
|
|
rgroup.long 0xff4++0x03
|
|
line.long 0x00 "UARTPCellID1,PrimeCell ID register bits15:8"
|
|
rgroup.long 0xff8++0x03
|
|
line.long 0x00 "UARTPCellID2,PrimeCell ID register bits23:16"
|
|
rgroup.long 0xffc++0x03
|
|
line.long 0x00 "UARTPCellID3,PrimeCell ID register bits31:24"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0xFF03C000
|
|
width 15.
|
|
group.long 0x000++0x03
|
|
line.long 0x00 "UARTDR,Data register"
|
|
bitfld.long 0x00 11. " OE_DR ," "No error,Error"
|
|
bitfld.long 0x00 10. " BE_DR ,Break Error" "No break receive,Break receive"
|
|
bitfld.long 0x00 9. " PE_DR ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 8. " FE_DR ,Frame Error" "No error,Error"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA[7:0] ,Data Value Field"
|
|
group.long 0x004++0x03
|
|
line.long 0x00 "UARTRSR,Receive status register/error clear register"
|
|
bitfld.long 0x00 3. " OE_RSR ,Overrun Error" "No error,Error"
|
|
bitfld.long 0x00 2. " BE_RSR ,Break Error" "No error,Error"
|
|
bitfld.long 0x00 1. " PE_RSR ,Parity Error" "No error,Error"
|
|
bitfld.long 0x00 0. " FE_RSR ,Frame Error" "No error,Error"
|
|
rgroup.long 0x018++0x03
|
|
line.long 0x00 "UARTFR,Flag register"
|
|
bitfld.long 0x00 31. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " RXFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 5. " TXFF ,Transmit FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RXFE ,Receive FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 3. " BUSY ,UART Busy" "Not Busy,Busy"
|
|
group.long 0x020++0x03
|
|
line.long 0x00 "UARTILPR,IrDA low power counter register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ILPDVSR[7:0] ,Low Power Divisor Value"
|
|
group.long 0x024++0x03
|
|
line.long 0x00 "UARTIBRD,Integer baud rate register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIVINT[15:0] ,Baud Rate Setting Bits"
|
|
group.long 0x028++0x03
|
|
line.long 0x00 "UARTFBRD,Funcational baud rate register"
|
|
hexmask.long.byte 0x00 0.--5. 1. " DIVFRAC[5:0] ,Baud Rate Selection Field"
|
|
group.long 0x02c++0x03
|
|
line.long 0x00 "UARTLCR_H,Line control register"
|
|
bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " WLEN[6:5] ,Word Length" "5,6,7,8"
|
|
bitfld.long 0x00 4. " FEN ,Enable FIFO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "One,Two"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EPS ,Even Parity Select" "Odd,Even"
|
|
bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BRK ,Send Break" "Cleared,Set"
|
|
group.long 0x030++0x03
|
|
line.long 0x00 "UARTCR,Control register"
|
|
bitfld.long 0x00 9. " RXE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIRLP ,IrDA SIR Low Power Mode" "Non-IrDA,IrDA"
|
|
bitfld.long 0x00 1. " SIREN ,SIR Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled"
|
|
group.long 0x034++0x03
|
|
line.long 0x00 "UARTIFLS,Interrupt FIFO level select register"
|
|
bitfld.long 0x00 3.--5. " RXIFLSEL[5:3] ,Receive Interrupt FIFO Level Select" "1/8,1/4,1/2,3/4,7/8,?..."
|
|
bitfld.long 0x00 0.--2. " TXIFLSEL[2:0] ,Transmit Interrupt FIFO Level Select" "1/8,1/4,1/2,3/4,7/8,?..."
|
|
group.long 0x038++0x03
|
|
line.long 0x00 "UARTIMSC,Interrupt mask set / clear register"
|
|
bitfld.long 0x00 10. " OEIM ,Overrun error interrupt mask set/clear" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BEIM ,Break error interrupt mask set/clear" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PEIM ,Parity error interrupt mask set/clear" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FEIM ,Framing error interrupt mask set/clear" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTIM ,Receive timeout interrupt mask set/clear" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TXIM ,Transmit interrupt mask set/clear" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXIM ,Receive interrupt mask set/clear" "Disabled,Enabled"
|
|
rgroup.long 0x03c++0x03
|
|
line.long 0x00 "UARTRIS,Raw interrupt status register"
|
|
bitfld.long 0x00 10. " OERIS ,Overrun Error Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BERIS ,Break Error Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PERIS ,Parity Error Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FERIS ,Framing Error Interrupt Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTRIS ,Receive Timeout Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TXRIS ,Transmit Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXRIS ,Receive Interrupt Status" "Disabled,Enabled"
|
|
rgroup.long 0x040++0x03
|
|
line.long 0x00 "UARTMIS,Masked interrupt status register"
|
|
bitfld.long 0x00 10. " OEMIS ,Overrun Error Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BEMIS ,Break Error Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PEMIS ,Parity Error Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FEMIS ,Framing Error Masked Interrupt Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTMIS ,Receive Timeout Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TXMIS ,Transmit Masked Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RXMIS ,Receive Masked Interrupt Status" "Disabled,Enabled"
|
|
wgroup.long 0x044++0x03
|
|
line.long 0x00 "UARTICR,Interrupt clear register"
|
|
bitfld.long 0x00 10. " OEIC ,Overrun error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " BEIC ,Break error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " PEIC ,Parity error interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " FEIC ,Framing error interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RTIC ,Receive timeout interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " TXIC ,Transmit interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " RXIC ,Receive interrupt clear" "No effect,Clear"
|
|
rgroup.long 0xfe0++0x03
|
|
line.long 0x00 "UARTPeriphID0,Peripheral ID register bits7:0"
|
|
rgroup.long 0xfe4++0x03
|
|
line.long 0x00 "UARTPeriphID1,Peripheral ID register bits15:8"
|
|
rgroup.long 0xfe8++0x03
|
|
line.long 0x00 "UARTPeriphID2,Peripheral ID register bits23:16"
|
|
rgroup.long 0xfec++0x03
|
|
line.long 0x00 "UARTPeriphID3,Peripheral ID register bits31:24"
|
|
rgroup.long 0xff0++0x03
|
|
line.long 0x00 "UARTPCellID0,PrimeCell ID register bits7:0"
|
|
rgroup.long 0xff4++0x03
|
|
line.long 0x00 "UARTPCellID1,PrimeCell ID register bits15:8"
|
|
rgroup.long 0xff8++0x03
|
|
line.long 0x00 "UARTPCellID2,PrimeCell ID register bits23:16"
|
|
rgroup.long 0xffc++0x03
|
|
line.long 0x00 "UARTPCellID3,PrimeCell ID register bits31:24"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
textline ""
|