5560 lines
405 KiB
Plaintext
5560 lines
405 KiB
Plaintext
; --------------------------------------------------------------------------------
|
|
; @Title: S32G2-LLCE On-Chip Peripherals
|
|
; @Props: Released
|
|
; @Author: CEZ, KWI, DAB
|
|
; @Changelog: 2019-09-12 CEZ
|
|
; 2020-06-03 KWI
|
|
; 2022-02-28 DAB
|
|
; @Manufacturer: NXP - NXP Semiconductors
|
|
; @Doc: SVD generated, based on: S32G274A_LLCE.svd (Ver. 1.2)
|
|
; @Core: Cortex-M0P
|
|
; @Chip: S32G233A-M0-0, S32G233A-M0-1, S32G233A-M0-2, S32G233A-M0-3,
|
|
; S32G234M-M0-0, S32G234M-M0-1, S32G234M-M0-2, S32G234M-M0-3,
|
|
; S32G254A-M0-0, S32G254A-M0-1, S32G254A-M0-2, S32G254A-M0-3,
|
|
; S32G274A-M0-0, S32G274A-M0-1, S32G274A-M0-2, S32G274A-M0-3
|
|
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: pers32g2-llce.per 17736 2024-04-08 09:26:07Z kwisniewski $
|
|
|
|
tree.close "Core Registers (Cortex-M0+)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0x8
|
|
if (CORENAME()=="CORTEXM1")
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
else
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
endif
|
|
if (CORENAME()=="CORTEXM1")
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
|
|
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
|
|
else
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
endif
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
|
|
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
|
|
group.long 0xd04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
group.long 0xd08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
else
|
|
textline " "
|
|
endif
|
|
group.long 0xd0c++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
|
|
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
|
|
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
|
|
group.long 0xd10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
rgroup.long 0xd14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
|
|
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
|
|
group.long 0xd1c++0x0b
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
|
|
line.long 0x04 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
|
|
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
|
|
line.long 0x08 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
else
|
|
textline " "
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "LLCE_BCAN"
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.) (list ad:0x430C0000 ad:0x430C1000 ad:0x430C2000 ad:0x430C3000 ad:0x430C4000 ad:0x430C5000 ad:0x430C6000 ad:0x430C7000 ad:0x430C8000 ad:0x430C9000 ad:0x430CA000 ad:0x430CB000 ad:0x430CC000 ad:0x430CD000 ad:0x430CE000 ad:0x430CF000)
|
|
tree "LLCE_BCAN_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,Configuration Register 1"
|
|
bitfld.long 0x00 31. "MDIS,Module Disable" "0: Enable BCAN module,1: Disable BCAN module"
|
|
bitfld.long 0x00 30. "FRZ,Freeze Mode Request" "0: No Freeze mode request,1: Freeze mode request"
|
|
newline
|
|
bitfld.long 0x00 29. "SOFTRST,Soft Reset" "0: No soft reset request,1: Soft reset request"
|
|
bitfld.long 0x00 1. "TXDRSDIS,FD Data Phase Rate Switch Disable" "0: Tx Data phase rate switch is enabled,1: Tx Data phase rate switch is disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ABRDIS,Automatic Bus-Off Recovery" "0: Automatic bus-off recovery is enabled,1: Automatic bus-off recovery is disabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,Configuration Register 2"
|
|
bitfld.long 0x00 31. "TLM,Tx LLCE Mode" "0: Tx LLCE mode is disabled,1: Tx LLCE mode is enabled"
|
|
bitfld.long 0x00 7. "EDFLTDIS,Integration Edge Filter Disable" "0: Edge Filter is enabled,1: Edge Filter is disabled"
|
|
newline
|
|
bitfld.long 0x00 6. "PREXCEN,Protocol Exception Enable" "0: Protocol exception feature disabled,1: Protocol exception feature enabled"
|
|
bitfld.long 0x00 5. "FDEN,CAN FD Protocol Enable" "0: CAN FD protocol disabled,1: CAN FD protocol enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "SRXEN,Self Reception Enable" "0: Self-reception is disabled,1: Self-reception is enabled"
|
|
bitfld.long 0x00 2.--3. "TSTAMPCAP,Time Stamp Capture Point" "0: Time stamp capture disabled,1: Time stamp is captured in the end of the CAN..,2: Time stamp is captured in the start of the..,3: Time stamp is captured in the start of frame.."
|
|
newline
|
|
bitfld.long 0x00 1. "LOM,Listen-Only Mode" "0: Listen-only mode disabled,1: Listen-only mode enabled"
|
|
bitfld.long 0x00 0. "LPB,Loop-Back Mode" "0: Loop-Back mode disabled,1: Loop-Back mode enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "NCBT,Nominal Bit Timing Register"
|
|
hexmask.long.word 0x00 23.--31. 1. "NPRESDIV,Nominal Prescaler Divisor Factor"
|
|
hexmask.long.byte 0x00 16.--22. 1. "NRJW,Nominal Resynchronization Jump Width"
|
|
newline
|
|
hexmask.long.byte 0x00 9.--15. 1. "NTSEG2,Nominal Time Segment 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "NTSEG1,Nominal Time Segment 1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DCBT,Data Bit Timing Register"
|
|
bitfld.long 0x00 23.--27. "DPRESDIV,Data Phase Prescaler Divisor Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--19. "DRJW,Data Phase Resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 9.--12. "DTSEG2,Data Time Segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. "DTSEG1,Data Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TDCCR,Transceiver Delay Compensation Control Register"
|
|
bitfld.long 0x00 31. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled"
|
|
bitfld.long 0x00 30. "TDMDIS,Transceiver Delay Measurement Disabled" "0: Secondary sample point position = TDC..,1: Secondary sample point position = TDCOFF"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "TDCOFF,Transceiver Delay Compensation Offset"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ECR,Error Counter"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DPTEC,Data Phase Tx Error Counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DPREC,Data Phase Rx Error Counter"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TEC,Tx Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REC,Rx Error Counter"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IE,Interrupt enable register"
|
|
bitfld.long 0x00 30. "FRZIE,Freeze Mode Interrupt Enable" "0: Freeze mode interrupt disabled,1: Freeze mode interrupt enabled"
|
|
bitfld.long 0x00 23. "PREXCIE,Protocol Exception Interrupt Enable" "0: Protocol exception interrupt is disabled,1: Protocol exception interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 22. "DPERRIE,Data Phase Error Interrupt Enable" "0: Data phase error interrupt disabled,1: Data phase error interrupt enabled"
|
|
bitfld.long 0x00 21. "TXWRNIE,Tx Error Warning Interrupt Enable" "0: Tx error warning interrupt is disabled,1: Tx error warning interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RXWRNIE,Rx Error Warning Interrupt Enable" "0: Rx Error warning interrupt is disabled,1: Rx Error warning interrupt is enabled"
|
|
bitfld.long 0x00 19. "BDONEIE,Bus-Off Done Interrupt Enable" "0: Bus-off done Interrupt is disabled,1: Bus-off done interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "BOFFIE,Bus-Off Interrupt Enable" "0: Bus-Off interrupt disabled,1: Bus-Off interrupt enabled"
|
|
bitfld.long 0x00 17. "PASSERRIE,Passive Error Interrupt Enable" "0: Passive error interrupt disabled,1: Passive error interrupted enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "ERRIE,Error Interrupt Enable" "0: Error interrupt disabled,1: Error interrupt enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
eventfld.long 0x00 30. "FRZI,Freeze Mode Interrupt" "0: No such occurrence,1: BCAN entered Freeze mode"
|
|
eventfld.long 0x00 23. "PREXC,Protocol Exception" "0: No such occurrence,1: Protocol exception occurred"
|
|
newline
|
|
eventfld.long 0x00 22. "DPERR,Data Phase Error" "0: No such occurrence,1: Error occurred in data phase"
|
|
eventfld.long 0x00 21. "TXWRN,Tx Error Warning" "0: No such occurrence,1: Tx error counter reached 96"
|
|
newline
|
|
eventfld.long 0x00 20. "RXWRN,Rx Error Warning" "0: No such occurrance,1: Rx Error Counter reached 96"
|
|
eventfld.long 0x00 19. "BDONE,Bus-Off Done" "0: No such occurrence,1: BCAN is ready to leave Bus-Off state"
|
|
newline
|
|
eventfld.long 0x00 18. "BOFF,Bus-Off State" "0: No such occurrence,1: BCAN entered Bus-Off state"
|
|
eventfld.long 0x00 17. "PASSERR,Passive Error State" "0: No such occurrence,1: BCAN entered Passive state"
|
|
newline
|
|
eventfld.long 0x00 16. "ERR,Error Flag" "0: No such occurence,1: A CAN bus error occurred"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 31. "LPMACK,Low Power Mode Acknowledge" "0: BCAN is not in Low-Power mode,1: BCAN is in Low-Power mode"
|
|
bitfld.long 0x00 30. "FRZACK,Freeze Mode Acknowledge" "0: BCAN is not in Freeze mode,1: BCAN is in Freeze mode"
|
|
newline
|
|
bitfld.long 0x00 29. "SRST_PEND,Soft Reset Pending" "0: There is no soft reset pending,1: Soft reset is pending"
|
|
bitfld.long 0x00 15. "ERROVR,Error Overrun" "0: No such occurrence,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 14. "DPCRCERR,Data Phase Cyclic Redundancy Check Error" "0: No such occurrence,1: A CRC error has occurred"
|
|
bitfld.long 0x00 13. "DPFRMERR,Data Phase Form Error" "0: No such occurrence,1: A form error has occurred"
|
|
newline
|
|
bitfld.long 0x00 12. "DPSTFERR,Data Phase Stuff Error" "0: No such occurrence,1: A stuffing error has occurred"
|
|
bitfld.long 0x00 11. "DPBIT0ERR,Data Phase Bit0 Error" "0: No such occurrence,1: A bit sent as dominant was received as.."
|
|
newline
|
|
bitfld.long 0x00 10. "DPBIT1ERR,Data Phase Bit1 Error" "0: No such occurrence,1: A bit sent as recessive was received as.."
|
|
bitfld.long 0x00 9. "BIT1ERR,Bit1 Error" "0: No such occurrence,1: A bit sent as recessive was received as.."
|
|
newline
|
|
bitfld.long 0x00 8. "BIT0ERR,Bit0 Error" "0: No such occurrence,1: A bit sent as dominant was received as.."
|
|
bitfld.long 0x00 7. "ACKERR,Acknowledge Error" "0: No such occurrence,1: An acknowledge error has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CRCERR,Cyclic Redundancy Check Error" "0: No such occurrence,1: A CRC error has occurred"
|
|
bitfld.long 0x00 5. "FRMERR,Form Error" "0: No such occurrence,1: A form error has occurred"
|
|
newline
|
|
bitfld.long 0x00 4. "STFERR,Stuffing Error" "0: No such occurrence,1: A stuffing error has occurred"
|
|
bitfld.long 0x00 2.--3. "FLTCONF,Fault Confinement" "0: Error active,1: Error passive,2: Bus Off,3: Bus Off"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "CANCS,CAN Communication State" "0: INTEGRATING,1: IDLE,2: RECEIVING,3: TRANSMITTING"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CRC,CRC"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. "CRC,CAN Frame CRC"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TDCSR,Transceiver Delay Compensation Status Register"
|
|
eventfld.long 0x00 31. "TDCFAIL,Transceiver Delay Compensation Fail" "0: Measured loop delay is in range,1: Measured loop delay is out of range"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TDCVAL,Transceiver Delay Compensation Value"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FFSR,FIFO Status Register"
|
|
rbitfld.long 0x00 12. "TXDO,Tx Data Process Ongoing" "0: Tx data transfer is not ongoing,1: Tx data transfer ongoing"
|
|
eventfld.long 0x00 11. "TFUFLW,Tx FIFO Underflow" "0: No Tx FIFO underflow,1: Tx FIFO underflow"
|
|
newline
|
|
eventfld.long 0x00 10. "TFOVR,Tx FIFO Overrun" "0: No Rx FIFO overrun,1: Rx FIFO overrun"
|
|
rbitfld.long 0x00 9. "TFEMPTY,Tx FIFO Empty" "0: Tx FIFO not empty,1: Tx FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 8. "TFFULL,Tx FIFO Full" "0: Tx FIFO not full,1: Tx FIFO full"
|
|
rbitfld.long 0x00 4. "RXDO,Rx Data Process Ongoing" "0: Rx process is not ongoing,1: Rx process is ongoing"
|
|
newline
|
|
eventfld.long 0x00 3. "RFUFLW,Rx FIFO Underflow" "0: No Rx FIFO underflow,1: Rx FIFO underflow"
|
|
eventfld.long 0x00 2. "RFOVR,Rx FIFO Overrun" "0: No Rx FIFO overrun,1: Rx FIFO overrun"
|
|
newline
|
|
rbitfld.long 0x00 1. "RFEMPTY,Rx FIFO Empty" "0: Rx FIFO not empty,1: Rx FIFO empty"
|
|
rbitfld.long 0x00 0. "RFFULL,Rx FIFO Full" "0: Rx FIFO not full,1: Rx FIFO full"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "FFDSR,Data Status Register"
|
|
bitfld.long 0x00 24.--25. "TXFE,Tx FIFO Elements" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. "RXFE,Rx FIFO Elements" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 13. "TXAW,Tx Arbitration Won" "0,1"
|
|
bitfld.long 0x00 12. "TXFRDY,Tx FIFO Ready" "0: Tx FIFO is busy,1: Tx FIFO is ready"
|
|
newline
|
|
bitfld.long 0x00 11. "TXND,Tx Next Data Request" "0: Tx next data is not requested,1: Tx next data is requested"
|
|
bitfld.long 0x00 10. "TXVD,Valid Transmission" "0: No valid transmission,1: Valid transmission"
|
|
newline
|
|
bitfld.long 0x00 9. "TXLA,Tx Frame Lost Bus Arbitration" "0: No transmission fail,1: Transmission fail"
|
|
bitfld.long 0x00 8. "TXFL,Tx Fail" "0: No transmission fail,1: Transmission fail"
|
|
newline
|
|
bitfld.long 0x00 3. "RXLD,Rx Last Data" "0: No such occurrence,1: Rx last data"
|
|
bitfld.long 0x00 2. "RXND,Rx Next Data Available" "0: Rx Next data not available,1: Rx Next data available"
|
|
newline
|
|
bitfld.long 0x00 1. "RXVD,Valid Reception" "0: Not a valid Rx frame,1: Valid Rx frame"
|
|
bitfld.long 0x00 0. "RXFL,Rx Fail" "0: No Rx error,1: Rx fail"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "RXFIFO,Rx FIFO register"
|
|
hexmask.long 0x00 0.--31. 1. "RXDATA,Rx FIFO Data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TXFIFO,Tx FIFO register"
|
|
hexmask.long 0x00 0.--31. 1. "TXDATA,Tx FIFO Data"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "TXTS,Tx TIME STAMP"
|
|
hexmask.long 0x00 0.--31. 1. "TX_TIME_STAMP,Transmission Time Stamp"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "BINF,BCAN information register"
|
|
bitfld.long 0x00 26. "PLOADEND,Payload Endianess" "0: FIFO payload is big-endian,1: FIFO payload is little-endian"
|
|
bitfld.long 0x00 21.--25. "RXFF,Number of Rx FIFO Elements" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "TXFF,Number of Tx FIFO Elements" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. "TSEN,Time Stamp Feature" "0: Time stamp feature is unavailable,1: Time stamp feature is available"
|
|
newline
|
|
bitfld.long 0x00 14. "FDEN,CAN FD Feature" "0: Classical CAN version only,1: Full CAN FD version"
|
|
bitfld.long 0x00 13. "MDISRV,MDIS Reset Value" "0: MDIS reset value is 0,1: MDIS reset value is 1"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "ABSIZE,Internal Address Bus Size Minus One" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BVER,BCAN Version"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LLCE_RXLUT"
|
|
base ad:0x43A10000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLCR,RxLUT Configuration Register"
|
|
bitfld.long 0x00 2. "SOVR,Search Result Over" "0: Search Result Overwrite Disabled,1: Search Result Overwrite Enabled"
|
|
bitfld.long 0x00 1. "OPMODE,Operating Mode" "0: Access Mode (writing or reading entry table),1: Search Mode (searching index information in.."
|
|
newline
|
|
bitfld.long 0x00 0. "RLEN,Module Enable" "0: RxLUT Module Disabled,1: RxLUT Module Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RLSR,RxLUT Status Register"
|
|
rbitfld.long 0x00 4. "PENDS,Pending Search Status" "0: No search is pending in queue,1: Next search is in queue"
|
|
eventfld.long 0x00 3. "NOMATS,No Match Status" "0: A match is found in the table,1: ID Match failed in last completed search.."
|
|
newline
|
|
eventfld.long 0x00 2. "SRHCS,Search Complete Status" "0: Search is ongoing or no search is initiated,1: Search is complete"
|
|
rbitfld.long 0x00 1. "OPMODES,Operating Mode Status" "0: Access Mode (writing or reading entry table)..,1: Search Mode (searching index information in.."
|
|
newline
|
|
rbitfld.long 0x00 0. "BUSYS,Busy Status" "0: RxLUT is NOT busy,1: RxLUT is busy in read write or search operation"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLIER,RxLUT Interrupt Enable Register"
|
|
bitfld.long 0x00 3. "NOMATIE,No Match Interrupt Enable" "0: No Match Interrupt is Disabled,1: No Match Interrupt is Enabled"
|
|
bitfld.long 0x00 2. "SRHCIE,Search Complete Interrupt Enable" "0: Search Complete Interrupt is Disabled,1: Search Complete Interrupt is Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLFIMER,RxLUT Frame ID Mask OR Frame ID End Register"
|
|
hexmask.long 0x00 0.--31. 1. "FIME,Frame ID Mask OR Frame ID End"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RLFISR,RxLUT Frame ID Start Register"
|
|
hexmask.long 0x00 0.--31. 1. "FIS,Frame ID Start"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RLCIXR,RxLUT Channel ID AND Index Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "INDX,Index"
|
|
bitfld.long 0x00 15. "VALID,Valid" "0: Entry is invalid,1: Entry is valid"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CTRL,Control" "0: Exact Match,1: Exact Match,2: CTRL_2,3: CTRL_3"
|
|
bitfld.long 0x00 0.--5. "CID,Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RLADRCR,RxLUT Address and Command Register"
|
|
bitfld.long 0x00 16. "CMD,Command" "0: Entry Read Command,1: Entry Write Command"
|
|
hexmask.long.word 0x00 0.--9. 1. "ADDR,Entry Address"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RLFIMESR,RxLUT Frame ID Mask OR Frame ID End Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "FIMES,Frame ID Mask OR Frame ID End Status"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RLFISSR,RxLUT Frame ID Start Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "FISS,Frame ID Start Status"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RLCIXSR,RxLUT Channel ID AND Index Status Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "INDXS,Index Status"
|
|
bitfld.long 0x00 15. "VALIDS,Valid Status" "0: Entry is invalid,1: Entry is valid"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CTRLS,Control Status" "0: Exact Match,1: Exact Match,2: CTRLS_2,3: CTRLS_3"
|
|
bitfld.long 0x00 0.--5. "CIDS,Channel ID Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RLADRSR,RxLUT Address Status Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "ADDRS,Entry Address Status"
|
|
tree.end
|
|
tree "LLCE_INTCONC"
|
|
base ad:0x43A14000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ICSR0,Interrupt Concentrator Status Register#0"
|
|
bitfld.long 0x00 7. "RIFA7,Rx In FIFO#7 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 6. "RIFA6,Rx In FIFO#6 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 5. "RIFA5,Rx In FIFO#5 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 4. "RIFA4,Rx In FIFO#4 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 3. "RIFA3,Rx In FIFO#3 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 2. "RIFA2,Rx In FIFO#2 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 1. "RIFA1,Rx In FIFO#1 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 0. "RIFA0,Rx In FIFO#0 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICSR1,Interrupt Concentrator Status Register#1"
|
|
bitfld.long 0x00 7. "RIFA15,Rx In FIFO#15 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 6. "RIFA14,Rx In FIFO#14 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 5. "RIFA13,Rx In FIFO#13 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 4. "RIFA12,Rx In FIFO#12 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 3. "RIFA11,Rx In FIFO#11 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 2. "RIFA10,Rx In FIFO#10 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 1. "RIFA9,Rx In FIFO#9 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 0. "RIFA8,Rx In FIFO#8 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ICSR2,Interrupt Concentrator Status Register#2"
|
|
bitfld.long 0x00 7. "ROFA7,Rx Out FIFO#7 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 6. "ROFA6,Rx Out FIFO#6 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 5. "ROFA5,Rx Out FIFO#5 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 4. "ROFA4,Rx Out FIFO#4 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 3. "ROFA3,Rx Out FIFO#3 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 2. "ROFA2,Rx Out FIFO#2 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 1. "ROFA1,Rx Out FIFO#1 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 0. "ROFA0,Rx Out FIFO#0 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICSR3,Interrupt Concentrator Status Register#3"
|
|
bitfld.long 0x00 7. "ROFA15,Rx Out FIFO#15 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 6. "ROFA14,Rx Out FIFO#14 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 5. "ROFA13,Rx Out FIFO#13 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 4. "ROFA12,Rx Out FIFO#12 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 3. "ROFA11,Rx Out FIFO#11 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 2. "ROFA10,Rx Out FIFO#10 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 1. "ROFA9,Rx Out FIFO#9 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 0. "ROFA8,Rx Out FIFO#8 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ICSR4,Interrupt Concentrator Status Register#4"
|
|
bitfld.long 0x00 7. "BIFA7,Blr In FIFO#7 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BIFA6,Blr In FIFO#6 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BIFA5,Blr In FIFO#5 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BIFA4,Blr In FIFO#4 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BIFA3,Blr In FIFO#3 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BIFA2,Blr In FIFO#2 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BIFA1,Blr In FIFO#1 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 0. "BIFA0,Blr In FIFO#0 Interrupt A" "0: Interrupt is absent,1: Interrupt is present"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ICSR5,Interrupt Concentrator Status Register#5"
|
|
bitfld.long 0x00 7. "BIFA15,Blr In FIFO#15 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BIFA14,Blr In FIFO#14 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BIFA13,Blr In FIFO#13 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BIFA12,Blr In FIFO#12 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BIFA11,Blr In FIFO#11 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BIFA10,Blr In FIFO#10 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BIFA9,Blr In FIFO#9 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "BIFA8,Blr In FIFO#8 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ICSR6,Interrupt Concentrator Status Register#6"
|
|
bitfld.long 0x00 7. "BOFA7,Blr Out FIFO#7 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BOFA6,Blr Out FIFO#6 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BOFA5,Blr Out FIFO#5 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BOFA4,Blr Out FIFO#4 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BOFA3,Blr Out FIFO#3 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BOFA2,Blr Out FIFO#2 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BOFA1,Blr Out FIFO#1 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "BOFA0,Blr Out FIFO#0 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ICSR7,Interrupt Concentrator Status Register#7"
|
|
bitfld.long 0x00 7. "BOFA15,Blr Out FIFO#15 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BOFA14,Blr Out FIFO#14 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BOFA13,Blr Out FIFO#13 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BOFA12,Blr Out FIFO#12 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BOFA11,Blr Out FIFO#11 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BOFA10,Blr Out FIFO#10 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BOFA9,Blr Out FIFO#9 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "BOFA8,Blr Out FIFO#8 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ICSR8,Interrupt Concentrator Status Register#8"
|
|
bitfld.long 0x00 7. "TAFA7,Tx Ack FIFO#7 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "TAFA6,Tx Ack FIFO#6 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "TAFA5,Tx Ack FIFO#5 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "TAFA4,Tx Ack FIFO#4 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "TAFA3,Tx Ack FIFO#3 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "TAFA2,Tx Ack FIFO#2 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "TAFA1,Tx Ack FIFO#1 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "TAFA0,Tx Ack FIFO#0 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ICSR9,Interrupt Concentrator Status Register#9"
|
|
bitfld.long 0x00 7. "TAFA15,Tx Ack FIFO#15 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "TAFA14,Tx Ack FIFO#14 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "TAFA13,Tx Ack FIFO#13 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "TAFA12,Tx Ack FIFO#12 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "TAFA11,Tx Ack FIFO#11 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "TAFA10,Tx Ack FIFO#10 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "TAFA9,Tx Ack FIFO#9 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "TAFA8,Tx Ack FIFO#8 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "ICSR10,Interrupt Concentrator Status Register#10"
|
|
bitfld.long 0x00 7. "ROFA19,Rx Out FIFO#19 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "ROFA18,Rx Out FIFO#18 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "ROFA17,Rx Out FIFO#17 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "ROFA16,Rx Out FIFO#16 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "RIFA19,Rx In FIFO#19 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "RIFA18,Rx In FIFO#18 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "RIFA17,Rx In FIFO#17 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "RIFA16,Rx In FIFO#16 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "ICSR11,Interrupt Concentrator Status Register#11"
|
|
bitfld.long 0x00 7. "BOFA19,Blr Out FIFO#19 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BOFA18,Blr Out FIFO#18 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BOFA17,Blr Out FIFO#17 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BOFA16,Blr Out FIFO#16 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BIFA19,Blr In FIFO#19 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BIFA18,Blr In FIFO#18 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BIFA17,Blr In FIFO#17 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "BIFA16,Blr In FIFO#16 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ICSR12,Interrupt Concentrator Status Register#12"
|
|
bitfld.long 0x00 3. "TAFA19,Tx Ack FIFO#19 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "TAFA18,Tx Ack FIFO#18 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "TAFA17,Tx Ack FIFO#17 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "TAFA16,Tx Ack FIFO#16 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "ICSR13,Interrupt Concentrator Status Register#13"
|
|
bitfld.long 0x00 4. "TAFA20,Tx Ack FIFO#20 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 3. "BOFA20,Blr Out FIFO#20 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 2. "BIFA20,Blr In FIFO#20 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 1. "ROFA20,Rx Out FIFO#20 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 0. "RIFA20,Rx In FIFO#20 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ICSR14,Interrupt Concentrator Status Register#14"
|
|
bitfld.long 0x00 7. "RIFB7,Rx In FIFO#7 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "RIFB6,Rx In FIFO#6 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "RIFB5,Rx In FIFO#5 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "RIFB4,Rx In FIFO#4 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "RIFB3,Rx In FIFO#3 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "RIFB2,Rx In FIFO#2 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "RIFB1,Rx In FIFO#1 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "RIFB0,Rx In FIFO#0 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "ICSR15,Interrupt Concentrator Status Register#15"
|
|
bitfld.long 0x00 7. "RIFB15,Rx In FIFO#15 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "RIFB14,Rx In FIFO#14 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "RIFB13,Rx In FIFO#13 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "RIFB12,Rx In FIFO#12 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "RIFB11,Rx In FIFO#11 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "RIFB10,Rx In FIFO#10 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "RIFB9,Rx In FIFO#9 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "RIFB8,Rx In FIFO#8 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ICSR16,Interrupt Concentrator Status Register#16"
|
|
bitfld.long 0x00 7. "ROFB7,Rx Out FIFO#7 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "ROFB6,Rx Out FIFO#6 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "ROFB5,Rx Out FIFO#5 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "ROFB4,Rx Out FIFO#4 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "ROFB3,Rx Out FIFO#3 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "ROFB2,Rx Out FIFO#2 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "ROFB1,Rx Out FIFO#1 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "ROFB0,Rx Out FIFO#0 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "ICSR17,Interrupt Concentrator Status Register#17"
|
|
bitfld.long 0x00 7. "ROFB15,Rx Out FIFO#15 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "ROFB14,Rx Out FIFO#14 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "ROFB13,Rx Out FIFO#13 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "ROFB12,Rx Out FIFO#12 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "ROFB11,Rx Out FIFO#11 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "ROFB10,Rx Out FIFO#10 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "ROFB9,Rx Out FIFO#9 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "ROFB8,Rx Out FIFO#8 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "ICSR18,Interrupt Concentrator Status Register#18"
|
|
bitfld.long 0x00 7. "BIFB7,Blr In FIFO#7 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BIFB6,Blr In FIFO#6 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BIFB5,Blr In FIFO#5 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BIFB4,Blr In FIFO#4 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BIFB3,Blr In FIFO#3 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BIFB2,Blr In FIFO#2 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BIFB1,Blr In FIFO#1 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "BIFB0,Blr In FIFO#0 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ICSR19,Interrupt Concentrator Status Register#19"
|
|
bitfld.long 0x00 7. "BIFB15,Blr In FIFO#15 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BIFB14,Blr In FIFO#14 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BIFB13,Blr In FIFO#13 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BIFB12,Blr In FIFO#12 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BIFB11,Blr In FIFO#11 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BIFB10,Blr In FIFO#10 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BIFB9,Blr In FIFO#9 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "BIFB8,Blr In FIFO#8 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ICSR20,Interrupt Concentrator Status Register#20"
|
|
bitfld.long 0x00 7. "BOFB7,Blr Out FIFO#7 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BOFB6,Blr Out FIFO#6 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BOFB5,Blr Out FIFO#5 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BOFB4,Blr Out FIFO#4 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BOFB3,Blr Out FIFO#3 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BOFB2,Blr Out FIFO#2 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BOFB1,Blr Out FIFO#1 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "BOFB0,Blr Out FIFO#0 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ICSR21,Interrupt Concentrator Status Register#21"
|
|
bitfld.long 0x00 7. "BOFB15,Blr Out FIFO#15 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BOFB14,Blr Out FIFO#14 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BOFB13,Blr Out FIFO#13 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BOFB12,Blr Out FIFO#12 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BOFB11,Blr Out FIFO#11 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BOFB10,Blr Out FIFO#10 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BOFB9,Blr Out FIFO#9 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "BOFB8,Blr Out FIFO#8 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "ICSR22,Interrupt Concentrator Status Register#22"
|
|
bitfld.long 0x00 7. "TAFB7,Tx Ack FIFO#7 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "TAFB6,Tx Ack FIFO#6 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "TAFB5,Tx Ack FIFO#5 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "TAFB4,Tx Ack FIFO#4 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "TAFB3,Tx Ack FIFO#3 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "TAFB2,Tx Ack FIFO#2 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "TAFB1,Tx Ack FIFO#1 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "TAFB0,Tx Ack FIFO#0 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "ICSR23,Interrupt Concentrator Status Register#23"
|
|
bitfld.long 0x00 7. "TAFB15,Tx Ack FIFO#15 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "TAFB14,Tx Ack FIFO#14 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "TAFB13,Tx Ack FIFO#13 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "TAFB12,Tx Ack FIFO#12 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "TAFB11,Tx Ack FIFO#11 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "TAFB10,Tx Ack FIFO#10 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "TAFB9,Tx Ack FIFO#9 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "TAFB8,Tx Ack FIFO#8 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ICSR24,Interrupt Concentrator Status Register#24"
|
|
bitfld.long 0x00 7. "ROFB19,Rx Out FIFO#19 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "ROFB18,Rx Out FIFO#18 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "ROFB17,Rx Out FIFO#17 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "ROFB16,Rx Out FIFO#16 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "RIFB19,Rx In FIFO#19 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "RIFB18,Rx In FIFO#18 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "RIFB17,Rx In FIFO#17 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "RIFB16,Rx In FIFO#16 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "ICSR25,Interrupt Concentrator Status Register#25"
|
|
bitfld.long 0x00 7. "BOFB19,Blr Out FIFO#19 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BOFB18,Blr Out FIFO#18 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BOFB17,Blr Out FIFO#17 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BOFB16,Blr Out FIFO#16 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BIFB19,Blr In FIFO#19 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BIFB18,Blr In FIFO#18 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BIFB17,Blr In FIFO#17 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "BIFB16,Blr In FIFO#16 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "ICSR26,Interrupt Concentrator Status Register#26"
|
|
bitfld.long 0x00 3. "TAFB19,Tx Ack FIFO#19 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "TAFB18,Tx Ack FIFO#18 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "TAFB17,Tx Ack FIFO#17 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "TAFB16,Tx Ack FIFO#16 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "ICSR27,Interrupt Concentrator Status Register#27"
|
|
bitfld.long 0x00 4. "TAFB20,Tx Ack FIFO#20 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 3. "BOFB20,Blr Out FIFO#20 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 2. "BIFB20,Blr In FIFO#20 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 1. "ROFB20,Rx Out FIFO#20 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 0. "RIFB20,Rx In FIFO#20 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "ICSR28,Interrupt Concentrator Status Register#28"
|
|
bitfld.long 0x00 7. "TLUTA7,Tx LUT #7 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "TLUTA6,Tx LUT #6 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "TLUTA5,Tx LUT #5 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "TLUTA4,Tx LUT #4 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "TLUTA3,Tx LUT #3 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "TLUTA2,Tx LUT #2 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "TLUTA1,Tx LUT #1 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "TLUTA0,Tx LUT #0 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "ICSR29,Interrupt Concentrator Status Register#29"
|
|
bitfld.long 0x00 7. "TLUTA15,Tx LUT #15 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "TLUTA14,Tx LUT #14 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "TLUTA13,Tx LUT #13 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "TLUTA12,Tx LUT #12 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "TLUTA11,Tx LUT #11 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "TLUTA10,Tx LUT #10 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "TLUTA9,Tx LUT #9 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "TLUTA8,Tx LUT #8 Interrupt A" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "ICSR30,Interrupt Concentrator Status Register#30"
|
|
bitfld.long 0x00 7. "TLUTB7,Tx LUT #7 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "TLUTB6,Tx LUT #6 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "TLUTB5,Tx LUT #5 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "TLUTB4,Tx LUT #4 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "TLUTB3,Tx LUT #3 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "TLUTB2,Tx LUT #2 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "TLUTB1,Tx LUT #1 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "TLUTB0,Tx LUT #0 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "ICSR31,Interrupt Concentrator Status Register#31"
|
|
bitfld.long 0x00 7. "TLUTB15,Tx LUT #15 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "TLUTB14,Tx LUT #14 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "TLUTB13,Tx LUT #13 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "TLUTB12,Tx LUT #12 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "TLUTB11,Tx LUT #11 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "TLUTB10,Tx LUT #10 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "TLUTB9,Tx LUT #9 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "TLUTB8,Tx LUT #8 Interrupt B" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "ICSR32,Interrupt Concentrator Status Register#32"
|
|
bitfld.long 0x00 7. "BCAN7,BCAN#7 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BCAN6,BCAN#6 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BCAN5,BCAN#5 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BCAN4,BCAN#4 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BCAN3,BCAN#3 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BCAN2,BCAN#2 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BCAN1,BCAN#1 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "BCAN0,BCAN #0 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "ICSR33,Interrupt Concentrator Status Register#33"
|
|
bitfld.long 0x00 7. "BCAN15,BCAN#15 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "BCAN14,BCAN#14 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "BCAN13,BCAN#13 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "BCAN12,BCAN#12 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "BCAN11,BCAN#11 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "BCAN10,BCAN#10 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "BCAN9,BCAN#9 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "BCAN8,BCAN#8 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "ICSR34,Interrupt Concentrator Status Register#34"
|
|
bitfld.long 0x00 3. "LIN3,LinFlex#3 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "LIN2,LinFlex#2 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "LIN1,LinFlex#1 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "LIN0,LinFlex#0 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "ICSR35,Interrupt Concentrator Status Register#35"
|
|
bitfld.long 0x00 7. "EFC3_INT1,External FlexCAN#3 Interrupt (ORing of input Line #3 and #2)" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 6. "EFC3_INT0,External FlexCAN#3 Interrupt (ORing of input Line #1 and #0)" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 5. "EFC2_INT1,External FlexCAN#2 Interrupt (ORing of input Line #3 and #2)" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "EFC2_INT0,External FlexCAN#2 Interrupt (ORing of input Line #1 and #0)" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 3. "EFC1_INT1,External FlexCAN#1 Interrupt (ORing of input Line #3 and #2)" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 2. "EFC1_INT0,External FlexCAN#1 Interrupt (ORing of input Line #1 and #0)" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 1. "EFC0_INT1,External FlexCAN#0 Interrupt (ORing of input Line #3 and #2)" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 0. "EFC0_INT0,External FlexCAN#0 Interrupt (ORing of input Line #1 and #0)" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "ICSR36,Interrupt Concentrator Status Register#36"
|
|
bitfld.long 0x00 2. "ELINT2,External LinFlex Int#2" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 1. "ELINT1,External LinFlex Int#1" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 0. "ELINT0,External LinFlex Int#0" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ICSR37,Interrupt Concentrator Status Register#37"
|
|
bitfld.long 0x00 8. "HSEINT2,External HSE2 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
bitfld.long 0x00 4. "HSEINT1,External HSE1 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
newline
|
|
bitfld.long 0x00 0. "HSEINT0,External HSE0 Interrupt" "0: Interrupt is Absent,1: Interrupt is Present"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "ICSR38,Interrupt Concentrator Status Register#38"
|
|
hexmask.long.word 0x00 0.--11. 1. "EFRINT,External FlexRay Interrupts"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "ICSR39,Interrupt Concentrator Status Register#39"
|
|
bitfld.long 0x00 7. "GF3BINT,Generic FIFO 3 interrupt B status" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 6. "GF2BINT,Generic FIFO 2 interrupt B status" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 5. "GF1BINT,Generic FIFO 1 interrupt B status" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 4. "GF0BINT,Generic FIFO 0 interrupt B status" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 3. "GF3AINT,Generic FIFO 3 interrupt A status" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 2. "GF2AINT,Generic FIFO 2 interrupt A status" "0: Interrupt is absent,1: Interrupt is present"
|
|
newline
|
|
bitfld.long 0x00 1. "GF1AINT,Generic FIFO 1 interrupt A status" "0: Interrupt is absent,1: Interrupt is present"
|
|
bitfld.long 0x00 0. "GF0AINT,Generic FIFO 0 interrupt A status" "0: Interrupt is absent,1: Interrupt is present"
|
|
tree.end
|
|
tree "LLCE_IRCM"
|
|
base ad:0x43A15000
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "LLCE_IRSPRC0,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC0 are allowed,1: Writes to the LLCE_IRSPRC0 are ignored"
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "LLCE_IRSPRC1,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC1 are allowed,1: Writes to the LLCE_IRSPRC1 are ignored"
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "LLCE_IRSPRC2,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC2 are allowed,1: Writes to the LLCE_IRSPRC2 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "LLCE_IRSPRC3,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC3 are allowed,1: Writes to the LLCE_IRSPRC3 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "LLCE_IRSPRC4,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC4 are allowed,1: Writes to the LLCE_IRSPRC4 are ignored"
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x0A++0x01
|
|
line.word 0x00 "LLCE_IRSPRC5,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC5 are allowed,1: Writes to the LLCE_IRSPRC5 are ignored"
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "LLCE_IRSPRC6,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC6 are allowed,1: Writes to the LLCE_IRSPRC6 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "LLCE_IRSPRC7,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC7 are allowed,1: Writes to the LLCE_IRSPRC7 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "LLCE_IRSPRC8,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC8 are allowed,1: Writes to the LLCE_IRSPRC8 are ignored"
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "LLCE_IRSPRC9,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC9 are allowed,1: Writes to the LLCE_IRSPRC9 are ignored"
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "LLCE_IRSPRC10,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC10 are allowed,1: Writes to the LLCE_IRSPRC10 are ignored"
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
group.word 0x16++0x01
|
|
line.word 0x00 "LLCE_IRSPRC11,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC11 are allowed,1: Writes to the LLCE_IRSPRC11 are ignored"
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "LLCE_IRSPRC12,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC12 are allowed,1: Writes to the LLCE_IRSPRC12 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "LLCE_IRSPRC13,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC13 are allowed,1: Writes to the LLCE_IRSPRC13 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "LLCE_IRSPRC14,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC14 are allowed,1: Writes to the LLCE_IRSPRC14 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "LLCE_IRSPRC15,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC15 are allowed,1: Writes to the LLCE_IRSPRC15 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "LLCE_IRSPRC16,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC16 are allowed,1: Writes to the LLCE_IRSPRC16 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "LLCE_IRSPRC17,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC17 are allowed,1: Writes to the LLCE_IRSPRC17 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "LLCE_IRSPRC18,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC18 are allowed,1: Writes to the LLCE_IRSPRC18 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x26++0x01
|
|
line.word 0x00 "LLCE_IRSPRC19,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC19 are allowed,1: Writes to the LLCE_IRSPRC19 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "LLCE_IRSPRC20,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC20 are allowed,1: Writes to the LLCE_IRSPRC20 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x2A++0x01
|
|
line.word 0x00 "LLCE_IRSPRC21,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC21 are allowed,1: Writes to the LLCE_IRSPRC21 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "LLCE_IRSPRC22,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC22 are allowed,1: Writes to the LLCE_IRSPRC22 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "LLCE_IRSPRC23,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC23 are allowed,1: Writes to the LLCE_IRSPRC23 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "LLCE_IRSPRC24,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC24 are allowed,1: Writes to the LLCE_IRSPRC24 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "LLCE_IRSPRC25,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC25 are allowed,1: Writes to the LLCE_IRSPRC25 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "LLCE_IRSPRC26,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC26 are allowed,1: Writes to the LLCE_IRSPRC26 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "LLCE_IRSPRC27,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC27 are allowed,1: Writes to the LLCE_IRSPRC27 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "LLCE_IRSPRC28,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC28 are allowed,1: Writes to the LLCE_IRSPRC28 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x3A++0x01
|
|
line.word 0x00 "LLCE_IRSPRC29,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC29 are allowed,1: Writes to the LLCE_IRSPRC29 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "LLCE_IRSPRC30,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC30 are allowed,1: Writes to the LLCE_IRSPRC30 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "LLCE_IRSPRC31,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC31 are allowed,1: Writes to the LLCE_IRSPRC31 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "LLCE_IRSPRC32,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC32 are allowed,1: Writes to the LLCE_IRSPRC32 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "LLCE_IRSPRC33,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC33 are allowed,1: Writes to the LLCE_IRSPRC33 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "LLCE_IRSPRC34,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC34 are allowed,1: Writes to the LLCE_IRSPRC34 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x46++0x01
|
|
line.word 0x00 "LLCE_IRSPRC35,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC35 are allowed,1: Writes to the LLCE_IRSPRC35 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "LLCE_IRSPRC36,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC36 are allowed,1: Writes to the LLCE_IRSPRC36 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x4A++0x01
|
|
line.word 0x00 "LLCE_IRSPRC37,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC37 are allowed,1: Writes to the LLCE_IRSPRC37 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "LLCE_IRSPRC38,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC38 are allowed,1: Writes to the LLCE_IRSPRC38 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x4E++0x01
|
|
line.word 0x00 "LLCE_IRSPRC39,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC39 are allowed,1: Writes to the LLCE_IRSPRC39 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "LLCE_IRSPRC40,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC40 are allowed,1: Writes to the LLCE_IRSPRC40 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x52++0x01
|
|
line.word 0x00 "LLCE_IRSPRC41,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC41 are allowed,1: Writes to the LLCE_IRSPRC41 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "LLCE_IRSPRC42,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC42 are allowed,1: Writes to the LLCE_IRSPRC42 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x56++0x01
|
|
line.word 0x00 "LLCE_IRSPRC43,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC43 are allowed,1: Writes to the LLCE_IRSPRC43 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "LLCE_IRSPRC44,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC44 are allowed,1: Writes to the LLCE_IRSPRC44 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x5A++0x01
|
|
line.word 0x00 "LLCE_IRSPRC45,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC45 are allowed,1: Writes to the LLCE_IRSPRC45 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x5C++0x01
|
|
line.word 0x00 "LLCE_IRSPRC46,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC46 are allowed,1: Writes to the LLCE_IRSPRC46 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x5E++0x01
|
|
line.word 0x00 "LLCE_IRSPRC47,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC47 are allowed,1: Writes to the LLCE_IRSPRC47 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "LLCE_IRSPRC48,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC48 are allowed,1: Writes to the LLCE_IRSPRC48 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x62++0x01
|
|
line.word 0x00 "LLCE_IRSPRC49,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC49 are allowed,1: Writes to the LLCE_IRSPRC49 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "LLCE_IRSPRC50,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC50 are allowed,1: Writes to the LLCE_IRSPRC50 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x66++0x01
|
|
line.word 0x00 "LLCE_IRSPRC51,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC51 are allowed,1: Writes to the LLCE_IRSPRC51 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "LLCE_IRSPRC52,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC52 are allowed,1: Writes to the LLCE_IRSPRC52 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "LLCE_IRSPRC53,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC53 are allowed,1: Writes to the LLCE_IRSPRC53 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "LLCE_IRSPRC54,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC54 are allowed,1: Writes to the LLCE_IRSPRC54 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x6E++0x01
|
|
line.word 0x00 "LLCE_IRSPRC55,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC55 are allowed,1: Writes to the LLCE_IRSPRC55 are ignored"
|
|
bitfld.word 0x00 4. "HOSTE,Enable HOST Interrupt" "0: Routing to HOSTE for the corresponding..,1: Routing to HOSTE for the corresponding.."
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "LLCE_IRSPRC56,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC56 are allowed,1: Writes to the LLCE_IRSPRC56 are ignored"
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x72++0x01
|
|
line.word 0x00 "LLCE_IRSPRC57,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC57 are allowed,1: Writes to the LLCE_IRSPRC57 are ignored"
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x74++0x01
|
|
line.word 0x00 "LLCE_IRSPRC58,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC58 are allowed,1: Writes to the LLCE_IRSPRC58 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x76++0x01
|
|
line.word 0x00 "LLCE_IRSPRC59,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC59 are allowed,1: Writes to the LLCE_IRSPRC59 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x78++0x01
|
|
line.word 0x00 "LLCE_IRSPRC60,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC60 are allowed,1: Writes to the LLCE_IRSPRC60 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x7A++0x01
|
|
line.word 0x00 "LLCE_IRSPRC61,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to this register are allowed,1: Writes to this register are ignored"
|
|
bitfld.word 0x00 14. "CP3B23E,CP3 B23 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
newline
|
|
bitfld.word 0x00 13. "CP2B23E,CP2 B23 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
bitfld.word 0x00 12. "CP0B23E,CP0 B23 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
newline
|
|
bitfld.word 0x00 11. "CP3A23E,CP3 A23 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
bitfld.word 0x00 9. "CP1A23E,CP1 A23 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
newline
|
|
bitfld.word 0x00 8. "CP0A23E,CP0 A23 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
bitfld.word 0x00 7. "CP3B01E,CP3 B01 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
newline
|
|
bitfld.word 0x00 6. "CP2B01E,CP2 B01 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
bitfld.word 0x00 4. "CP0B01E,CP0 B01 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
newline
|
|
bitfld.word 0x00 3. "CP3A01E,CP3 A01 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
bitfld.word 0x00 1. "CP1A01E,CP1 A01 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
newline
|
|
bitfld.word 0x00 0. "CP0A01E,CP0 A01 Interrupt Enable" "0: Routing of the corresponding interrupt..,1: Routing of the corresponding interrupt.."
|
|
group.word 0x7C++0x01
|
|
line.word 0x00 "LLCE_IRSPRC62,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC62 are allowed,1: Writes to the LLCE_IRSPRC62 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x7E++0x01
|
|
line.word 0x00 "LLCE_IRSPRC63,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC63 are allowed,1: Writes to the LLCE_IRSPRC63 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "LLCE_IRSPRC64,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC64 are allowed,1: Writes to the LLCE_IRSPRC64 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x82++0x01
|
|
line.word 0x00 "LLCE_IRSPRC65,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC65 are allowed,1: Writes to the LLCE_IRSPRC65 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "LLCE_IRSPRC66,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC66 are allowed,1: Writes to the LLCE_IRSPRC66 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x86++0x01
|
|
line.word 0x00 "LLCE_IRSPRC67,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC67 are allowed,1: Writes to the LLCE_IRSPRC67 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 0. "CP0E,Enable CP0 Interrupt" "0: Routing to CP0 for the corresponding..,1: Routing to CP0 for the corresponding.."
|
|
group.word 0x88++0x01
|
|
line.word 0x00 "LLCE_IRSPRC68,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC68 are allowed,1: Writes to the LLCE_IRSPRC68 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
group.word 0x8A++0x01
|
|
line.word 0x00 "LLCE_IRSPRC69,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC69 are allowed,1: Writes to the LLCE_IRSPRC69 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
group.word 0x8C++0x01
|
|
line.word 0x00 "LLCE_IRSPRC70,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC70 are allowed,1: Writes to the LLCE_IRSPRC70 are ignored"
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
group.word 0x8E++0x01
|
|
line.word 0x00 "LLCE_IRSPRC71,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC71 are allowed,1: Writes to the LLCE_IRSPRC71 are ignored"
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
group.word 0x90++0x01
|
|
line.word 0x00 "LLCE_IRSPRC72,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC72 are allowed,1: Writes to the LLCE_IRSPRC72 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
group.word 0x92++0x01
|
|
line.word 0x00 "LLCE_IRSPRC73,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC73 are allowed,1: Writes to the LLCE_IRSPRC73 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
group.word 0x94++0x01
|
|
line.word 0x00 "LLCE_IRSPRC74,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC74 are allowed,1: Writes to the LLCE_IRSPRC74 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
group.word 0x96++0x01
|
|
line.word 0x00 "LLCE_IRSPRC75,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC75 are allowed,1: Writes to the LLCE_IRSPRC75 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
newline
|
|
bitfld.word 0x00 2. "CP2E,Enable CP2 Interrupt" "0: Routing to CP2 for the corresponding..,1: Routing to CP2 for the corresponding.."
|
|
bitfld.word 0x00 1. "CP1E,Enable CP1 Interrupt" "0: Routing to CP1 for the corresponding..,1: Routing to CP1 for the corresponding.."
|
|
group.word 0x98++0x01
|
|
line.word 0x00 "LLCE_IRSPRC76,LLCE Interrupt Router Shared Peripheral Routing Control Register"
|
|
bitfld.word 0x00 15. "WRLOCK,Write Lock" "0: Writes to the LLCE_IRSPRC76 are allowed,1: Writes to the LLCE_IRSPRC76 are ignored"
|
|
bitfld.word 0x00 3. "CP3E,Enable CP3 Interrupt" "0: Routing to CP3 for the corresponding..,1: Routing to CP3 for the corresponding.."
|
|
tree.end
|
|
tree "LLCE_FIFO"
|
|
tree "LLCE_BLR_IN_FIFO_0"
|
|
base ad:0x43B00000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.) (list ad:0x43A00000 ad:0x43A00400 ad:0x43A00800 ad:0x43A00C00 ad:0x43A01000 ad:0x43A01400 ad:0x43A01800 ad:0x43A01C00 ad:0x43A02000 ad:0x43A02400 ad:0x43A02800 ad:0x43A02C00 ad:0x43A03000 ad:0x43A03400 ad:0x43A03800 ad:0x43A03C00)
|
|
tree "LLCE_RX_IN_FIFO_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat.end
|
|
repeat 5. (list 16. 17. 18. 19. 20.) (list ad:0x43A04000 ad:0x43A04400 ad:0x43A04800 ad:0x43A04C00 ad:0x43A05000)
|
|
tree "LLCE_RX_IN_FIFO_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.) (list ad:0x43A08000 ad:0x43A08400 ad:0x43A08800 ad:0x43A08C00 ad:0x43A09000 ad:0x43A09400 ad:0x43A09800 ad:0x43A09C00 ad:0x43A0A000 ad:0x43A0A400 ad:0x43A0A800 ad:0x43A0AC00 ad:0x43A0B000 ad:0x43A0B400 ad:0x43A0B800 ad:0x43A0BC00)
|
|
tree "LLCE_RX_OUT_FIFO_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat.end
|
|
repeat 5. (list 16. 17. 18. 19. 20.) (list ad:0x43A0C000 ad:0x43A0C400 ad:0x43A0C800 ad:0x43A0CC00 ad:0x43A0D000)
|
|
tree "LLCE_RX_OUT_FIFO_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat.end
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x43A12000 ad:0x43A12400 ad:0x43A12800 ad:0x43A12C00)
|
|
tree "LLCE_GENERIC_FIFO_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16.) (list ad:0x43B00400 ad:0x43B00800 ad:0x43B00C00 ad:0x43B01000 ad:0x43B01400 ad:0x43B01800 ad:0x43B01C00 ad:0x43B02000 ad:0x43B02400 ad:0x43B02800 ad:0x43B02C00 ad:0x43B03000 ad:0x43B03400 ad:0x43B03800 ad:0x43B03C00 ad:0x43B04000)
|
|
tree "LLCE_BLR_IN_FIFO_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat.end
|
|
repeat 4. (list 17. 18. 19. 20.) (list ad:0x43B04400 ad:0x43B04800 ad:0x43B04C00 ad:0x43B05000)
|
|
tree "LLCE_BLR_IN_FIFO_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.) (list ad:0x43B08000 ad:0x43B08400 ad:0x43B08800 ad:0x43B08C00 ad:0x43B09000 ad:0x43B09400 ad:0x43B09800 ad:0x43B09C00 ad:0x43B0A000 ad:0x43B0A400 ad:0x43B0A800 ad:0x43B0AC00 ad:0x43B0B000 ad:0x43B0B400 ad:0x43B0B800 ad:0x43B0BC00)
|
|
tree "LLCE_BLR_OUT_FIFO_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat.end
|
|
repeat 5. (list 16. 17. 18. 19. 20.) (list ad:0x43B0C000 ad:0x43B0C400 ad:0x43B0C800 ad:0x43B0CC00 ad:0x43B0D000)
|
|
tree "LLCE_BLR_OUT_FIFO_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.) (list ad:0x43B10000 ad:0x43B10400 ad:0x43B10800 ad:0x43B10C00 ad:0x43B11000 ad:0x43B11400 ad:0x43B11800 ad:0x43B11C00 ad:0x43B12000 ad:0x43B12400 ad:0x43B12800 ad:0x43B12C00 ad:0x43B13000 ad:0x43B13400 ad:0x43B13800 ad:0x43B13C00)
|
|
tree "LLCE_TX_ACK_FIFO_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat.end
|
|
repeat 5. (list 16. 17. 18. 19. 20.) (list ad:0x43B14000 ad:0x43B14400 ad:0x43B14800 ad:0x43B14C00 ad:0x43B15000)
|
|
tree "LLCE_TX_ACK_FIFO_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCR,FIFO Configuration Register"
|
|
bitfld.long 0x00 24.--27. "WMKEMTYL,Watermark Empty Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "WMKFULLL,Watermark Full Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 5. "RD_POP_DIS,Read when POP Disabled" "0: RD_POP_DIS_0,1: POP operation"
|
|
bitfld.long 0x00 4. "FFLUSH,FIFO Flush" "0: No operation,1: FIFO Flush"
|
|
newline
|
|
bitfld.long 0x00 3. "PUSHEN,PUSH enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
bitfld.long 0x00 2. "POPEN,POP enable" "0: POP Disabled,1: POP Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "LENOWEN,Last entry overwrite enable" "0: Overwrite disabled,1: Overwrite enabled"
|
|
bitfld.long 0x00 0. "FIFOEN,FIFO enable" "0: FIFO Disabled,1: FIFO Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,FIFO Status Register 0"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark empty flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,FIFO Status Register 1"
|
|
rbitfld.long 0x00 24.--28. "FCOUNT,FIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSBNOMT_0,1: MSB mismatch"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH overflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP underflow flag" "0: No POP underflow,1: POP underflow"
|
|
newline
|
|
eventfld.long 0x00 14. "WMKEMTY,Watermark Empty Flag" "0: No Watermark Empty Event,1: Watermark Emty Event"
|
|
eventfld.long 0x00 13. "WMKFULL,Watermark Full Flag" "0: No Watermark Full Event,1: Watermark Full Event"
|
|
newline
|
|
eventfld.long 0x00 12. "POPEVT,POP event flag" "0: No POP event,1: POP event"
|
|
eventfld.long 0x00 11. "FNEMTY,FIFO not empty flag" "0: FIFO empty,1: FIFO not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "FEMTY,FIFO empty Flag" "0: FIFO not empty,1: FIFO empty"
|
|
eventfld.long 0x00 9. "FNFULL,FIFO not full flag" "0: FIFO Full,1: FIFO not Full"
|
|
newline
|
|
eventfld.long 0x00 8. "FFULL,FIFO Full Flag" "0: FIFO not Full,1: FIFO Full"
|
|
rbitfld.long 0x00 1. "FEMTYD,FIFO Not Empy Dynamic" "0: FIFO not empty,1: FIFO empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "FFULLD,FIFO Full Dynamic" "0: FIFO not Full,1: FIFO Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,FIFO interrupt enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP underflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "WMKEM_IE,Watermark empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IE,Watermark full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "POPEVT_IE,POP event interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IE,FIFO not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "FEMTY_IE,FIFO empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IE,FIFO not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "FFULL_IE,FIFO Full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,FIFO Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP underflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "WMKEM_IL,Watermark empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "WMKFL_IL,Watermark full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "POPEVT_IL,POP event interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "FNEMTY_IL,FIFO not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "FEMTY_IL,FIFO empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "FNFULL_IL,FIFO not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "FFULL_IL,FIFO Full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PUSHR0,FIFO push register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR0,FIFO POP Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FMR0,FIFO Fixed MSB Register"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LLCE_TXLUT"
|
|
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.) (list ad:0x43B18000 ad:0x43B18400 ad:0x43B18800 ad:0x43B18C00 ad:0x43B19000 ad:0x43B19400 ad:0x43B19800 ad:0x43B19C00 ad:0x43B1A000 ad:0x43B1A400 ad:0x43B1A800 ad:0x43B1AC00 ad:0x43B1B000 ad:0x43B1B400 ad:0x43B1B800 ad:0x43B1BC00)
|
|
tree "LLCE_TX_LUT_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 6. "LBEN,Last is Best Enable" "0: Last-is-best functionality is disabled and..,1: Last-is-best functionality is enabled such.."
|
|
bitfld.long 0x00 5. "TPEN,Transport Protocol Frame Enable" "0: Data written into PUSHR_ID and PUSHR_PTR is..,1: Data written into PUSHR_ID and PUSHR_PTR is.."
|
|
newline
|
|
bitfld.long 0x00 4. "QFLUSH,Queue Flush" "0: No operation,1: Queue Flush"
|
|
bitfld.long 0x00 3. "REMEN,Remove Enable" "0: Remove functionality disabled,1: Remove functionality enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "POPEN,POP Enable" "0: Entry is not removed from queue,1: Entry is removed from queue and a new search.."
|
|
bitfld.long 0x00 1. "PUSHEN,PUSH Enable" "0: PUSH Disabled,1: PUSH Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "MODEN,Module Enable" "0: Module Disabled,1: Module Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SR0,Status Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "QCOUNT,Queue Count"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB Not Matching Flag" "0: MSB matching,1: MSB not matching"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH Overflow Flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP Uderflow Flag" "0: No POP underflow,1: POP undeflow"
|
|
newline
|
|
eventfld.long 0x00 14. "REM_ERR,Remove Error Flag" "0: No remove error,1: Remove error"
|
|
eventfld.long 0x00 13. "REM_COMP,Remove Complete Flag" "0: Remove not complete,1: Remove complete"
|
|
newline
|
|
eventfld.long 0x00 12. "SE_COMP,Search Complete Flag" "0: Search not complete,1: Search complete"
|
|
eventfld.long 0x00 11. "QNEMTY,Queue Not Empty Flag" "0: Queue empty,1: Queue not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "QEMTY,Queue Empty Flag" "0: Queue not empty,1: Queue empty"
|
|
eventfld.long 0x00 9. "QNFULL,Queue Not Full Flag" "0: Queue full,1: Queue not full"
|
|
newline
|
|
eventfld.long 0x00 8. "QFULL,Queue Full Flag" "0: Queue not full,1: Queue full"
|
|
rbitfld.long 0x00 1. "QEMTYD,Queue Empty Dynamic" "0: Queue not empty,1: Queue empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "QFULLD,Queue Full Dynamic" "0: Queue not full,1: Queue Full"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR1,Status Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "QCOUNT,Queue Count"
|
|
eventfld.long 0x00 17. "MSBNOMT,MSB not matching flag" "0: MSB matching,1: MSB not matching"
|
|
newline
|
|
eventfld.long 0x00 16. "PUSHOVR,PUSH oveflow flag" "0: No PUSH overflow,1: PUSH overflow"
|
|
eventfld.long 0x00 15. "POPUND,POP undeflow flag" "0: No POP underflow,1: POP undeflow"
|
|
newline
|
|
eventfld.long 0x00 14. "REM_ERR,Remove error flag" "0: No remove error,1: Remove error"
|
|
eventfld.long 0x00 13. "REM_COMP,Remove complete flag" "0: Remove not complete,1: Remove complete"
|
|
newline
|
|
eventfld.long 0x00 12. "SE_COMP,Search complete flag" "0: Search not complete,1: Search complete"
|
|
eventfld.long 0x00 11. "QNEMTY,Queue not empty flag" "0: Queue empty,1: Queue not empty"
|
|
newline
|
|
eventfld.long 0x00 10. "QEMTY,Queue empty flag" "0: Queue not empty,1: Queue empty"
|
|
eventfld.long 0x00 9. "QNFULL,Queue not full flag" "0: Queue full,1: Queue not full"
|
|
newline
|
|
eventfld.long 0x00 8. "QFULL,Queue Full Flag" "0: Queue not full,1: Queue full"
|
|
rbitfld.long 0x00 1. "QEMTYD,Queue empty dynamic" "0: Queue not empty,1: Queue empty"
|
|
newline
|
|
rbitfld.long 0x00 0. "QFULLD,Queue Full Dynamic" "0: Queue not full,1: Queue Full"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,Interrupt Enable register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IE,MSB not matching interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "PUSHOVR_IE,PUSH overflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IE,POP undeflow interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "REM_ERR_IE,Remove error interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "REM_COMP_IE,Remove complete interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "SE_COMP_IE,Search complete interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "QNEMTY_IE,Queue not empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "QEMTY_IE,Queue empty interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "QNFULL_IE,Queue not full interrupt enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "QFULL_IE,Queue Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ILR,Interrupt Line Register"
|
|
bitfld.long 0x00 17. "MSBNOMT_IL,MSB not matching interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 16. "PUSHOVR_IL,PUSH overflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 15. "POPUND_IL,POP undeflow interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 14. "REM_ERR_IL,Remove error interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 13. "REM_COMP_IL,Remove complete interrupt" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 12. "SE_COMP_IL,Search complete interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 11. "QNEMTY_IL,Queue not empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 10. "QEMTY_IL,Queue empty interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
newline
|
|
bitfld.long 0x00 9. "QNFULL_IL,Queue not full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
bitfld.long 0x00 8. "QFULL_IL,Queue full interrupt line" "0: Flag routed to interrupt line A,1: Flag routed to interrupt line B"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FMR_PTR,Fixed MSB Register Pointer"
|
|
hexmask.long.word 0x00 0.--12. 1. "ENTRFMSB,Entry Fixed MSB"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PUSHR_PTR,PUSH Register Pointer"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PUSHR_ID,PUSH Register ID"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPUSH,Entry PUSH"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "POPR_HIGH,POP Register High"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,This field reads the memory pointer corresponding to highest priority CAN ID"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "POPR_LOW,POP Register Low"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRPOP,Entry POP"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "REMR,Remove Register"
|
|
hexmask.long 0x00 0.--31. 1. "ENTRREM,Entry Remove"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LLCE_LPSPI"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x43C00000 ad:0x43C01000 ad:0x43C02000 ad:0x43C03000)
|
|
tree "LLCE_LPSPI_$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSNUM,PCS Number"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: NO_EFFECT,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: NO_EFFECT,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: LPSPI module is disabled in debug mode,1: LPSPI module is enabled in debug mode"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
newline
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
eventfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
eventfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
eventfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
eventfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
eventfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
eventfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer of a received word has not yet..,1: Transfer of a received word has completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: DISABLED,1: ENABLED"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the Data.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is the LPSPI_HREQ pin,1: Host request input is the input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: LPSPI_HREQ pin is active high provided..,1: LPSPI_HREQ pin is active low provided.."
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request is disabled,1: Host request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are configured for chip select..,1: PCS[3:2] are configured for half-duplex 4-bit.."
|
|
bitfld.long 0x00 26. "OUTCFG,Output Configuration" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT is used..,1: SIN is used for both input and output data..,2: SOUT is used for both input and output data..,3: SOUT is used for input data and SIN is used.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: 010b - Match is enabled if 1st data word..,3: 011b - Match is enabled if any data word..,4: 100b - Match is enabled if 1st data word..,5: 101b - Match is enabled if any data word..,6: 110b - Match is enabled if (1st data word AND..,7: 111b - Match is enabled if (any data word AND.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when the transmit FIFO..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation is disabled,1: Automatic PCS generation is enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data is sampled on SCK edge,1: Input data is sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: SLAVE_MODE,1: MASTER_MODE"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK-to-PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS-to-SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,The FIFO Control register contains the RXWATER and TXWATER control fields"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap is disabled,1: Byte swap is enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer is disabled,1: Continuous transfer is enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: 1 bit transfer,1: 2 bit transfer,2: 4 bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LLCE_LINFLEXD"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x43C08000 ad:0x43C08400 ad:0x43C08800 ad:0x43C08C00)
|
|
tree "LLCE_LINFLEXD_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LINCR1,LIN Control Register 1"
|
|
bitfld.long 0x00 16. "NLSE,LIN State Capture Enable on Bit Error Enables capture of LIN state LINSR[LINS] whenever bit error flag occur that is LINESR[BEF] set to 1" "0: LIN state LINSR[LINS] shows the current LIN..,1: LIN state LINSR[LINS] is captured whenever.."
|
|
bitfld.long 0x00 15. "CCD,Checksum Calculation Disable You can read this field at any time and write to it only in Initialization mode" "0: Hardware performs the checksum calculation,1: Checksum calculation disabled"
|
|
newline
|
|
bitfld.long 0x00 14. "CFD,Checksum Field Disable You can read this field at any time and write to it only in Initialization mode" "0: Checksum field is sent after the required..,1: No checksum field is sent in the frame"
|
|
bitfld.long 0x00 12. "AUTOWU,Auto Wakeup You can read this field at any time and write to it only in Initialization mode" "0: Sleep bit is cleared by software only,1: Sleep bit gets cleared by hardware whenever.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "MBL,Master Break Length Chooses the length of the Sync break that the master generates" "0: 10-bit break length,1: 11-bit break length,2: 12-bit break length,3: 13-bit break length,4: 14-bit break length,5: 15-bit break length,6: 16-bit break length,7: 17-bit break length,8: 18-bit break length,9: 19-bit break length,10: 20-bit break length,11: 21-bit break length,12: 22-bit break length,13: 23-bit break length,14: 36-bit break length,15: 50-bit break length"
|
|
bitfld.long 0x00 5. "LBKM,Loop Back mode See Loop back mode in" "0: Loop Back mode disabled,1: Loop Back mode enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "MME,Master Mode Enable You can read this field at any time and write to it only in Initialization mode" "0: Slave mode,1: Master mode"
|
|
bitfld.long 0x00 3. "SSBL,Slave Mode Sync Break Length You can read this field at any time and write to it only in Initialization mode" "0: 11-bit break length,1: 10-bit break length"
|
|
newline
|
|
bitfld.long 0x00 2. "RBLM,Receiver Buffer Locked mode You can read this field at any time and write to it only in Initialization mode" "0: Receiver buffer not locked,1: Receiver buffer locked against overrun"
|
|
bitfld.long 0x00 1. "SLEEP,Sleep Mode Request Write a 1 to this field to request LINFlexD to enter Sleep mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "INIT,Initialization Mode Request Write a 1 to this field to request LINFlexD to enter Initialization mode" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "LINIER,LIN Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SZIE,Stuck at Zero Interrupt Enable An interrupt is generated if this bit is set and the Stuck at Zero Flag (SZF) in LINESR or UARTSR is set" "0: No interrupt,1: Interrupt enabled"
|
|
bitfld.long 0x00 14. "OCIE,Output Compare Interrupt Enable" "0: No interrupt,1: Interrupt generated when OCF bit in LINESR or.."
|
|
newline
|
|
bitfld.long 0x00 13. "BEIE,Bit Error Interrupt Enable" "0: No interrupt,1: Interrupt generated when BEF bit in LINESR is.."
|
|
bitfld.long 0x00 12. "CEIE,Checksum Error Interrupt Enable An interrupt is generated if this bit is set and the Checksum Error Flag (CEF) is set in LINESR" "0: No interrupt,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "HEIE,Header Error Interrupt Enable An interrupt is generated when this bit is set and either of the following flags are set: SFEF SDEF or IDPEF" "0: No interrupt,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "FEIE,Frame Error Interrupt Enable" "0: No interrupt,1: Interrupt generated if Frame Error Flag (FEF).."
|
|
newline
|
|
bitfld.long 0x00 7. "BOIE,Buffer Overrun Error Interrupt Enable An interrupt is generated if this bit is set and the Buffer Overrun Flag (BOF) is set in LINESR or UARTSR" "0: No interrupt,1: Interrupt enabled"
|
|
bitfld.long 0x00 6. "LSIE,LIN State Interrupt Enable Interrupt is generated only when entering the above fields" "0: No interrupt,1: Interrupt generated when entering the.."
|
|
newline
|
|
bitfld.long 0x00 5. "WUIE,Wakeup Interrupt Enable If WUIE=1 and the WUF in LINSR or UARTSR is set then an interrupt is generated" "0: No interrupt,1: Interrupt enabled"
|
|
bitfld.long 0x00 3. "TOIE,Timeout Interrupt Enable An interrupt is generated if this bit is set and UARTSR[TO]=1 (in UART mode)" "0: No interrupt,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "DRIE,Data Reception Complete Interrupt Enable An interrupt is generated when this bit is set and Data Received flag (DRF) in LINSR or UARTSR is set" "0: No interrupt,1: Interrupt enabled"
|
|
bitfld.long 0x00 1. "DTIE,Data Transmitted Interrupt enable An interrupt is generated when this bit is set and Data Transmitted flag (DTF) in LINSR or UARTSR is set" "0: No interrupt,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "HRIE,Header Received Interrupt An interrupt is generated when this bit is set and the Header Received flag (HRF) in LINSR is set" "0: No interrupt,1: Interrupt enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LINSR,LIN Status Register"
|
|
rbitfld.long 0x00 16.--18. "RDC,Receive Data Byte Count Contains the number of entries (bytes) in the Receive data buffer in LIN mode" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes,4: 5 bytes,5: 6 bytes,6: 7 bytes,7: 8 bytes"
|
|
bitfld.long 0x00 12.--15. "LINS,LIN State" "0: Sleep mode,1: Init mode,2: Idle mode,3: Sync break,4: Sync Del,5: Sync Field,6: Identifier Field,7: Header Reception/Transmission,8: Data Reception/Data Transmission,9: Checksum,?..."
|
|
newline
|
|
eventfld.long 0x00 9. "RMB,Release Message Buffer" "0: Buffer data is free and is reset by hardware..,1: Buffer data ready to be read by software"
|
|
eventfld.long 0x00 8. "DRBNE,Data Reception Buffer Not Empty LINFlexD writes a 1 to this field as soon as the first byte of response has been received and stored in BDRL (when there is at least one data byte in reception buffer)" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 7. "RXBUSY,Receiver Busy In Slave mode after header reception if DIR bit is reset and reception starts then this bit is set" "0: Receiver idle,1: Reception ongoing"
|
|
rbitfld.long 0x00 6. "RDI,Receiver Data Input Reflects the current status of the Rx pin After reset is released RDI reflects the actual value of Rx pin" "0,1"
|
|
newline
|
|
eventfld.long 0x00 5. "WUF,Wakeup flag This bit is set by hardware when a falling edge is detected on the Rx pin" "0,1"
|
|
eventfld.long 0x00 2. "DRF,Data Reception Completed Flag This bit is set by hardware and indicates that data reception completed" "0,1"
|
|
newline
|
|
eventfld.long 0x00 1. "DTF,Data Transmission Completed Flag This bit is set by hardware and indicates that data transmission completed" "0,1"
|
|
eventfld.long 0x00 0. "HRF,Header Received flag This bit is set when the header reception is completed" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LINESR,LIN Error Status Register"
|
|
eventfld.long 0x00 15. "SZF,Stuck At Zero Flag This bit is set when there is a stuck-at-zero timeout error" "0,1"
|
|
eventfld.long 0x00 14. "OCF,Output Compare Flag" "0: No output compare event occurred,1: In master mode LINESR[OCF] flag is set when.."
|
|
newline
|
|
eventfld.long 0x00 13. "BEF,Bit Error Flag LINFlexD writes a 1 to this field when a bit error occurs" "0,1"
|
|
eventfld.long 0x00 12. "CEF,Checksum Error Flag LINFlexD writes a 1 to this field if the received checksum does not match the hardware-calculated checksum" "0,1"
|
|
newline
|
|
eventfld.long 0x00 11. "SFEF,Sync Field Error Flag LINFlexD writes a 1 to this field when the received Sync Field is inconsistent" "0,1"
|
|
eventfld.long 0x00 10. "SDEF,Sync Delimiter Error Flag TLINFlexD writes a 1 to this field when the delimiter is too short (in other words less than one bit time)" "0,1"
|
|
newline
|
|
eventfld.long 0x00 9. "IDPEF,ID Parity Error Flag TLINFlexD writes a 1 to this field when an error in the ID parity occurs" "0,1"
|
|
eventfld.long 0x00 8. "FEF,Framing Error Flag LINFlexD writes a 1 to this field when a framing error (invalid stop bit) occurs" "0,1"
|
|
newline
|
|
eventfld.long 0x00 7. "BOF,Buffer Overrun Flag This bit is set by hardware when there is a new byte received and RMB bit is not cleared" "0,1"
|
|
eventfld.long 0x00 0. "NF,Noise Flag This bit is set by hardware when noise is detected in the received character" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "UARTCR,UART Mode Control Register"
|
|
bitfld.long 0x00 31. "MIS,Monitor Idle State Controls what UARTCTO monitors" "0: UARTCTO monitors the number of bits to be..,1: UARTCTO monitors the idle state of the.."
|
|
bitfld.long 0x00 28.--30. "CSP,Configurable Sample Point Decides the sample point during reduced oversampling" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "OSR,Over Sampling Rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "ROSE,Reduced Over Sampling Enable" "0: Each bit is over sampled sixteen times,1: OSR determines the oversampling rate"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "NEF,Number of expected frames" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19. "DTU_PCETX,Disable Timeout in UART mode" "0: Timeout has to be handled by software,1: Timeout in UART mode is disabled after the.."
|
|
newline
|
|
bitfld.long 0x00 17.--18. "SBUR,Stop Bits In UART Reception Mode When the UART is used for transmission and reception you need to set the same number of stop bits in GCR and SBUR" "0: 1 stop bit,1: 2 stop bits,2: 3 stop bits,?..."
|
|
bitfld.long 0x00 13.--15. "TDFL_TFC,Transmitter Data Field Length/TX FIFO Counter TDFL defines the number of bytes to be transmitted in UART buffer mode (TFBM = 0)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RDFL_RFC,Reception Data Field Length/RX FIFO Counter RDFL defines the number of bytes to be received in UART buffer mode (RFBM = 0)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. "RFBM,Rx FIFO/Buffer Mode Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Rx Buffer mode enabled,1: Rx FIFO mode enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "TFBM,Tx FIFO/Buffer Mode Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Tx Buffer mode enabled,1: Tx FIFO mode enabled"
|
|
bitfld.long 0x00 7. "WL1,Word Length In UART Mode Works with WL0 to configure word length as shown in the following table" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "PC1,Parity Control Works with PC0 to configure parity as shown in the following table" "0,1"
|
|
bitfld.long 0x00 5. "RxEn,Receiver Enable This bit can be programmed only when the UART bit is set" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "TxEn,Transmitter Enable This bit can be programmed only when UART bit is set" "0: Transmitter disabled,1: Transmitter enabled transmission starts only.."
|
|
bitfld.long 0x00 3. "PC0,Parity Control Works with PC1 to configure parity" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PCE,Parity Control Enable Register bit can be read in any mode written only in initialization mode when UART bit is set" "0: Parity transmit/check disabled,1: Parity transmit/check enabled"
|
|
bitfld.long 0x00 1. "WL0,Word Length in UART mode Works with WL1 to configure word length" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "UART,UART Mode Register bit can be read in any mode written only in initialization mode" "0: LIN mode,1: UART mode"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "UARTSR,UART Mode Status Register"
|
|
eventfld.long 0x00 15. "SZF,Stuck At Zero Flag LINFlexD writes a 1 to this field when LINFlexD detects 100 dominant bits" "0,1"
|
|
eventfld.long 0x00 14. "OCF,Output Compare Flag An interrupt will be generated if the OCIE bit in LINIER is set" "0: No output compare event occurred,1: The content of the counter has matched the.."
|
|
newline
|
|
eventfld.long 0x00 10.--13. "PE,Parity Error Flag Indicates whether a parity error occurred in the corresponding byte" "0: No parity error,1: Parity error in the corresponding received byte,?..."
|
|
eventfld.long 0x00 9. "RMB,Release Message Buffer This bit must be cleared by software" "0: Buffer data is free,1: Buffer data ready for software to"
|
|
newline
|
|
eventfld.long 0x00 8. "FEF,Framing Error Flag LINFlexD writes a 1 to this field when a framing error (invalid stop bit) occurs" "0: No framing error,1: Framing error occurs"
|
|
eventfld.long 0x00 7. "BOF,FIFO/Buffer overrun flag This bit is set by hardware when there is a new byte received and the RMB bit is not cleared in UART buffer mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 6. "RDI,Receiver Data Input signal This bit reflects the current status of the RX pin when UART bit is set" "0,1"
|
|
eventfld.long 0x00 5. "WUF,Wakeup flag This bit is set by hardware when a falling edge is detected on the RX pin in sleep mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4. "RFNE,Receive FIFO Not Empty RFNE bit is set by hardware in UART FIFO mode (RFBM = 1) when there is at least one data byte present in the receive FIFO" "0,1"
|
|
eventfld.long 0x00 3. "TO,Timeout This bit is set by hardware when a UART timeout occurs - in other words the value of UARTCTO becomes equal to the preset value of the timeout (UARTPTO register setting)" "0,1"
|
|
newline
|
|
eventfld.long 0x00 2. "DRFRFE,Data Reception Completed Flag /Rx FIFO Empty Flag DRF is set by hardware in UART buffer mode (RFBM = 0) and indicates that the number of bytes programmed in RDFL have been received" "0,1"
|
|
eventfld.long 0x00 1. "DTFTFF,Data Transmission Completed Flag/ TX FIFO Full Flag DTF is set by hardware in UART buffer mode (TFBM = 0) and indicates that data transmission is completed" "0,1"
|
|
newline
|
|
eventfld.long 0x00 0. "NF,Noise flag This bit is set by hardware when noise is detected in the received character" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LINTCSR,LIN Time-Out Control Status Register"
|
|
bitfld.long 0x00 10. "MODE,Time-out counter mode This bit can be configured only during initialization" "0: LIN mode,1: Output compare mode"
|
|
bitfld.long 0x00 9. "IOT,Idle on timeout Register bit can be read in any mode written only in initialization mode" "0: LIN state machine does not reset to Idle on..,1: LIN state machine resets to Idle on timeout.."
|
|
newline
|
|
bitfld.long 0x00 8. "TOCE,Time-out counter enable TOCE is always configurable by software in Initialization mode" "0: Time-out counter disable,1: Time-out counter enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CNT,Counter Value These bits reflect the value of a counter used for timeout"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "LINOCR,LIN Output Compare Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "OC2,Output compare value 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OC1,Output compare value 1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "LINTOCR,LIN Time-Out Control Register"
|
|
bitfld.long 0x00 8.--11. "RTO,Response timeout value This is the response timeout duration (in bit time) for 1 byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--6. 1. "HTO,Header timeout value This register contains the header timeout duration (in bit time)"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "LINFBRR,LIN Fractional Baud Rate Register"
|
|
bitfld.long 0x00 0.--3. "FBR,Fractional Baud rates Register bit can be read in any mode written only in initialization mode" "0: Fraction(LDIV) = 0,1: Fraction(LDIV) = 1/16,2: Fraction(LDIV) = 2/16,3: Fraction(LDIV) = 3/16,4: Fraction(LDIV) = 4/16,5: Fraction(LDIV) = 5/16,6: Fraction(LDIV) = 6/16,7: Fraction(LDIV) = 7/16,8: Fraction(LDIV) = 8/16,9: Fraction(LDIV) = 9/16,10: Fraction(LDIV) = 10/16,11: Fraction(LDIV) = 11/16,12: Fraction(LDIV) = 12/16,13: Fraction(LDIV) = 13/16,14: Fraction(LDIV) = 14/16,15: Fraction(LDIV) = 15/16"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "LINIBRR,LIN Integer Baud Rate Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. "IBR,Integer Baud rates These bits along with the fractional baud rate bits decide the LIN baud rate"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "LINCFR,LIN Checksum Field Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CF,Checksum bits When the CCD bit is reset these bits are read-only and are calculated by hardware"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "LINCR2,LIN Control Register 2"
|
|
bitfld.long 0x00 15. "TBDE,Two Bit delimiter bit This bit can be set in Initialization mode only" "0: Delimiter length in break field is 1 bit,1: Delimiter length in break field is 2 bits"
|
|
bitfld.long 0x00 14. "IOBE,Idle on Bit Error This bit can be set in Initialization mode only" "0: Bit Error does not reset LIN state machine,1: Bit Error resets LIN state machine"
|
|
newline
|
|
bitfld.long 0x00 13. "IOPE,Idle on Identifier Parity Error This bit can be set in Initialization mode only" "0: Parity Error does not reset LIN state machine,1: Parity Error resets LIN state machine"
|
|
bitfld.long 0x00 12. "WURQ,Wakeup Generate Request Setting this bit will generate a wakeup pulse" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "DDRQ,Data Discard request Set by software to stop data reception if the frame does not concern the node" "0,1"
|
|
bitfld.long 0x00 10. "DTRQ,Data Transmission Request Set by software in slave mode to request the transmission of the LIN Data field stored in the Buffer data register" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "ABRQ,Abort Request Set by software to abort the current transmission" "0,1"
|
|
bitfld.long 0x00 8. "HTRQ,Header Transmission Request Set by software to request the transmission of the LIN Header" "0,1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "BIDR,Buffer Identifier Register"
|
|
bitfld.long 0x00 10.--12. "DFL,Data Field Length Number of data bytes in the response part of the frame" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9. "DIR,Direction This bit controls the direction of the data field" "0: LINFlexD receives the data and copy them in..,1: LINFlexD transmits the data from the BDR.."
|
|
newline
|
|
bitfld.long 0x00 8. "CCS,Classic Checksum This bit controls the type of checksum applied on the current message" "0: Enhanced Checksum covering Identifier and..,1: Classic Checksum covering Data filed only"
|
|
bitfld.long 0x00 0.--5. "ID,Identifier Identifier part of the identifier field without the identifier parity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "BDRL,Buffer Data Register Least Significant"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA3,Data Byte 3 Data byte 3 of the data field"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA2,Data Byte 2 Data byte 2 of the data field"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA1,Data Byte 1 Data byte 1of the data field"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA0,Data Byte 0 Data byte 0 of the data field"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "BDRM,Buffer Data Register Most Significant"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA7,Data Byte 7 Data byte 7 of the data field"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA6,Data Byte 6 Data byte 6 of the data field"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA5,Data Byte 5 Data byte 5 of the data field"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA4,Data Byte 4 Data byte 4 of the data field"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GCR,Global Control Register"
|
|
bitfld.long 0x00 5. "TDFBM,Transmit data first bit MSB This bit controls the first bit of transmit data (payload only) as MSB/LSB in both UART and LIN modes" "0: The first bit of transmitted data is LSB - in..,1: The first bit of transmitted data is MSB - in.."
|
|
bitfld.long 0x00 4. "RDFBM,Received data first bit MSB This bit controls the first bit of received data (payload only) as MSB/LSB both in UART and LIN modes" "0: The first bit of received data is LSB - in..,1: The first bit of received data is MSB - in.."
|
|
newline
|
|
bitfld.long 0x00 3. "TDLIS,Transmit data level inversion selection This bit controls the data inversion of transmitted data (payload only) in both UART and LIN modes" "0: Transmitted data is not inverted,1: Transmitted data is inverted"
|
|
bitfld.long 0x00 2. "RDLIS,Received data level inversion selection This bit controls the data inversion of received data (payload only) in both UART and LIN modes" "0: Received data is not inverted,1: Received data is inverted"
|
|
newline
|
|
bitfld.long 0x00 1. "STOP,1/2 stop bit configuration This bit controls the number of stop bit transmitted data in both UART and LIN modes" "0: 1 stop bit,1: 2 stop bits"
|
|
bitfld.long 0x00 0. "SR,Soft reset SR executes a soft reset of the LINFlexD controller (FSMs FIFO pointers counters timers status and error registers) without modifying the configuration registers when a 1 write operation is performed" "0,1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "UARTPTO,UART Preset Timeout Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "PTO,Preset Timeout PTO defines the preset value of timeout counter"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "UARTCTO,UART Current Timeout Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "CTO,Current Timeout CTO defines the current value of the timeout counter"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LLCE_FR"
|
|
base ad:0x43C10000
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "MVR,Module Version Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. "CHIVER,CHI Version Number"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--7. 1. "PEVER,PE Version Number"
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "MCR,Module Configuration Register"
|
|
bitfld.word 0x00 15. "MEN,Module Enable" "0: Write: only during POC,1: Write: enable CC Read: CC enabled"
|
|
newline
|
|
bitfld.word 0x00 14. "SBFF,System Bus Failure Freeze" "0: Continue normal operation,1: Transition to freeze mode"
|
|
newline
|
|
bitfld.word 0x00 13. "SCM,Single Channel Device Mode" "0: CC works in dual channel device mode,1: CC works in single channel device mode"
|
|
newline
|
|
bitfld.word 0x00 12. "CHB,Channel B Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 11. "CHA,Channel A Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x00 10. "SFFE,Synchronization Frame Filter Enable" "0: Synchronization frame filtering disabled,1: Synchronization frame filtering enabled"
|
|
newline
|
|
bitfld.word 0x00 9. "ECCE,ECC Functionality Enable" "0: ECC functionality (injection detection..,1: ECC functionality enabled"
|
|
newline
|
|
bitfld.word 0x00 7. "FUM,FIFO Update Mode" "0: FIFOA/FIFOB is updated on writing 1 to..,1: FIFOA/FIFOB) is not updated on writing 1 to.."
|
|
newline
|
|
bitfld.word 0x00 6. "FAM,FIFO Address Mode" "0: FIFO Base Address located in,1: FIFO Base Address located in"
|
|
newline
|
|
bitfld.word 0x00 4. "CLKSEL,Protocol Engine Clock Source Select" "0: PE clock source is generated by on-chip..,1: PE clock source is generated by on-chip PLL"
|
|
newline
|
|
bitfld.word 0x00 1.--3. "BITRATE,FlexRay Bus Bit Rate" "0: 10.0 Mbit/sec,1: 5.0 Mbit/sec,2: 2.5 Mbit/sec,3: 8.0 Mbit/sec,?..."
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SYMBADHR,System Memory Base Address High Register"
|
|
hexmask.word 0x00 0.--15. 1. "SMBA,System Memory Base Address high"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SYMBADLR,System Memory Base Address Low Register"
|
|
hexmask.word 0x00 4.--15. 1. "SMBA,System Memory Base Address low"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "STBSCR,Strobe Signal Control Register"
|
|
bitfld.word 0x00 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL field only on write access"
|
|
newline
|
|
bitfld.word 0x00 8.--11. "SEL,Strobe Signal Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 4. "ENB,Strobe Signal Enable" "0: Strobe signal is disabled and not assigned to..,1: Strobe signal is enabled and assigned to the.."
|
|
newline
|
|
bitfld.word 0x00 0.--1. "STBPSEL,Strobe Port Select" "0: Assign selected signal to FR_DBG[0],1: Assign selected signal to FR_DBG[1],2: Assign selected signal to FR_DBG[2],3: Assign selected signal to FR_DBG[3]"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MBDSR,Message Buffer Data Size Register"
|
|
hexmask.word.byte 0x00 8.--14. 1. "MBSEG2DS,Message Buffer Segment 2 Data Size"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--6. 1. "MBSEG1DS,Message Buffer Segment 1 Data Size"
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MBSSUTR,Message Buffer Segment Size and Utilization Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. "LAST_MB_SEG1,Last Message Buffer In Segment 1"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--7. 1. "LAST_MB_UTIL,Last Message Buffer Utilized"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "PEDRAR,PE DRAM Access Register"
|
|
bitfld.word 0x00 12.--15. "INST,PE DRAM Access Instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 1.--11. 1. "ADDR,PE DRAM Access Address"
|
|
newline
|
|
rbitfld.word 0x00 0. "DAD,PE DRAM Access Done" "0: PE DRAM access running,1: PE DRAM access done"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "PEDRDR,PE DRAM Data Register"
|
|
hexmask.word 0x00 0.--15. 1. "DATA,Data to be written to or read from PE DRAM by the access initiated by write access to PEDRAR"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "POCR,Protocol Operation Control Register"
|
|
bitfld.word 0x00 15. "WME,Write Mode External Correction" "0: Write to EOC_AP and ERC_AP fields on register,1: No write to EOC_AP and ERC_AP fields on.."
|
|
newline
|
|
bitfld.word 0x00 10.--11. "EOC_AP,External Offset Correction Application" "0: Do not apply external offset correction value,?,2: Subtract external offset correction value,3: Add external offset correction value"
|
|
newline
|
|
bitfld.word 0x00 8.--9. "ERC_AP,External Rate Correction Application" "0: Do not apply external rate correction value,?,2: Subtract external rate correction value,3: Add external rate correction value"
|
|
newline
|
|
bitfld.word 0x00 7. "BSY_WMC,The name and function of this field varies depending on whether it is being read or written" "0: (Write-Only) Write to POCCMD field on register,1: (Write-Only) Do not write to POCCMD field on.."
|
|
newline
|
|
bitfld.word 0x00 0.--3. "POCCMD,Protocol Control Command" "0: ALLOW_COLDSTART,1: ALL_SLOTS,2: CONFIG,3: FREEZE,4: READY CONFIG_COMPLETE,5: RUN,6: DEFAULT_CONFIG,7: HALT,8: WAKEUP,?..."
|
|
group.word 0x16++0x01
|
|
line.word 0x00 "GIFER,Global Interrupt Flag and Enable Register"
|
|
rbitfld.word 0x00 15. "MIF,Module Interrupt Flag" "0: No interrupt flag and related interrupt..,1: At least one of the other interrupt flags in.."
|
|
newline
|
|
rbitfld.word 0x00 14. "PRIF,Protocol Interrupt Flag" "0: No individual protocol interrupt flag and..,1: At least one of the individual protocol.."
|
|
newline
|
|
rbitfld.word 0x00 13. "CHIF,CHI Interrupt Flag" "0: All CHI error flags are equal to 0 or the chi..,1: At least one CHI error flag and the chi error.."
|
|
newline
|
|
eventfld.word 0x00 12. "WUPIF,Wakeup Interrupt Flag" "0: No Wakeup symbol received on the FlexRay bus,1: Wakeup symbol received on the FlexRay bus"
|
|
newline
|
|
eventfld.word 0x00 11. "FAFBIF,Receive FIFO Channel B Almost Full Interrupt Flag" "0: No such event,1: FIFO B almost full event has occurred"
|
|
newline
|
|
eventfld.word 0x00 10. "FAFAIF,Receive FIFO Channel A Almost Full Interrupt Flag" "0: No such event,1: FIFO A almost full event has occurred"
|
|
newline
|
|
rbitfld.word 0x00 9. "RBIF,Receive Message Buffer Interrupt Flag" "0: None of the individual receive message..,1: At least one individual receive message.."
|
|
newline
|
|
rbitfld.word 0x00 8. "TBIF,Transmit Message Buffer Interrupt Flag" "0: None of the individual transmit message..,1: At least one individual transmit message.."
|
|
newline
|
|
bitfld.word 0x00 7. "MIE,Module Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
newline
|
|
bitfld.word 0x00 6. "PRIE,Protocol Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
newline
|
|
bitfld.word 0x00 5. "CHIE,CHI Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
newline
|
|
bitfld.word 0x00 4. "WUPIE,Wakeup Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
newline
|
|
bitfld.word 0x00 3. "FAFBIE,Receive FIFO Channel B Almost Full Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
newline
|
|
bitfld.word 0x00 2. "FAFAIE,Receive FIFO Channel A Almost Full Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
newline
|
|
bitfld.word 0x00 1. "RBIE,Receive Message Buffer Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
newline
|
|
bitfld.word 0x00 0. "TBIE,Transmit Message Buffer Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "PIFR0,Protocol Interrupt Flag Register 0"
|
|
eventfld.word 0x00 15. "FATL_IF,Fatal Protocol Error Interrupt Flag" "0: No such event,1: Fatal protocol error detected"
|
|
newline
|
|
eventfld.word 0x00 14. "INTL_IF,Internal Protocol Error Interrupt Flag" "0: No such event,1: Internal protocol error detected"
|
|
newline
|
|
eventfld.word 0x00 13. "ILCF_IF,Illegal Protocol Configuration Interrupt Flag" "0: No such event,1: Illegal protocol configuration detected"
|
|
newline
|
|
eventfld.word 0x00 12. "CSA_IF,Cold Start Abort Interrupt Flag" "0: No such event,1: Cold start aborted and no more coldstart.."
|
|
newline
|
|
eventfld.word 0x00 11. "MRC_IF,Missing Rate Correction Interrupt Flag" "0: No such event,1: Insufficient number of measurements for rate.."
|
|
newline
|
|
eventfld.word 0x00 10. "MOC_IF,Missing Offset Correction Interrupt Flag" "0: No such event,1: Insufficient number of measurements for.."
|
|
newline
|
|
eventfld.word 0x00 9. "CCL_IF,Clock Correction Limit Reached Interrupt Flag" "0: No such event,1: Offset or rate correction limit reached"
|
|
newline
|
|
eventfld.word 0x00 8. "MXS_IF,Max Sync Frames Detected Interrupt Flag" "0: No such event,1: More than node_sync_max sync frames detected"
|
|
newline
|
|
eventfld.word 0x00 7. "MTX_IF,Media Access Test Symbol Received Interrupt Flag" "0: No such event,1: MTS symbol received"
|
|
newline
|
|
eventfld.word 0x00 6. "LTXB_IF,pLatestTx Violation on Channel B Interrupt Flag" "0: No such event,1: pLatestTx violation occurred on channel B"
|
|
newline
|
|
eventfld.word 0x00 5. "LTXA_IF,pLatestTx Violation on Channel A Interrupt Flag" "0: No such event,1: pLatestTx violation occurred on channel A"
|
|
newline
|
|
eventfld.word 0x00 4. "TBVB_IF,Transmission across boundary on channel B Interrupt Flag" "0: No such event,1: Transmission across boundary violation.."
|
|
newline
|
|
eventfld.word 0x00 3. "TBVA_IF,Transmission across boundary on channel A Interrupt Flag" "0: No such event,1: Transmission across boundary violation.."
|
|
newline
|
|
eventfld.word 0x00 2. "TI2_IF,Timer 2 Expired Interrupt Flag" "0: No such event,1: Timer 2 has reached its time limit"
|
|
newline
|
|
eventfld.word 0x00 1. "TI1_IF,Timer 1 Expired Interrupt Flag" "0: No such event,1: Timer 1 has reached its time limit"
|
|
newline
|
|
eventfld.word 0x00 0. "CYS_IF,Cycle Start Interrupt Flag" "0: No such event,1: Communication cycle started"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "PIFR1,Protocol Interrupt Flag Register 1"
|
|
eventfld.word 0x00 15. "EMC_IF,Error Mode Changed Interrupt Flag" "0: No such event,1: ERRMODE field changed"
|
|
newline
|
|
eventfld.word 0x00 14. "IPC_IF,Illegal Protocol Control Command Interrupt Flag" "0: No such event,1: Illegal protocol control command detected"
|
|
newline
|
|
eventfld.word 0x00 13. "PECF_IF,Protocol Engine Communication Failure Interrupt Flag" "0: No such event,1: Protocol Engine Communication Failure detected"
|
|
newline
|
|
eventfld.word 0x00 12. "PSC_IF,Protocol State Changed Interrupt Flag" "0: No such event,1: Protocol state changed"
|
|
newline
|
|
eventfld.word 0x00 11. "SSI3_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.."
|
|
newline
|
|
eventfld.word 0x00 10. "SSI2_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.."
|
|
newline
|
|
eventfld.word 0x00 9. "SSI1_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.."
|
|
newline
|
|
eventfld.word 0x00 8. "SSI0_IF,Slot Status Counter Incremented Interrupt Flag" "0: No such event,1: The corresponding slot status counter has.."
|
|
newline
|
|
eventfld.word 0x00 5. "EVT_IF,Even Cycle Table Written Interrupt Flag" "0: No such event,1: Sync frame measurement table written"
|
|
newline
|
|
eventfld.word 0x00 4. "ODT_IF,Odd Cycle Table Written Interrupt Flag" "0: No such event,1: Sync frame measurement table written"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "PIER0,Protocol Interrupt Enable Register 0"
|
|
bitfld.word 0x00 15. "FATL_IE,Fatal Protocol Error Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 14. "INTL_IE,Internal Protocol Error Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 13. "ILCF_IE,Illegal Protocol Configuration Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 12. "CSA_IE,Cold Start Abort Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 11. "MRC_IE,Missing Rate Correction Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 10. "MOC_IE,Missing Offset Correction Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 9. "CCL_IE,Clock Correction Limit Reached Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 8. "MXS_IE,Max Sync Frames Detected Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 7. "MTX_IE,Media Access Test Symbol Received Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 6. "LTXB_IE,pLatestTx Violation on Channel B Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "LTXA_IE,pLatestTx Violation on Channel A Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 4. "TBVB_IE,Transmission across boundary on channel B Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 3. "TBVA_IE,Transmission across boundary on channel A Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 2. "TI2_IE,Timer 2 Expired Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "TI1_IE,Timer 1 Expired Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 0. "CYS_IE,Cycle Start Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "PIER1,Protocol Interrupt Enable Register 1"
|
|
bitfld.word 0x00 15. "EMC_IE,Error Mode Changed Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 14. "IPC_IE,Illegal Protocol Control Command Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 13. "PECF_IE,Protocol Engine Communication Failure Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 12. "PSC_IE,Protocol State Changed Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 11. "SSI3_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 10. "SSI2_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 9. "SSI1_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 8. "SSI0_IE,Slot Status Counter Incremented Interrupt Enable" "0: interrupt request generation disabled,1: interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 5. "EVT_IE,Even Cycle Table Written Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
bitfld.word 0x00 4. "ODT_IE,Odd Cycle Table Written Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CHIERFR,CHI Error Flag Register"
|
|
eventfld.word 0x00 15. "FRLB_EF,Frame Lost Channel B Error Flag" "0: No such event,1: Frame lost on channel B detected"
|
|
newline
|
|
eventfld.word 0x00 14. "FRLA_EF,Frame Lost Channel A Error Flag" "0: No such error,1: Frame lost on channel A detected"
|
|
newline
|
|
eventfld.word 0x00 13. "PCMI_EF,Protocol Command Ignored Error Flag" "0: No such error,1: POC command is ignored"
|
|
newline
|
|
eventfld.word 0x00 12. "FOVB_EF,Receive FIFO Overrun Channel B Error Flag" "0: No such error,1: FIFO overrun on channel B is detected"
|
|
newline
|
|
eventfld.word 0x00 11. "FOVA_EF,Receive FIFO Overrun Channel A Error Flag" "0: No such error,1: FIFO overrun on channel B is detected"
|
|
newline
|
|
eventfld.word 0x00 10. "MBS_EF,Message Buffer Search Error Flag" "0: No such event,1: Search engine is active while search start.."
|
|
newline
|
|
eventfld.word 0x00 9. "MBU_EF,Message Buffer Utilization Error Flag" "0: No such event,1: Non-utilized message buffer enabled"
|
|
newline
|
|
eventfld.word 0x00 8. "LCK_EF,Lock Error Flag" "0: No such error,1: Lock error detected"
|
|
newline
|
|
eventfld.word 0x00 6. "SBCF_EF,System Bus Communication Failure Error Flag" "0: No such event,1: System bus access not finished in time"
|
|
newline
|
|
eventfld.word 0x00 5. "FID_EF,Frame ID Error Flag" "0: No such error occurred,1: Frame ID error occurred"
|
|
newline
|
|
eventfld.word 0x00 4. "DPL_EF,Dynamic Payload Length Error Flag" "0: No such error occurred,1: Dynamic payload length error occurred"
|
|
newline
|
|
eventfld.word 0x00 3. "SPL_EF,Static Payload Length Error Flag" "0: No such error occurred,1: Static payload length error occurred"
|
|
newline
|
|
eventfld.word 0x00 2. "NML_EF,Network Management Length Error Flag" "0: No such error occurred,1: Network management length error occurred"
|
|
newline
|
|
eventfld.word 0x00 1. "NMF_EF,Network Management Frame Error Flag" "0: No such error occurred,1: Network management frame error occurred"
|
|
newline
|
|
eventfld.word 0x00 0. "ILSA_EF,Illegal System Bus Address Error Flag" "0: No such event,1: Illegal system bus address accessed"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "MBIVEC,Message Buffer Interrupt Vector Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. "TBIVEC,Transmit Buffer Interrupt Vector"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--7. 1. "RBIVEC,Receive Buffer Interrupt Vector"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "CASERCR,Channel A Status Error Counter Register"
|
|
hexmask.word 0x00 0.--15. 1. "CHAERSCNT,Channel A Status Error Counter"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "CBSERCR,Channel B Status Error Counter Register"
|
|
hexmask.word 0x00 0.--15. 1. "CHBERSCNT,Channel B Status Error Counter"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "PSR0,Protocol Status Register 0"
|
|
bitfld.word 0x00 14.--15. "ERRMODE,Error Mode" "0: ERRMODE_0,1: ERRMODE_1,2: ERRMODE_2,?..."
|
|
newline
|
|
bitfld.word 0x00 12.--13. "SLOTMODE,Slot Mode" "0: SLOTMODE_0,1: ALL_PENDING,2: SLOTMODE_2,?..."
|
|
newline
|
|
bitfld.word 0x00 8.--10. "PROTSTATE,Protocol State" "0: POC,1: PROTSTATE_1,2: PROTSTATE_2,3: PROTSTATE_3,4: POC,5: POC,6: PROTSTATE_6,7: PROTSTATE_7"
|
|
newline
|
|
bitfld.word 0x00 4.--7. "STARTUPSTATE,Startup State" "?,?,2: POC,3: POC,4: POC,5: POC,?,7: POC,?,?,10: POC,?,?,13: POC,14: POC,15: POC"
|
|
newline
|
|
bitfld.word 0x00 0.--2. "WAKEUPSTATUS,Wakeup Status" "0: WAKEUPSTATUS_0,1: RECEIVED_HEADER,2: WAKEUPSTATUS_2,3: COLLISION_ HEADER,4: WAKEUPSTATUS_4,5: COLLISION_UNKNOWN,6: WAKEUPSTATUS_6,?..."
|
|
group.word 0x2A++0x01
|
|
line.word 0x00 "PSR1,Protocol Status Register 1"
|
|
eventfld.word 0x00 15. "CSAA,Cold Start Attempt Aborted Flag" "0: No such event,1: Cold start attempt aborted"
|
|
newline
|
|
rbitfld.word 0x00 14. "CSP,Leading Cold Start Path" "0: No such event,1: POC"
|
|
newline
|
|
rbitfld.word 0x00 8.--12. "REMCSAT,Remaining Coldstart Attempts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
rbitfld.word 0x00 7. "CPN,Leading Cold Start Path Noise" "0: No such event,1: POC"
|
|
newline
|
|
rbitfld.word 0x00 6. "HHR,Host Halt Request Pending" "0: No such event,1: HALT command received"
|
|
newline
|
|
rbitfld.word 0x00 5. "FRZ,Freeze Occurred" "0: No such event,1: Immediate halt because of FREEZE or internal.."
|
|
newline
|
|
rbitfld.word 0x00 0.--4. "APTAC,Allow Passive to Active Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "PSR2,Protocol Status Register 2"
|
|
bitfld.word 0x00 15. "NBVB,NIT Boundary Violation on Channel B" "0: No such event,1: Media activity at boundaries detected"
|
|
newline
|
|
bitfld.word 0x00 14. "NSEB,NIT Syntax Error on Channel B" "0: No such event,1: Syntax error detected"
|
|
newline
|
|
bitfld.word 0x00 13. "STCB,Symbol Window Transmit Conflict on Channel B" "0: No such event,1: Transmission conflict detected"
|
|
newline
|
|
bitfld.word 0x00 12. "SBVB,Symbol Window Boundary Violation on Channel B" "0: No such event,1: Media activity at boundaries detected"
|
|
newline
|
|
bitfld.word 0x00 11. "SSEB,Symbol Window Syntax Error on Channel B" "0: No such event,1: Syntax error detected"
|
|
newline
|
|
bitfld.word 0x00 10. "MTB,Media Access Test Symbol MTS Received on Channel B" "0: No such event,1: MTS symbol received"
|
|
newline
|
|
bitfld.word 0x00 9. "NBVA,NIT Boundary Violation on Channel A" "0: No such event,1: Media activity at boundaries detected"
|
|
newline
|
|
bitfld.word 0x00 8. "NSEA,NIT Syntax Error on Channel A" "0: No such event,1: Syntax error detected"
|
|
newline
|
|
bitfld.word 0x00 7. "STCA,Symbol Window Transmit Conflict on Channel A" "0: No such event,1: Transmission conflict detected"
|
|
newline
|
|
bitfld.word 0x00 6. "SBVA,Symbol Window Boundary Violation on Channel A" "0: No such event,1: Media activity at boundaries detected"
|
|
newline
|
|
bitfld.word 0x00 5. "SSEA,Symbol Window Syntax Error on Channel A" "0: No such event,1: Syntax error detected"
|
|
newline
|
|
bitfld.word 0x00 4. "MTA,Media Access Test Symbol MTS Received on Channel A" "0: No such event,1: MTS symbol received"
|
|
newline
|
|
bitfld.word 0x00 0.--3. "CKCORFCNT,Clock Correction Failed Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "PSR3,Protocol Status Register 3"
|
|
eventfld.word 0x00 13. "WUB,Wakeup Symbol Received on Channel B" "0: No wakeup symbol received,1: Wakeup symbol received"
|
|
newline
|
|
eventfld.word 0x00 12. "ABVB,Aggregated Boundary Violation on Channel B" "0: No boundary violation detected,1: Boundary violation detected"
|
|
newline
|
|
eventfld.word 0x00 11. "AACB,Aggregated Additional Communication on Channel B" "0: No additional communication detected,1: Additional communication detected"
|
|
newline
|
|
eventfld.word 0x00 10. "ACEB,Aggregated Content Error on Channel B" "0: No content error detected,1: Content error detected"
|
|
newline
|
|
eventfld.word 0x00 9. "ASEB,Aggregated Syntax Error on Channel B" "0: No syntax error detected,1: Syntax errors detected"
|
|
newline
|
|
eventfld.word 0x00 8. "AVFB,Aggregated Valid Frame on Channel B" "0: No syntactically valid frames received,1: At least one syntactically valid frame received"
|
|
newline
|
|
eventfld.word 0x00 5. "WUA,Wakeup Symbol Received on Channel A" "0: No wakeup symbol received,1: Wakeup symbol received"
|
|
newline
|
|
eventfld.word 0x00 4. "ABVA,Aggregated Boundary Violation on Channel A" "0: No boundary violation detected,1: Boundary violation detected"
|
|
newline
|
|
eventfld.word 0x00 3. "AACA,Aggregated Additional Communication on Channel A" "0: No additional communication detected,1: Additional communication detected"
|
|
newline
|
|
eventfld.word 0x00 2. "ACEA,Aggregated Content Error on Channel A" "0: No content error detected,1: Content error detected"
|
|
newline
|
|
eventfld.word 0x00 1. "ASEA,Aggregated Syntax Error on Channel A" "0: No syntax error detected,1: Syntax errors detected"
|
|
newline
|
|
eventfld.word 0x00 0. "AVFA,Aggregated Valid Frame on Channel A" "0: No syntactically valid frames received,1: At least one syntactically valid frame received"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "MTCTR,Macrotick Counter Register"
|
|
hexmask.word 0x00 0.--13. 1. "MTCT,Macrotick Counter"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "CYCTR,Cycle Counter Register"
|
|
bitfld.word 0x00 0.--5. "CYCCNT,Cycle Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "SLTCTAR,Slot Counter Channel A Register"
|
|
hexmask.word 0x00 0.--10. 1. "SLOTCNTA,Slot Counter Value for Channel A"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "SLTCTBR,Slot Counter Channel B Register"
|
|
hexmask.word 0x00 0.--10. 1. "SLOTCNTB,Slot Counter Value for Channel B"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "RTCORVR,Rate Correction Value Register"
|
|
hexmask.word 0x00 0.--15. 1. "RATECORR,Rate Correction Value"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "OFCORVR,Offset Correction Value Register"
|
|
hexmask.word 0x00 0.--15. 1. "OFFSETCORR,Offset Correction Value"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "CIFR,Combined Interrupt Flag Register"
|
|
bitfld.word 0x00 7. "MIF,Module Interrupt Flag" "0: No interrupt source has its interrupt flag..,1: At least one interrupt source has its.."
|
|
newline
|
|
bitfld.word 0x00 6. "PRIF,Protocol Interrupt Flag" "0: All individual protocol interrupt flags are..,1: At least one of the individual protocol.."
|
|
newline
|
|
bitfld.word 0x00 5. "CHIF,CHI Interrupt Flag" "0: All CHI error flags are equal to 0,1: At least one CHI error flag is equal to 1"
|
|
newline
|
|
bitfld.word 0x00 4. "WUPIF,Wakeup Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 3. "FAFBIF,Receive FIFO Channel B Almost Full Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 2. "FAFAIF,Receive FIFO Channel A Almost Full Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x00 1. "RBIF,Receive Message Buffer Interrupt Flag" "0: None of the individual receive message..,1: At least one individual receive message.."
|
|
newline
|
|
bitfld.word 0x00 0. "TBIF,Transmit Message Buffer Interrupt Flag" "0: None of the individual transmit message..,1: At least one individual transmit message.."
|
|
group.word 0x3E++0x01
|
|
line.word 0x00 "SYMATOR,System Memory Access Time-Out Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. "TIMEOUT,System Memory Access Time-Out"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "SFCNTR,Sync Frame Counter Register"
|
|
bitfld.word 0x00 12.--15. "SFEVB,Sync Frames Channel B even cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 8.--11. "SFEVA,Sync Frames Channel A even cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 4.--7. "SFODB,Sync Frames Channel B odd cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 0.--3. "SFODA,Sync Frames Channel A odd cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "SFTOR,Sync Frame Table Offset Register"
|
|
hexmask.word 0x00 1.--15. 1. "SFT_OFFSET,Sync Frame Table Offset"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "SFTCCSR,Sync Frame Table Configuration Control Status Register"
|
|
bitfld.word 0x00 15. "ELKT,Even Cycle Tables Lock/Unlock Trigger" "0: No effect,1: Triggers lock/unlock of the even cycle tables"
|
|
newline
|
|
bitfld.word 0x00 14. "OLKT,Odd Cycle Tables Lock/Unlock Trigger" "0: No effect,1: Triggers lock/unlock of the odd cycle tables"
|
|
newline
|
|
rbitfld.word 0x00 8.--13. "CYCNUM,Cycle Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.word 0x00 7. "ELKS,Even Cycle Tables Lock Status" "0: Application has not locked the even cycle..,1: Application has locked the even cycle tables"
|
|
newline
|
|
rbitfld.word 0x00 6. "OLKS,Odd Cycle Tables Lock Status" "0: Application has not locked the odd cycle tables,1: Application has locked the odd cycle tables"
|
|
newline
|
|
rbitfld.word 0x00 5. "EVAL,Even Cycle Tables Valid" "0: Tables are not valid (update is ongoing),1: Tables are valid (consistent)"
|
|
newline
|
|
rbitfld.word 0x00 4. "OVAL,Odd Cycle Tables Valid" "0: Tables are not valid (update is ongoing),1: Tables are valid (consistent)"
|
|
newline
|
|
bitfld.word 0x00 2. "OPT,One Pair Trigger" "0: Write continuously pairs of enabled Sync..,1: Write only one pair of enabled Sync Frame.."
|
|
newline
|
|
bitfld.word 0x00 1. "SDVEN,Sync Frame Deviation Table Enable" "0: Do not write Sync Frame Deviation Tables,1: Write Sync Frame Deviation Tables into.."
|
|
newline
|
|
bitfld.word 0x00 0. "SIDEN,SIDEN" "0: Do not write Sync Frame ID Tables,1: Write Sync Frame ID Tables into FlexRay.."
|
|
group.word 0x46++0x01
|
|
line.word 0x00 "SFIDRFR,Sync Frame ID Rejection Filter Register"
|
|
hexmask.word 0x00 0.--9. 1. "SYNFRID,Sync Frame Rejection ID"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "SFIDAFVR,Sync Frame ID Acceptance Filter Value Register"
|
|
hexmask.word 0x00 0.--9. 1. "FVAL,Filter Value"
|
|
group.word 0x4A++0x01
|
|
line.word 0x00 "SFIDAFMR,Sync Frame ID Acceptance Filter Mask Register"
|
|
hexmask.word 0x00 0.--9. 1. "FMSK,Filter Mask"
|
|
repeat 6. (increment 0 1) (increment 0 0x2)
|
|
rgroup.word ($2+0x4C)++0x01
|
|
line.word 0x00 "NMVR[$1],Network Management Vector Register $1"
|
|
hexmask.word 0x00 0.--15. 1. "NMVP,Network Management Vector Part"
|
|
repeat.end
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "NMVLR,Network Management Vector Length Register"
|
|
bitfld.word 0x00 0.--3. "NMVL,Network Management Vector Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x5A++0x01
|
|
line.word 0x00 "TICCR,Timer Configuration and Control Register"
|
|
bitfld.word 0x00 13. "T2_CFG,Timer T2 Configuration" "0: T2 is an absolute timer,1: T2 is a relative timer"
|
|
newline
|
|
bitfld.word 0x00 12. "T2_REP,Timer T2 Repetitive Mode" "0: T2 is non repetitive,1: T2 is repetitive"
|
|
newline
|
|
bitfld.word 0x00 10. "T2SP,Timer T2 Stop" "0: No effect,1: Stop timer T2"
|
|
newline
|
|
bitfld.word 0x00 9. "T2TR,Timer T2 Trigger" "0: No effect,1: Start timer T2"
|
|
newline
|
|
rbitfld.word 0x00 8. "T2ST,Timer T2 State" "0: Timer T2 is idle,1: Timer T2 is running"
|
|
newline
|
|
bitfld.word 0x00 4. "T1_REP,Timer T1 Repetitive Mode" "0: T1 is non repetitive,1: T1 is repetitive"
|
|
newline
|
|
bitfld.word 0x00 2. "T1SP,Timer T1 Stop" "0: No effect,1: Stop timer T1"
|
|
newline
|
|
bitfld.word 0x00 1. "T1TR,Timer T1 Trigger" "0: No effect,1: Start timer T1"
|
|
newline
|
|
rbitfld.word 0x00 0. "T1ST,Timer T1 State" "0: Timer T1 is idle,1: Timer T1 is running"
|
|
group.word 0x5C++0x01
|
|
line.word 0x00 "TI1CYSR,Timer 1 Cycle Set Register"
|
|
bitfld.word 0x00 8.--13. "T1_CYC_VAL,Timer T1 Cycle Filter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.word 0x00 0.--5. "T1_CYC_MSK,Timer T1 Cycle Filter Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x5E++0x01
|
|
line.word 0x00 "TI1MTOR,Timer 1 Macrotick Offset Register"
|
|
hexmask.word 0x00 0.--13. 1. "T1_MTOFFSET,Timer 1 Macrotick Offset"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "TI2CR0_ABS,Timer 2 Configuration Register 0 (Absolute Timer Configuration)"
|
|
bitfld.word 0x00 8.--13. "T2CYCVAL,Timer T2 Cycle Filter Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.word 0x00 0.--5. "T2CYCMSK,Timer T2 Cycle Filter Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "TI2CR0_REL,Timer 2 Configuration Register 0 (Relative Timer Configuration)"
|
|
hexmask.word 0x00 0.--15. 1. "T2MTCNT,Timer T2 Macrotick High Word"
|
|
group.word 0x62++0x01
|
|
line.word 0x00 "TI2CR1_ABS,Timer 2 Configuration Register 1 (Absolute Timer Configuration)"
|
|
hexmask.word 0x00 0.--13. 1. "T2MOFF,Timer T2 Macrotick Offset"
|
|
group.word 0x62++0x01
|
|
line.word 0x00 "TI2CR1_REL,Timer 2 Configuration Register 1 (Relative Timer Configuration)"
|
|
hexmask.word 0x00 0.--15. 1. "T2MTCNT,Timer T2 Macrotick Low Word"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "SSSR,Slot Status Selection Register"
|
|
bitfld.word 0x00 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL field only on write access"
|
|
newline
|
|
bitfld.word 0x00 12.--13. "SEL,Selector" "0: Select SSSR0,1: Select SSSR1,2: Select SSSR2,3: Select SSSR3"
|
|
newline
|
|
hexmask.word 0x00 0.--10. 1. "SLOTNUMBER,Slot Number"
|
|
group.word 0x66++0x01
|
|
line.word 0x00 "SSCCR,Slot Status Counter Condition Register"
|
|
bitfld.word 0x00 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL field only on write access"
|
|
newline
|
|
bitfld.word 0x00 12.--13. "SEL,Selector" "0: Select SSCCR0,1: Select SSCCR1,2: Select SSCCR2,3: Select SSCCR3"
|
|
newline
|
|
bitfld.word 0x00 9.--10. "CNTCFG,Counter Configuration" "0: Increment by 1 if condition is fulfilled on..,1: Increment by 1 if condition is fulfilled on..,2: Increment by 1 if condition is fulfilled on..,3: Increment by 2 if condition is fulfilled on.."
|
|
newline
|
|
bitfld.word 0x00 8. "MCY,Multi Cycle Selection" "0: The Slot Status Counter provides information..,1: The Slot Status Counter accumulates over.."
|
|
newline
|
|
bitfld.word 0x00 7. "VFR,Valid Frame Restriction" "0: The counter is not restricted to valid frames..,1: The counter is restricted to valid frames only"
|
|
newline
|
|
bitfld.word 0x00 6. "SYF,Sync Frame Restriction" "0: The counter is not restricted with respect to..,1: The counter is restricted to frames with the.."
|
|
newline
|
|
bitfld.word 0x00 5. "NUF,Null Frame Restriction" "0: The counter is not restricted with respect to..,1: The counter is restricted to frames with the.."
|
|
newline
|
|
bitfld.word 0x00 4. "SUF,Startup Frame Restriction" "0: The counter is not restricted with respect to..,1: The counter is restricted to received frames.."
|
|
newline
|
|
bitfld.word 0x00 0.--3. "STATUSMASK,Slot Status Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 8. (increment 0 1) (increment 0 0x2)
|
|
rgroup.word ($2+0x68)++0x01
|
|
line.word 0x00 "SSR[$1],Slot Status Register $1"
|
|
bitfld.word 0x00 15. "VFB,Valid Frame on Channel B" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1"
|
|
newline
|
|
bitfld.word 0x00 14. "SYB,Sync Frame Indicator Channel B" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1"
|
|
newline
|
|
bitfld.word 0x00 13. "NFB,Null Frame Indicator Channel B" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1"
|
|
newline
|
|
bitfld.word 0x00 12. "SUB,Startup Frame Indicator Channel B" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1"
|
|
newline
|
|
bitfld.word 0x00 11. "SEB,Syntax Error on Channel B" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1"
|
|
newline
|
|
bitfld.word 0x00 10. "CEB,Content Error on Channel B" "0: vSS!ContentError = 0,1: vSS!ContentError = 1"
|
|
newline
|
|
bitfld.word 0x00 9. "BVB,Boundary Violation on Channel B" "0: vSS!BViolation = 0,1: vSS!BViolation = 1"
|
|
newline
|
|
bitfld.word 0x00 8. "TCB,Transmission Conflict on Channel B" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1"
|
|
newline
|
|
bitfld.word 0x00 7. "VFA,Valid Frame on Channel A" "0: vSS!ValidFrame = 0,1: vSS!ValidFrame = 1"
|
|
newline
|
|
bitfld.word 0x00 6. "SYA,Sync Frame Indicator Channel A" "0: vRF!Header!SyFIndicator = 0,1: vRF!Header!SyFIndicator = 1"
|
|
newline
|
|
bitfld.word 0x00 5. "NFA,Null Frame Indicator Channel A" "0: vRF!Header!NFIndicator = 0,1: vRF!Header!NFIndicator = 1"
|
|
newline
|
|
bitfld.word 0x00 4. "SUA,Startup Frame Indicator Channel A" "0: vRF!Header!SuFIndicator = 0,1: vRF!Header!SuFIndicator = 1"
|
|
newline
|
|
bitfld.word 0x00 3. "SEA,SEA" "0: vSS!SyntaxError = 0,1: vSS!SyntaxError = 1"
|
|
newline
|
|
bitfld.word 0x00 2. "CEA,Content Error on Channel A" "0: vSS!ContentError = 0,1: vSS!ContentError = 1"
|
|
newline
|
|
bitfld.word 0x00 1. "BVA,Boundary Violation on Channel A" "0: vSS!BViolation = 0,1: vSS!BViolation = 1"
|
|
newline
|
|
bitfld.word 0x00 0. "TCA,Transmission Conflict on Channel A" "0: vSS!TxConflict = 0,1: vSS!TxConflict = 1"
|
|
repeat.end
|
|
repeat 4. (increment 0 1) (increment 0 0x2)
|
|
rgroup.word ($2+0x78)++0x01
|
|
line.word 0x00 "SSCR[$1],Slot Status Counter Register $1"
|
|
hexmask.word 0x00 0.--15. 1. "SLOTSTATUSCNT,Slot Status Counter"
|
|
repeat.end
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "MTSACFR,MTS A Configuration Register"
|
|
bitfld.word 0x00 15. "MTE,Media Access Test Symbol Transmission Enable" "0: MTS transmission disabled,1: MTS transmission enabled"
|
|
newline
|
|
bitfld.word 0x00 8.--13. "CYCCNTMSK,Cycle Counter Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.word 0x00 0.--5. "CYCCNTVAL,Cycle Counter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x82++0x01
|
|
line.word 0x00 "MTSBCFR,MTS B Configuration Register"
|
|
bitfld.word 0x00 15. "MTE,Media Access Test Symbol Transmission Enable" "0: MTS transmission disabled,1: MTS transmission enabled"
|
|
newline
|
|
bitfld.word 0x00 8.--13. "CYCCNTMSK,Cycle Counter Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.word 0x00 0.--5. "CYCCNTVAL,Cycle Counter Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "RSBIR,Receive Shadow Buffer Index Register"
|
|
bitfld.word 0x00 15. "WMD,Write Mode" "0: Update SEL and RSBIDX field on register,1: Update only SEL field on register"
|
|
newline
|
|
bitfld.word 0x00 12.--13. "SEL,Selector" "0: RSBIR_A1-receive shadow buffer index register..,1: RSBIR_A2-receive shadow buffer index register..,2: RSBIR_B1-receive shadow buffer index register..,3: RSBIR_B2-receive shadow buffer index register.."
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "RSBIDX,RSBIDXA1/RSBIDXA2/RSBIDXB1/RSBIDXB2- Receive Shadow Buffer Index"
|
|
group.word 0x86++0x01
|
|
line.word 0x00 "RFWMSR,Receive FIFO Watermark and Selection Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. "WM,WMA/WMB - Watermark"
|
|
newline
|
|
bitfld.word 0x00 0. "SEL,Select" "0: Receiver FIFO for channel A selected,1: Receiver FIFO for channel B selected"
|
|
group.word 0x88++0x01
|
|
line.word 0x00 "RFSIR,Receive FIFO Start Index Register"
|
|
hexmask.word 0x00 0.--9. 1. "SIDX,SIDXA/SIDXB - Start Index"
|
|
group.word 0x8A++0x01
|
|
line.word 0x00 "RFDSR,Receive FIFO Depth and Size Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. "FIFO_DEPTH,FIFO_DEPTHA/FIFO_DEPTHB - FIFO Depth"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--6. 1. "ENTRY_SIZE,ENTRY_SIZEA/ENTRY_SIZEB - Entry Size"
|
|
rgroup.word 0x8C++0x01
|
|
line.word 0x00 "RFARIR,Receive FIFO A Read Index Register"
|
|
hexmask.word 0x00 0.--9. 1. "RDIDX,Read Index"
|
|
rgroup.word 0x8E++0x01
|
|
line.word 0x00 "RFBRIR,Receive FIFO B Read Index Register"
|
|
hexmask.word 0x00 0.--9. 1. "RDIDX,Read Index"
|
|
group.word 0x90++0x01
|
|
line.word 0x00 "RFMIDAFVR,Receive FIFO Message ID Acceptance Filter Value Register"
|
|
hexmask.word 0x00 0.--15. 1. "MIDAFVAL,MIDAFVALA/MIDAFVALB - Message ID Acceptance Filter Value"
|
|
group.word 0x92++0x01
|
|
line.word 0x00 "RFMIDAFMR,Receive FIFO Message ID Acceptance Filter Mask Register"
|
|
hexmask.word 0x00 0.--15. 1. "MIDAFMSK,MIDAFMSKA/MIDAFMSKB - Message ID Acceptance Filter Mask"
|
|
group.word 0x94++0x01
|
|
line.word 0x00 "RFFIDRFVR,Receive FIFO Frame ID Rejection Filter Value Register"
|
|
hexmask.word 0x00 0.--10. 1. "FIDRFVAL,FIDRFVALA/FIDRFVALB - Frame ID Rejection Filter Value"
|
|
group.word 0x96++0x01
|
|
line.word 0x00 "RFFIDRFMR,Receive FIFO Frame ID Rejection Filter Mask Register"
|
|
hexmask.word 0x00 0.--10. 1. "FIDRFMSK,Frame ID Rejection Filter Mask"
|
|
group.word 0x98++0x01
|
|
line.word 0x00 "RFRFCFR,Receive FIFO Range Filter Configuration Register"
|
|
bitfld.word 0x00 15. "WMD,Write Mode" "0: Write to all fields in this register on write..,1: Write to SEL and IBD field only on write access"
|
|
newline
|
|
bitfld.word 0x00 14. "IBD,Interval Boundary" "0: Program lower interval boundary,1: Program upper interval boundary"
|
|
newline
|
|
bitfld.word 0x00 12.--13. "SEL,Filter Selector" "0: Select frame ID range filter 0,1: Select frame ID range filter 1,2: Select frame ID range filter 2,3: Select frame ID range filter 3"
|
|
newline
|
|
hexmask.word 0x00 0.--10. 1. "SID,Slot ID"
|
|
group.word 0x9A++0x01
|
|
line.word 0x00 "RFRFCTR,Receive FIFO Range Filter Control Register"
|
|
bitfld.word 0x00 11. "F3MD,Range Filter 3 Mode" "0: Range filter 3 runs as acceptance filter,1: Range filter 3 runs as rejection filter"
|
|
newline
|
|
bitfld.word 0x00 10. "F2MD,Range Filter 2 Mode" "0: Range filter 2 runs as acceptance filter,1: Range filter 2 runs as rejection filter"
|
|
newline
|
|
bitfld.word 0x00 9. "F1MD,Range Filter 1 Mode" "0: Range filter 1 runs as acceptance filter,1: Range filter 1 runs as rejection filter"
|
|
newline
|
|
bitfld.word 0x00 8. "F0MD,Range Filter 0 Mode" "0: Range filter 0 runs as acceptance filter,1: Range filter 0 runs as rejection filter"
|
|
newline
|
|
bitfld.word 0x00 3. "F3EN,Range Filter 3 Enable" "0: Range filter 3 disabled,1: Range filter 3 enabled"
|
|
newline
|
|
bitfld.word 0x00 2. "F2EN,Range Filter 2 Enable" "0: Range filter 2 disabled,1: Range filter 2 enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "F1EN,Range Filter 1 Enable" "0: Range filter 1 disabled,1: Range filter 1 enabled"
|
|
newline
|
|
bitfld.word 0x00 0. "F0EN,Range Filter 0 Enable" "0: Range filter 0 disabled,1: Range filter 0 enabled"
|
|
rgroup.word 0x9C++0x01
|
|
line.word 0x00 "LDTXSLAR,Last Dynamic Transmit Slot Channel A Register"
|
|
hexmask.word 0x00 0.--10. 1. "LDYNTXSLOTA,Last Dynamic Transmission Slot Channel A"
|
|
rgroup.word 0x9E++0x01
|
|
line.word 0x00 "LDTXSLBR,Last Dynamic Transmit Slot Channel B Register"
|
|
hexmask.word 0x00 0.--10. 1. "LDYNTXSLOTB,Last Dynamic Transmission Slot Channel B"
|
|
group.word 0xA0++0x01
|
|
line.word 0x00 "PCR0,Protocol Configuration Register 0"
|
|
bitfld.word 0x00 10.--15. "action_point_offset,action_point_offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.word 0x00 0.--9. 1. "static_slot_length,static_slot_length"
|
|
group.word 0xA2++0x01
|
|
line.word 0x00 "PCR1,Protocol Configuration Register 1"
|
|
hexmask.word 0x00 0.--13. 1. "macro_after_first_static_slot,macro_after_first_static_slot"
|
|
group.word 0xA4++0x01
|
|
line.word 0x00 "PCR2,Protocol Configuration Register 2"
|
|
bitfld.word 0x00 10.--15. "minislot_after_action_point,minislot_after_action_point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.word 0x00 0.--9. 1. "number_of_static_slots,gNumberOfStaticSlots"
|
|
group.word 0xA6++0x01
|
|
line.word 0x00 "PCR3,Protocol Configuration Register 3"
|
|
bitfld.word 0x00 10.--15. "wakeup_symbol_rx_low,wakeup_symbol_rx_low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.word 0x00 5.--9. "minislot_action_point_offset,minislot_action_point_offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.word 0x00 0.--4. "coldstart_attempts,coldstart_attempts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xA8++0x01
|
|
line.word 0x00 "PCR4,Protocol Configuration Register 4"
|
|
hexmask.word.byte 0x00 9.--15. 1. "cas_rx_low_max,cas_rx_low_max"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "wakeup_symbol_rx_window,wakeup_symbol_rx_window"
|
|
group.word 0xAA++0x01
|
|
line.word 0x00 "PCR5,Protocol Configuration Register 5"
|
|
bitfld.word 0x00 12.--15. "tss_transmitter,tss_transmitter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 6.--11. "wakeup_symbol_tx_low,wakeup_symbol_tx_low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.word 0x00 0.--5. "wakeup_symbol_rx_idle,wakeup_symbol_rx_idle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0xAC++0x01
|
|
line.word 0x00 "PCR6,Protocol Configuration Register 6"
|
|
hexmask.word.byte 0x00 7.--14. 1. "symbol_window_after_action_point,symbol_window_after_action_point"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--6. 1. "macro_initial_offset_a,macro_initial_offset_a"
|
|
group.word 0xAE++0x01
|
|
line.word 0x00 "PCR7,Protocol Configuration Register 7"
|
|
hexmask.word 0x00 7.--15. 1. "decoding_correction_b,decoding_correction_b"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--6. 1. "micro_per_macro_nom_half,micro_per_macro_nom_half"
|
|
group.word 0xB0++0x01
|
|
line.word 0x00 "PCR8,Protocol Configuration Register 8"
|
|
bitfld.word 0x00 12.--15. "max_without_clock_correction_fatal,max_without_clock_correction_fatal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 8.--11. "max_without_clock_correction_passive,max_without_clock_correction_passive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--7. 1. "wakeup_symbol_tx_idle,wakeup_symbol_tx_idle"
|
|
group.word 0xB2++0x01
|
|
line.word 0x00 "PCR9,Protocol Configuration Register 9"
|
|
bitfld.word 0x00 15. "minislot_exists,minislot_exists" "0,1"
|
|
newline
|
|
bitfld.word 0x00 14. "symbol_window_exists,symbol_window_exists" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--13. 1. "offset_correction_out,offset_correction_out"
|
|
group.word 0xB4++0x01
|
|
line.word 0x00 "PCR10,Protocol Configuration Register 10"
|
|
bitfld.word 0x00 15. "single_slot_enabled,single_slot_enabled" "0,1"
|
|
newline
|
|
bitfld.word 0x00 14. "wakeup_channel,wakeup_channel" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--13. 1. "macro_per_cycle,macro_per_cycle"
|
|
group.word 0xB6++0x01
|
|
line.word 0x00 "PCR11,Protocol Configuration Register 11"
|
|
bitfld.word 0x00 15. "key_slot_used_for_startup,key_slot_used_for_startup" "0,1"
|
|
newline
|
|
bitfld.word 0x00 14. "key_slot_used_for_sync,key_slot_used_for_sync" "0,1"
|
|
newline
|
|
hexmask.word 0x00 0.--13. 1. "offset_correction_start,offset_correction_start"
|
|
group.word 0xB8++0x01
|
|
line.word 0x00 "PCR12,Protocol Configuration Register 12"
|
|
bitfld.word 0x00 11.--15. "allow_passive_to_active,allow_passive_to_active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word 0x00 0.--10. 1. "key_slot_header_crc,key_slot_header_crc"
|
|
group.word 0xBA++0x01
|
|
line.word 0x00 "PCR13,Protocol Configuration Register 13"
|
|
bitfld.word 0x00 10.--15. "first_minislot_action_point_offset,first_minislot_action_point_offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.word 0x00 0.--9. 1. "static_slot_after_action_point,static_slot_after_action_point"
|
|
group.word 0xBC++0x01
|
|
line.word 0x00 "PCR14,Protocol Configuration Register 14"
|
|
hexmask.word 0x00 5.--15. 1. "rate_correction_out,rate_correction_out"
|
|
newline
|
|
bitfld.word 0x00 0.--4. "listen_timeout,listen_timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xBE++0x01
|
|
line.word 0x00 "PCR15,Protocol Configuration Register 15"
|
|
hexmask.word 0x00 0.--15. 1. "listen_timeout,listen_timeout"
|
|
group.word 0xC0++0x01
|
|
line.word 0x00 "PCR16,Protocol Configuration Register 16"
|
|
hexmask.word.byte 0x00 9.--15. 1. "macro_initial_offset_b,macro_initial_offset_b"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "noise_listen_timeout,noise_listen_timeout"
|
|
group.word 0xC2++0x01
|
|
line.word 0x00 "PCR17,Protocol Configuration Register 17"
|
|
hexmask.word 0x00 0.--15. 1. "noise_listen_timeout,noise_listen_timeout"
|
|
group.word 0xC4++0x01
|
|
line.word 0x00 "PCR18,Protocol Configuration Register 18"
|
|
bitfld.word 0x00 10.--15. "wakeup_pattern,wakeup_pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.word 0x00 0.--9. 1. "key_slot_id,key_slot_id"
|
|
group.word 0xC6++0x01
|
|
line.word 0x00 "PCR19,Protocol Configuration Register 19"
|
|
hexmask.word 0x00 7.--15. 1. "decoding_correction_a,decoding_correction_a"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--6. 1. "payload_length_static,payload_length_static"
|
|
group.word 0xC8++0x01
|
|
line.word 0x00 "PCR20,Protocol Configuration Register 20"
|
|
hexmask.word.byte 0x00 8.--15. 1. "micro_initial_offset_b,micro_initial_offset_b"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--7. 1. "micro_initial_offset_a,micro_initial_offset_a"
|
|
group.word 0xCA++0x01
|
|
line.word 0x00 "PCR21,Protocol Configuration Register 21"
|
|
bitfld.word 0x00 13.--15. "extern_rate_correction,extern_rate_correction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--12. 1. "latest_tx,latest_tx"
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "PCR22,Protocol Configuration Register 22"
|
|
bitfld.word 0x00 15. "dypldchken,dypldchken" "0,1"
|
|
newline
|
|
hexmask.word 0x00 4.--14. 1. "comp_accepted_startup_range_a,comp_accepted_startup_range_a"
|
|
newline
|
|
bitfld.word 0x00 0.--3. "micro_per_cycle,micro_per_cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xCE++0x01
|
|
line.word 0x00 "PCR23,Protocol Configuration Register 23"
|
|
hexmask.word 0x00 0.--15. 1. "micro_per_cycle,micro_per_cycle"
|
|
group.word 0xD0++0x01
|
|
line.word 0x00 "PCR24,Protocol Configuration Register 24"
|
|
bitfld.word 0x00 11.--15. "cluster_drift_damping,cluster_drift_damping" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.word.byte 0x00 4.--10. 1. "max_payload_length_dynamic,max_payload_length_dynamic"
|
|
newline
|
|
bitfld.word 0x00 0.--3. "micro_per_cycle_min,micro_per_cycle_min" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD2++0x01
|
|
line.word 0x00 "PCR25,Protocol Configuration Register 25"
|
|
hexmask.word 0x00 0.--15. 1. "micro_per_cycle_min,micro_per_cycle_min"
|
|
group.word 0xD4++0x01
|
|
line.word 0x00 "PCR26,Protocol Configuration Register 26"
|
|
bitfld.word 0x00 15. "allow_halt_due_to_clock,allow_halt_due_to_clock" "0,1"
|
|
newline
|
|
hexmask.word 0x00 4.--14. 1. "comp_accepted_startup_range_b,comp_accepted_startup_range_b"
|
|
newline
|
|
bitfld.word 0x00 0.--3. "micro_per_cycle_max,micro_per_cycle_max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD6++0x01
|
|
line.word 0x00 "PCR27,Protocol Configuration Register 27"
|
|
hexmask.word 0x00 0.--15. 1. "micro_per_cycle_max,micro_per_cycle_max"
|
|
group.word 0xD8++0x01
|
|
line.word 0x00 "PCR28,Protocol Configuration Register 28"
|
|
bitfld.word 0x00 14.--15. "dynamic_slot_idle_phase,dynamic_slot_idle_phase" "0,1,2,3"
|
|
newline
|
|
hexmask.word 0x00 0.--13. 1. "macro_after_offset_correction,macro_after_offset_correction"
|
|
group.word 0xDA++0x01
|
|
line.word 0x00 "PCR29,Protocol Configuration Register 29"
|
|
bitfld.word 0x00 13.--15. "extern_offset_correction,extern_offset_correction" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--12. 1. "minislots_max,minislots_max"
|
|
group.word 0xDC++0x01
|
|
line.word 0x00 "PCR30,Protocol Configuration Register 30"
|
|
bitfld.word 0x00 0.--3. "sync_node_max,sync_node_max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE6++0x01
|
|
line.word 0x00 "RFSDOR,Receive FIFO Start Data Offset Register"
|
|
hexmask.word 0x00 0.--15. 1. "SDO,SDOA/SDOB - Start Data Field Offset"
|
|
group.word 0xE8++0x01
|
|
line.word 0x00 "RFSYMBADHR,Receive FIFO System Memory Base Address High Register"
|
|
hexmask.word 0x00 0.--15. 1. "SMBA,System Memory Base Address"
|
|
group.word 0xEA++0x01
|
|
line.word 0x00 "RFSYMBADLR,Receive FIFO System Memory Base Address Low Register"
|
|
hexmask.word 0x00 4.--15. 1. "SMBA,System Memory Base Address"
|
|
group.word 0xEC++0x01
|
|
line.word 0x00 "RFPTR,Receive FIFO Periodic Timer Register"
|
|
hexmask.word 0x00 0.--13. 1. "PTD,Periodic Timer Duration"
|
|
group.word 0xEE++0x01
|
|
line.word 0x00 "RFFLPCR,Receive FIFO Fill Level and POP Count Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. "FLB_or_PCB,FLB_or_PCB"
|
|
newline
|
|
hexmask.word.byte 0x00 0.--7. 1. "FLA_or_PCA,FLA_or_PCA"
|
|
group.word 0xF0++0x01
|
|
line.word 0x00 "EEIFER,ECC Error Interrupt Flag and Enable Register"
|
|
eventfld.word 0x00 15. "LRNE_OF,LRAM Non-Corrected Error Overflow Flag" "0: No such event,1: Non-corrected error overflow detected on CHI.."
|
|
newline
|
|
eventfld.word 0x00 14. "LRCE_OF,LRAM Corrected Error Overflow Flag" "0: No such event,1: Corrected error overflow detected on CHI LRAM"
|
|
newline
|
|
eventfld.word 0x00 13. "DRNE_OF,DRAM Non-Corrected Error Overflow Flag" "0: No such event,1: Non-corrected error overflow detected on PE.."
|
|
newline
|
|
eventfld.word 0x00 12. "DRCE_OF,DRAM Corrected Error Overflow Flag" "0: No such event,1: Corrected error overflow detected on PE DRAM"
|
|
newline
|
|
eventfld.word 0x00 11. "LRNE_IF,LRAM Non-Corrected Error Interrupt Flag" "0: No such event,1: Non-corrected Error detected on CHI LRAM"
|
|
newline
|
|
eventfld.word 0x00 10. "LRCE_IF,LRAM Corrected Error Interrupt Flag" "0: No such event,1: Corrected error detected on CHI LRAM"
|
|
newline
|
|
eventfld.word 0x00 9. "DRNE_IF,DRAM Non-Corrected Error Interrupt Flag" "0: No such event,1: Non-corrected error detected on PE DRAM"
|
|
newline
|
|
eventfld.word 0x00 8. "DRCE_IF,DRAM Corrected Error Interrupt Flag" "0: No such event,1: Corrected error detected on PE DRAM"
|
|
newline
|
|
bitfld.word 0x00 3. "LRNE_IE,LRAM Non-Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
newline
|
|
bitfld.word 0x00 2. "LRCE_IE,LRAM Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
newline
|
|
bitfld.word 0x00 1. "DRNE_IE,DRAM Non-Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
newline
|
|
bitfld.word 0x00 0. "DRCE_IE,DRAM Corrected Error Interrupt Enable" "0: Disable interrupt line,1: Enable interrupt line"
|
|
group.word 0xF2++0x01
|
|
line.word 0x00 "EERICR,ECC Error Report and Injection Control Register"
|
|
rbitfld.word 0x00 15. "BSY,Register Update Busy" "0: ECC configuration is idle,1: ECC configuration is running"
|
|
newline
|
|
bitfld.word 0x00 8.--9. "ERS,Error Report Select" "0: Show PE DRAM non-corrected error information,1: Show PE DRAM corrected error information,2: Show CHI LRAM non-corrected error information,3: Show CHI LRAM corrected error information"
|
|
newline
|
|
bitfld.word 0x00 4. "ERM,Error Report Mode" "0: Store data and code as delivered by ecc..,1: Store data and code as read from the memory"
|
|
newline
|
|
bitfld.word 0x00 1. "EIM,Error Injection Mode" "0: Use EEIDR[DATA] and EEICR[CODE] as XOR..,1: Use EEIDR[DATA] and EEICR[CODE] as write.."
|
|
newline
|
|
bitfld.word 0x00 0. "EIE,Error Injection Enable" "0: Error injection disabled,1: Error injection enabled"
|
|
rgroup.word 0xF4++0x01
|
|
line.word 0x00 "EERAR,ECC Error Report Address Register"
|
|
bitfld.word 0x00 15. "MID,Memory Identifier" "0: PE DRAM,1: CHI LRAM"
|
|
newline
|
|
bitfld.word 0x00 12.--14. "BANK,Memory Bank" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--11. 1. "ADDR,Memory Address"
|
|
rgroup.word 0xF6++0x01
|
|
line.word 0x00 "EERDR,ECC Error Report Data Register"
|
|
hexmask.word 0x00 0.--15. 1. "DATA,Data"
|
|
rgroup.word 0xF8++0x01
|
|
line.word 0x00 "EERCR,ECC Error Report Code Register"
|
|
bitfld.word 0x00 0.--4. "CODE,Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xFA++0x01
|
|
line.word 0x00 "EEIAR,ECC Error Injection Address Register"
|
|
bitfld.word 0x00 15. "MID,Memory Identifier" "0: PE DRAM,1: CHI LRAM"
|
|
newline
|
|
bitfld.word 0x00 12.--14. "BANK,Memory Bank" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.word 0x00 0.--11. 1. "ADDR,Memory Address"
|
|
group.word 0xFC++0x01
|
|
line.word 0x00 "EEIDR,ECC Error Injection Data Register"
|
|
hexmask.word 0x00 0.--15. 1. "DATA,Data"
|
|
group.word 0xFE++0x01
|
|
line.word 0x00 "EEICR,ECC Error Injection Code Register"
|
|
bitfld.word 0x00 0.--4. "CODE,Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 260. (increment 0 1) (increment 0 0x02)
|
|
group.word ($2+0x1000)++0x01
|
|
line.word 0x00 "MBDOR[$1],Message Buffer Data Field Offset Register $1"
|
|
hexmask.word 0x00 0.--15. 1. "MBDO,Message Buffer Data Field Offset"
|
|
repeat.end
|
|
repeat 6. (increment 0 1) (increment 0 0x02)
|
|
group.word ($2+0x1210)++0x01
|
|
line.word 0x00 "LEETR[$1],LRAM ECC Error Test Register $1"
|
|
hexmask.word 0x00 0.--15. 1. "LEETD,LRAM ECC Error Test Data"
|
|
repeat.end
|
|
repeat 256. (increment 0 1)(increment 0 0x08)
|
|
tree "MB[$1]"
|
|
group.word ($2+0x800)++0x01
|
|
line.word 0x00 "MBCCSR,Message Buffer Configuration Control Status Register"
|
|
bitfld.word 0x00 12. "MTD,Message Buffer Transfer Direction" "0: Receive message buffer,1: Transmit message buffer"
|
|
newline
|
|
bitfld.word 0x00 11. "CMT,Commit for Transmission" "0: Message buffer data not ready for transmission,1: Message buffer data ready for transmission"
|
|
newline
|
|
bitfld.word 0x00 10. "EDT,Enable/Disable Trigger" "0: No effect,1: Message buffer enable or disable is triggered"
|
|
newline
|
|
bitfld.word 0x00 9. "LCKT,Lock/Unlock Trigger" "0: No effect,1: Message buffer lock or unlock is triggered"
|
|
newline
|
|
bitfld.word 0x00 8. "MBIE,Message Buffer Interrupt Enable" "0: Interrupt request generation disabled,1: Interrupt request generation enabled"
|
|
newline
|
|
rbitfld.word 0x00 4. "DUP,Data Updated" "0: Frame Header and Message buffer data field..,1: Frame Header and Message buffer data field.."
|
|
newline
|
|
rbitfld.word 0x00 3. "DVAL,Data Valid" "0: Receive message buffer contains no valid..,1: Receive message buffer contains valid frame.."
|
|
newline
|
|
rbitfld.word 0x00 2. "EDS,Enable/Disable Status" "0: Message buffer is disabled,1: Message buffer is enabled"
|
|
newline
|
|
rbitfld.word 0x00 1. "LCKS,Lock Status" "0: Message buffer is not locked by the application,1: Message buffer is locked by the application"
|
|
newline
|
|
eventfld.word 0x00 0. "MBIF,Message Buffer Interrupt Flag" "0: No such event,1: Slot status field updated or transmit message.."
|
|
group.word ($2+0x802)++0x01
|
|
line.word 0x00 "MBCCFR,Message Buffer Cycle Counter Filter Register"
|
|
bitfld.word 0x00 15. "MTM,Message Buffer Transmission Mode" "0: Event transmission mode,1: State transmission mode"
|
|
newline
|
|
bitfld.word 0x00 14. "CHA,Channel Assignment" "0,1"
|
|
newline
|
|
bitfld.word 0x00 13. "CHB,Channel Assignment" "0,1"
|
|
newline
|
|
bitfld.word 0x00 12. "CCFE,Cycle Counter Filtering Enable" "0: Cycle counter filtering disabled,1: Cycle counter filtering enabled"
|
|
newline
|
|
bitfld.word 0x00 6.--11. "CCFMSK,Cycle Counter Filtering Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.word 0x00 0.--5. "CCFVAL,Cycle Counter Filtering Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word ($2+0x804)++0x01
|
|
line.word 0x00 "MBFIDR,Message Buffer Frame ID Register"
|
|
hexmask.word 0x00 0.--10. 1. "FID,Frame ID"
|
|
group.word ($2+0x806)++0x01
|
|
line.word 0x00 "MBIDXR,Message Buffer Index Register"
|
|
hexmask.word 0x00 0.--8. 1. "MBIDX,Message Buffer Index"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LLCE_TS"
|
|
base ad:0x43C18000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSCR0,TimeStamp Configuration Register#0"
|
|
hexmask.long.word 0x00 16.--24. 1. "NRSSLT,Number of Static Slot in One Communication Cycle"
|
|
bitfld.long 0x00 9. "FMB,FIFO B Slot Selection Mode" "0: Stores only second static and all dynamic..,1: Stores all static and all dynamic timestamp.."
|
|
newline
|
|
bitfld.long 0x00 8. "FMA,FIFO A Slot Selection Mode" "0: Stores only second static and all dynamic..,1: Stores all static and all dynamic timestamp.."
|
|
bitfld.long 0x00 4. "OPMODE,TimeStamp Capture Operation Mode" "0: Basic Mode Enabled,1: Advanced Mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "FLSC,Flush Cycle Start Time Stamp FIFO" "0: No Action on Cycle Start FIFO,1: Flush TimeStamp Values Stored in Cycle Start.."
|
|
bitfld.long 0x00 2. "FLSB,Flush Time Stamp FIFO B" "0: No Action on FIFO B,1: Flush TimeStamp Values Stored in FIFO B"
|
|
newline
|
|
bitfld.long 0x00 1. "FLSA,Flush Time Stamp FIFO A" "0: No Action on FIFO A,1: Flush TimeStamp Values Stored in FIFO A"
|
|
bitfld.long 0x00 0. "TSEN,Time Stamp Module Enable" "0: TimeStamp Module Disabled,1: TimeStamp Module Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TSCR1,TimeStamp Configuration Register#1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "WMB,Water Mark of TimeStamp FIFO B"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WMA,Water Mark of TimeStamp FIFO A"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TSSR,TimeStamp Status Register"
|
|
hexmask.long.word 0x00 20.--28. 1. "TSCNTB,Dynamic Count of Number of Captured TimeStamps in FIFO B"
|
|
hexmask.long.word 0x00 4.--12. 1. "TSCNTA,Dynamic Count of Number of Captured TimeStamps in FIFO A"
|
|
newline
|
|
bitfld.long 0x00 0. "TSENS,TimeStamp Module Enable Status" "0: TimeStamp Module Disabled,1: TimeStamp Module Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TSISR,TimeStamp Interrupt Status Register"
|
|
eventfld.long 0x00 29. "RERRB,TimeStamp FIFO B Read Error" "0: Interrupt Absent,1: Interrupt Present"
|
|
eventfld.long 0x00 28. "WERRB,TimeStamp FIFO B Write Error" "0: Interrupt Absent,1: Interrupt Present"
|
|
newline
|
|
eventfld.long 0x00 27. "FULB,TimeStamp FIFO B Full" "0: Interrupt Absent,1: Interrupt Present"
|
|
eventfld.long 0x00 26. "WMCB,TimeStamp FIFO B Water Mark Level Crossed" "0: Interrupt Absent,1: Interrupt Present"
|
|
newline
|
|
eventfld.long 0x00 25. "NEB,TimeStamp FIFO B Not Empty Event" "0: Interrupt Absent,1: Interrupt Present"
|
|
eventfld.long 0x00 24. "TCB,Time Slot Start Pulse of Channel B" "0: Interrupt Absent,1: Interrupt Present"
|
|
newline
|
|
eventfld.long 0x00 13. "RERRA,TimeStamp FIFO A Read Error" "0: Interrupt Absent,1: Interrupt Present"
|
|
eventfld.long 0x00 12. "WERRA,TimeStamp FIFO A Write Error" "0: Interrupt Absent,1: Interrupt Present"
|
|
newline
|
|
eventfld.long 0x00 11. "FULA,TimeStamp FIFO A Full" "0: Interrupt Absent,1: Interrupt Present"
|
|
eventfld.long 0x00 10. "WMCA,TimeStamp FIFO A Water Mark Level Crossed" "0: Interrupt Absent,1: Interrupt Present"
|
|
newline
|
|
eventfld.long 0x00 9. "NEA,TimeStamp FIFO A Not Empty Event" "0: Interrupt Absent,1: Interrupt Present"
|
|
eventfld.long 0x00 8. "TCA,Time Slot Start Pulse of Channel A" "0: Interrupt Absent,1: Interrupt Present"
|
|
newline
|
|
eventfld.long 0x00 3. "RERRC,Cycle Start Time stamp FIFO Read Error" "0: Interrupt Absent,1: Interrupt Present"
|
|
eventfld.long 0x00 2. "WERRC,Cycle Start Time stamp FIFO Write Error" "0: Interrupt Absent,1: Interrupt Present"
|
|
newline
|
|
eventfld.long 0x00 1. "ST2C,Static Slot Second TimeStamp Status" "0: Interrupt Absent,1: Interrupt Present"
|
|
eventfld.long 0x00 0. "CST,Cycle Start Event Status" "0: Interrupt Absent,1: Interrupt Present"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TSIER,TimeStamp Interrupt Enable Register"
|
|
bitfld.long 0x00 29. "RERRBIE,TimeStamp FIFO B Read Error" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 28. "WERRBIE,TimeStamp FIFO B Write Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. "FULBIE,TimeStamp FIFO B Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 26. "WMCBIE,TimeStamp FIFO B Water Mark Level Crossed Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "NEBIE,TimeStamp FIFO B Not Empty Event Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 24. "TCBIE,Time Slot Start Pulse of Channel B Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "RERRAIE,TimeStamp FIFO A Read Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "WERRAIE,TimeStamp FIFO A Write Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FULAIE,TimeStamp FIFO A Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "WMCAIE,TimeStamp FIFO A Water Mark Level Crossed Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "NEAIE,TimeStamp FIFO A Not Empty Event Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "TCAIE,Time Slot Start Pulse of Channel A Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "RERRCIE,Cycle Start Time stamp FIFO Read Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 2. "WERRCIE,Cycle Start Time stamp FIFO Write Error Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "ST2CIE,Static Slot Second TimeStamp Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 0. "CSTIE,Cycle Start Event Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TSGTBR,TimeStamp Global Time Base Register"
|
|
hexmask.long 0x00 0.--31. 1. "GTB,Global Time Base Dynamic Value"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "TSCSTFRR,TimeStamp Cycle Start Time FIFO Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "CSTS,Cycle Start Time Stamp Value"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TSFARR,TimeStamp FIFO A Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSFA,TimeStamp Value from FIFO A"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "TSFBRR,TimeStamp FIFO B Read Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSFB,TimeStamp Value from FIFO B"
|
|
tree.end
|
|
tree "LLCE_CRC"
|
|
base ad:0x43C19000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,CRC Data register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "HU,CRC High Upper Byte"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HL,CRC High Lower Byte"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "LU,CRC Low Upper Byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LL,CRC Low Lower Byte"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GPOLY,CRC Polynomial register"
|
|
hexmask.long.word 0x00 16.--31. 1. "HIGH,High Polynominal Half-word"
|
|
hexmask.long.word 0x00 0.--15. 1. "LOW,Low Polynominal Half-word"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,CRC Control register"
|
|
bitfld.long 0x00 30.--31. "TOT,Type Of Transpose For Writes" "0: No transposition,1: Bits in bytes are transposed bytes are not..,2: Both bits in bytes and bytes are transposed,3: Only bytes are transposed no bits in a byte.."
|
|
bitfld.long 0x00 28.--29. "TOTR,Type Of Transpose For Read" "0: No transposition,1: Bits in bytes are transposed bytes are not..,2: Both bits in bytes and bytes are transposed,3: Only bytes are transposed no bits in a byte.."
|
|
newline
|
|
bitfld.long 0x00 26. "FXOR,Complement Read Of CRC Data Register" "0: No XOR on reading,1: Invert or complement the read value of the.."
|
|
bitfld.long 0x00 25. "WAS,Write CRC Data Register As Seed" "0: Writes to the CRC data register are data values,1: Writes to the CRC data register are seed values"
|
|
newline
|
|
bitfld.long 0x00 24. "TCRC,TCRC" "0: 16-bit CRC protocol,1: 32-bit CRC protocol"
|
|
tree.end
|
|
tree "LLCE_STM"
|
|
base ad:0x43C1A000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CPS,Counter Prescaler"
|
|
bitfld.long 0x00 1. "FRZ,Freeze" "0: Timer runs in Debug mode,1: Timer stops in Debug mode"
|
|
newline
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: disabled,1: enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Count"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,Timer Count"
|
|
repeat 4. (increment 0 1)(increment 0 0x10)
|
|
tree "CHANNEL[$1]"
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "CCR,Channel Control"
|
|
bitfld.long 0x00 0. "CEN,Channel Enable" "0: disabled,1: enabled"
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "CIR,Channel Interrupt"
|
|
eventfld.long 0x00 0. "CIF,Channel Interrupt Flag" "0: Read: IRQ is not asserted,1: Read: IRQ is asserted"
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "CMP,Channel Compare"
|
|
hexmask.long 0x00 0.--31. 1. "CMP,Channel Compare"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LLCE_SEMA42"
|
|
base ad:0x43C20000
|
|
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x00)++0x00
|
|
line.byte 0x00 "GATE$1,Gate Register"
|
|
bitfld.byte 0x00 0.--3. "GTFSM,Gate finite state machine" "0: The gate is unlocked (free),1: Domain 0 locked the gate,2: Domain 1 locked the gate,3: Domain 2 locked the gate,4: Domain 3 locked the gate,5: Domain 4 locked the gate,6: Domain 5 locked the gate,7: Domain 6 locked the gate,8: Domain 7 locked the gate,9: Domain 8 locked the gate,10: Domain 9 locked the gate,11: Domain 10 locked the gate,12: Domain 11 locked the gate,13: Domain 12 locked the gate,14: Domain 13 locked the gate,15: Domain 14 locked the gate"
|
|
repeat.end
|
|
repeat 16. (strings "19" "18" "17" "16" "23" "22" "21" "20" "27" "26" "25" "24" "31" "30" "29" "28" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x10)++0x00
|
|
line.byte 0x00 "GATE$1,Gate Register"
|
|
bitfld.byte 0x00 0.--3. "GTFSM,Gate finite state machine" "0: The gate is unlocked (free),1: Domain 0 locked the gate,2: Domain 1 locked the gate,3: Domain 2 locked the gate,4: Domain 3 locked the gate,5: Domain 4 locked the gate,6: Domain 5 locked the gate,7: Domain 6 locked the gate,8: Domain 7 locked the gate,9: Domain 8 locked the gate,10: Domain 9 locked the gate,11: Domain 10 locked the gate,12: Domain 11 locked the gate,13: Domain 12 locked the gate,14: Domain 13 locked the gate,15: Domain 14 locked the gate"
|
|
repeat.end
|
|
repeat 16. (strings "35" "34" "33" "32" "39" "38" "37" "36" "43" "42" "41" "40" "47" "46" "45" "44" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x20)++0x00
|
|
line.byte 0x00 "GATE$1,Gate Register"
|
|
bitfld.byte 0x00 0.--3. "GTFSM,Gate finite state machine" "0: The gate is unlocked (free),1: Domain 0 locked the gate,2: Domain 1 locked the gate,3: Domain 2 locked the gate,4: Domain 3 locked the gate,5: Domain 4 locked the gate,6: Domain 5 locked the gate,7: Domain 6 locked the gate,8: Domain 7 locked the gate,9: Domain 8 locked the gate,10: Domain 9 locked the gate,11: Domain 10 locked the gate,12: Domain 11 locked the gate,13: Domain 12 locked the gate,14: Domain 13 locked the gate,15: Domain 14 locked the gate"
|
|
repeat.end
|
|
repeat 16. (strings "51" "50" "49" "48" "55" "54" "53" "52" "59" "58" "57" "56" "63" "62" "61" "60" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x30)++0x00
|
|
line.byte 0x00 "GATE$1,Gate Register"
|
|
bitfld.byte 0x00 0.--3. "GTFSM,Gate finite state machine" "0: The gate is unlocked (free),1: Domain 0 locked the gate,2: Domain 1 locked the gate,3: Domain 2 locked the gate,4: Domain 3 locked the gate,5: Domain 4 locked the gate,6: Domain 5 locked the gate,7: Domain 6 locked the gate,8: Domain 7 locked the gate,9: Domain 8 locked the gate,10: Domain 9 locked the gate,11: Domain 10 locked the gate,12: Domain 11 locked the gate,13: Domain 12 locked the gate,14: Domain 13 locked the gate,15: Domain 14 locked the gate"
|
|
repeat.end
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "RSTGT_R,Reset Gate"
|
|
bitfld.word 0x00 14.--15. "ROZ,ROZ" "0,1,2,3"
|
|
bitfld.word 0x00 12.--13. "RSTGSM,Reset gate finite state machine" "0: Idle waiting for the first data pattern,1: Waiting for the second data pattern,2: The 2-write sequence has completed,?..."
|
|
newline
|
|
bitfld.word 0x00 8.--11. "RSTGMS,Reset gate domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,Reset gate number"
|
|
wgroup.word 0x42++0x01
|
|
line.word 0x00 "RSTGT_W,Reset Gate"
|
|
hexmask.word.byte 0x00 8.--15. 1. "RSTGDP,Reset gate data pattern"
|
|
hexmask.word.byte 0x00 0.--7. 1. "RSTGTN,Reset gate number"
|
|
tree.end
|
|
tree "LLCE_SWT"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x43C21000 ad:0x43C22000 ad:0x43C23000 ad:0x43C24000)
|
|
tree "LLCE_SWT_$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control"
|
|
bitfld.long 0x00 31. "MAP0,Master Access Protection For Master 0" "0: Access disabled,1: Access enabled"
|
|
bitfld.long 0x00 30. "MAP1,Master Access Protection For Master 1" "0: Access disabled,1: Access enabled"
|
|
newline
|
|
bitfld.long 0x00 29. "MAP2,Master Access Protection For Master 2" "0: Access disabled,1: Access enabled"
|
|
bitfld.long 0x00 28. "MAP3,Master Access Protection For Master 3" "0: Access disabled,1: Access enabled"
|
|
newline
|
|
bitfld.long 0x00 27. "MAP4,Master Access Protection For Master 4" "0: Access disabled,1: Access enabled"
|
|
bitfld.long 0x00 26. "MAP5,Master Access Protection For Master 5" "0: Access disabled,1: Access enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "MAP6,Master Access Protection For Master 6" "0: Access disabled,1: Access enabled"
|
|
bitfld.long 0x00 24. "MAP7,Master Access Protection For Master 7" "0: Access disabled,1: Access enabled"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "SMD,Service Mode" "0: Fixed Service Sequence,1: Keyed Service Sequence,?..."
|
|
bitfld.long 0x00 8. "RIA,Reset on Invalid Access" "0: Generate a bus error,1: Generate a bus error and reset request"
|
|
newline
|
|
bitfld.long 0x00 7. "WND,Window Mode" "0: Regular mode,1: Window mode"
|
|
bitfld.long 0x00 6. "ITR,Interrupt Then Reset Request" "0: Generate a reset request on a timeout,1: Generate an interrupt on an initial timeout.."
|
|
newline
|
|
bitfld.long 0x00 5. "HLK,Hard Lock" "0: CR TO WN and SK are read/write registers if..,1: CR TO WN and SK are read-only registers"
|
|
bitfld.long 0x00 4. "SLK,Soft Lock" "0: CR TO WN and SK are read/write registers if..,1: CR TO WN and SK are read-only registers"
|
|
newline
|
|
bitfld.long 0x00 1. "FRZ,Debug Mode Control" "0: Timer continues,1: Timer stops"
|
|
bitfld.long 0x00 0. "WEN,Watchdog Enable" "0: disabled,1: enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IR,Interrupt"
|
|
eventfld.long 0x00 0. "TIF,Timeout Interrupt Flag" "0: No interrupt request,1: Interrupt request due to an initial timeout"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TO,Timeout"
|
|
hexmask.long 0x00 0.--31. 1. "WTO,Watchdog Timeout"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WN,Window"
|
|
hexmask.long 0x00 0.--31. 1. "WST,Window Start Value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR,Service"
|
|
hexmask.long.word 0x00 0.--15. 1. "WSC,Watchdog Service Code"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CO,Counter Output"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,Watchdog Count"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SK,Service Key"
|
|
hexmask.long.word 0x00 0.--15. 1. "SK,Service Key"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RRR,Reset Request"
|
|
eventfld.long 0x00 0. "RRF,Reset Request Flag" "0: No reset request,1: Any reset request initiated"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LLCE_CORE2CORE"
|
|
base ad:0x43C26000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "HINTC0R,HOST interrupt from Core 0 Register"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by Core 0 by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HINTC1R,HOST Interrupt from Core 1 Register"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by Core 1 by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "HINTC2R,HOST Interrupt from Core 2 Register"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by Core 2 by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "HINTC3R,HOST Interrupt from Core 3 Register"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by Core 3 by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C0INTHR,Core 0 Interrupt from HOST"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "C1INTHR,Core 1 Interrupt From HOST Register"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "C2INTHR,Core 2 Interrupt from HOST Register"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "C3INTHR,Core 3 Interrupt from HOST Register"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by HOST by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "C0INTCR,Core 0 Interrupt from Core 1/2/3"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by Core 1/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "C1INTCR,Core 1 Interrupt from Core 0/2/3"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by Core 0/2/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "C2INTCR,Core 2 Interrupt from Core 0/1/3 Register"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by Core 0/1/3 by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "C3INTCR,Core 3 Interrupt from Core 0/1/2Register"
|
|
bitfld.long 0x00 15. "FLG15,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG15_1"
|
|
bitfld.long 0x00 14. "FLG14,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG14_1"
|
|
newline
|
|
bitfld.long 0x00 13. "FLG13,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG13_1"
|
|
bitfld.long 0x00 12. "FLG12,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG12_1"
|
|
newline
|
|
bitfld.long 0x00 11. "FLG11,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG11_1"
|
|
bitfld.long 0x00 10. "FLG10,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG10_1"
|
|
newline
|
|
bitfld.long 0x00 9. "FLG9,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG9_1"
|
|
bitfld.long 0x00 8. "FLG8,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG8_1"
|
|
newline
|
|
bitfld.long 0x00 7. "FLG7,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG7_1"
|
|
bitfld.long 0x00 6. "FLG6,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG6_1"
|
|
newline
|
|
bitfld.long 0x00 5. "FLG5,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG5_1"
|
|
bitfld.long 0x00 4. "FLG4,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG4_1"
|
|
newline
|
|
bitfld.long 0x00 3. "FLG3,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG3_1"
|
|
bitfld.long 0x00 2. "FLG2,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG2_1"
|
|
newline
|
|
bitfld.long 0x00 1. "FLG1,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG1_1"
|
|
bitfld.long 0x00 0. "FLG0,This flag is set by Core 0/1/2 by writing 1 into it to indicate an event" "0: No Event,1: FLG0_1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "HINTC0ER,HOST Interrupt from Core 0 Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "HINTC1ER,HOST Interrupt from Core 1 Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "HINTC2ER,HOST Interrupt from Core 2 Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "HINTC3ER,HOST Interrupt from Core 3 Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "C0INTHER,Core 0 Interrupt from Host Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "C1INTHER,Core 1 Interrupt from HOST Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14npropagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "C2INTHER,Core 2 Interrupt from HOST Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "C3INTHER,Core 3 Interrupt from HOST Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "C0INTCER,Core 0 Interrupt from Cores 1/2/3 Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "C1INTCER,Core 1 Interrupt from COres 0/2/3 Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "C2INTCER,Core 2 Interrupt from Cores /0/1/3 Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "C3INTCER,Core 3 Interrupt from Cores /0/1/2 Enable Register"
|
|
bitfld.long 0x00 15. "IEN15,This bit enables/disables FLG15 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 14. "IEN14,This bit enables/disables FLG14 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "IEN13,This bit enables/disables FLG13 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 12. "IEN12,This bit enables/disables FLG12 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "IEN11,This bit enables/disables FLG11 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 10. "IEN10,This bit enables/disables FLG10 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "IEN9,This bit enables/disables FLG9 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 8. "IEN8,This bit enables/disables FLG8 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "IEN7,This bit enables/disables FLG7 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 6. "IEN6,This bit enables/disables FLG6 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "IEN5,This bit enables/disables FLG5 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 4. "IEN4,This bit enables/disables FLG4 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "IEN3,This bit enables/disables FLG3 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 2. "IEN2,This bit enables/disables FLG2 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "IEN1,This bit enables/disables FLG1 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
bitfld.long 0x00 0. "IEN0,This bit enables/disables FLG0 propagation to the interrupt line" "0: Flag disabled,1: Flag enabled"
|
|
tree.end
|
|
tree "LLCE_SYSCTRL"
|
|
base ad:0x43FF8000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LLCE_SYSRSTR,System reset control register"
|
|
bitfld.long 0x00 3. "CPU_RST3,CPU Reset 3" "0: CPU under reset (Default),1: CPU out of reset"
|
|
bitfld.long 0x00 2. "CPU_RST2,CPU Reset 2" "0: CPU under reset (Default),1: CPU out of reset"
|
|
newline
|
|
bitfld.long 0x00 1. "CPU_RST1,CPU Reset 1" "0: CPU under reset (Default),1: CPU out of reset"
|
|
bitfld.long 0x00 0. "CPU_RST0,CPU Reset 0" "0: CPU under reset (Default),1: CPU out of reset"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LLCE_MASIDR,LLCE master ID register"
|
|
bitfld.long 0x00 0.--4. "MASIDHST,Master ID of Host" "?,?,?,?,?,?,?,?,8: MASIDHST_8,?..."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LLCE_RAMCCSR,RAM Controller Configuration and Status Register"
|
|
rbitfld.long 0x00 21. "RCRWSS5,RAM read path data retiming status for RAM Controller attached with CAN TX Data RAM" "0,1"
|
|
rbitfld.long 0x00 20. "RCRWSS4,RAM read path data retiming status for RAM Controller attached with CAN RX Data RAM" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 19. "RCRWSS3,RAM read path data retiming status for RAM Controller attached with FRPE" "0,1"
|
|
rbitfld.long 0x00 18. "RCRWSS2,RAM read path data retiming status for RAM Controller attached with TXPPE" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 17. "RCRWSS1,RAM read path data retiming status for RAM Controller attached with RXPPE" "0,1"
|
|
rbitfld.long 0x00 16. "RCRWSS0,RAM read path data retiming status for RAM Controller attached with DTE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "RCRWSC5,Configure RAM read path data retiming for RAM Controller attached with CAN TX" "0: Retiming disabled,1: Retiming enabled"
|
|
bitfld.long 0x00 4. "RCRWSC4,Configure RAM read path data retiming for RAM Controller attached with CAN RX" "0: Retiming disabled,1: Retiming enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "RCRWSC3,Configure RAM read path data retiming for RAM Controller attached with FRPE" "0: Retiming disabled,1: Retiming enabled"
|
|
bitfld.long 0x00 2. "RCRWSC2,Configure RAM read path data retiming for RAM Controller attached with TXPPE" "0: Retiming disabled,1: Retiming enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RCRWSC1,Configure RAM read path data retiming for RAM Controller attached with RXPPE" "0: Retiming disabled,1: Retiming enabled"
|
|
bitfld.long 0x00 0. "RCRWSC0,Configure RAM read path data retiming for RAM Controller attached with DTE" "0: Retiming disabled,1: Retiming enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LLCE_CHLTMSKR,Core Halt Mask Register"
|
|
bitfld.long 0x00 23. "MC3HSPI,Mask core 3 halt to LPSPI modules" "0: Enable core 3 halt to LPSPI modules (default),1: Mask/disable core 3 halt to LPSPI modules"
|
|
bitfld.long 0x00 22. "MC2HSPI,Mask core 2 halt to LPSPI modules" "0: Enable core 2 halt to LPSPI modules (default),1: Mask/disable core 2 halt to LPSPI modules"
|
|
newline
|
|
bitfld.long 0x00 21. "MC1HSPI,Mask core 1 halt to LPSPI modules" "0: Enable core 1 halt to LPSPI modules (default),1: Mask/disable core 1 halt to LPSPI modules"
|
|
bitfld.long 0x00 20. "MC0HSPI,Mask core 0 halt to LPSPI modules" "0: Enable core 0 halt to LPSPI modules (default),1: Mask/disable core 0 halt to LPSPI modules"
|
|
newline
|
|
bitfld.long 0x00 19. "MC3HSTM,Mask core 3 halt to STM" "0: Enable core 3 halt to STM (default),1: Mask/disable core 3 halt to STM"
|
|
bitfld.long 0x00 18. "MC2HSTM,Mask core 2 halt to STM" "0: Enable core 2 halt to STM (default),1: Mask/disable core 2 halt to STM"
|
|
newline
|
|
bitfld.long 0x00 17. "MC1HSTM,Mask core 1 halt to STM" "0: Enable core 1 halt to STM (default),1: Mask/disable core 1 halt to STM"
|
|
bitfld.long 0x00 16. "MC0HSTM,Mask core 0 halt to STM" "0: Enable core 0 halt to STM (default),1: Mask/disable core 0 halt to STM"
|
|
newline
|
|
rbitfld.long 0x00 15. "MC3HSW3,Mask core 3 halt to SWT 3" "0: Enable core 3 halt to SWT 3 (default),1: Mask/disable core 3 halt to SWT 3"
|
|
rbitfld.long 0x00 14. "MC2HSW3,Mask core 2 halt to SWT 3" "0: Enable core 2 halt to SWT 3,1: Mask/disable core 2 halt to SWT 3 (default)"
|
|
newline
|
|
rbitfld.long 0x00 13. "MC1HSW3,Mask core 1 halt to SWT 3" "0: Enable core 1 halt to SWT 3,1: Mask/disable core 1 halt to SWT 3 (default)"
|
|
rbitfld.long 0x00 12. "MC0HSW3,Mask core 0 halt to SWT 3" "0: Enable core 0 halt to SWT 3,1: Mask/disable core 0 halt to SWT 3 (default)"
|
|
newline
|
|
rbitfld.long 0x00 11. "MC3HSW2,Mask core 3 halt to SWT 2" "0: Enable core 3 halt to SWT 2,1: Mask/disable core 3 halt to SWT 2 (default)"
|
|
rbitfld.long 0x00 10. "MC2HSW2,Mask core 2 halt to SWT 2" "0: Enable core 2 halt to SWT 2 (default),1: Mask/disable core 2 halt to SWT 2"
|
|
newline
|
|
rbitfld.long 0x00 9. "MC1HSW2,Mask core 1 halt to SWT 2" "0: Enable core 1 halt to SWT 2,1: Mask/disable core 1 halt to SWT 2 (default)"
|
|
rbitfld.long 0x00 8. "MC0HSW2,Mask core 0 halt to SWT 2" "0: Enable core 0 halt to SWT 2,1: Mask/disable core 0 halt to SWT 2 (default)"
|
|
newline
|
|
rbitfld.long 0x00 7. "MC3HSW1,Mask core 3 halt to SWT 1" "0: Enable core 3 halt to SWT 1,1: Mask/disable core 3 halt to SWT 1 (default)"
|
|
rbitfld.long 0x00 6. "MC2HSW1,Mask core 2 halt to SWT 1" "0: Enable core 2 halt to SWT 1,1: Mask/disable core 2 halt to SWT 1 (default)"
|
|
newline
|
|
rbitfld.long 0x00 5. "MC1HSW1,Mask core 1 halt to SWT 1" "0: Enable core 1 halt to SWT 1 (default),1: Mask/disable core 1 halt to SWT 1"
|
|
rbitfld.long 0x00 4. "MC0HSW1,Mask core 0 halt to SWT 1" "0: Enable core 0 halt to SWT 1,1: Mask/disable core 0 halt to SWT 1 (default)"
|
|
newline
|
|
rbitfld.long 0x00 3. "MC3HSW0,Mask core 3 halt to SWT 0" "0: Enable core 3 halt to SWT 0,1: Mask/disable core 3 halt to SWT 0 (default)"
|
|
rbitfld.long 0x00 2. "MC2HSW0,Mask core 2 halt to SWT 0" "0: Enable core 2 halt to SWT 0,1: Mask/disable core 2 halt to SWT 0 (default)"
|
|
newline
|
|
rbitfld.long 0x00 1. "MC1HSW0,Mask core 1 halt to SWT 0" "0: Enable core 1 halt to SWT 0,1: Mask/disable core 1 halt to SWT 0 (default)"
|
|
rbitfld.long 0x00 0. "MC0HSW0,Mask core 0 halt to SWT 0" "0: Enable core 0 halt to SWT 0 (default),1: Mask/disable core 0 halt to SWT 0"
|
|
tree.end
|
|
tree "LLCE_AXBS"
|
|
base ad:0x43FFC000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PRS0,Priority Slave Registers"
|
|
bitfld.long 0x00 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRS0,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PRS1,Priority Slave Registers"
|
|
bitfld.long 0x00 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CRS1,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PRS2,Priority Slave Registers"
|
|
bitfld.long 0x00 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "CRS2,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PRS4,Priority Slave Registers"
|
|
bitfld.long 0x00 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "CRS4,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "PRS5,Priority Slave Registers"
|
|
bitfld.long 0x00 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "CRS5,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "PRS6,Priority Slave Registers"
|
|
bitfld.long 0x00 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "CRS6,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "PRS7,Priority Slave Registers"
|
|
bitfld.long 0x00 28.--30. "M7,Master 7 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 24.--26. "M6,Master 6 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 20.--22. "M5,Master 5 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 16.--18. "M4,Master 4 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 12.--14. "M3,Master 3 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 8.--10. "M2,Master 2 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "M1,Master 1 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
bitfld.long 0x00 0.--2. "M0,Master 0 Priority" "0: This master has level 1 or highest priority..,1: This master has level 2 priority when..,2: This master has level 3 priority when..,3: This master has level 4 priority when..,4: This master has level 5 priority when..,5: This master has level 6 priority when..,6: This master has level 7 priority when..,7: This master has level 8 or lowest priority.."
|
|
group.long 0x710++0x03
|
|
line.long 0x00 "CRS7,Control Register"
|
|
bitfld.long 0x00 31. "RO,Read Only" "0: The slave port's registers are writeable,1: The slave port's registers are read-only and.."
|
|
bitfld.long 0x00 8.--9. "ARB,Arbitration Mode" "0: Fixed priority,1: Round-robin(RR) or rotating priority,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. "PCTL,Parking Control" "0: When no master makes a request the arbiter..,1: When no master makes a request the arbiter..,2: When no master makes a request the slave port..,?..."
|
|
bitfld.long 0x00 0.--2. "PARK,Park" "0: Park on master port M0,1: Park on master port M1,2: Park on master port M2,3: Park on master port M3,4: Park on master port M4,5: Park on master port M5,6: Park on master port M6,7: Park on master port M7"
|
|
tree.end
|
|
autoindent.off
|
|
newline
|