16809 lines
1.6 MiB
16809 lines
1.6 MiB
; --------------------------------------------------------------------------------
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; @Title: NUC400 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2022-03-03 NEJ
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: SVD generated, based on: NUC400_v1.svd (Ver. 1.0)
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; @Core: Cortex-M4F
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; @Chip: NUC442JG8AE, NUC442JI8AE, NUC442KG8AE, NUC442KI8AE, NUC442VG8AE,
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; NUC442VI8AE, NUC442RG8AE, NUC442RI8AE, NUC472HG8AE, NUC472HI8AE,
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; NUC472JG8AE, NUC472JI8AE, NUC472KG8AE, NUC472KI8AE, NUC472VG8AE,
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; NUC472VI8AE
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pernuc400.per 14445 2022-03-04 09:32:41Z kwisniewski $
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "ACMP"
|
|
base ad:0x40045000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ACMP_CTL0,Analog Comparator 0 Control Register"
|
|
bitfld.long 0x00 5.--7. "POSSEL,Comparator 0 Positive Input Selection\nThe other options are reserved" "0: Input from ACMP0_P0,1: Input from ACMP0_P1,2: Input from ACMP0_P2,3: Input from ACMP0_P3,4: Input from OPA0,?..."
|
|
bitfld.long 0x00 4. "NEGSEL,Comparator 0 Negative Input Selection\n" "0: The source of comparator 0 negative input is..,1: The internal comparator reference voltage.."
|
|
newline
|
|
bitfld.long 0x00 3. "ACMPOINV,Comparator 0 Output Inverse\n" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled"
|
|
bitfld.long 0x00 2. "HYSEN,Comparator 0 Hysteresis Enable Bit\n" "0: Comparator 0 hysteresis Disabled (Default),1: Comparator 0 hysteresis Enabled (typical.."
|
|
newline
|
|
bitfld.long 0x00 1. "ACMPIE,Comparator 0 Interrupt Enable Bit\n" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled"
|
|
bitfld.long 0x00 0. "ACMPEN,Comparator 0 Enable Bit\nNote: The comparator output needs to wait 2 us stable time after ACMPEN is set" "0: Comparator 0 Disabled,1: Comparator 0 Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ACMP_CTL1,Analog Comparator 1 Control Register"
|
|
bitfld.long 0x00 5.--7. "POSSEL,Comparator 1 Positive Input Selection\nThe other options are reserved" "0: Input from ACMP1_P0,1: Input from ACMP1_P1,2: Input from ACMP1_P2,3: Input from ACMP1_P3,4: Input from OPA1,?..."
|
|
bitfld.long 0x00 4. "NEGSEL,Comparator 1 Negative Input Selection\n" "0: The source of comparator 1 negative input is..,1: The internal comparator reference voltage.."
|
|
newline
|
|
bitfld.long 0x00 3. "ACMPOINV,Comparator 1 Output Inverse Control\n" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled"
|
|
bitfld.long 0x00 2. "HYSEN,Comparator 1 Hysteresis Enable Bit\n" "0: Comparator 1 hysteresis Disabled (Default),1: Comparator 1 hysteresis Enabled (typical.."
|
|
newline
|
|
bitfld.long 0x00 1. "ACMPIE,Comparator 1 Interrupt Enable Bit\n" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled"
|
|
bitfld.long 0x00 0. "ACMPEN,Comparator 1 Enable Bit\nThe comparator output needs to wait 2 us stable time after ACMPEN is set" "0: Comparator 1 Disabled,1: Comparator 1 Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACMP_CTL2,Analog Comparator 2 Control Register"
|
|
bitfld.long 0x00 5.--7. "POSSEL,Comparator 2 Positive Input Selection\nThe other options are reserved" "0: Input from ACMP2_P0,1: Input from ACMP2_P1,2: Input from ACMP2_P2,3: Input from ACMP2_P3,?..."
|
|
bitfld.long 0x00 4. "NEGSEL,Comparator 2 Negative Input Selection\n" "0: The source of comparator 2 negative input is..,1: The internal comparator reference voltage.."
|
|
newline
|
|
bitfld.long 0x00 3. "ACMPOINV,Comparator 2 Output Inverse Control\n" "0: Comparator 2 output inverse Disabled,1: Comparator 2 output inverse Enabled"
|
|
bitfld.long 0x00 2. "HYSEN,Comparator 2 Hysteresis Enable Bit\n" "0: Comparator 2 hysteresis Disabled (Default),1: Comparator 2 hysteresis Enabled (typical.."
|
|
newline
|
|
bitfld.long 0x00 1. "ACMPIE,Comparator 2 Interrupt Enable Bit\n" "0: Comparator 2 interrupt Disabled,1: Comparator 2 interrupt Enabled"
|
|
bitfld.long 0x00 0. "ACMPEN,Comparator 2 Enable Bit\nThe comparator output needs to wait 2 us stable time after ACMPEN is set" "0: Comparator 2 Disabled,1: Comparator 2 Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ACMP_STATUS,Analog Comparator Status Register"
|
|
bitfld.long 0x00 5. "ACMPO2,Comparator 2 Output\n" "0,1"
|
|
bitfld.long 0x00 4. "ACMPO1,Comparator 1 Output\n" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "ACMPO0,Comparator 0 Output\n" "0,1"
|
|
bitfld.long 0x00 2. "ACMPIF2,Comparator 2 Flag\nThis bit is set by hardware whenever the comparator 2 output changes state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "ACMPIF1,Comparator 1 Flag\nThis bit is set by hardware whenever the comparator 1 output changes state" "0,1"
|
|
bitfld.long 0x00 0. "ACMPIF0,Comparator 0 Flag\nThis bit is set by hardware whenever the comparator 0 output changes state" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
|
|
bitfld.long 0x00 7. "IREFSEL,Internal Reference Selection\n" "0: Band-gap voltage is selected as internal..,1: CRV is selected as internal reference"
|
|
bitfld.long 0x00 6. "CRVSSEL,CRV Source Voltage Selection\n" "0: AVDD is selected as CRV source voltage,1: Internal reference voltage is selected as CRV.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "CRVCTL,Comparator Reference Voltage Setting\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "ADC"
|
|
base ad:0x40043000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC_DAT0,ADC Data Register 0"
|
|
bitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is" "0: Data in RESULT (ADC_DATx[15:0]) bits is not..,1: Data in RESULT (ADC_DATx[15:0]) bits is valid"
|
|
bitfld.long 0x00 16. "OV,Overrun Flag (Read Only)\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone" "0: Data in RESULT (ADC_DATx[15:0]) is recent..,1: Data in RESULT (ADC_DATx[15:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF (ADC_CTL[31]) bit is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
repeat 11. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 )
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "ADC_DAT$1,ADC Data Register $1"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is" "0: Data in RESULT (ADC_DATx[15:0]) bits is not..,1: Data in RESULT (ADC_DATx[15:0]) bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag (Read Only)\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone" "0: Data in RESULT (ADC_DATx[15:0]) is recent..,1: Data in RESULT (ADC_DATx[15:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF (ADC_CTL[31]) bit is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
repeat.end
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ADC_DAT12,ADC Data Register 12 (for Band-gap Voltage)"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is" "0: Data in RESULT (ADC_DATx[15:0]) bits is not..,1: Data in RESULT (ADC_DATx[15:0]) bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag (Read Only)\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone" "0: Data in RESULT (ADC_DATx[15:0]) is recent..,1: Data in RESULT (ADC_DATx[15:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF (ADC_CTL[31]) bit is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ADC_DAT13,ADC Data Register 13 (for Temperature Sensor)"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is" "0: Data in RESULT (ADC_DATx[15:0]) bits is not..,1: Data in RESULT (ADC_DATx[15:0]) bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag (Read Only)\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1 and previous conversion result is gone" "0: Data in RESULT (ADC_DATx[15:0]) is recent..,1: Data in RESULT (ADC_DATx[15:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF (ADC_CTL[31]) bit is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ADC_CTL,ADC Control Register"
|
|
bitfld.long 0x00 31. "DMOF,ADC Differential Input Mode Output Format\n" "0: A/D conversion result will be filled in..,1: A/D conversion result will be filled in.."
|
|
hexmask.long.byte 0x00 16.--23. 1. "PWMTRGDLY,PWM Trigger Delay Time\nSetting this field will delay ADC start conversion time after PWM trigger comes.\nPWM trigger delay time is 4 * system clock * PWMTRGDLY (ADC_CTL[23:16])"
|
|
newline
|
|
bitfld.long 0x00 11. "SWTRG,A/D Conversion Start\nThe SWTRG (ADC_CTL[11]) bit can be set to 1 from two sources: software and hardware trigger" "0: Conversion stopped and A/D converter enter..,1: Conversion start"
|
|
bitfld.long 0x00 10. "DIFFEN,Differential Input Mode Enable Bit\nIn differential input mode only the even number of the two corresponding channels needs to be enabled in ADCHER (ADC_CHEN[11:0])" "0: Single-end analog input mode,1: Differential analog input mode"
|
|
newline
|
|
bitfld.long 0x00 9. "PDMAEN,PDMA Transfer Enable Bit\nWhen A/D conversion is completed the converted data is loaded into ADC_DATx software can enable this bit to generate a PDMA data transfer request.\nWhen PDMAEN (ADC_CTL[9]) is set to 1 software must set ADCIEN.." "0: PDMA data transfer Disabled,1: PDMA data transfer in ADC_DATx Enabled"
|
|
bitfld.long 0x00 8. "HWTRGEN,External Hardware Trigger Enable Bit\nEnable or disable hardware triggering of A/D conversion" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "HWTRGCOND,External Pin Trigger Conditions\nThese two bits decide external pin (STADC) trigger event" "0: Low level,1: High level,2: Falling edge,3: Rising edge"
|
|
bitfld.long 0x00 4.--5. "HWTRGSEL,External Hardware Trigger Source\nSoftware should disable HWTRGCOND (ADC_CTL[8]) and SWTRG (ADC_CTL[11]) before changing HWTRGSEL (ADC_CTL[5:4]).\nIn hardware trigger mode the SWTRG (ADC_CTL[11]) bit is set by hardware trigger source" "0: A/D conversion is started by external pin..,1: Reserved,2: Reserved,3: PWM0 or PWM1 trigger condition is matched"
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newline
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bitfld.long 0x00 2.--3. "OPMODE,ADC Operation Mode\nWhen changing the operation mode software should disable SWTRG (ADC_CTL[11]) bit firstly" "0: Single conversion,1: Reserved,2: Single-cycle scan,3: Continuous scan"
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bitfld.long 0x00 1. "ADCIEN,ADC Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADCIEN (ADC_CTL[1]) bit is set to 1" "0: ADC interrupt function Disabled,1: ADC interrupt function Enabled"
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|
newline
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bitfld.long 0x00 0. "ADCEN,ADC Enable Bit\nBefore disabling ADC clock this bit should be cleared to 0 by software" "0: ADC analog circuit Disabled,1: ADC analog circuit Enabled"
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|
group.long 0x44++0x03
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|
line.long 0x00 "ADC_CHEN,ADC Channel Enable Control Register"
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|
bitfld.long 0x00 17. "ADTSEN,Internal Temperature Sensor Selection\nADC can only work at Single mode when software selects the temperature sensor voltage as the analog input source of ADC" "0: Internal temperature sensor is not selected..,1: Internal temperature sensor is selected to be.."
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bitfld.long 0x00 16. "ADBGEN,Internal Band-Gap Selection\nADC can only work at Single mode when software selects the band-gap voltage as the analog input source of ADC" "0: Internal band-gap is not selected to be the..,1: Internal band-gap is selected to be the.."
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newline
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hexmask.long.word 0x00 0.--11. 1. "CHEN,Analog Input Channel Enable Bit\nSet CHEN (ADC_CHEN[11:0]) to enable the corresponding analog input channel (ADC0_CH1 ~ ADC0_CH11)"
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repeat 2. (strings "0" "1" )(list 0x0 0x4 )
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|
group.long ($2+0x48)++0x03
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|
line.long 0x00 "ADC_CMP$1,ADC Compare Register $1"
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hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Compared Data\nWhen DMOF (ADC_CTL[31]) bit is set to 0 ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with unsigned format"
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bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count\nWhen the specified ADC channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]) the internal match counter will increase 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 3.--6. "CMPCH,Compare Channel Selection\n" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,2: Channel 2 conversion result is selected to be..,3: Channel 3 conversion result is selected to be..,4: Channel 4 conversion result is selected to be..,5: Channel 5 conversion result is selected to be..,6: Channel 6 conversion result is selected to be..,7: Channel 7 conversion result is selected to be..,8: Channel 8 conversion result is selected to be..,9: Channel 9 conversion result is selected to be..,10: Channel 10 conversion result is selected to..,11: Channel 11 conversion result is selected to..,12: band-gap voltage result is selected to be..,13: temperature sensor conversion result is..,?..."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1 the ADCMPFx (ADC_STATUS0[2:1]) bit will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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newline
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bitfld.long 0x00 1. "ADCMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT(ADC_CMPx[11:8]) ADCMPFx (ADC_STATUS0[2:1]) bit will be asserted in the meanwhile if ADCMPIE.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x00 0. "ADCMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPDAT (ADC_CMPx[27:16]) with the conversion result of the channel specified by CMPCH (ADC_CMPx[6:3]) when the conversion data of the specified channel is loaded into.." "0: Compare function Disabled,1: Compare function Enabled"
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repeat.end
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group.long 0x50++0x03
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line.long 0x00 "ADC_STATUS0,ADC Status Register 0"
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rbitfld.long 0x00 4.--7. "CHANNEL,Current Conversion Channel (Read Only)\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 3. "BUSY,BUSY/IDLE (Read Only)\nThis bit is mirror of as SWTRG (ADC_CTL[11]) bit" "0: ADC is in idle state,1: ADC is doing conversion"
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newline
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bitfld.long 0x00 2. "ADCMPF1,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1" "0: Conversion result in ADC_DATx does not meet..,1: Conversion result in ADC_DATx meets ADCMPR1.."
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bitfld.long 0x00 1. "ADCMPF0,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1" "0: Conversion result in ADC_DATx does not meet..,1: Conversion result in ADC_DATx meets ADCMPR0.."
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newline
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bitfld.long 0x00 0. "ADIF,ADC Interrupt Flag\nA status flag that indicates the end of A/D conversion.\nADIF (ADC_STATUS0[0]) is set to 1 at these two conditions:\n1" "0,1"
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rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADC_STATUS1,ADC Status Register 1"
|
|
hexmask.long.word 0x00 16.--29. 1. "OV,Overrun Flag (Read Only)\nIt is a mirror to OV (ADC_DATx[16]) bit"
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|
hexmask.long.word 0x00 0.--13. 1. "VALID,Data Valid Flag (Read Only)\nIt is a mirror of VALID (ADC_DATx[17]) bit"
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|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "ADC_CURDAT,ADC PDMA Current Transfer Data Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "CURDAT,ADC PDMA Current Transfer Data Bit (Read Only)\nWhen PDMA transferring read this register can monitor current PDMA transfer data"
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|
tree.end
|
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tree "CAN"
|
|
repeat 2. (list 0. 1.) (list ad:0x400A0000 ad:0x400A1000)
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|
tree "CAN$1"
|
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base $2
|
|
group.long 0x00++0x03
|
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line.long 0x00 "CAN_CON,Control Register"
|
|
bitfld.long 0x00 7. "Test,Test Mode Enable Bit\n" "0: Normal Operation,1: Test Mode"
|
|
bitfld.long 0x00 6. "CCE,Configuration Change Enable Bit\n" "0: No write access to the Bit Timing Register,1: Write access to the Bit Timing Register.."
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|
newline
|
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bitfld.long 0x00 5. "DAR,Automatic Re-Transmission Disable Bit\n" "0: Automatic Retransmission of disturbed..,1: Automatic Retransmission disabled"
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|
bitfld.long 0x00 3. "EIE,Error Interrupt Enable Bit\n" "0: Disabled - No Error Status Interrupt will be..,1: Enabled - A change in the bits BOff.."
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|
newline
|
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bitfld.long 0x00 2. "SIE,Status Change Interrupt Enable Bit\n" "0: Disabled - No Status Change Interrupt will be..,1: Enabled - An interrupt will be generated when.."
|
|
bitfld.long 0x00 1. "IE,Module Interrupt Enable Bit\n" "0: Disabled,1: Enabled"
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|
newline
|
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bitfld.long 0x00 0. "Init,Init Initialization\n" "0: Normal Operation,1: Initialization is started"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CAN_STATUS,Status Register"
|
|
rbitfld.long 0x00 7. "BOff,Bus-Off Status (Read Only) \n" "0: The CAN module is not in bus-off state,1: The CAN module is in bus-off state"
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rbitfld.long 0x00 6. "EWarn,Error Warning Status (Read Only)\n" "0: Both error counters are below the error..,1: At least one of the error counters in the EML.."
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newline
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rbitfld.long 0x00 5. "EPass,Error Passive (Read Only)\n" "0: The CAN Core is error active,1: The CAN Core is in the error passive state as.."
|
|
bitfld.long 0x00 4. "RxOK,Received A Message Successfully\n" "0: No message has been successfully received..,1: A message has been successfully received.."
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|
newline
|
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bitfld.long 0x00 3. "TxOK,Transmitted A Message Successfully\n" "0: Since this bit was reset by the CPU no..,1: Since this bit was last reset by the CPU a.."
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bitfld.long 0x00 0.--2. "LEC,Last Error Code (Type Of The Last Error To Occur On The CAN Bus)\nThe LEC field holds a code which indicates the type of the last error to occur on the CAN bus" "0,1,2,3,4,5,6,7"
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|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CAN_ERR,Error Counter Register"
|
|
bitfld.long 0x00 15. "RP,Receive Error Passive\n" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the.."
|
|
hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter"
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|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CAN_BTIME,Bit Timing Register"
|
|
bitfld.long 0x00 12.--14. "TSeg2,Time Segment After Sample Point \n0x0-0x7: Valid values for TSeg2 are [0 ... 7]" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 8.--11. "TSeg1,Time Segment Before The Sample Point Minus Sync_Seg\n0x01-0x0F: valid values for TSeg1 are [1 ... 15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 6.--7. "SJW,(Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0 ... 3]" "0,1,2,3"
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|
bitfld.long 0x00 0.--5. "BRP,Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rgroup.long 0x10++0x03
|
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line.long 0x00 "CAN_IIDR,Interrupt Identifier Register"
|
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hexmask.long.word 0x00 0.--15. 1. "IntId,Interrupt Identifier (Indicates The Source Of The Interrupt)\nIf several interrupts are pending the CAN Interrupt Register will point to the pending interrupt with the highest priority disregarding their chronological order"
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group.long 0x14++0x03
|
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line.long 0x00 "CAN_TEST,Test Register"
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rbitfld.long 0x00 7. "Rx,Monitors The Actual Value Of CAN_RX Pin (Read Only) *(1)\n" "0: The CAN bus is dominant (CAN_RX = '0'),1: The CAN bus is recessive (CAN_RX = '1')"
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|
bitfld.long 0x00 5.--6. "Tx,Tx[1:0]: Control Of CAN_TX Pin\n" "0: Reset value CAN_TX pin is controlled by the..,1: Sample Point can be monitored at CAN_TX pin,2: CAN_TX pin drives a dominant ('0') value,3: CAN_TX pin drives a recessive ('1') value"
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newline
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bitfld.long 0x00 4. "LBack,Loop Back Mode Enable Bit\n" "0: Loop Back Mode is disabled,1: Loop Back Mode is enabled"
|
|
bitfld.long 0x00 3. "Silent,Silent Mode\n" "0: Normal operation,1: The module is in Silent Mode"
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newline
|
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bitfld.long 0x00 2. "Basic,Basic Mode\n" "0: Basic Mode disabled,1: IF1 Registers used as Tx Buffer IF2 Registers.."
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|
bitfld.long 0x00 0.--1. "Res,Reserved\nThere are reserved bits.\nThese bits are always read as '0' and must always be written with '0'" "0,1,2,3"
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|
group.long 0x18++0x03
|
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line.long 0x00 "CAN_BRPE,Baud Rate Prescaler Extension Register"
|
|
bitfld.long 0x00 0.--3. "BRPE,BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x20++0x03
|
|
line.long 0x00 "CAN_IF1_CREQ,IF1 Command Request Register"
|
|
bitfld.long 0x00 15. "Busy,Busy Flag\n" "0: Read/write action has finished,1: Writing to the IFn Command Request Register.."
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|
bitfld.long 0x00 0.--5. "MessageNumber,Message Number\n0x01-0x20: Valid Message Number the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number interpreted as 0x01-0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CAN_IF1_CMASK,IF1 Command Mask Register"
|
|
bitfld.long 0x00 7. "WR_RD,Write / Read Mode\n" "0: Read: Transfer data from the Message Object..,1: Write: Transfer data from the selected.."
|
|
bitfld.long 0x00 6. "Mask,Access Mask Bits\nWrite Operation:\n" "0: Mask bits unchanged,1: Transfer Identifier Mask + MDir + MXtd to.."
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newline
|
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bitfld.long 0x00 5. "Arb,Access Arbitration Bits\nWrite Operation:\n" "0: Arbitration bits unchanged,1: Transfer Identifier + Dir (CAN_IFn_ARB2[13]).."
|
|
bitfld.long 0x00 4. "Control,Control Access Control Bits\nWrite Operation:\n" "0: Control Bits unchanged,1: Transfer Control Bits to Message.."
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|
newline
|
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bitfld.long 0x00 3. "ClrIntPnd,Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object this bit is ignored.\nRead Operation:\n" "0: IntPnd bit (CAN_IFn_MCON[13]) remains unchanged,1: Clear IntPnd bit in the Message Object"
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bitfld.long 0x00 2. "TxRqst_NewDat,Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat" "0: TxRqst bit unchanged.\nNewDat bit remains..,1: Set TxRqst bit.\nClear NewDat bit in the.."
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|
newline
|
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bitfld.long 0x00 1. "DAT_A,Access Data Bytes [3:0]\nWrite Operation:\n" "0: Data Bytes [3:0] unchanged,1: Transfer Data Bytes [3:0] to Message.."
|
|
bitfld.long 0x00 0. "DAT_B,Access Data Bytes [7:4]\nWrite Operation: \n" "0: Data Bytes [7:4] unchanged,1: Transfer Data Bytes [7:4] to Message.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CAN_IF1_MASK1,IF1 Mask 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "Msk,Identifier Mask 15-0\n"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CAN_IF1_MASK2,IF1 Mask 2 Register"
|
|
bitfld.long 0x00 15. "MXtd,Mask Extended Identifier\nNote: When 11-bit ( standard ) Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])" "0: The extended identifier bit (IDE) has no..,1: The extended identifier bit (IDE) is used for.."
|
|
bitfld.long 0x00 14. "MDir,Mask Message Direction\n" "0: The message direction bit (Dir..,1: The message direction bit (Dir) is used for.."
|
|
newline
|
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hexmask.long.word 0x00 0.--12. 1. "Msk,Identifier Mask 28-16\n"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CAN_IF1_ARB1,IF1 Arbitration 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ID,Message Identifier 15-0\nID28 - ID0 29-bit Identifier ( Extended Frame ).\nID28 - ID18 11-bit Identifier ( Standard Frame )"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CAN_IF1_ARB2,IF1 Arbitration 2 Register"
|
|
bitfld.long 0x00 15. "MsgVal,Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])" "0: The Message Object is ignored by the Message..,1: The Message Object is configured and should.."
|
|
bitfld.long 0x00 14. "Xtd,Extended Identifier\n" "0: The 11-bit ( standard ) Identifier will be..,1: The 29-bit ( extended ) Identifier will be.."
|
|
newline
|
|
bitfld.long 0x00 13. "Dir,Message Direction\n" "0: Direction is receive,1: Direction is transmit"
|
|
hexmask.long.word 0x00 0.--12. 1. "ID,Message Identifier 28-16\nID28 - ID0 29-bit Identifier ( Extended Frame ).\nID28 - ID18 11-bit Identifier ( Standard Frame )"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CAN_IF1_MCON,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. "NewDat,New Data\n" "0: No new data has been written into the data..,1: The Message Handler or the application.."
|
|
bitfld.long 0x00 14. "MsgLst," "0: No message lost since last time this bit was..,1: The Message Handler stored a new message into.."
|
|
newline
|
|
bitfld.long 0x00 13. "IntPnd,Interrupt Pending\n" "0: This message object is not the source of an..,1: This message object is the source of an.."
|
|
bitfld.long 0x00 12. "UMask,Use Acceptance Mask\nNote: If the UMask bit is set to one the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one" "0: Mask ignored,1: Use Mask (Msk28-0 MXtd and MDir) for.."
|
|
newline
|
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bitfld.long 0x00 11. "TxIE,Transmit Interrupt Enable Bit\n" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
|
|
bitfld.long 0x00 10. "RxIE,Receive Interrupt Enable Bit\n" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
|
|
newline
|
|
bitfld.long 0x00 9. "RmtEn,Remote Enable Bit\n" "0: At the reception of a Remote Frame TxRqst..,1: At the reception of a Remote Frame TxRqst is.."
|
|
bitfld.long 0x00 8. "TxRqst,Transmit Request\n" "0: This Message Object is not waiting for..,1: The transmission of this Message Object is.."
|
|
newline
|
|
bitfld.long 0x00 7. "EoB,End Of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer" "0: Message Object belongs to a FIFO Buffer and..,1: Single Message Object or last Message Object.."
|
|
bitfld.long 0x00 0.--3. "DLC,Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes" "0: 1st data byte of a CAN Data Frame\nData,1: 2nd data byte of a CAN Data Frame\nData,2: 3rd data byte of a CAN Data Frame\nData,3: 4th data byte of a CAN Data Frame\nData,4: 5th data byte of a CAN Data Frame\nData,5: 6th data byte of a CAN Data Frame\nData,6: 7th data byte of a CAN Data Frame\nData,7: 8th data byte of a CAN Data Frame\n,?..."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CAN_IF1_DAT_A1,IF1 Data A1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data1,Data Byte 1\n2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data0,Data Byte 0\n1st data byte of a CAN Data Frame"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CAN_IF1_DAT_A2,IF1 Data A2 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data3,Data Byte 3\n4th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data2,Data Byte 2\n3rd data byte of CAN Data Frame"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CAN_IF1_DAT_B1,IF1 Data B1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data5,Data Byte 5\n6th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data4,Data Byte 4\n5th data byte of CAN Data Frame"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAN_IF1_DAT_B2,IF1 Data B2 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data7,Data Byte 7\n8th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data6,Data Byte 6\n7th data byte of CAN Data Frame"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CAN_IF2_CREQ,IF2 Command Request Register"
|
|
bitfld.long 0x00 15. "Busy,Busy Flag\n" "0: Read/write action has finished,1: Writing to the IFn Command Request Register.."
|
|
bitfld.long 0x00 0.--5. "MessageNumber,Message Number\n0x01-0x20: Valid Message Number the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number interpreted as 0x01-0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CAN_IF2_CMASK,IF2 Command Mask Register"
|
|
bitfld.long 0x00 7. "WR_RD,Write / Read Mode\n" "0: Read: Transfer data from the Message Object..,1: Write: Transfer data from the selected.."
|
|
bitfld.long 0x00 6. "Mask,Access Mask Bits\nWrite Operation:\n" "0: Mask bits unchanged,1: Transfer Identifier Mask + MDir + MXtd to.."
|
|
newline
|
|
bitfld.long 0x00 5. "Arb,Access Arbitration Bits\nWrite Operation:\n" "0: Arbitration bits unchanged,1: Transfer Identifier + Dir (CAN_IFn_ARB2[13]).."
|
|
bitfld.long 0x00 4. "Control,Control Access Control Bits\nWrite Operation:\n" "0: Control Bits unchanged,1: Transfer Control Bits to Message.."
|
|
newline
|
|
bitfld.long 0x00 3. "ClrIntPnd,Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object this bit is ignored.\nRead Operation:\n" "0: IntPnd bit (CAN_IFn_MCON[13]) remains unchanged,1: Clear IntPnd bit in the Message Object"
|
|
bitfld.long 0x00 2. "TxRqst_NewDat,Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat" "0: TxRqst bit unchanged.\nNewDat bit remains..,1: Set TxRqst bit.\nClear NewDat bit in the.."
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bitfld.long 0x00 1. "DAT_A,Access Data Bytes [3:0]\nWrite Operation:\n" "0: Data Bytes [3:0] unchanged,1: Transfer Data Bytes [3:0] to Message.."
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bitfld.long 0x00 0. "DAT_B,Access Data Bytes [7:4]\nWrite Operation: \n" "0: Data Bytes [7:4] unchanged,1: Transfer Data Bytes [7:4] to Message.."
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group.long 0x88++0x03
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line.long 0x00 "CAN_IF2_MASK1,IF2 Mask 1 Register"
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|
hexmask.long.word 0x00 0.--15. 1. "Msk,Identifier Mask 15-0\n"
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group.long 0x8C++0x03
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line.long 0x00 "CAN_IF2_MASK2,IF2 Mask 2 Register"
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|
bitfld.long 0x00 15. "MXtd,Mask Extended Identifier\nNote: When 11-bit ( standard ) Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])" "0: The extended identifier bit (IDE) has no..,1: The extended identifier bit (IDE) is used for.."
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bitfld.long 0x00 14. "MDir,Mask Message Direction\n" "0: The message direction bit (Dir..,1: The message direction bit (Dir) is used for.."
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|
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hexmask.long.word 0x00 0.--12. 1. "Msk,Identifier Mask 28-16\n"
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|
group.long 0x90++0x03
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|
line.long 0x00 "CAN_IF2_ARB1,IF2 Arbitration 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ID,Message Identifier 15-0\nID28 - ID0 29-bit Identifier ( Extended Frame ).\nID28 - ID18 11-bit Identifier ( Standard Frame )"
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|
group.long 0x94++0x03
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|
line.long 0x00 "CAN_IF2_ARB2,IF2 Arbitration 2 Register"
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|
bitfld.long 0x00 15. "MsgVal,Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])" "0: The Message Object is ignored by the Message..,1: The Message Object is configured and should.."
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bitfld.long 0x00 14. "Xtd,Extended Identifier\n" "0: The 11-bit ( standard ) Identifier will be..,1: The 29-bit ( extended ) Identifier will be.."
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bitfld.long 0x00 13. "Dir,Message Direction\n" "0: Direction is receive,1: Direction is transmit"
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hexmask.long.word 0x00 0.--12. 1. "ID,Message Identifier 28-16\nID28 - ID0 29-bit Identifier ( Extended Frame ).\nID28 - ID18 11-bit Identifier ( Standard Frame )"
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group.long 0x98++0x03
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|
line.long 0x00 "CAN_IF2_MCON,IF2 Message Control Register"
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|
bitfld.long 0x00 15. "NewDat,New Data\n" "0: No new data has been written into the data..,1: The Message Handler or the application.."
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|
bitfld.long 0x00 14. "MsgLst," "0: No message lost since last time this bit was..,1: The Message Handler stored a new message into.."
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bitfld.long 0x00 13. "IntPnd,Interrupt Pending\n" "0: This message object is not the source of an..,1: This message object is the source of an.."
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bitfld.long 0x00 12. "UMask,Use Acceptance Mask\nNote: If the UMask bit is set to one the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one" "0: Mask ignored,1: Use Mask (Msk28-0 MXtd and MDir) for.."
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bitfld.long 0x00 11. "TxIE,Transmit Interrupt Enable Bit\n" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
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bitfld.long 0x00 10. "RxIE,Receive Interrupt Enable Bit\n" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
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bitfld.long 0x00 9. "RmtEn,Remote Enable Bit\n" "0: At the reception of a Remote Frame TxRqst..,1: At the reception of a Remote Frame TxRqst is.."
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bitfld.long 0x00 8. "TxRqst,Transmit Request\n" "0: This Message Object is not waiting for..,1: The transmission of this Message Object is.."
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bitfld.long 0x00 7. "EoB,End Of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer" "0: Message Object belongs to a FIFO Buffer and..,1: Single Message Object or last Message Object.."
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bitfld.long 0x00 0.--3. "DLC,Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes" "0: 1st data byte of a CAN Data Frame\nData,1: 2nd data byte of a CAN Data Frame\nData,2: 3rd data byte of a CAN Data Frame\nData,3: 4th data byte of a CAN Data Frame\nData,4: 5th data byte of a CAN Data Frame\nData,5: 6th data byte of a CAN Data Frame\nData,6: 7th data byte of a CAN Data Frame\nData,7: 8th data byte of a CAN Data Frame\n,?..."
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group.long 0x9C++0x03
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line.long 0x00 "CAN_IF2_DAT_A1,IF2 Data A1 Register"
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hexmask.long.byte 0x00 8.--15. 1. "Data1,Data Byte 1\n2nd data byte of a CAN Data Frame"
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hexmask.long.byte 0x00 0.--7. 1. "Data0,Data Byte 0\n1st data byte of a CAN Data Frame"
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group.long 0xA0++0x03
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line.long 0x00 "CAN_IF2_DAT_A2,IF2 Data A2 Register"
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hexmask.long.byte 0x00 8.--15. 1. "Data3,Data Byte 3\n4th data byte of CAN Data Frame"
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hexmask.long.byte 0x00 0.--7. 1. "Data2,Data Byte 2\n3rd data byte of CAN Data Frame"
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group.long 0xA4++0x03
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line.long 0x00 "CAN_IF2_DAT_B1,IF2 Data B1 Register"
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hexmask.long.byte 0x00 8.--15. 1. "Data5,Data Byte 5\n6th data byte of CAN Data Frame"
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hexmask.long.byte 0x00 0.--7. 1. "Data4,Data Byte 4\n5th data byte of CAN Data Frame"
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group.long 0xA8++0x03
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line.long 0x00 "CAN_IF2_DAT_B2,IF2 Data B2 Register"
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hexmask.long.byte 0x00 8.--15. 1. "Data7,Data Byte 7\n8th data byte of CAN Data Frame"
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hexmask.long.byte 0x00 0.--7. 1. "Data6,Data Byte 6\n7th data byte of CAN Data Frame"
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rgroup.long 0x100++0x03
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line.long 0x00 "CAN_TXREQ1,Transmission Request Register 1"
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hexmask.long.word 0x00 0.--15. 1. "TxRqst16_1,Transmission Request Bits 16-1 (Of All Message Objects)\nThese bits are read only"
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|
rgroup.long 0x104++0x03
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line.long 0x00 "CAN_TXREQ2,Transmission Request Register 2"
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hexmask.long.word 0x00 0.--15. 1. "TxRqst32_17,Transmission Request Bits 32-17 (Of All Message Objects)\nThese bits are read only"
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rgroup.long 0x120++0x03
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line.long 0x00 "CAN_NDAT1,New Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "NewData16_1,New Data Bits 16-1 (Of All Message Objects)\n"
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rgroup.long 0x124++0x03
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line.long 0x00 "CAN_NDAT2,New Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "NewData32_17,New Data Bits 32-17 (Of All Message Objects)\n"
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rgroup.long 0x140++0x03
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line.long 0x00 "CAN_IPND1,Interrupt Pending Register 1"
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hexmask.long.word 0x00 0.--15. 1. "IntPnd16_1,Interrupt Pending Bits 16-1 (Of All Message Objects)\n"
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rgroup.long 0x144++0x03
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|
line.long 0x00 "CAN_IPND2,Interrupt Pending Register 2"
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|
hexmask.long.word 0x00 0.--15. 1. "IntPnd32_17,Interrupt Pending Bits 32-17(Of All Message Objects)\n"
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rgroup.long 0x160++0x03
|
|
line.long 0x00 "CAN_MVLD1,Message Valid Register 1"
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|
hexmask.long.word 0x00 0.--15. 1. "MsgVal16_1,Message Valid Bits 16-1 (Of All Message Objects) (Read Only)\nEx"
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|
rgroup.long 0x164++0x03
|
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line.long 0x00 "CAN_MVLD2,Message Valid Register 2"
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hexmask.long.word 0x00 0.--15. 1. "MsgVal32_17,Message Valid Bits 32-17 (Of All Message Objects) (Read Only)\nEx.CAN_MVLD2[15] means Message object No.32 is valid or not"
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group.long 0x168++0x03
|
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line.long 0x00 "CAN_WU_EN,Wake-up Enable Control Register"
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bitfld.long 0x00 0. "WAKUP_EN,Wake-Up Enable Bit\nNote: User can wake-up system when there is a falling edge in the CAN_Rx pin" "0: The wake-up function Disabled,1: The wake-up function Enabled"
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group.long 0x16C++0x03
|
|
line.long 0x00 "CAN_WU_STATUS,Wake-up Status Register"
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|
bitfld.long 0x00 0. "WAKUP_STS,Wake-Up Status \nNote: This bit can be cleared by writing '0'" "0: No wake-up event occurred,1: Wake-up event occurred"
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tree.end
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repeat.end
|
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tree.end
|
|
tree "CAP"
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base ad:0x40030000
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group.long 0x00++0x03
|
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line.long 0x00 "CAP_CTL,Image Capture Interface Control Register"
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bitfld.long 0x00 24. "VPRST,Capture Interface Reset\n" "0: Capture interface reset Disabled,1: Capture interface reset Enabled"
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bitfld.long 0x00 20. "UPDATE,Update Register At New Frame\n" "0: Update register at new frame Disabled,1: Update register at new frame Enabled (Auto.."
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bitfld.long 0x00 16. "SHUTTER,Image Capture Interface Automatically Disable The Capture Inteface After A Frame Had Been Captured\n" "0: Shutter Disabled,1: Shutter Enabled"
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bitfld.long 0x00 6. "PKTEN,Packet Output Enable\n" "0: Packet output Disabled,1: Packet output Enabled"
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bitfld.long 0x00 5. "PLNEN,Planar Output Enable\n" "0: Planar output Disabled,1: Planar output Enabled"
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bitfld.long 0x00 3. "ADDRSW,Packet Buffer Address Switch\n" "0: Packet buffer address switch Disabled,1: Packet buffer address switch Enabled"
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bitfld.long 0x00 0. "CAPEN,Image Capture Interface Enable\n" "0: Image Capture Interface Disabled,1: Image Capture Interface Enabled"
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group.long 0x04++0x03
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line.long 0x00 "CAP_PAR,Image Capture Interface Parameter Register"
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bitfld.long 0x00 18. "FBB,Field By Blank\nHardware will tag field0 or field1 by vertical blanking instead of FIELD flag in ccir-656 mode.\n" "0: Field by blank Disabled,1: Field by blank Enabled"
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bitfld.long 0x00 11.--12. "COLORCTL,Special COLORCTL Processing\n" "0: Normal Color,1: Sepia effect corresponding U V component..,2: Negative picture,3: Posterize image the Y U V components.."
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bitfld.long 0x00 10. "VSP,Sensor Vsync Polarity\n" "0: Sync Low,1: Sync High"
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bitfld.long 0x00 9. "HSP,Sensor Hsync Polarity\n" "0: Sync Low,1: Sync High"
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bitfld.long 0x00 8. "PCLKP,Sensor Pixel Clock Polarity\n" "0: Input video data and signals are latched by..,1: Input video data and signals are latched by.."
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bitfld.long 0x00 7. "PLNFMT,Planar Output YUV Format\n" "0: YUV422,1: YUV420"
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bitfld.long 0x00 6. "RANGE,Scale Input YUV CCIR601 Color Range To Full Range\n" "0: default,1: Scale to full range"
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bitfld.long 0x00 4.--5. "OUTFMT,Image Data Format Output To System Memory\n" "0: YCbCr422,1: Only output Y,2: RGB555,3: RGB565"
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bitfld.long 0x00 2.--3. "INDATORD,Sensor Input Data Order\n" "0: Y0 U0 Y1 V0,1: Y0 V0 Y1 U0,2: U0 Y0 V0 Y1,3: V0 Y0 U0 Y1"
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bitfld.long 0x00 1. "SENTYPE,Sensor Input Type\n" "0: CCIR601,1: CCIR656 VSync Hsync embedded in the data signal"
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bitfld.long 0x00 0. "INFMT,Sensor Input Data Format\n" "0: YCbCr422,1: RGB565"
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group.long 0x08++0x03
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line.long 0x00 "CAP_INT,Image Capture Interface Interrupt Register"
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bitfld.long 0x00 20. "MDIEN,Motion Detection Output Finish Interrupt Enable\n" "0: CAP_MD finish interrupt Disabled,1: CAP_MD finish interrupt Enabled"
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bitfld.long 0x00 19. "ADDRMIEN,Address Match Interrupt Enable\n" "0: Address match interrupt Disabled,1: Address match interrupt Enabled"
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bitfld.long 0x00 17. "MEIEN,System Memory Error Interrupt Enable\n" "0: System memory error interrupt Disabled,1: System memory error interrupt Enabled"
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bitfld.long 0x00 16. "VIEN,Video Frame End Interrupt Enable\n" "0: Video frame end interrupt Disabled,1: Video frame end interrupt Enabled"
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bitfld.long 0x00 4. "MDINTF,Motion Detection Output Finish Interrupt\nIf this bit shows 1 Motion Detection Output Finish Interrupt occurred.\nWrite 1 to clear it" "0,1"
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bitfld.long 0x00 3. "ADDRMINTF,Memory Address Match Interrupt\nIf this bit shows 1 Memory Address Match Interrupt occurred.\nWrite 1 to clear it" "0,1"
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bitfld.long 0x00 1. "MEINTF,Bus Master Transfer Error Interrupt\nIf this bit shows 1 Transfer Error occurred" "0,1"
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bitfld.long 0x00 0. "VINTF,Video Frame End Interrupt\nIf this bit shows 1 receiving a frame completed.\nWrite 1 to clear it" "0,1"
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group.long 0x0C++0x03
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line.long 0x00 "CAP_POSTERIZE,YUV Component Posterizing Factor Register"
|
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hexmask.long.byte 0x00 16.--23. 1. "YCOMP,Y Component Posterizing Factor\n"
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hexmask.long.byte 0x00 8.--15. 1. "UCOMP,U Component Posterizing Factor\n"
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hexmask.long.byte 0x00 0.--7. 1. "VCOMP,V Component Posterizing Factor\n"
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group.long 0x10++0x03
|
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line.long 0x00 "CAP_MD,Motion Detection Register"
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bitfld.long 0x00 16.--20. "MDTHR,Motion Detection Differential Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10.--11. "MDDF,Motion Detection Detect Frequency\n" "0: Each frame,1: Every 2 frame,2: Every 3 frame,3: Every 4 frame"
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bitfld.long 0x00 9. "MDSM,Motion Detection Save Mode\n" "0: 1 bit DIFF + 7 bit Y Differential,1: 1 bit DIFF only"
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bitfld.long 0x00 8. "MDBS,Motion Detection Block Size\n" "0: 16x16,1: 8x8"
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newline
|
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bitfld.long 0x00 0. "MDEN,Motion Detection Enable\n" "0: CAP_MD Disabled,1: CAP_MD Enabled"
|
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group.long 0x14++0x03
|
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line.long 0x00 "CAP_MDADDR,Motion Detection Output Address Register"
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hexmask.long 0x00 0.--31. 1. "MDADDR,Motion Detection Output Address Register (Word Alignment)"
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group.long 0x18++0x03
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line.long 0x00 "CAP_MDYADDR,Motion Detection Temp Y Output Address Register"
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hexmask.long 0x00 0.--31. 1. "MDYADDR,Motion Detection Temp Y Output Address Register (Word Alignment)"
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group.long 0x1C++0x03
|
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line.long 0x00 "CAP_SEPIA,Sepia Effect Control Register"
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hexmask.long.byte 0x00 8.--15. 1. "UCOMP,Define the constant U component while Sepia color effect is turned on"
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hexmask.long.byte 0x00 0.--7. 1. "VCOMP,Define the constant V component while Sepia color effect is turned on"
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group.long 0x20++0x03
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line.long 0x00 "CAP_CWSP,Cropping Window Starting Address Register"
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hexmask.long.word 0x00 16.--26. 1. "CWSADDRV,Cropping Window Vertical Starting Address"
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hexmask.long.word 0x00 0.--11. 1. "CWSADDRH,Cropping Window Horizontal Starting Address"
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group.long 0x24++0x03
|
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line.long 0x00 "CAP_CWS,Cropping Window Size Register"
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hexmask.long.word 0x00 16.--26. 1. "CWH,Cropping Window Height"
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hexmask.long.word 0x00 0.--11. 1. "CWW,Cropping Window Width"
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group.long 0x28++0x03
|
|
line.long 0x00 "CAP_PKTSL,Packet Scaling Vertical/Horizontal Factor Register (LSB)"
|
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hexmask.long.byte 0x00 24.--31. 1. "PKTSVNL,Packet Scaling Vertical Factor N (Lower 8-Bit)\nSpecify the lower 8-bit of numerator part (N) of the vertical scaling factor"
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hexmask.long.byte 0x00 16.--23. 1. "PKTSVML,Packet Scaling Vertical Factor M (Lower 8-Bit)\nSpecify the lower 8-bit of denominator part (M) of the vertical scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical.."
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newline
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hexmask.long.byte 0x00 8.--15. 1. "PKTSHNL,Packet Scaling Horizontal Factor N (Lower 8-Bit)\nSpecify the lower 8-bit of numerator part (N) of the horizontal scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor"
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hexmask.long.byte 0x00 0.--7. 1. "PKTSHML,Packet Scaling Horizontal Factor M (Lower 8-Bit)\nSpecifies the lower 8-bit of denominator part (M) of the horizontal scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical.."
|
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group.long 0x2C++0x03
|
|
line.long 0x00 "CAP_PLNSL,Planar Scaling Vertical/Horizontal Factor Register (LSB)"
|
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hexmask.long.byte 0x00 24.--31. 1. "PLNSVNL,Planar Scaling Vertical Factor N (Lower 8-Bit)\nSpecify the lower 8-bit of numerator part (N) of the vertical scaling factor"
|
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hexmask.long.byte 0x00 16.--23. 1. "PLNSVML,Planar Scaling Vertical Factor M (Lower 8-Bit)\nSpecify the lower 8-bit of denominator part (M) of the vertical scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PNDSVMH) to form a 16-bit denominator (M) of vertical.."
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|
newline
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hexmask.long.byte 0x00 8.--15. 1. "PLNSHNL,Planar Scaling Horizontal Factor N (Lower 8-Bit)\nSpecify the lower 8-bit of numerator part (N) of the horizontal scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PNDSHNH) to form a 16-bit numerator of horizontal factor"
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hexmask.long.byte 0x00 0.--7. 1. "PLNSHML,Planar Scaling Horizontal Factor M (Lower 8-Bit)\nSpecify the lower 8-bit of denominator part (M) of the horizontal scaling factor.\nThe lower 8-bit will be cascaded with higher 8-bit (PNDSHMH) to form a 16-bit denominator (M) of vertical.."
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group.long 0x30++0x03
|
|
line.long 0x00 "CAP_FRCTL,Scaling Frame Rate Factor Register"
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bitfld.long 0x00 8.--13. "FRN,Scaling Frame Rate Factor N\nSpecify the denominator part (N) of the frame rate scaling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "FRM,Scaling Frame Rate Factor M\nSpecify the denominator part (M) of the frame rate scaling factor.\nThe output image frame rate will be equal to input image frame rate * (N/M).\nNote: The value of N must be equal to or less than M" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x34++0x03
|
|
line.long 0x00 "CAP_STRIDE,Frame Output Pixel Stride Width Register"
|
|
hexmask.long.word 0x00 16.--29. 1. "PLNSTRIDE,Planar Frame Output Pixel Stride Width\nThe output pixel stride size of planar pipe"
|
|
hexmask.long.word 0x00 0.--13. 1. "PKTSTRIDE,Packet Frame Output Pixel Stride Width\nThe output pixel stride size of packet pipe"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CAP_FIFOTH,FIFO Threshold Register"
|
|
bitfld.long 0x00 31. "OVF,FIFO Overflow Flag" "0,1"
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|
bitfld.long 0x00 24.--28. "PKTFTH,Packet FIFO Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 16.--20. "PLNYFTH,Planar Y FIFO Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--11. "PLNUFTH,Planar U FIFO Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 0.--3. "PLNVFTH,Planar V FIFO Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x40++0x03
|
|
line.long 0x00 "CAP_CMPADDR,Compare Memory Base Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "CMPADDR,Compare Memory Base Address\nWord aligns address ignore the bits [1:0]"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAP_PKTSM,Packet Scaling Vertical/Horizontal Factor Register (MSB)"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PKTSVNH,Packet Scaling Vertical Factor N (Higher 8-Bit)\nSpecify the higher 8-bit of numerator part (N) of the vertical scaling factor"
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hexmask.long.byte 0x00 16.--23. 1. "PKTSVMH,Packet Scaling Vertical Factor M (Higher 8-Bit)\nSpecify the lower 8-bit of denominator part (M) of the vertical scaling factor.\nPlease refer to the register CAP_PKTSL to check the cooperation between these two registers"
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hexmask.long.byte 0x00 8.--15. 1. "PKTSHNH,Packet Scaling Horizontal Factor N (Higher 8-Bit)\nSpecify the lower 8-bit of numerator part (N) of the horizontal scaling factor.\nPlease refer to the register CAP_PKTSL for the detailed operation"
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hexmask.long.byte 0x00 0.--7. 1. "PKTSHMH,Packet Scaling Horizontal Factor M (Higher 8-Bit)\nSpecify the lower 8-bit of denominator part (M) of the horizontal scaling factor.\nPlease refer to the register CAP_PKTSL for the detailed operation"
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group.long 0x4C++0x03
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line.long 0x00 "CAP_PLNSM,Planar Scaling Vertical/Horizontal Factor Register (MSB)"
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hexmask.long.byte 0x00 24.--31. 1. "PLNSVNH,Planar Scaling Vertical Factor N (Higher 8-Bit)\nSpecifies the higher 8-bit of numerator part (N) of the vertical scaling factor"
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hexmask.long.byte 0x00 16.--23. 1. "PLNSVMH,Planar Scaling Vertical Factor M (Higher 8-Bit)\nSpecifies the lower 8-bit of denominator part (M) of the vertical scaling factor.\nFor detailed programming please refer to the register CAP_PLNSL"
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hexmask.long.byte 0x00 8.--15. 1. "PLNSHNH,Planar Scaling Horizontal Factor N (Higher 8-Bit)\nSpecifies the higher 8-bit of numerator part (N) of the horizontal scaling factor.\nFor detailed programming please refer to the register CAP_PLNSL"
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hexmask.long.byte 0x00 0.--7. 1. "PLNSHMH,Planar Scaling Horizontal Factor M (Higher 8-Bit)\nSpecifies the higher 8-bit of denominator part (M) of the horizontal scaling factor\nFor detailed programming please refer to the register CAP_PLNSL"
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rgroup.long 0x50++0x03
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line.long 0x00 "CAP_CURADDRP,Current Packet System Memory Address Register"
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hexmask.long 0x00 0.--31. 1. "CURADDR,Current Packet Output Memory Address"
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rgroup.long 0x54++0x03
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line.long 0x00 "CAP_CURADDRY,Current Planar Y System Memory Address Register"
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hexmask.long 0x00 0.--31. 1. "CURADDR,Current Planar Y Output Memory Address"
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rgroup.long 0x58++0x03
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line.long 0x00 "CAP_CURADDRU,Current Planar U System Memory Address Register"
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hexmask.long 0x00 0.--31. 1. "CURADDR,Current Planar U Output Memory Address"
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rgroup.long 0x5C++0x03
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line.long 0x00 "CAP_CURVADDR,Current Planar V System Memory Address Register"
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hexmask.long 0x00 0.--31. 1. "CURADDR,Current Planar V Output Memory Address"
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group.long 0x60++0x03
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line.long 0x00 "CAP_PKTBA0,System Memory Packet Base Address 0 Register"
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hexmask.long 0x00 0.--31. 1. "BASEADDR,System Memory Packet Base Address 0\nWord aligns address ignore the bits [1:0]"
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group.long 0x64++0x03
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line.long 0x00 "CAP_PKTBA1,System Memory Packet Base Address 1 Register"
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hexmask.long 0x00 0.--31. 1. "BASEADDR,System Memory Packet Base Address 1\nWord aligns address ignore the bits [1:0]"
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group.long 0x80++0x03
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line.long 0x00 "CAP_YBA,System Memory Planar Y Base Address Register"
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hexmask.long 0x00 0.--31. 1. "BASEADDR,System Memory Planar Y Base Address\nWord aligns address ignore the bits [1:0]"
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group.long 0x84++0x03
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line.long 0x00 "CAP_UBA,System Memory Planar U Base Address Register"
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hexmask.long 0x00 0.--31. 1. "BASEADDR,System Memory Planar U Base Address\nWord aligns address ignore the bits [1:0]"
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group.long 0x88++0x03
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line.long 0x00 "CAP_VBA,System Memory Planar V Base Address Register"
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hexmask.long 0x00 0.--31. 1. "BASEADDR,System Memory Planar V Base Address\nWord aligns address ignore the bits [1:0]"
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tree.end
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tree "CLK"
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base ad:0x40000200
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group.long 0x00++0x03
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line.long 0x00 "CLK_PWRCTL,System Power-down Control Register"
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bitfld.long 0x00 9. "DBPDEN,Chip Entering Power-Down Even ICE Connected\n" "0: Chip enters power-down disabled in Debug mode,1: Chip enters power-down enabled in Debug mode"
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bitfld.long 0x00 8. "PDWTCPU,This Bit Control The Power-Down Entry Condition (Write Protect)\n" "0: Chip enters Power-down mode when the PDEN bit..,1: Chip enters Power-down mode when the both.."
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bitfld.long 0x00 7. "PDEN,System Power-Down Enable Bit (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip power-down behavior will depend on the PDWTCPU bit.\n(a) If the PDWTCPU is 0 then the chip enters Power-down mode immediately after the PDEN.." "0: Chip operating normally or chip in idle mode..,1: Chip enters Power-down mode instant or waits.."
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bitfld.long 0x00 6. "PDWKIF,Power-Down Mode Wake-Up Interrupt Status\nSet by power-down wake-up event it indicates that resume from Power-down mode \nThe flag is set if the GPIO USB UART WDT CAN ACMP BOD RTC or SDHOST wake-up occurred\nNote1: Write 1 to clear the bit to.." "0,1"
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bitfld.long 0x00 5. "PDWKIEN,Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are high" "0: Power-down Mode Wake-up Interrupt Disabled,1: Power-down Mode Wake-up Interrupt Enabled"
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bitfld.long 0x00 4. "PDWKDLY,Wake-Up Delay Counter Enable Bit (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at HXT and.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
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bitfld.long 0x00 3. "LIRCEN,10 KHz Internal Low-Speed Oscillator (LIRC) Enable Bit (Write Protect)\n" "0: LIRC Disabled,1: LIRC Enabled (default 1)"
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bitfld.long 0x00 2. "HIRCEN,22.1184 MHz Internal High-Speed Oscillator Clock (HIRC) Enable Bit (Write Protect)\n" "0: HIRC Disabled,1: HIRC Enabled"
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bitfld.long 0x00 1. "LXTEN,32.768 KHz External Low-Speed Crystal Clock (LXT) Enable Bit (Write Protect)\n" "0: LXT Disabled,1: LXT (Normal operation) Enabled"
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bitfld.long 0x00 0. "HXTEN,4~24 MHz External High-Speed Crystal Clock (HXT) Enable Bit (Write Protect)\nThe bit default value is set by flash controller user configuration register config0 [26:24]" "0: HXT Disabled,1: HXT Enabled"
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group.long 0x04++0x03
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line.long 0x00 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
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bitfld.long 0x00 12. "CRPTCKEN,Cryptographic Accelerator Clock Enable Bit \n" "0: Cryptographic Accelerator clock Disabled,1: Cryptographic Accelerator clock Enabled"
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bitfld.long 0x00 10. "USBDCKEN,USB 2.0 Device Clock Enable Bit\n" "0: USB device controller's clock Disabled,1: USB device controller's clock Enabled"
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bitfld.long 0x00 9. "SENCKEN,Sensor Clock Enable Bit \n" "0: Sensor clock Disabled,1: Sensor clock Enabled"
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bitfld.long 0x00 8. "CAPCKEN,Image Capture Interface Controller Clock Enable Bit \n" "0: CAP controller's clock Disabled,1: CAP controller's clock Enabled"
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bitfld.long 0x00 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit\n" "0: CRC engine clock Disabled,1: CRC engine clock Enabled"
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bitfld.long 0x00 6. "SDHCKEN,SDHOST Controller Clock Enable Bit \n" "0: SDHOST engine clock Disabled,1: SDHOST engine clock Enabled"
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bitfld.long 0x00 5. "EMACCKEN,Ethernet Controller Clock Enable Bit (NUC472 Only)\n" "0: Ethernet Controller engine clock Disabled,1: Ethernet Controller engine clock Enabled"
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bitfld.long 0x00 4. "USBHCKEN,USB HOST Controller Clock Enable Bit \n" "0: USB HOST engine clock Disabled,1: USB HOST engine clock Enabled"
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bitfld.long 0x00 3. "EBICKEN,EBI Controller Clock Enable Bit \n" "0: EBI engine clock Disabled,1: EBI engine clock Enabled"
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bitfld.long 0x00 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit\n" "0: Flash ISP engine clock Disabled,1: Flash ISP engine clock Enabled"
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bitfld.long 0x00 1. "PDMACKEN,PDMA Controller Clock Enable Bit\n" "0: PDMA engine clock Disabled,1: PDMA engine clock Enabled"
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group.long 0x08++0x03
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line.long 0x00 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0"
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bitfld.long 0x00 31. "PS2CKEN,PS/2 Clock Enable Bit\n" "0: PS/2 clock Disabled,1: PS/2 clock Enabled"
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bitfld.long 0x00 30. "I2S1CKEN,I2S1 Clock Enable Bit\n" "0: I2S1 Clock Disabled,1: I2S1 Clock Enabled"
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bitfld.long 0x00 29. "I2S0CKEN,I2S0 Clock Enable Bit\n" "0: I2S Clock Disabled,1: I2S Clock Enabled"
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bitfld.long 0x00 28. "ADCCKEN,Analog-Digital-Converter (ADC) Clock Enable Bit\n" "0: ADC clock Disabled,1: ADC clock Enabled"
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bitfld.long 0x00 26. "OTGCKEN,USB 2.0 OTG Device Controller Clock Enable Bit\n" "0: OTG clock Disabled,1: OTG clock Enabled"
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bitfld.long 0x00 25. "CAN1CKEN,CAN Bus Controller-1 Clock Enable Bit\n" "0: CAN1 clock Disabled,1: CAN1 clock Enabled"
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bitfld.long 0x00 24. "CAN0CKEN,CAN Bus Controller-0 Clock Enable Bit\n" "0: CAN0 clock Disabled,1: CAN0 clock Enabled"
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bitfld.long 0x00 21. "UART5CKEN,UART5 Clock Enable Bit \n" "0: UART5 clock Disabled,1: UART5 clock Enabled"
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bitfld.long 0x00 20. "UART4CKEN,UART4 Clock Enable Bit \n" "0: UART4 clock Disabled,1: UART4 clock Enabled"
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bitfld.long 0x00 19. "UART3CKEN,UART3 Clock Enable Bit \n" "0: UART3 clock Disabled,1: UART3 clock Enabled"
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bitfld.long 0x00 18. "UART2CKEN,UART2 Clock Enable Bit \n" "0: UART2 clock Disabled,1: UART2 clock Enabled"
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bitfld.long 0x00 17. "UART1CKEN,UART1 Clock Enable Bit\n" "0: UART1 clock Disabled,1: UART1 clock Enabled"
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bitfld.long 0x00 16. "UART0CKEN,UART0 Clock Enable Bit\n" "0: UART0 clock Disabled,1: UART0 clock Enabled"
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bitfld.long 0x00 15. "SPI3CKEN,SPI3 Clock Enable Bit \n" "0: SPI3 Clock Disabled,1: SPI3 Clock Enabled"
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bitfld.long 0x00 14. "SPI2CKEN,SPI2 Clock Enable Bit\n" "0: SPI2 Clock Disabled,1: SPI2 Clock Enabled"
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bitfld.long 0x00 13. "SPI1CKEN,SPI1 Clock Enable Bit\n" "0: SPI1 Clock Disabled,1: SPI1 Clock Enabled"
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bitfld.long 0x00 12. "SPI0CKEN,SPI0 Clock Enable Bit\n" "0: SPI0 Clock Disabled,1: SPI0 Clock Enabled"
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bitfld.long 0x00 11. "I2C3CKEN,I2C3 Clock Enable Bit\n" "0: I2C3 Clock Disabled,1: I2C3 Clock Enabled"
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bitfld.long 0x00 10. "I2C2CKEN,I2C2 Clock Enable Bit\n" "0: I2C2 Clock Disabled,1: I2C2 Clock Enabled"
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bitfld.long 0x00 9. "I2C1CKEN,I2C1 Clock Enable Bit\n" "0: I2C1 Clock Disabled,1: I2C1 Clock Enabled"
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bitfld.long 0x00 8. "I2C0CKEN,I2C0 Clock Enable Bit\n" "0: I2C0 Clock Disabled,1: I2C0 Clock Enabled"
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bitfld.long 0x00 7. "ACMPCKEN,Analog Comparator Clock Enable Bit\n" "0: Analog Comparator Clock Disabled,1: Analog Comparator Clock Enabled"
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bitfld.long 0x00 6. "FDIVCKEN,Frequency Divider Output Clock Enable Bit\n" "0: FDIV Clock Disabled,1: FDIV Clock Enabled"
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bitfld.long 0x00 5. "TMR3CKEN,Timer3 Clock Enable Bit\n" "0: Timer3 Clock Disabled,1: Timer3 Clock Enabled"
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newline
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bitfld.long 0x00 4. "TMR2CKEN,Timer2 Clock Enable Bit\n" "0: Timer2 Clock Disabled,1: Timer2 Clock Enabled"
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bitfld.long 0x00 3. "TMR1CKEN,Timer1 Clock Enable Bit\n" "0: Timer1 Clock Disabled,1: Timer1 Clock Enabled"
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newline
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bitfld.long 0x00 2. "TMR0CKEN,Timer0 Clock Enable Bit\n" "0: Timer0 Clock Disabled,1: Timer0 Clock Enabled"
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bitfld.long 0x00 1. "RTCCKEN,Real-Time-Clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only The RTC engine clock source is from the 32.768 kHz external low-speed crystal.\n" "0: RTC Clock Disabled,1: RTC Clock Enabled"
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newline
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bitfld.long 0x00 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\nThis bit is the protected bit which means programming this needs to write 59h 16h 88h to address 0x4000_0100 to disable register protection" "0: Watchdog Timer Clock Disabled,1: Watchdog Timer Clock Enabled"
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group.long 0x0C++0x03
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line.long 0x00 "CLK_APBCLK1,APB Devices Clock Enable Control Register 1"
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bitfld.long 0x00 31. "EADCCKEN,Enhanced Analog-Digital-Converter (E ADC) Clock Enable Bit\n" "0: EADC clock Disabled,1: EADC clock Enabled"
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bitfld.long 0x00 30. "OPACKEN,OP Amplifier (OPA) Clock Enable Bit\n" "0: OPA clock Disabled,1: OPA clock Enabled"
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bitfld.long 0x00 29. "EPWM1CKEN,Enhanced PWM1 (EPWM) Clock Enable Bit\n" "0: EPWM1 clock Disabled,1: EPWM1 clock Enabled"
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bitfld.long 0x00 28. "EPWM0CKEN,Enhanced PWM0 (EPWM) Clock Enable Bit\n" "0: EPWM0 clock Disabled,1: EPWM0 clock Enabled"
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newline
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bitfld.long 0x00 27. "ECAP1CKEN,Enhanced CAP (ECAP1) Clock Enable Bit\n" "0: ECAP1 clock Disabled,1: ECAP1 clock Enabled"
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bitfld.long 0x00 26. "ECAP0CKEN,Enhanced CAP (ECAP0) Clock Enable Bit\n" "0: ECAP0 clock Disabled,1: ECAP0 clock Enabled"
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newline
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bitfld.long 0x00 23. "QEI1CKEN,Quadrature Encoder Interface (QEI1) Clock Enable Bit\n" "0: QEI1 clock Disabled,1: QEI1 clock Enabled"
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bitfld.long 0x00 22. "QEI0CKEN,Quadrature Encoder Interface (QEI0) Clock Enable Bit\n" "0: QEI0 clock Disabled,1: QEI0 clock Enabled"
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newline
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bitfld.long 0x00 21. "PWM1CH45CKEN,PWM1_45 Clock Enable Bit\n" "0: PWM1_45 Clock Disabled,1: PWM1_45 Clock Enabled"
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bitfld.long 0x00 20. "PWM1CH23CKEN,PWM1_23 Clock Enable Bit\n" "0: PWM1_23 Clock Disabled,1: PWM1_23 Clock Enabled"
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newline
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bitfld.long 0x00 19. "PWM1CH01CKEN,PWM1_01 Clock Enable Bit\n" "0: PWM1_01 Clock Disabled,1: PWM1_01 Clock Enabled"
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bitfld.long 0x00 18. "PWM0CH45CKEN,PWM0_45 Clock Enable Bit\n" "0: PWM0_45 Clock Disabled,1: PWM0_45 Clock Enabled"
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newline
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bitfld.long 0x00 17. "PWM0CH23CKEN,PWM0_23 Clock Enable Bit\n" "0: PWM0_23 Clock Disabled,1: PWM0_23 Clock Enabled"
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bitfld.long 0x00 16. "PWM0CH01CKEN,PWM0_01 Clock Enable Bit\n" "0: PWM0_01 Clock Disabled,1: PWM0_01 Clock Enabled"
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newline
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bitfld.long 0x00 8. "I2C4CKEN,I2C4 Clock Enable Bit\n" "0: I2C4 Clock Disabled,1: I2C4 Clock Enabled"
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bitfld.long 0x00 5. "SC5CKEN,SC5 Clock Enable Bit\n" "0: SC5 Clock Disabled,1: SC5 Clock Enabled"
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newline
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bitfld.long 0x00 4. "SC4CKEN,SC4 Clock Enable Bit\n" "0: SC4 Clock Disabled,1: SC4 Clock Enabled"
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bitfld.long 0x00 3. "SC3CKEN,SC3 Clock Enable Bit\n" "0: SC3 Clock Disabled,1: SC3 Clock Enabled"
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newline
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bitfld.long 0x00 2. "SC2CKEN,SC2 Clock Enable Bit\n" "0: SC2 Clock Disabled,1: SC2 Clock Enabled"
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bitfld.long 0x00 1. "SC1CKEN,SC1 Clock Enable Bit\n" "0: SC1 Clock Disabled,1: SC1 Clock Enabled"
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newline
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bitfld.long 0x00 0. "SC0CKEN,SC0 Clock Enable Bit\n" "0: SC0 Clock Disabled,1: SC0 Clock Enabled"
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group.long 0x10++0x03
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line.long 0x00 "CLK_CLKSEL0,Clock Source Select Control Register 0"
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bitfld.long 0x00 20.--21. "SDHSEL,SDHOST Engine Clock Source Selection\nThese bits are protected bit" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: Clock source from HCLK,3: Clock source from HIRC clock"
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bitfld.long 0x00 16.--17. "ICAPSEL,Image Capture Interface Clock Source Selection\nThese bits are protected bit" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: Clock source from HCLK,3: Clock source from HIRC clock"
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bitfld.long 0x00 8. "USBHSEL,USB Host Clock Source Selection (Write Protect)\nThese bits are protected bit" "0: Clock source from PLL2,1: Clock source from PLL"
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bitfld.long 0x00 6. "PCLKSEL,PCLK Clock Source Selection (Write Protect)\nThese bits are protected bit" "0: Clock source from HCLK,1: Clock source from HCLK/2"
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newline
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bitfld.long 0x00 3.--5. "STCLKSEL,Cortex-M4 SysTick Clock Source Selection (Write Protect)\n" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from HXT clock/2,3: Clock source from HCLK/2,?,?,?,7: Clock source from HIRC clock/2"
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bitfld.long 0x00 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration.." "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from PLL clock,3: Clock source from LIRC clock,4: Clock source from PLL2 clock,?,?,7: Clock source from HIRC clock"
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group.long 0x14++0x03
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line.long 0x00 "CLK_CLKSEL1,Clock Source Select Control Register 1"
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bitfld.long 0x00 30.--31. "WWDTSEL,Window Watchdog Timer Clock Source Selection\n" "0: Reserved,1: Reserved,2: Clock source from HCLK/2048 clock,3: Clock source from LIRC clock"
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bitfld.long 0x00 28.--29. "CLKOSEL,Clock Divider Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from HCLK,3: Clock source from HIRC clock"
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newline
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bitfld.long 0x00 24.--25. "UARTSEL,UART Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from PLL clock,?..."
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bitfld.long 0x00 20.--22. "TMR3SEL,TIMER3 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from PCLK,3: Clock source from external trigger,?,5: Clock source from LIRC clock,?,7: Clock source from HIRC clock"
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newline
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bitfld.long 0x00 16.--18. "TMR2SEL,TIMER2 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from PCLK,3: Clock source from external trigger,?,5: Clock source from LIRC clock,?,7: Clock source from HIRC clock"
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bitfld.long 0x00 12.--14. "TMR1SEL,TIMER1 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from PCLK,3: Clock source from external trigger,?,5: Clock source from LIRC clock,?,7: Clock source from HIRC clock"
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bitfld.long 0x00 8.--10. "TMR0SEL,TIMER0 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from PCLK,3: Clock source from external trigger,?,5: Clock source from LIRC clock,?,7: Clock source from HIRC clock"
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bitfld.long 0x00 7. "SPI3SEL,SPI3 Clock Source Selection\n" "0: Clock source from PLL clock,1: Clock source from PCLK"
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bitfld.long 0x00 6. "SPI2SEL,SPI2 Clock Source Selection\n" "0: Clock source from PLL clock,1: Clock source from PCLK"
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bitfld.long 0x00 5. "SPI1SEL,SPI1 Clock Source Selection\n" "0: Clock source from PLL clock,1: Clock source from PCLK"
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newline
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bitfld.long 0x00 4. "SPI0SEL,SPI0 Clock Source Selection\n" "0: Clock source from PLL clock,1: Clock source from PCLK"
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bitfld.long 0x00 2.--3. "EADCSEL,ADC Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: Clock source from PCLK,3: Clock source from HIRC clock"
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newline
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bitfld.long 0x00 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\nThese bits are protected bit and programming this needs to write 59h 16h 88h to address 0x4000_0100 to disable register protection" "0: Clock source from 4~24 MHz external..,1: Clock source from LXT clock,2: Clock source from HCLK/2048 clock,3: Clock source from LIRC clock"
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group.long 0x18++0x03
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line.long 0x00 "CLK_CLKSEL2,Clock Source Select Control Register 2"
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bitfld.long 0x00 20.--22. "PWM1CH45SEL,PWM1_4 And PWM1_5 Clock Source Selection\nPWM1_4 and PWM1_5 used the same Engine clock source both of them use the same prescaler" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from PCLK,3: Clock source from HIRC clock,4: Clock source from LIRC clock,?..."
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bitfld.long 0x00 16.--18. "PWM1CH23SEL,PWM1_2 And PWM1_3 Clock Source Selection\nPWM1_2 and PWM1_3 uses the same Engine clock source both of them use the same prescaler" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from PCLK,3: Clock source from HIRC clock,4: Clock source from LIRC clock,?..."
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newline
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bitfld.long 0x00 12.--14. "PWM1CH01SEL,PWM1_0 And PWM1_1 Clock Source Selection\nPWM1_0 and PWM1_1 uses the same Engine clock source both of them use the same prescaler" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from PCLK,3: Clock source from HIRC clock,4: Clock source from LIRC clock,?..."
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bitfld.long 0x00 8.--10. "PWM0CH45SEL,PWM0_4 And PWM0_5 Clock Source Selection\nPWM0_4 and PWM0_5 used the same Engine clock source both of them use the same prescaler" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from PCLK,3: Clock source from HIRC clock,4: Clock source from LIRC clock,?..."
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|
newline
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bitfld.long 0x00 4.--6. "PPWM0CH23SEL,PWM0_2 And PWM0_3 Clock Source Selection\nPWM0_2 and PWM0_3 uses the same Engine clock source both of them use the same prescaler" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from PCLK,3: Clock source from HIRC clock,4: Clock source from LIRC clock,?..."
|
|
bitfld.long 0x00 0.--2. "PWM0CH01SEL,PWM0_0 And PWM0_1 Clock Source Selection\nPWM0_0 and PWM0_1 uses the same Engine clock source both of them use the same prescaler" "0: Clock source from HXT clock,1: Clock source from LXT clock,2: Clock source from PCLK,3: Clock source from HIRC clock,4: Clock source from LIRC clock,?..."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CLK_CLKSEL3,Clock Source Select Control Register 3"
|
|
bitfld.long 0x00 18.--19. "I2S1SEL,I2S1 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: Clock source from PCLK,3: Clock source from HIRC clock"
|
|
bitfld.long 0x00 16.--17. "I2S0SEL,I2S0 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: Clock source from PCLK,3: Clock source from HIRC clock"
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|
newline
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bitfld.long 0x00 10.--11. "SC5SEL,SC5 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: PCLK,3: Clock source from HIRC clock"
|
|
bitfld.long 0x00 8.--9. "SC4SEL,SC4 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: PCLK,3: Clock source from HIRC clock"
|
|
newline
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bitfld.long 0x00 6.--7. "SC3SEL,SC3 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: PCLK,3: Clock source from HIRC clock"
|
|
bitfld.long 0x00 4.--5. "SC2SEL,SC2 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: PCLK,3: Clock source from HIRC clock"
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|
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bitfld.long 0x00 2.--3. "SC1SEL,SC1 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: PCLK,3: Clock source from HIRC clock"
|
|
bitfld.long 0x00 0.--1. "SC0SEL,SC0 Clock Source Selection\n" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: PCLK,3: Clock source from HIRC clock"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CLK_CLKDIV0,Clock Divider Number Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SDHDIV,SDHOST Clock Divide Number From SDHOST Clock Source\n"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source\n"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "UARTDIV,UART Clock Divide Number From UART Clock Source\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 4.--7. "USBHDIV,USB Host Clock Divide Number From PLL Clock\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 0.--3. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CLK_CLKDIV1,Clock Divider Number Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SC3DIV,SC3 Clock Divide Number From SC3 Clock Source\n"
|
|
hexmask.long.byte 0x00 16.--23. 1. "SC2DIV,SC2 Clock Divide Number From SC2 Clock Source\n"
|
|
newline
|
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hexmask.long.byte 0x00 8.--15. 1. "SC1DIV,SC1 Clock Divide Number From SC1 Clock Source\n"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SC0DIV,SC0 Clock Divide Number From SC0 Clock Source\n"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CLK_CLKDIV2,Clock Divider Number Register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SC5DIV,SC5 Clock Divide Number From SC5 Clock Source\n"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SC4DIV,SC4 Clock Divide Number From SC4 Clock Source\n"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CLK_CLKDIV3,Clock Divider Number Register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EMACDIV,Ethernet Clock Divide Number Form HCLK (NUC472 Only)\n"
|
|
hexmask.long.byte 0x00 8.--15. 1. "VSENSEDIV,Video Pixel Clock Divide Number From ICAP Clock Source\n"
|
|
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|
|
hexmask.long.byte 0x00 0.--7. 1. "CAPDIV,Image Capture Seneor Clock Divide Number From ICAP Clock Source\n"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CLK_PLLCTL,PLL Control Register"
|
|
bitfld.long 0x00 20. "PLLREMAP,PLL Remap Enable Bit\n" "0: PLL remap enable,1: PLL remap disable"
|
|
bitfld.long 0x00 19. "PLLSRC,PLL Source Clock Selection\n" "0: PLL source clock from HXT,1: PLL source clock from HIRC"
|
|
newline
|
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bitfld.long 0x00 18. "OE,PLL OE (FOUT Enable) Pin Control\n" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
|
|
bitfld.long 0x00 17. "BP,PLL Bypass Control\n" "0: PLL is in normal mode (default),1: PLL clock output is same as clock input.."
|
|
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|
|
bitfld.long 0x00 16. "PD,Power-Down Mode\nIf set the PDEN bit to 1 in CLK_PWRCTL register the PLL will enter Power-down mode too.\n" "0: PLL is in normal mode,1: PLL is in Power-down mode (default)"
|
|
bitfld.long 0x00 14.--15. "OUTDV,PLL Output Divider Control Pins\nRefer to the formulas below the table" "0,1,2,3"
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|
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|
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bitfld.long 0x00 9.--13. "INDIV,PLL Input Divider Control Pins\nRefer to the formulas below the table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--8. 1. "FBDIV,PLL Feedback Divider Control Pins\nRefer to the formulas below the table"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CLK_PLL2CTL,PLL2 Control Register"
|
|
bitfld.long 0x00 8. "PLL2CKEN,USB PHY 480 MHz Enable Bit\nThis bit enables USB PHY PLL (480 MHz) and user needs to care the extenal crystal is 12 MHz or 24 MHz source.\nNote: Refer to OTG_PHYCTL[8] register to set the exteranl crystal frequency HXT" "0: USB PHY PLL (480 MHz) Disabled,1: USB PHY PLL (480 MHz) Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PLL2DIV,PLL2 Divider Control\nNote: Max"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CLK_STATUS,Clock Status Monitor Register"
|
|
bitfld.long 0x00 7. "CLKSFAIL,Clock Switching Fail Flag\nNote1: This bit is updated when software switches system clock source" "0: Clock switching success,1: Clock switching failure"
|
|
bitfld.long 0x00 5. "PLL2STB,Internal PLL2 Clock Source Stable Flag\nNote: This bit is read only" "0: Internal PLL2 clock is not stable or disabled,1: Internal PLL2 clock is stable"
|
|
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|
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bitfld.long 0x00 4. "HIRCSTB,22.1184 MHz Internal High-Speed Oscillator Clock (HIRC) Clock Source Stable Flag\nNote: This bit is read only" "0: HIRC clock is not stable or disabled,1: HIRC clock is stable"
|
|
bitfld.long 0x00 3. "LIRCSTB,10 KHz Internal Low-Speed Oscillator Clock (LIRC)Source Stable Flag\nNote: This bit is read only" "0: LIRC clock is not stable or disabled,1: LIRC clock is stable"
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|
newline
|
|
bitfld.long 0x00 2. "PLLSTB,Internal PLL Clock Source Stable Flag\nNote: This bit is read only" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable"
|
|
bitfld.long 0x00 1. "LXTSTB,32.768 KHz External Low-Speed Crystal Clock(LXT) Source Stable Flag\nNote: This is read only" "0: LXT clock is not stable or disabled,1: LXT clock is stabled"
|
|
newline
|
|
bitfld.long 0x00 0. "HXTSTB,4~24 MHz External High-Speed Crystal Clock(HXT) Source Stable Flag\nNote: This bit is read only" "0: HXT clock is not stable or disabled,1: HXT clock is stable"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CLK_CLKOCTL,Frequency Divider Control Register"
|
|
bitfld.long 0x00 5. "DIV1EN,Frequency Divider 1 Enable Bit \n" "0: Divider output frequency is dependent on FSEL..,1: Divider output frequency is input clock.."
|
|
bitfld.long 0x00 4. "CLKOEN,Clock Output Enable Bit\n" "0: Clock output disabled,1: Clock output enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "FSEL,Divider Output Frequency Selection\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CLK_CLKDCTL,Clock Fail Detector Control Register"
|
|
bitfld.long 0x00 10. "IRCFIF,Internal RC Clock Fail Flag\n" "0: IRC clock normal,1: IRC abnormal (write 1 to clear)"
|
|
bitfld.long 0x00 9. "IRCFIEN,Internal RC Clock Detector Interrupt Enable Bit\n" "0: IRC clock fail interrupt disabled,1: IRC clock fail interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "IRCDEN,Internal RC Clock Detector Enable Bit\n" "0: IRC clock fail interrupt disabled,1: IRC clock fail interrupt enabled"
|
|
bitfld.long 0x00 2. "SYSFIF,System Clock Detect Fail Flag\n" "0: System clock normal,1: System clock abnormal (write 1 to clear)"
|
|
newline
|
|
bitfld.long 0x00 1. "SYSFIEN,System Clock Detector Interrupt Enable Bit\n" "0: system clock fail interrupt disabled,1: system clock fail interrupt enabled"
|
|
bitfld.long 0x00 0. "SYSFDEN,System Clock Detector Enable Bit\n" "0: system clock fail interrupt disabled,1: system clock fail interrupt enabled"
|
|
tree.end
|
|
tree "CRC"
|
|
base ad:0x40031000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRC_CTL,CRC Control Register"
|
|
bitfld.long 0x00 30.--31. "CRCMODE,CRC Polynomial Mode Selection\n" "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,2: CRC-16 Polynomial mode,3: CRC-32 Polynomial mode"
|
|
bitfld.long 0x00 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the write data length.\nNote: When the data length is 8-bit mode the valid data is DATA [7:0] if the data length is 16-bit mode the valid data is DATA [15:0]" "0: Data length is 8-bit mode,1: Data length is 16-bit mode.\nData length is..,?..."
|
|
newline
|
|
bitfld.long 0x00 27. "CHKSFMT,Checksum Complement\n" "0: No bit order reverse for CRC checksum,1: 1's complement for CRC checksum"
|
|
bitfld.long 0x00 26. "DATFMT,Write Data Complement\n" "0: No bit order reversed for CRC write data in,1: 1's complement for CRC write data in"
|
|
newline
|
|
bitfld.long 0x00 25. "CHKSREV,Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E the bit order reversed for CRC checksum is 0x74F0DEBB" "0: No bit order reverse for CRC checksum,1: Bit order reverse for CRC checksum"
|
|
bitfld.long 0x00 24. "DATREV,Write Data Order Reverse\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: No bit order reversed for CRC write data in,1: Bit order reversed for CRC write data in (per.."
|
|
newline
|
|
bitfld.long 0x00 1. "CRCRST,CRC Engine Reset\nNote: Setting this bit will reload the initial seed value" "0: No effect,1: Reset the internal CRC state machine and.."
|
|
bitfld.long 0x00 0. "CRCEN,CRC Channel Enable Bit\n" "0: CRC function Disabled,1: CRC function Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRC_DAT,CRC Write Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,CRC Write Data Bits\nSoftware can write data to this field to perform CRC operation or uses PDMA function to get the data from memory\n"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRC_SEED,CRC Seed Register"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,CRC Seed Bits\nThis field indicates the CRC seed value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRC_CHECKSUM,CRC Checksum Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHECKSUM,CRC Checksum Bits\nThis field indicates the CRC checksum"
|
|
tree.end
|
|
tree "CRYPTO"
|
|
base ad:0x50080000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRPT_INTEN,Crypto Interrupt Enable Control Register"
|
|
bitfld.long 0x00 25. "SHAERRIEN,SHA Error Interrupt Enable Bit\n" "0: SHA error interrupt flag Disabled,1: SHA error interrupt flag Enabled"
|
|
bitfld.long 0x00 24. "SHAIEN,SHA Interrupt Enable Bit\nIn DMA mode an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine" "0: SHA interrupt Disabled,1: SHA interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "PRNGIEN,PRNG Interrupt Enable Bit \n" "0: PRNG interrupt Disabled,1: PRNG interrupt Enabled"
|
|
bitfld.long 0x00 9. "TDESERRIEN,TDES/DES Error Flag Enable Bit\n" "0: TDES/DES error interrupt flag Disabled,1: TDES/DES error interrupt flag Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "TDESIEN,TDES/DES Interrupt Enable Bit\nIn DMA mode an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.\nIn Non-DMA mode an interrupt will be triggered when the TDES engine finishes the operation" "0: TDES/DES interrupt Disabled,1: TDES/DES interrupt Enabled"
|
|
bitfld.long 0x00 1. "AESERRIEN,AES Error Flag Enable Bit\n" "0: AES error interrupt flag Disabled,1: AES error interrupt flag Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "AESIEN,AES Interrupt Enable Bit\nIn DMA mode an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.\nIn Non-DMA mode an interrupt will be triggered when the AES engine finishes the operation" "0: AES interrupt Disabled,1: AES interrupt Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRPT_INTSTS,Crypto Interrupt Flag"
|
|
bitfld.long 0x00 25. "SHAERRIF,SHA Error Flag\nThis register includes operating and setting error" "0: No SHA error,1: SHA error interrupt"
|
|
bitfld.long 0x00 24. "SHAIF,SHA Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0.\n" "0: No SHA interrupt,1: SHA operation done interrupt"
|
|
newline
|
|
bitfld.long 0x00 16. "PRNGIF,PRNG Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0.\n" "0: No PRNG interrupt,1: PRNG key generation done interrupt"
|
|
bitfld.long 0x00 9. "TDESERRIF,TDES/DES Error Flag\nThis bit includes the operating and setting error" "0: No TDES/DES error,1: TDES/DES encryption/decryption error interrupt"
|
|
newline
|
|
bitfld.long 0x00 8. "TDESIF,TDES/DES Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0.\n" "0: No TDES/DES interrupt,1: TDES/DES encryption/decryption done interrupt"
|
|
bitfld.long 0x00 1. "AESERRIF,AES Error Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0.\n" "0: No AES error,1: AES encryption/decryption done interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. "AESIF,AES Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0.\n" "0: No AES interrupt,1: AES encryption/decryption done interrupt"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRPT_PRNG_CTL,PRNG Control Register"
|
|
rbitfld.long 0x00 8. "BUSY,PRNG Busy (Read Only)\n" "0: PRNG engine is idle,1: Indicate that the PRNG engine is generating.."
|
|
bitfld.long 0x00 2.--3. "KEYSZ,PRNG Generate Key Size\n" "0: 64 bits,1: 128 bits,2: 192 bits,3: 256 bits"
|
|
newline
|
|
bitfld.long 0x00 1. "SEEDRLD,Reload New Seed For PRNG Engine\n" "0: Generating key based on the current seed,1: Reload new seed"
|
|
bitfld.long 0x00 0. "START,Start PRNG Engine\n" "0: Stop PRNG engine,1: Generate new key and store the new key to.."
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRPT_PRNG_SEED,Seed for PRNG"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,Seed For PRNG (Write Only)\nThe bits store the seed for PRNG engine"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CRPT_PRNG_KEY0,PRNG Generated Key0"
|
|
hexmask.long 0x00 0.--31. 1. "KEYx,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 )
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "CRPT_PRNG_KEY$1,PRNG Generated Key $1"
|
|
hexmask.long 0x00 0.--31. 1. "KEYx,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
repeat.end
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CRPT_AES_FDBCK0,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for IV.."
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "CRPT_AES_FDBCK$1,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for IV.."
|
|
repeat.end
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "CRPT_TDES_FDBCKH,TDES/DES Engine Output Feedback High Word Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,TDES/DES Feedback\nThe feedback value is 64 bits in size.\nThe TDES/DES engine uses the data from {CRPT_TDES_FDBCKH CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH CRPT_TDESn_IVL} for the next block in DMA cascade mode"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CRPT_TDES_FDBCKL,TDES/DES Engine Output Feedback Low Word Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,TDES/DES Feedback\nThe feedback value is 64 bits in size.\nThe TDES/DES engine uses the data from {CRPT_TDES_FDBCKH CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH CRPT_TDESn_IVL} for the next block in DMA cascade mode"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CRPT_AES_CTL,AES Control Register"
|
|
bitfld.long 0x00 31. "KEYPRT,Protect Key\nRead as a flag to reflect KEYPRT.\n" "0: No effect,1: Protect the content of the AES key from reading"
|
|
bitfld.long 0x00 26.--30. "KEYUNPRT,Unprotect Key\nWriting 0 to CRPT_AES_CTL [31] and 10110 to CRPT_AES_CTL [30:26] is to unprotect the AES key.\nThe KEYUNPRT can be read and written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "CHANNEL,AES Engine Working Channel\n" "0: Current control register setting is for..,1: Current control register setting is for..,2: Current control register setting is for..,3: Current control register setting is for.."
|
|
bitfld.long 0x00 23. "INSWAP,AES Engine Input Data Swap \n" "0: Keep the original order,1: The order that CPU feeds data to the.."
|
|
newline
|
|
bitfld.long 0x00 22. "OUTSWAP,AES Engine Output Data Swap \n" "0: Keep the original order,1: The order that CPU outputs data from the.."
|
|
bitfld.long 0x00 16. "ENCRPT,AES Encryption/Decryption\n" "0: AES engine executes decryption operation,1: AES engine executes encryption operation"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "OPMODE,AES Engine Operation Modes\n"
|
|
bitfld.long 0x00 7. "DMAEN,AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode and data movement from/to the engine is done by DMA logic" "0: AES DMA engine Disabled,1: AES DMA engine Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "DMACSCAD,AES Engine DMA With Cascade Mode\n" "0: DMA cascade function Disabled,1: In DMA cascade mode software can update DMA.."
|
|
bitfld.long 0x00 5. "DMALAST,AES Last Block\nIn DMA mode this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode this bit must be set when feeding in the last block of data in ECB CBC CTR OFB and CFB mode and feeding in the (last-1) block of data at.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "KEYSZ,AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1 updating this register has no effect" "0,1,2,3"
|
|
bitfld.long 0x00 1. "STOP,AES Engine Stop\nNote: This bit is always 0 when it's read back" "0: No effect,1: Stop AES engine"
|
|
newline
|
|
bitfld.long 0x00 0. "START,AES Engine Start\nNote: This bit is always 0 when it's read back" "0: No effect,1: Start AES engine"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CRPT_AES_STS,AES Engine Flag"
|
|
bitfld.long 0x00 20. "BUSERR,AES DMA Access Bus Error Flag\n" "0: No error,1: Bus error will stop DMA operation and AES.."
|
|
bitfld.long 0x00 18. "OUTBUFERR,AES Out Buffer Error Flag\n" "0: No error,1: Error happens during getting the result from.."
|
|
newline
|
|
bitfld.long 0x00 17. "OUTBUFFULL,AES Out Buffer Full Flag\n" "0: AES output buffer is not full,1: AES output buffer is full and software needs.."
|
|
bitfld.long 0x00 16. "OUTBUFEMPTY,AES Out Buffer Empty\n" "0: AES output buffer is not empty,1: AES output buffer is empty"
|
|
newline
|
|
bitfld.long 0x00 12. "CNTERR,AES_CNT Setting Error\n" "0: No error in AES_CNT setting,1: AES_CNT is not a multiply of 16 in ECB CBC.."
|
|
bitfld.long 0x00 10. "INBUFERR,AES Input Buffer Error Flag\n" "0: No error,1: Error happens during feeding data to the AES.."
|
|
newline
|
|
bitfld.long 0x00 9. "INBUFFULL,AES Input Buffer Full Flag\n" "0: AES input buffer is not full,1: AES input buffer is full"
|
|
bitfld.long 0x00 8. "INBUFEMPTY,AES Input Buffer Empty\n" "0: There are some data in input buffer waiting..,1: AES input buffer is empty"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSY,AES Engine Busy\n" "0: The AES engine is idle or finished,1: The AES engine is under processing"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CRPT_AES_DATIN,AES Engine Data Input Port Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATIN,AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRPT_AES_STS"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "CRPT_AES_DATOUT,AES Engine Data Output Port Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATOUT,AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRPT_AES_STS"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CRPT_AES0_KEY0,AES Key Word 0 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CRPT_AES0_KEY1,AES Key Word 1 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CRPT_AES0_KEY2,AES Key Word 2 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CRPT_AES0_KEY3,AES Key Word 3 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CRPT_AES0_KEY4,AES Key Word 4 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CRPT_AES0_KEY5,AES Key Word 5 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CRPT_AES0_KEY6,AES Key Word 6 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CRPT_AES0_KEY7,AES Key Word 7 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CRPT_AES0_IV0,AES Initial Vector Word 0 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CRPT_AES0_IV1,AES Initial Vector Word 1 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CRPT_AES0_IV2,AES Initial Vector Word 2 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CRPT_AES0_IV3,AES Initial Vector Word 3 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CRPT_AES0_SADDR,AES DMA Source Address Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CRPT_AES0_DADDR,AES DMA Destination Address Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CRPT_AES0_CNT,AES Byte Count Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "CRPT_AES1_KEY0,AES Key Word 0 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CRPT_AES1_KEY1,AES Key Word 1 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CRPT_AES1_KEY2,AES Key Word 2 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CRPT_AES1_KEY3,AES Key Word 3 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CRPT_AES1_KEY4,AES Key Word 4 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CRPT_AES1_KEY5,AES Key Word 5 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CRPT_AES1_KEY6,AES Key Word 6 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CRPT_AES1_KEY7,AES Key Word 7 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CRPT_AES1_IV0,AES Initial Vector Word 0 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CRPT_AES1_IV1,AES Initial Vector Word 1 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CRPT_AES1_IV2,AES Initial Vector Word 2 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "CRPT_AES1_IV3,AES Initial Vector Word 3 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "CRPT_AES1_SADDR,AES DMA Source Address Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CRPT_AES1_DADDR,AES DMA Destination Address Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "CRPT_AES1_CNT,AES Byte Count Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "CRPT_AES2_KEY0,AES Key Word 0 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CRPT_AES2_KEY1,AES Key Word 1 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CRPT_AES2_KEY2,AES Key Word 2 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "CRPT_AES2_KEY3,AES Key Word 3 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CRPT_AES2_KEY4,AES Key Word 4 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "CRPT_AES2_KEY5,AES Key Word 5 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CRPT_AES2_KEY6,AES Key Word 6 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CRPT_AES2_KEY7,AES Key Word 7 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "CRPT_AES2_IV0,AES Initial Vector Word 0 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "CRPT_AES2_IV1,AES Initial Vector Word 1 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CRPT_AES2_IV2,AES Initial Vector Word 2 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "CRPT_AES2_IV3,AES Initial Vector Word 3 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "CRPT_AES2_SADDR,AES DMA Source Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CRPT_AES2_DADDR,AES DMA Destination Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CRPT_AES2_CNT,AES Byte Count Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CRPT_AES3_KEY0,AES Key Word 0 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "CRPT_AES3_KEY1,AES Key Word 1 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "CRPT_AES3_KEY2,AES Key Word 2 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "CRPT_AES3_KEY3,AES Key Word 3 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "CRPT_AES3_KEY4,AES Key Word 4 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "CRPT_AES3_KEY5,AES Key Word 5 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "CRPT_AES3_KEY6,AES Key Word 6 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "CRPT_AES3_KEY7,AES Key Word 7 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "CRPT_AES3_IV0,AES Initial Vector Word 0 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "CRPT_AES3_IV1,AES Initial Vector Word 1 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "CRPT_AES3_IV2,AES Initial Vector Word 2 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "CRPT_AES3_IV3,AES Initial Vector Word 3 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0 CRPT_AESn_IV1 CRPT_AESn_IV2 and CRPT_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "CRPT_AES3_SADDR,AES DMA Source Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "CRPT_AES3_DADDR,AES DMA Destination Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "CRPT_AES3_CNT,AES Byte Count Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CRPT_TDES_CTL,TDES/DES Control Register"
|
|
bitfld.long 0x00 31. "KEYPRT,Protect Key\nRead as a flag to reflect KEYPRT.\n" "0: No effect,1: This bit is to protect the content of TDES.."
|
|
bitfld.long 0x00 26.--30. "KEYUNPRT,Unprotect Key\nWriting 0 to CRPT_TDES_CTL [31] and 10110 to CRPT_TDES_CTL [30:26] is to unprotect TDES key.\nThe KEYUNPRT can be read and written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
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bitfld.long 0x00 24.--25. "CHANNEL,TDES/DES Engine Working Channel\n" "0: Current control register setting is for..,1: Current control register setting is for..,2: Current control register setting is for..,3: Current control register setting is for.."
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|
bitfld.long 0x00 23. "INSWAP,TDES/DES Engine Input Data Swap \n" "0: Keep the original order,1: The order that CPU feeds data to the.."
|
|
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bitfld.long 0x00 22. "OUTSWAP,TDES/DES Engine Output Data Swap \n" "0: Keep the original order,1: The order that CPU outputs data from the.."
|
|
bitfld.long 0x00 21. "BLKSWAP,TDES/DES Engine Block Double Word Endian Swap \n" "0: Keep the original order e.g,1: When this bit is set to 1 the TDES engine.."
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|
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bitfld.long 0x00 16. "ENCRPT,TDES/DES Encryption/Decryption\n" "0: TDES engine executes decryption operation,1: TDES engine executes encryption operation"
|
|
bitfld.long 0x00 8.--10. "OPMODE,TDES/DES Engine Operation Mode\n" "0: ECB (Electronic Codebook Mode),1: CBC (Cipher Block Chaining Mode),2: CFB (Cipher Feedback Mode),3: OFB (Output Feedback Mode),4: CTR (Counter Mode),?..."
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|
newline
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bitfld.long 0x00 7. "DMAEN,TDES/DES Engine DMA Enable Bit\nTDES engine operates in DMA mode and data movement from/to the engine is done by DMA logic" "0: TDES_DMA engine Disabled,1: TDES_DMA engine Enabled"
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|
bitfld.long 0x00 6. "DMACSCAD,TDES/DES Engine DMA With Cascade Mode\n" "0: DMA cascade function Disabled,1: In DMA Cascade mode software can update DMA.."
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|
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bitfld.long 0x00 5. "DMALAST,TDES/DES Engine Start For The Last Block \nIn DMA mode this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode this bit must be set as feeding in last block of data" "0,1"
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|
bitfld.long 0x00 3. "_3KEYS,TDES/DES Key Number\n" "0: Select KEY1 and KEY2 in TDES/DES engine,1: Triple keys in TDES/DES engine Enabled"
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|
newline
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bitfld.long 0x00 2. "TMODE,TDES/DES Engine Operating Mode\n" "0: Set DES mode for TDES/DES engine,1: Set Triple DES mode for TDES/DES engine"
|
|
bitfld.long 0x00 1. "STOP,TDES/DES Engine Stop\nNote: The bit is always 0 when it's read back" "0: No effect,1: Stop TDES/DES engine"
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|
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bitfld.long 0x00 0. "START,TDES/DES Engine Start\nNote: The bit is always 0 when it's read back" "0: No effect,1: Start TDES/DES engine"
|
|
rgroup.long 0x204++0x03
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|
line.long 0x00 "CRPT_TDES_STS,TDES/DES Engine Flag"
|
|
bitfld.long 0x00 20. "BUSERR,TDES/DES DMA Access Bus Error Flag\n" "0: No error,1: Bus error will stop DMA operation and.."
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|
bitfld.long 0x00 18. "OUTBUFERR,TDES/DES Out Buffer Error Flag\n" "0: No error,1: Error happens during getting test result from.."
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|
newline
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bitfld.long 0x00 17. "OUTBUFFULL,TDES/DES Output Buffer Full Flag\n" "0: TDES/DES output buffer is not full,1: TDES/DES output buffer is full and software.."
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|
bitfld.long 0x00 16. "OUTBUFEMPTY,TDES/DES Output Buffer Empty Flag\n" "0: TDES/DES output buffer is not empty,1: TDES/DES output buffer is empty Software.."
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|
newline
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bitfld.long 0x00 10. "INBUFERR,TDES/DES In Buffer Error Flag\n" "0: No error,1: Error happens during feeding data to the.."
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bitfld.long 0x00 9. "INBUFFULL,TDES/DES In Buffer Full Flag\n" "0: TDES/DES input buffer is not full,1: TDES input buffer is full"
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|
newline
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bitfld.long 0x00 8. "INBUFEMPTY,TDES/DES In Buffer Empty\n" "0: There are some data in input buffer waiting..,1: TDES/DES input buffer is empty"
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bitfld.long 0x00 0. "BUSY,TDES/DES Engine Busy \n" "0: TDES/DES engine is idle or finished,1: TDES/DES engine is under processing"
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|
group.long 0x208++0x03
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line.long 0x00 "CRPT_TDES0_KEY1H,TDES/DES Key 1 High Word Register for Channel 0"
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|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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|
group.long 0x20C++0x03
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line.long 0x00 "CRPT_TDES0_KEY1L,TDES/DES Key 1 Low Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x210++0x03
|
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line.long 0x00 "CRPT_TDES0_KEY2H,TDES Key 2 High Word Register for Channel 0"
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|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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group.long 0x214++0x03
|
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line.long 0x00 "CRPT_TDES0_KEY2L,TDES Key 2 Low Word Register for Channel 0"
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|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x218++0x03
|
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line.long 0x00 "CRPT_TDES0_KEY3H,TDES Key 3 High Word Register for Channel 0"
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|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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group.long 0x21C++0x03
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line.long 0x00 "CRPT_TDES0_KEY3L,TDES Key 3 Low Word Register for Channel 0"
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|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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group.long 0x220++0x03
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line.long 0x00 "CRPT_TDES0_IVH,TDES/DES Initial Vector High Word Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "IVH_IVL,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
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group.long 0x224++0x03
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line.long 0x00 "CRPT_TDES0_IVL,TDES/DES Initial Vector Low Word Register for Channel 0"
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|
hexmask.long 0x00 0.--31. 1. "IVH_IVL,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
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group.long 0x228++0x03
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line.long 0x00 "CRPT_TDES0_SADDR,TDES/DES DMA Source Address Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO"
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group.long 0x22C++0x03
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line.long 0x00 "CRPT_TDES0_DADDR,TDES/DES DMA Destination Address Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO"
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group.long 0x230++0x03
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line.long 0x00 "CRPT_TDES0_CNT,TDES/DES Byte Count Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
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group.long 0x234++0x03
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line.long 0x00 "CRPT_TDES_DATIN,TDES/DES Engine Input Data Word Register"
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hexmask.long 0x00 0.--31. 1. "DATIN,TDES/DES Engine Input Port\nCPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS"
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rgroup.long 0x238++0x03
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line.long 0x00 "CRPT_TDES_DATOUT,TDES/DES Engine Output Data Word Register"
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hexmask.long 0x00 0.--31. 1. "DATOUT,TDES/DES Engine Output Port\nCPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS"
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group.long 0x248++0x03
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line.long 0x00 "CRPT_TDES1_KEY1H,TDES/DES Key 1 High Word Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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group.long 0x24C++0x03
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line.long 0x00 "CRPT_TDES1_KEY1L,TDES/DES Key 1 Low Word Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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group.long 0x250++0x03
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line.long 0x00 "CRPT_TDES1_KEY2H,TDES Key 2 High Word Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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group.long 0x254++0x03
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line.long 0x00 "CRPT_TDES1_KEY2L,TDES Key 2 Low Word Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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group.long 0x258++0x03
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line.long 0x00 "CRPT_TDES1_KEY3H,TDES Key 3 High Word Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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group.long 0x25C++0x03
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line.long 0x00 "CRPT_TDES1_KEY3L,TDES Key 3 Low Word Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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group.long 0x260++0x03
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line.long 0x00 "CRPT_TDES1_IVH,TDES/DES Initial Vector High Word Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "IVH_IVL,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
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group.long 0x264++0x03
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line.long 0x00 "CRPT_TDES1_IVL,TDES/DES Initial Vector Low Word Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "IVH_IVL,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
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group.long 0x268++0x03
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line.long 0x00 "CRPT_TDES1_SADDR,TDES/DES DMA Source Address Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO"
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group.long 0x26C++0x03
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line.long 0x00 "CRPT_TDES1_DADDR,TDES/DES DMA Destination Address Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO"
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group.long 0x270++0x03
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line.long 0x00 "CRPT_TDES1_CNT,TDES/DES Byte Count Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
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group.long 0x288++0x03
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line.long 0x00 "CRPT_TDES2_KEY1H,TDES/DES Key 1 High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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group.long 0x28C++0x03
|
|
line.long 0x00 "CRPT_TDES2_KEY1L,TDES/DES Key 1 Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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group.long 0x290++0x03
|
|
line.long 0x00 "CRPT_TDES2_KEY2H,TDES Key 2 High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "CRPT_TDES2_KEY2L,TDES Key 2 Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
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|
group.long 0x298++0x03
|
|
line.long 0x00 "CRPT_TDES2_KEY3H,TDES Key 3 High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "CRPT_TDES2_KEY3L,TDES Key 3 Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "CRPT_TDES2_IVH,TDES/DES Initial Vector High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IVH_IVL,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "CRPT_TDES2_IVL,TDES/DES Initial Vector Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IVH_IVL,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "CRPT_TDES2_SADDR,TDES/DES DMA Source Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "CRPT_TDES2_DADDR,TDES/DES DMA Destination Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "CRPT_TDES2_CNT,TDES/DES Byte Count Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "CRPT_TDES3_KEY1H,TDES/DES Key 1 High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "CRPT_TDES3_KEY1L,TDES/DES Key 1 Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "CRPT_TDES3_KEY2H,TDES Key 2 High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "CRPT_TDES3_KEY2L,TDES Key 2 Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "CRPT_TDES3_KEY3H,TDES Key 3 High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "CRPT_TDES3_KEY3L,TDES Key 3 Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEYH_KEYL,TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "CRPT_TDES3_IVH,TDES/DES Initial Vector High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IVH_IVL,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "CRPT_TDES3_IVL,TDES/DES Initial Vector Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IVH_IVL,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "CRPT_TDES3_SADDR,TDES/DES DMA Source Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "CRPT_TDES3_DADDR,TDES/DES DMA Destination Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "CRPT_TDES3_CNT,TDES/DES Byte Count Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "CRPT_SHA_CTL,SHA Control Register"
|
|
bitfld.long 0x00 23. "INSWAP,SHA Engine Input Data Swap\n" "0: Keep the original order,1: The order that CPU feeds data to the.."
|
|
bitfld.long 0x00 22. "OUTSWAP,SHA Engine Output Data Swap\n" "0: Keep the original order,1: The order that CPU feeds data to the.."
|
|
newline
|
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bitfld.long 0x00 8.--10. "OPMODE,SHA Engine Operation Modes\nNote: These bits can be read and written but writing to them wouldn't take effect as BUSY is 1" "0: SHA160,?,?,?,4: SHA256,5: SHA224,?..."
|
|
bitfld.long 0x00 7. "DMAEN,SHA Engine DMA Enable Bit\nThe SHA engine operates in DMA mode and data movement from/to the engine is done by DMA logic" "0: SHA_DMA engine Disabled,1: SHA_DMA engine Enabled"
|
|
newline
|
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bitfld.long 0x00 5. "DMALAST,SHA Last Block\nIn DMA mode this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode this bit must be set as feeding in last byte of data" "0,1"
|
|
bitfld.long 0x00 1. "STOP,SHA Engine Stop\nNote: This bit is always 0 when it's read back" "0: No effect,1: Stop SHA engine"
|
|
newline
|
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bitfld.long 0x00 0. "START,SHA Engine Start\nNote: This bit is always 0 when it's read back" "0: No effect,1: Start SHA engine"
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "CRPT_SHA_STS,SHA Status Flag"
|
|
bitfld.long 0x00 16. "DATINREQ,SHA Non-DMA Mode Data Input Request\n" "0: No effect,1: Request SHA Non-DMA mode data input"
|
|
bitfld.long 0x00 8. "DMAERR,SHA Engine DMA Error Flag\n" "0: Show the SHA engine access normal,1: Show the SHA engine access error"
|
|
newline
|
|
bitfld.long 0x00 1. "DMABUSY,SHA Engine DMA Busy Flag\n" "0: SHA DMA engine is idle or finished,1: SHA DMA engine is busy"
|
|
bitfld.long 0x00 0. "BUSY,SHA Engine Busy \n" "0: SHA engine is idle or finished,1: SHA engine is busy"
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "CRPT_SHA_DGST0,SHA Digest Message 0"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Word\nFor SHA-160 the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.\nFor SHA-224 the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.\nFor SHA-256 the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7"
|
|
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
|
|
group.long ($2+0x30C)++0x03
|
|
line.long 0x00 "CRPT_SHA_DGST$1,SHA Digest Message $1"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Word\nFor SHA-160 the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.\nFor SHA-224 the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.\nFor SHA-256 the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7"
|
|
repeat.end
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "CRPT_SHA_KEYCNT,SHA Key Byte Count Register"
|
|
hexmask.long 0x00 0.--31. 1. "KEYCNT,SHA Key Byte Count\nThe CRPT_SHA_KEYCNT keeps the byte count of key that SHA engine operates"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "CRPT_SHA_SADDR,SHA DMA Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,SHA DMA Source Address\nThe SHA accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "CRPT_SHA_DMACNT,SHA Byte Count Register"
|
|
hexmask.long 0x00 0.--31. 1. "DMACNT,SHA Operation Byte Count\nThe CRPT_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "CRPT_SHA_DATIN,SHA Engine Non-dMA Mode Data Input Port Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATIN,SHA Engine Input Port\nCPU feeds data to SHA engine through this port by checking CRPT_SHA_STS"
|
|
tree.end
|
|
tree "EADC"
|
|
base ad:0x40044000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "EADC_AD0DAT0,A/D Data Register 0 for SAMPLE00"
|
|
bitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
bitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EADC_AD0DAT1,A/D Data Register 1 for SAMPLE01"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EADC_AD0DAT2,A/D Data Register 2 for SAMPLE02"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EADC_AD0DAT3,A/D Data Register 3 for SAMPLE03"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "EADC_AD0DAT4,A/D Data Register 4 for SAMPLE04"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EADC_AD0DAT5,A/D Data Register 5 for SAMPLE05"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "EADC_AD0DAT6,A/D Data Register 6 for SAMPLE06"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EADC_AD0DAT7,A/D Data Register 7 for SAMPLE07"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EADC_AD1DAT0,A/D Data Register 8 for SAMPLE10"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "EADC_AD1DAT1,A/D Data Register 9 for SAMPLE11"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "EADC_AD1DAT2,A/D Data Register 10 for SAMPLE12"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "EADC_AD1DAT3,A/D Data Register 11 for SAMPLE13"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "EADC_AD1DAT4,A/D Data Register 12 for SAMPLE14"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EADC_AD1DAT5,A/D Data Register 13 for SAMPLE15"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "EADC_AD1DAT6,A/D Data Register 14 for SAMPLE16"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "EADC_AD1DAT7,A/D Data Register 15 for SAMPLE17"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is not..,1: Data in RESULT (EADC_ADnDATx[11:0]) is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\n" "0: Data in RESULT (EADC_ADnDATx[11:0]) is recent..,1: Data in RESULT (EADC_ADnDATx[11:0]) is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "EADC_CTL,A/D Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SWTRG15_8,A/D SAMPLE17~SAMPLE10 Software Force To Start ADC Conversion\n"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SWTRG7_0,A/D SAMPLE07~SAMPLE00 Software Force To Start ADC Conversion\n"
|
|
wgroup.long 0x48++0x03
|
|
line.long 0x00 "EADC_SWTRG,A/D SAMPLE Module Software Start Register"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "EADC_PENDSTS,A/D Start of Conversion Pending Flag Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "STPF15_8,A/D SAMPLE17~SAMPLE10 Start Of Conversion Pending Flag \n"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STPF7_0,A/D SAMPLE07~SAMPLE00 Start Of Conversion Pending Flag\n"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "EADC_ADIFOV,A/D ADINT3~0 Interrupt Flag Overrun Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SPOVF15_8,A/D SAMPLE17~SAMPLE10 Start Of Conversion Overrun Flag\n"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SPOVF7_0,A/D SAMPLE07~SAMPLE00 Start Of Conversion Overrun Flag\n"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "EADC_OVSTS,A/D SAMPLE Module Start of Conversion Overrun Flag Register"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "EADC_AD0SPCTL0,A/D SAMPLE00 Control Register"
|
|
bitfld.long 0x00 21. "EXTFEN,A/D External Pin Falling Edge Trigger Enable Bit\n" "0: A/D external pin falling edge trigger Disabled,1: A/D external pin falling edge trigger Enabled"
|
|
bitfld.long 0x00 20. "EXTREN,A/D External Pin Rising Edge Trigger Enable Bit\n" "0: A/D external pin rising edge trigger Disabled,1: A/D external pin rising edge trigger Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Time\n"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE MODULE Start Of Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External pin (STADC) trigger,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: EPWM0_CH0 trigger,9: EPWM0_CH2 trigger,10: EPWM0_CH4 trigger,11: EPWM1_CH0 trigger,12: EPWM1_CH2 trigger,13: EPWM1_CH4 trigger,14: PWM0_CH0 trigger,15: PWM0_CH1 trigger"
|
|
bitfld.long 0x00 0.--3. "CHSEL,A/D SAMPLE MODULE 0 1 Channel Selection\n" "0: ADCn_CH0,1: ADCn_CH1,2: ADCn_CH2,3: ADCn_CH3,4: ADCn_CH4,5: ADCn_CH5,6: ADCn_CH6,7: ADCn_CH7,8: VBG.\nOP1,9: VTEMP,10: AVSS,11: OP0,?..."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "EADC_AD0SPCTL1,A/D SAMPLE01 Control Register"
|
|
bitfld.long 0x00 21. "EXTFEN,A/D External Pin Falling Edge Trigger Enable Bit\n" "0: A/D external pin falling edge trigger Disabled,1: A/D external pin falling edge trigger Enabled"
|
|
bitfld.long 0x00 20. "EXTREN,A/D External Pin Rising Edge Trigger Enable Bit\n" "0: A/D external pin rising edge trigger Disabled,1: A/D external pin rising edge trigger Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Time\n"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE MODULE Start Of Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External pin (STADC) trigger,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: EPWM0_CH0 trigger,9: EPWM0_CH2 trigger,10: EPWM0_CH4 trigger,11: EPWM1_CH0 trigger,12: EPWM1_CH2 trigger,13: EPWM1_CH4 trigger,14: PWM0_CH0 trigger,15: PWM0_CH1 trigger"
|
|
bitfld.long 0x00 0.--3. "CHSEL,A/D SAMPLE MODULE 0 1 Channel Selection\n" "0: ADCn_CH0,1: ADCn_CH1,2: ADCn_CH2,3: ADCn_CH3,4: ADCn_CH4,5: ADCn_CH5,6: ADCn_CH6,7: ADCn_CH7,8: VBG.\nOP1,9: VTEMP,10: AVSS,11: OP0,?..."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "EADC_AD0SPCTL2,A/D SAMPLE02 Control Register"
|
|
bitfld.long 0x00 21. "EXTFEN,A/D External Pin Falling Edge Trigger Enable Bit\n" "0: A/D external pin falling edge trigger Disabled,1: A/D external pin falling edge trigger Enabled"
|
|
bitfld.long 0x00 20. "EXTREN,A/D External Pin Rising Edge Trigger Enable Bit\n" "0: A/D external pin rising edge trigger Disabled,1: A/D external pin rising edge trigger Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Time\n"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE MODULE Start Of Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External pin (STADC) trigger,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: EPWM0_CH0 trigger,9: EPWM0_CH2 trigger,10: EPWM0_CH4 trigger,11: EPWM1_CH0 trigger,12: EPWM1_CH2 trigger,13: EPWM1_CH4 trigger,14: PWM0_CH0 trigger,15: PWM0_CH1 trigger"
|
|
bitfld.long 0x00 0.--3. "CHSEL,A/D SAMPLE MODULE 0 1 Channel Selection\n" "0: ADCn_CH0,1: ADCn_CH1,2: ADCn_CH2,3: ADCn_CH3,4: ADCn_CH4,5: ADCn_CH5,6: ADCn_CH6,7: ADCn_CH7,8: VBG.\nOP1,9: VTEMP,10: AVSS,11: OP0,?..."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "EADC_AD0SPCTL3,A/D SAMPLE03 Control Register"
|
|
bitfld.long 0x00 21. "EXTFEN,A/D External Pin Falling Edge Trigger Enable Bit\n" "0: A/D external pin falling edge trigger Disabled,1: A/D external pin falling edge trigger Enabled"
|
|
bitfld.long 0x00 20. "EXTREN,A/D External Pin Rising Edge Trigger Enable Bit\n" "0: A/D external pin rising edge trigger Disabled,1: A/D external pin rising edge trigger Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Time\n"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE MODULE Start Of Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External pin (STADC) trigger,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: EPWM0_CH0 trigger,9: EPWM0_CH2 trigger,10: EPWM0_CH4 trigger,11: EPWM1_CH0 trigger,12: EPWM1_CH2 trigger,13: EPWM1_CH4 trigger,14: PWM0_CH0 trigger,15: PWM0_CH1 trigger"
|
|
bitfld.long 0x00 0.--3. "CHSEL,A/D SAMPLE MODULE 0 1 Channel Selection\n" "0: ADCn_CH0,1: ADCn_CH1,2: ADCn_CH2,3: ADCn_CH3,4: ADCn_CH4,5: ADCn_CH5,6: ADCn_CH6,7: ADCn_CH7,8: VBG.\nOP1,9: VTEMP,10: AVSS,11: OP0,?..."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "EADC_AD0SPCTL4,A/D SAMPLE04 Control Register"
|
|
bitfld.long 0x00 7. "SIMUSEL7,A/D SAMPLE07 SAMPLE17 Simultaneous Sampling Mode Selection \n" "0: SAMPLE07 SAMPLE17 are in single sampling mode..,1: SAMPLE07 SAMPLE17 are in simultaneous.."
|
|
bitfld.long 0x00 6. "SIMUSEL6,A/D SAMPLE06 SAMPLE16 Simultaneous Sampling Mode Selection\n" "0: SAMPLE06 SAMPLE16 are in single sampling mode..,1: SAMPLE06 SAMPLE16 are in simultaneous.."
|
|
newline
|
|
bitfld.long 0x00 5. "SIMUSEL5,A/D SAMPLE05 SAMPLE15 Simultaneous Sampling Mode Selection\n" "0: SAMPLE05 SAMPLE15 are in single sampling mode..,1: SAMPLE05 SAMPLE15 are in simultaneous.."
|
|
bitfld.long 0x00 4. "SIMUSEL4,A/D SAMPLE04 SAMPLE14 Simultaneous Sampling Mode Selection\n" "0: SAMPLE04 SAMPLE14 are in single sampling mode..,1: SAMPLE04 SAMPLE14 are in simultaneous.."
|
|
newline
|
|
bitfld.long 0x00 3. "SIMUSEL3,A/D SAMPLE03 SAMPLE13 Simultaneous Sampling Mode Selection\n" "0: SAMPLE03 SAMPLE13 are in single sampling mode..,1: SAMPLE03 SAMPLE13 are in simultaneous.."
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bitfld.long 0x00 2. "SIMUSEL2,A/D SAMPLE02 SAMPLE12 Simultaneous Sampling Mode Selection\n" "0: SAMPLE02 SAMPLE12 are in single sampling mode..,1: SAMPLE02 SAMPLE12 are in simultaneous.."
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newline
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bitfld.long 0x00 1. "SIMUSEL1,A/D SAMPLE01 SAMPLE11 Simultaneous Sampling Mode Selection\n" "0: SAMPLE01 SAMPLE11 are in single sampling mode..,1: SAMPLE01 SAMPLE11 are in simultaneous.."
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bitfld.long 0x00 0. "SIMUSEL0,A/D SAMPLE00 SAMPLE10 Simultaneous Sampling Mode Selection\n" "0: SAMPLE00 SAMPLE10 are in single sampling mode..,1: SAMPLE00 SAMPLE10 are in simultaneous.."
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group.long 0x6C++0x03
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line.long 0x00 "EADC_AD0SPCTL5,A/D SAMPLE05 Control Register"
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bitfld.long 0x00 7. "SIMUSEL7,A/D SAMPLE07 SAMPLE17 Simultaneous Sampling Mode Selection \n" "0: SAMPLE07 SAMPLE17 are in single sampling mode..,1: SAMPLE07 SAMPLE17 are in simultaneous.."
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bitfld.long 0x00 6. "SIMUSEL6,A/D SAMPLE06 SAMPLE16 Simultaneous Sampling Mode Selection\n" "0: SAMPLE06 SAMPLE16 are in single sampling mode..,1: SAMPLE06 SAMPLE16 are in simultaneous.."
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bitfld.long 0x00 5. "SIMUSEL5,A/D SAMPLE05 SAMPLE15 Simultaneous Sampling Mode Selection\n" "0: SAMPLE05 SAMPLE15 are in single sampling mode..,1: SAMPLE05 SAMPLE15 are in simultaneous.."
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bitfld.long 0x00 4. "SIMUSEL4,A/D SAMPLE04 SAMPLE14 Simultaneous Sampling Mode Selection\n" "0: SAMPLE04 SAMPLE14 are in single sampling mode..,1: SAMPLE04 SAMPLE14 are in simultaneous.."
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bitfld.long 0x00 3. "SIMUSEL3,A/D SAMPLE03 SAMPLE13 Simultaneous Sampling Mode Selection\n" "0: SAMPLE03 SAMPLE13 are in single sampling mode..,1: SAMPLE03 SAMPLE13 are in simultaneous.."
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bitfld.long 0x00 2. "SIMUSEL2,A/D SAMPLE02 SAMPLE12 Simultaneous Sampling Mode Selection\n" "0: SAMPLE02 SAMPLE12 are in single sampling mode..,1: SAMPLE02 SAMPLE12 are in simultaneous.."
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newline
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bitfld.long 0x00 1. "SIMUSEL1,A/D SAMPLE01 SAMPLE11 Simultaneous Sampling Mode Selection\n" "0: SAMPLE01 SAMPLE11 are in single sampling mode..,1: SAMPLE01 SAMPLE11 are in simultaneous.."
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bitfld.long 0x00 0. "SIMUSEL0,A/D SAMPLE00 SAMPLE10 Simultaneous Sampling Mode Selection\n" "0: SAMPLE00 SAMPLE10 are in single sampling mode..,1: SAMPLE00 SAMPLE10 are in simultaneous.."
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group.long 0x70++0x03
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line.long 0x00 "EADC_AD0SPCTL6,A/D SAMPLE06 Control Register"
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bitfld.long 0x00 7. "SIMUSEL7,A/D SAMPLE07 SAMPLE17 Simultaneous Sampling Mode Selection \n" "0: SAMPLE07 SAMPLE17 are in single sampling mode..,1: SAMPLE07 SAMPLE17 are in simultaneous.."
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bitfld.long 0x00 6. "SIMUSEL6,A/D SAMPLE06 SAMPLE16 Simultaneous Sampling Mode Selection\n" "0: SAMPLE06 SAMPLE16 are in single sampling mode..,1: SAMPLE06 SAMPLE16 are in simultaneous.."
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bitfld.long 0x00 5. "SIMUSEL5,A/D SAMPLE05 SAMPLE15 Simultaneous Sampling Mode Selection\n" "0: SAMPLE05 SAMPLE15 are in single sampling mode..,1: SAMPLE05 SAMPLE15 are in simultaneous.."
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bitfld.long 0x00 4. "SIMUSEL4,A/D SAMPLE04 SAMPLE14 Simultaneous Sampling Mode Selection\n" "0: SAMPLE04 SAMPLE14 are in single sampling mode..,1: SAMPLE04 SAMPLE14 are in simultaneous.."
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newline
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bitfld.long 0x00 3. "SIMUSEL3,A/D SAMPLE03 SAMPLE13 Simultaneous Sampling Mode Selection\n" "0: SAMPLE03 SAMPLE13 are in single sampling mode..,1: SAMPLE03 SAMPLE13 are in simultaneous.."
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bitfld.long 0x00 2. "SIMUSEL2,A/D SAMPLE02 SAMPLE12 Simultaneous Sampling Mode Selection\n" "0: SAMPLE02 SAMPLE12 are in single sampling mode..,1: SAMPLE02 SAMPLE12 are in simultaneous.."
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newline
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bitfld.long 0x00 1. "SIMUSEL1,A/D SAMPLE01 SAMPLE11 Simultaneous Sampling Mode Selection\n" "0: SAMPLE01 SAMPLE11 are in single sampling mode..,1: SAMPLE01 SAMPLE11 are in simultaneous.."
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bitfld.long 0x00 0. "SIMUSEL0,A/D SAMPLE00 SAMPLE10 Simultaneous Sampling Mode Selection\n" "0: SAMPLE00 SAMPLE10 are in single sampling mode..,1: SAMPLE00 SAMPLE10 are in simultaneous.."
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group.long 0x74++0x03
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line.long 0x00 "EADC_AD0SPCTL7,A/D SAMPLE07 Control Register"
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bitfld.long 0x00 7. "SIMUSEL7,A/D SAMPLE07 SAMPLE17 Simultaneous Sampling Mode Selection \n" "0: SAMPLE07 SAMPLE17 are in single sampling mode..,1: SAMPLE07 SAMPLE17 are in simultaneous.."
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bitfld.long 0x00 6. "SIMUSEL6,A/D SAMPLE06 SAMPLE16 Simultaneous Sampling Mode Selection\n" "0: SAMPLE06 SAMPLE16 are in single sampling mode..,1: SAMPLE06 SAMPLE16 are in simultaneous.."
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newline
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bitfld.long 0x00 5. "SIMUSEL5,A/D SAMPLE05 SAMPLE15 Simultaneous Sampling Mode Selection\n" "0: SAMPLE05 SAMPLE15 are in single sampling mode..,1: SAMPLE05 SAMPLE15 are in simultaneous.."
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bitfld.long 0x00 4. "SIMUSEL4,A/D SAMPLE04 SAMPLE14 Simultaneous Sampling Mode Selection\n" "0: SAMPLE04 SAMPLE14 are in single sampling mode..,1: SAMPLE04 SAMPLE14 are in simultaneous.."
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bitfld.long 0x00 3. "SIMUSEL3,A/D SAMPLE03 SAMPLE13 Simultaneous Sampling Mode Selection\n" "0: SAMPLE03 SAMPLE13 are in single sampling mode..,1: SAMPLE03 SAMPLE13 are in simultaneous.."
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bitfld.long 0x00 2. "SIMUSEL2,A/D SAMPLE02 SAMPLE12 Simultaneous Sampling Mode Selection\n" "0: SAMPLE02 SAMPLE12 are in single sampling mode..,1: SAMPLE02 SAMPLE12 are in simultaneous.."
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newline
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bitfld.long 0x00 1. "SIMUSEL1,A/D SAMPLE01 SAMPLE11 Simultaneous Sampling Mode Selection\n" "0: SAMPLE01 SAMPLE11 are in single sampling mode..,1: SAMPLE01 SAMPLE11 are in simultaneous.."
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bitfld.long 0x00 0. "SIMUSEL0,A/D SAMPLE00 SAMPLE10 Simultaneous Sampling Mode Selection\n" "0: SAMPLE00 SAMPLE10 are in single sampling mode..,1: SAMPLE00 SAMPLE10 are in simultaneous.."
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group.long 0x78++0x03
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line.long 0x00 "EADC_AD1SPCTL0,A/D SAMPLE10 Control Register"
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bitfld.long 0x00 21. "EXTFEN,A/D External Pin Falling Edge Trigger Enable Bit\n" "0: A/D external pin falling edge trigger Disabled,1: A/D external pin falling edge trigger Enabled"
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bitfld.long 0x00 20. "EXTREN,A/D External Pin Rising Edge Trigger Enable Bit\n" "0: A/D external pin rising edge trigger Disabled,1: A/D external pin rising edge trigger Enabled"
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newline
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Time\n"
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newline
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE MODULE Start Of Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External pin (STADC) trigger,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: EPWM0_CH0 trigger,9: EPWM0_CH2 trigger,10: EPWM0_CH4 trigger,11: EPWM1_CH0 trigger,12: EPWM1_CH2 trigger,13: EPWM1_CH4 trigger,14: PWM0_CH0 trigger,15: PWM0_CH1 trigger"
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bitfld.long 0x00 0.--3. "CHSEL,A/D SAMPLE MODULE 0 1 Channel Selection\n" "0: ADCn_CH0,1: ADCn_CH1,2: ADCn_CH2,3: ADCn_CH3,4: ADCn_CH4,5: ADCn_CH5,6: ADCn_CH6,7: ADCn_CH7,8: VBG.\nOP1,9: VTEMP,10: AVSS,11: OP0,?..."
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group.long 0x7C++0x03
|
|
line.long 0x00 "EADC_AD1SPCTL1,A/D SAMPLE11 Control Register"
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bitfld.long 0x00 21. "EXTFEN,A/D External Pin Falling Edge Trigger Enable Bit\n" "0: A/D external pin falling edge trigger Disabled,1: A/D external pin falling edge trigger Enabled"
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bitfld.long 0x00 20. "EXTREN,A/D External Pin Rising Edge Trigger Enable Bit\n" "0: A/D external pin rising edge trigger Disabled,1: A/D external pin rising edge trigger Enabled"
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newline
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Time\n"
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newline
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE MODULE Start Of Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External pin (STADC) trigger,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: EPWM0_CH0 trigger,9: EPWM0_CH2 trigger,10: EPWM0_CH4 trigger,11: EPWM1_CH0 trigger,12: EPWM1_CH2 trigger,13: EPWM1_CH4 trigger,14: PWM0_CH0 trigger,15: PWM0_CH1 trigger"
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bitfld.long 0x00 0.--3. "CHSEL,A/D SAMPLE MODULE 0 1 Channel Selection\n" "0: ADCn_CH0,1: ADCn_CH1,2: ADCn_CH2,3: ADCn_CH3,4: ADCn_CH4,5: ADCn_CH5,6: ADCn_CH6,7: ADCn_CH7,8: VBG.\nOP1,9: VTEMP,10: AVSS,11: OP0,?..."
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group.long 0x80++0x03
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|
line.long 0x00 "EADC_AD1SPCTL2,A/D SAMPLE12 Control Register"
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|
bitfld.long 0x00 21. "EXTFEN,A/D External Pin Falling Edge Trigger Enable Bit\n" "0: A/D external pin falling edge trigger Disabled,1: A/D external pin falling edge trigger Enabled"
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bitfld.long 0x00 20. "EXTREN,A/D External Pin Rising Edge Trigger Enable Bit\n" "0: A/D external pin rising edge trigger Disabled,1: A/D external pin rising edge trigger Enabled"
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newline
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Time\n"
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newline
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE MODULE Start Of Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External pin (STADC) trigger,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: EPWM0_CH0 trigger,9: EPWM0_CH2 trigger,10: EPWM0_CH4 trigger,11: EPWM1_CH0 trigger,12: EPWM1_CH2 trigger,13: EPWM1_CH4 trigger,14: PWM0_CH0 trigger,15: PWM0_CH1 trigger"
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bitfld.long 0x00 0.--3. "CHSEL,A/D SAMPLE MODULE 0 1 Channel Selection\n" "0: ADCn_CH0,1: ADCn_CH1,2: ADCn_CH2,3: ADCn_CH3,4: ADCn_CH4,5: ADCn_CH5,6: ADCn_CH6,7: ADCn_CH7,8: VBG.\nOP1,9: VTEMP,10: AVSS,11: OP0,?..."
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group.long 0x84++0x03
|
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line.long 0x00 "EADC_AD1SPCTL3,A/D SAMPLE13 Control Register"
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|
bitfld.long 0x00 21. "EXTFEN,A/D External Pin Falling Edge Trigger Enable Bit\n" "0: A/D external pin falling edge trigger Disabled,1: A/D external pin falling edge trigger Enabled"
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bitfld.long 0x00 20. "EXTREN,A/D External Pin Rising Edge Trigger Enable Bit\n" "0: A/D external pin rising edge trigger Disabled,1: A/D external pin rising edge trigger Enabled"
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|
newline
|
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE MODULE Start Of Conversion Trigger Delay Time\n"
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newline
|
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE MODULE Start Of Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External pin (STADC) trigger,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: EPWM0_CH0 trigger,9: EPWM0_CH2 trigger,10: EPWM0_CH4 trigger,11: EPWM1_CH0 trigger,12: EPWM1_CH2 trigger,13: EPWM1_CH4 trigger,14: PWM0_CH0 trigger,15: PWM0_CH1 trigger"
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bitfld.long 0x00 0.--3. "CHSEL,A/D SAMPLE MODULE 0 1 Channel Selection\n" "0: ADCn_CH0,1: ADCn_CH1,2: ADCn_CH2,3: ADCn_CH3,4: ADCn_CH4,5: ADCn_CH5,6: ADCn_CH6,7: ADCn_CH7,8: VBG.\nOP1,9: VTEMP,10: AVSS,11: OP0,?..."
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|
group.long 0x88++0x03
|
|
line.long 0x00 "EADC_AD1SPCTL4,A/D SAMPLE14 Control Register"
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|
bitfld.long 0x00 7. "SIMUSEL7,A/D SAMPLE07 SAMPLE17 Simultaneous Sampling Mode Selection \n" "0: SAMPLE07 SAMPLE17 are in single sampling mode..,1: SAMPLE07 SAMPLE17 are in simultaneous.."
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bitfld.long 0x00 6. "SIMUSEL6,A/D SAMPLE06 SAMPLE16 Simultaneous Sampling Mode Selection\n" "0: SAMPLE06 SAMPLE16 are in single sampling mode..,1: SAMPLE06 SAMPLE16 are in simultaneous.."
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newline
|
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bitfld.long 0x00 5. "SIMUSEL5,A/D SAMPLE05 SAMPLE15 Simultaneous Sampling Mode Selection\n" "0: SAMPLE05 SAMPLE15 are in single sampling mode..,1: SAMPLE05 SAMPLE15 are in simultaneous.."
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bitfld.long 0x00 4. "SIMUSEL4,A/D SAMPLE04 SAMPLE14 Simultaneous Sampling Mode Selection\n" "0: SAMPLE04 SAMPLE14 are in single sampling mode..,1: SAMPLE04 SAMPLE14 are in simultaneous.."
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newline
|
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bitfld.long 0x00 3. "SIMUSEL3,A/D SAMPLE03 SAMPLE13 Simultaneous Sampling Mode Selection\n" "0: SAMPLE03 SAMPLE13 are in single sampling mode..,1: SAMPLE03 SAMPLE13 are in simultaneous.."
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bitfld.long 0x00 2. "SIMUSEL2,A/D SAMPLE02 SAMPLE12 Simultaneous Sampling Mode Selection\n" "0: SAMPLE02 SAMPLE12 are in single sampling mode..,1: SAMPLE02 SAMPLE12 are in simultaneous.."
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newline
|
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bitfld.long 0x00 1. "SIMUSEL1,A/D SAMPLE01 SAMPLE11 Simultaneous Sampling Mode Selection\n" "0: SAMPLE01 SAMPLE11 are in single sampling mode..,1: SAMPLE01 SAMPLE11 are in simultaneous.."
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bitfld.long 0x00 0. "SIMUSEL0,A/D SAMPLE00 SAMPLE10 Simultaneous Sampling Mode Selection\n" "0: SAMPLE00 SAMPLE10 are in single sampling mode..,1: SAMPLE00 SAMPLE10 are in simultaneous.."
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group.long 0x8C++0x03
|
|
line.long 0x00 "EADC_AD1SPCTL5,A/D SAMPLE15 Control Register"
|
|
bitfld.long 0x00 7. "SIMUSEL7,A/D SAMPLE07 SAMPLE17 Simultaneous Sampling Mode Selection \n" "0: SAMPLE07 SAMPLE17 are in single sampling mode..,1: SAMPLE07 SAMPLE17 are in simultaneous.."
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bitfld.long 0x00 6. "SIMUSEL6,A/D SAMPLE06 SAMPLE16 Simultaneous Sampling Mode Selection\n" "0: SAMPLE06 SAMPLE16 are in single sampling mode..,1: SAMPLE06 SAMPLE16 are in simultaneous.."
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newline
|
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bitfld.long 0x00 5. "SIMUSEL5,A/D SAMPLE05 SAMPLE15 Simultaneous Sampling Mode Selection\n" "0: SAMPLE05 SAMPLE15 are in single sampling mode..,1: SAMPLE05 SAMPLE15 are in simultaneous.."
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bitfld.long 0x00 4. "SIMUSEL4,A/D SAMPLE04 SAMPLE14 Simultaneous Sampling Mode Selection\n" "0: SAMPLE04 SAMPLE14 are in single sampling mode..,1: SAMPLE04 SAMPLE14 are in simultaneous.."
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newline
|
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bitfld.long 0x00 3. "SIMUSEL3,A/D SAMPLE03 SAMPLE13 Simultaneous Sampling Mode Selection\n" "0: SAMPLE03 SAMPLE13 are in single sampling mode..,1: SAMPLE03 SAMPLE13 are in simultaneous.."
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bitfld.long 0x00 2. "SIMUSEL2,A/D SAMPLE02 SAMPLE12 Simultaneous Sampling Mode Selection\n" "0: SAMPLE02 SAMPLE12 are in single sampling mode..,1: SAMPLE02 SAMPLE12 are in simultaneous.."
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newline
|
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bitfld.long 0x00 1. "SIMUSEL1,A/D SAMPLE01 SAMPLE11 Simultaneous Sampling Mode Selection\n" "0: SAMPLE01 SAMPLE11 are in single sampling mode..,1: SAMPLE01 SAMPLE11 are in simultaneous.."
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bitfld.long 0x00 0. "SIMUSEL0,A/D SAMPLE00 SAMPLE10 Simultaneous Sampling Mode Selection\n" "0: SAMPLE00 SAMPLE10 are in single sampling mode..,1: SAMPLE00 SAMPLE10 are in simultaneous.."
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group.long 0x90++0x03
|
|
line.long 0x00 "EADC_AD1SPCTL6,A/D SAMPLE16 Control Register"
|
|
bitfld.long 0x00 7. "SIMUSEL7,A/D SAMPLE07 SAMPLE17 Simultaneous Sampling Mode Selection \n" "0: SAMPLE07 SAMPLE17 are in single sampling mode..,1: SAMPLE07 SAMPLE17 are in simultaneous.."
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bitfld.long 0x00 6. "SIMUSEL6,A/D SAMPLE06 SAMPLE16 Simultaneous Sampling Mode Selection\n" "0: SAMPLE06 SAMPLE16 are in single sampling mode..,1: SAMPLE06 SAMPLE16 are in simultaneous.."
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newline
|
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bitfld.long 0x00 5. "SIMUSEL5,A/D SAMPLE05 SAMPLE15 Simultaneous Sampling Mode Selection\n" "0: SAMPLE05 SAMPLE15 are in single sampling mode..,1: SAMPLE05 SAMPLE15 are in simultaneous.."
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bitfld.long 0x00 4. "SIMUSEL4,A/D SAMPLE04 SAMPLE14 Simultaneous Sampling Mode Selection\n" "0: SAMPLE04 SAMPLE14 are in single sampling mode..,1: SAMPLE04 SAMPLE14 are in simultaneous.."
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newline
|
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bitfld.long 0x00 3. "SIMUSEL3,A/D SAMPLE03 SAMPLE13 Simultaneous Sampling Mode Selection\n" "0: SAMPLE03 SAMPLE13 are in single sampling mode..,1: SAMPLE03 SAMPLE13 are in simultaneous.."
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|
bitfld.long 0x00 2. "SIMUSEL2,A/D SAMPLE02 SAMPLE12 Simultaneous Sampling Mode Selection\n" "0: SAMPLE02 SAMPLE12 are in single sampling mode..,1: SAMPLE02 SAMPLE12 are in simultaneous.."
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newline
|
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bitfld.long 0x00 1. "SIMUSEL1,A/D SAMPLE01 SAMPLE11 Simultaneous Sampling Mode Selection\n" "0: SAMPLE01 SAMPLE11 are in single sampling mode..,1: SAMPLE01 SAMPLE11 are in simultaneous.."
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|
bitfld.long 0x00 0. "SIMUSEL0,A/D SAMPLE00 SAMPLE10 Simultaneous Sampling Mode Selection\n" "0: SAMPLE00 SAMPLE10 are in single sampling mode..,1: SAMPLE00 SAMPLE10 are in simultaneous.."
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "EADC_AD1SPCTL7,A/D SAMPLE17 Control Register"
|
|
bitfld.long 0x00 7. "SIMUSEL7,A/D SAMPLE07 SAMPLE17 Simultaneous Sampling Mode Selection \n" "0: SAMPLE07 SAMPLE17 are in single sampling mode..,1: SAMPLE07 SAMPLE17 are in simultaneous.."
|
|
bitfld.long 0x00 6. "SIMUSEL6,A/D SAMPLE06 SAMPLE16 Simultaneous Sampling Mode Selection\n" "0: SAMPLE06 SAMPLE16 are in single sampling mode..,1: SAMPLE06 SAMPLE16 are in simultaneous.."
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newline
|
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bitfld.long 0x00 5. "SIMUSEL5,A/D SAMPLE05 SAMPLE15 Simultaneous Sampling Mode Selection\n" "0: SAMPLE05 SAMPLE15 are in single sampling mode..,1: SAMPLE05 SAMPLE15 are in simultaneous.."
|
|
bitfld.long 0x00 4. "SIMUSEL4,A/D SAMPLE04 SAMPLE14 Simultaneous Sampling Mode Selection\n" "0: SAMPLE04 SAMPLE14 are in single sampling mode..,1: SAMPLE04 SAMPLE14 are in simultaneous.."
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newline
|
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bitfld.long 0x00 3. "SIMUSEL3,A/D SAMPLE03 SAMPLE13 Simultaneous Sampling Mode Selection\n" "0: SAMPLE03 SAMPLE13 are in single sampling mode..,1: SAMPLE03 SAMPLE13 are in simultaneous.."
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|
bitfld.long 0x00 2. "SIMUSEL2,A/D SAMPLE02 SAMPLE12 Simultaneous Sampling Mode Selection\n" "0: SAMPLE02 SAMPLE12 are in single sampling mode..,1: SAMPLE02 SAMPLE12 are in simultaneous.."
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|
newline
|
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bitfld.long 0x00 1. "SIMUSEL1,A/D SAMPLE01 SAMPLE11 Simultaneous Sampling Mode Selection\n" "0: SAMPLE01 SAMPLE11 are in single sampling mode..,1: SAMPLE01 SAMPLE11 are in simultaneous.."
|
|
bitfld.long 0x00 0. "SIMUSEL0,A/D SAMPLE00 SAMPLE10 Simultaneous Sampling Mode Selection\n" "0: SAMPLE00 SAMPLE10 are in single sampling mode..,1: SAMPLE00 SAMPLE10 are in simultaneous.."
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "EADC_SIMUSEL,A/D SAMPLE Module Simultaneous Sampling Mode Select Register"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0xA8)++0x03
|
|
line.long 0x00 "EADC_CMP$1,A/D Result Compare Register $1"
|
|
hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Compared Data\nThe 12 bits data is used to compare with conversion result of specified SAMPLE"
|
|
bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count\nWhen the specified A/D SAMPLE MODULE analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPx[2]) the internal match counter will increase 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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bitfld.long 0x00 3.--5. "CMPSPL,Compare SAMPLE MODULE Selection\n" "0: SAMPLE00 conversion result EADC_AD0DAT0 is..,1: SAMPLE01 conversion result EADC_AD0DAT1 is..,2: SAMPLE02 conversion result EADC_AD0DAT2 is..,3: SAMPLE03 conversion result EADC_AD0DAT3 is..,4: SAMPLE10 conversion result EADC_AD1DAT0 is..,5: SAMPLE11 conversion result EADC_AD1DAT1 is..,6: SAMPLE12 conversion result EADC_AD1DAT2 is..,7: SAMPLE13 conversion result EADC_AD1DAT3 is.."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8]) + 1 the CMPF bit will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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newline
|
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bitfld.long 0x00 1. "ADCMPIE,A/D Result Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPx[2]) and CMPMCNT (EADC_CMPx[11:8]) ADCMPF (EADC_STATUS1 [7:6]) bit will be asserted in the meanwhile.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
|
|
bitfld.long 0x00 0. "ADCMPEN,A/D Result Compare Enable Bit\nSet this bit to 1 to enable compare CMPDAT (EADC_CMPx[27:16]) with specified SAMPLE MODULE conversion result when converted data is loaded into ADDR register" "0: Compare Disabled,1: Compare Enabled"
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repeat.end
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rgroup.long 0xB0++0x03
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line.long 0x00 "EADC_STATUS0,A/D Status Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "OV15_8,ADDR17~ADDR10 Overrun Flag (Read Only)\nIt is a mirror to OV bit in SAMPLE 1 A/D result data register EADC_AD0DAT1x.\n"
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hexmask.long.byte 0x00 16.--23. 1. "OV7_0,ADDR07~ ADDR00 Overrun Flag (Read Only)\nIt is a mirror to OV bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.\n"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "VALID15_8,ADDR17~ ADDR10 Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in SAMPLE1 A/D result data register EADC_AD0DAT1x.\n"
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|
hexmask.long.byte 0x00 0.--7. 1. "VALID7_0,ADDR07~ ADDR00 Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.\n"
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|
group.long 0xB4++0x03
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line.long 0x00 "EADC_STATUS1,A/D Status Register 1"
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|
bitfld.long 0x00 27. "AOV,For All SAMPLE MODULE A/D Result Data Register Overrun Flags Check \nNote: This bit will keep 1 when any OVx (EADC_ADnDATx[16]) Flag is equal to 1" "0: None of SAMPLE MODULE data register overrun..,1: Any one of SAMPLE MODULE data register.."
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bitfld.long 0x00 26. "AVALID,For All SAMPLE MODULE A/D Result Data Register ADDR Data Valid Flag Check\nNote: This bit will keep 1 when any VALIDx (EADC_ADnDATx[17]) Flag is equal to 1" "0: None of SAMPLE MODULE data register valid..,1: Any one of SAMPLE MODULE data register valid.."
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|
newline
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bitfld.long 0x00 25. "STOVF,For All A/D SAMPLE MODULE Start Of Conversion Overrun Flags Check\nNote: This bit will keep 1 when any SPOVFx (ADSPOVFR [15:0]) Flag is equal to 1" "0: None of SAMPLE MODULE event overrun flag..,1: Any one of SAMPLE MODULE event overrun flag.."
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bitfld.long 0x00 24. "ADOVIF,All A/D Interrupt Flag Overrun Bits Check \nNote: This bit will keep 1 when any ADFOVx (ADIFOVR [15:0]) Flag is equal to 1" "0: None of ADINT interrupt flag ADFOVx (ADIFOVR..,1: Any one of ADINT interrupt flag ADFOVx.."
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newline
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rbitfld.long 0x00 20.--23. "CHANNEL1,Current Conversion Channel (Read Only)\n" "0: ADC1_CH0,1: ADC1_CH1,2: ADC1_CH2,3: ADC1_CH3,4: ADC1_CH4,5: ADC1_CH5,6: ADC1_CH6,7: ADC1_CH7,8: OPA1_O,?..."
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bitfld.long 0x00 16. "BUSY1,Busy/Idle\n" "0: A/D converter 1 (ADC1) is in idle state,1: A/D converter 1 (ADC1) is doing conversion"
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newline
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rbitfld.long 0x00 12.--15. "CHANNEL0,Current Conversion Channel (Read Only)\n" "0: ADC0_CH0,1: ADC0_CH1,2: ADC0_CH2,3: ADC0_CH3,4: ADC0_CH4.\nADC0_CH5,?,6: ADC0_CH6,7: ADC0_CH7,8: VBG,9: VTEMP,10: AVSS,11: OPA0_O,?..."
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rbitfld.long 0x00 8. "BUSY0,Busy/Idle (Read Only)\n" "0: A/D converter 0 (ADC0) is in idle state,1: A/D converter 0 (ADC0) is doing conversion"
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newline
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bitfld.long 0x00 7. "ADCMPF1,ADC Compare 1 Flag\nWhen the specific SAMPLE MODULE A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets EADC_CMP1.."
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bitfld.long 0x00 6. "ADCMPF0,ADC Compare 0 Flag\nWhen the specific SAMPLE MODULE A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets EADC_CMP0.."
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newline
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bitfld.long 0x00 5. "ADCMPO1,ADC Compare 1 Output Status\nThe 12 bits compare1 data CMPDAT (EADC_CMP1 [27:16]) is used to compare with conversion result of specified SAMPLE MODULE" "0: Conversion result in ADDR less than CMPDAT..,1: Conversion result in ADDR great than or equal.."
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bitfld.long 0x00 4. "ADCMPO0,ADC Compare 0 Output Status\nThe 12 bits compare0 data CMPDAT EADC_CMP0 [27:16]) is used to compare with conversion result of specified SAMPLE MODULE. Software can use it to monitor the external analog input pin voltage status.\n" "0: Conversion result in ADDR less than CMPDAT..,1: Conversion result in ADDR great than or equal.."
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bitfld.long 0x00 3. "ADIF3,A/D ADINT3 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific SAMPLE MODULE has been completed" "0: No ADINT3 interrupt pulse received,1: ADINT3 interrupt pulse has been received"
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bitfld.long 0x00 2. "ADIF2,A/D ADINT2 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it" "0: no ADINT2 interrupt pulse received,1: ADINT2 interrupt pulse has been received"
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newline
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bitfld.long 0x00 1. "ADIF1,A/D ADINT1 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific SAMPLE MODULE has been completed" "0: No ADINT1 interrupt pulse received,1: ADINT1 interrupt pulse has been received"
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bitfld.long 0x00 0. "ADIF0,A/D ADINT0 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific SAMPLE MODULE has been completed" "0: No ADINT0 interrupt pulse received,1: ADINT0 interrupt pulse has been received"
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group.long 0xB8++0x03
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line.long 0x00 "EADC_EXTSMPT,A/D Timing Control Register"
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hexmask.long.byte 0x00 16.--23. 1. "EXTSMPT1,ADC1 Extend Sampling Time \nWhen A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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hexmask.long.byte 0x00 0.--7. 1. "EXTSMPT0,ADC0 Extend Sampling Time \nWhen A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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rgroup.long 0x100++0x03
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line.long 0x00 "EADC_AD0DDAT0,A/D Double Data Register 0 for SAMPLE00"
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bitfld.long 0x00 16. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE MODULE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is" "0: Double buffer data in RESULT..,1: Double buffer data in RESULT.."
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hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
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group.long 0x104++0x03
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line.long 0x00 "EADC_AD0DDAT1,A/D Double Data Register 1 for SAMPLE01"
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rbitfld.long 0x00 16. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE MODULE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is" "0: Double buffer data in RESULT..,1: Double buffer data in RESULT.."
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hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
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group.long 0x108++0x03
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line.long 0x00 "EADC_AD0DDAT2,A/D Double Data Register 2 for SAMPLE02"
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rbitfld.long 0x00 16. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE MODULE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is" "0: Double buffer data in RESULT..,1: Double buffer data in RESULT.."
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hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
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group.long 0x10C++0x03
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line.long 0x00 "EADC_AD0DDAT3,A/D Double Data Register 3 for SAMPLE03"
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rbitfld.long 0x00 16. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE MODULE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is" "0: Double buffer data in RESULT..,1: Double buffer data in RESULT.."
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hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
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group.long 0x120++0x03
|
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line.long 0x00 "EADC_AD1DDAT0,A/D Double Data Register 0 for SAMPLE10"
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rbitfld.long 0x00 16. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE MODULE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is" "0: Double buffer data in RESULT..,1: Double buffer data in RESULT.."
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hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
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group.long 0x124++0x03
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line.long 0x00 "EADC_AD1DDAT1,A/D Double Data Register 1 for SAMPLE11"
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rbitfld.long 0x00 16. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE MODULE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is" "0: Double buffer data in RESULT..,1: Double buffer data in RESULT.."
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hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
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group.long 0x128++0x03
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line.long 0x00 "EADC_AD1DDAT2,A/D Double Data Register 2 for SAMPLE12"
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rbitfld.long 0x00 16. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE MODULE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is" "0: Double buffer data in RESULT..,1: Double buffer data in RESULT.."
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hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
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group.long 0x12C++0x03
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line.long 0x00 "EADC_AD1DDAT3,A/D Double Data Register 3 for SAMPLE13"
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rbitfld.long 0x00 16. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE MODULE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is" "0: Double buffer data in RESULT..,1: Double buffer data in RESULT.."
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hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains 12 bits conversion result"
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group.long 0x130++0x03
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line.long 0x00 "EADC_DBMEN,A/D Double Buffer Mode Select"
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bitfld.long 0x00 11. "AD1DBM3,Double Buffer Mode For SAMPLE13 \n" "0: SAMPLE13 has one sample result register,1: SAMPLE13 has two sample result registers"
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|
bitfld.long 0x00 10. "AD1DBM2,Double Buffer Mode For SAMPLE12 \n" "0: SAMPLE12 has one sample result register,1: SAMPLE12 has two sample result registers"
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newline
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bitfld.long 0x00 9. "AD1DBM1,Double Buffer Mode For SAMPLE11 \n" "0: SAMPLE11 has one sample result register,1: SAMPLE11 has two sample result registers"
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bitfld.long 0x00 8. "AD1DBM0,Double Buffer Mode For SAMPLE10 \n" "0: SAMPLE10 has one sample result register,1: SAMPLE10 has two sample result registers"
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newline
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bitfld.long 0x00 3. "AD0DBM3,Double Buffer Mode For SAMPLE03 \n" "0: SAMPLE03 has one sample result register,1: SAMPLE03 has two sample result registers"
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bitfld.long 0x00 2. "AD0DBM2,Double Buffer Mode For SAMPLE02 \n" "0: SAMPLE02 has one sample result register,1: SAMPLE02 has two sample result registers"
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newline
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bitfld.long 0x00 1. "AD0DBM1,Double Buffer Mode For SAMPLE01 \n" "0: SAMPLE01 has one sample result register,1: SAMPLE01 has two sample result registers"
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bitfld.long 0x00 0. "AD0DBM0,Double Buffer Mode For SAMPLE00 \n" "0: SAMPLE00 has one sample result register,1: SAMPLE00 has two sample result registers"
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group.long 0x134++0x03
|
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line.long 0x00 "EADC_INTSRC0,A/D Interrupt 0 Source Enable Control Register"
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bitfld.long 0x00 15. "AD1SPIE7,SAMPLE17 Interrupt Mask Enable Bit\n" "0: SAMPLE17 interrupt mask Disabled,1: SAMPLE17 interrupt mask Enabled"
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bitfld.long 0x00 14. "AD1SPIE6,SAMPLE16 Interrupt Mask Enable Bit\n" "0: SAMPLE16 interrupt mask Disabled,1: SAMPLE16 interrupt mask Enabled"
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newline
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bitfld.long 0x00 13. "AD1SPIE5,SAMPLE15 Interrupt Mask Enable Bit\n" "0: SAMPLE15 interrupt mask Disabled,1: SAMPLE15 interrupt mask Enabled"
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bitfld.long 0x00 12. "AD1SPIE4,SAMPLE14 Interrupt Mask Enable Bit\n" "0: SAMPLE14 interrupt mask Disabled,1: SAMPLE14 interrupt mask Enabled"
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newline
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bitfld.long 0x00 11. "AD1SPIE3,SAMPLE13 Interrupt Mask Enable Bit\n" "0: SAMPLE13 interrupt mask Disabled,1: SAMPLE13 interrupt mask Enabled"
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bitfld.long 0x00 10. "AD1SPIE2,SAMPLE12 Interrupt Mask Enable Bit\n" "0: SAMPLE12 interrupt mask Disabled,1: SAMPLE12 interrupt mask Enabled"
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newline
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bitfld.long 0x00 9. "AD1SPIE1,SAMPLE11 Interrupt Mask Enable Bit\n" "0: SAMPLE11 interrupt mask Disabled,1: SAMPLE11 interrupt mask Enabled"
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bitfld.long 0x00 8. "AD1SPIE0,SAMPLE10 Interrupt Mask Enable Bit\n" "0: SAMPLE10 interrupt mask Disabled,1: SAMPLE10 interrupt mask Enabled"
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newline
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bitfld.long 0x00 7. "AD0SPIE7,SAMPLE07 Interrupt Mask Enable Bit\n" "0: SAMPLE07 interrupt mask Disabled,1: SAMPLE07 interrupt mask Enabled"
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bitfld.long 0x00 6. "AD0SPIE6,SAMPLE06 Interrupt Mask Enable Bit\n" "0: SAMPLE06 interrupt mask Disabled,1: SAMPLE06 interrupt mask Enabled"
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newline
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bitfld.long 0x00 5. "AD0SPIE5,SAMPLE05 Interrupt Mask Enable Bit\n" "0: SAMPLE05 interrupt mask Disabled,1: SAMPLE05 interrupt mask Enabled"
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bitfld.long 0x00 4. "AD0SPIE4,SAMPLE04 Interrupt Mask Enable Bit\n" "0: SAMPLE04 interrupt mask Disabled,1: SAMPLE04 interrupt mask Enabled"
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newline
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bitfld.long 0x00 3. "AD0SPIE3,SAMPLE03 Interrupt Mask Enable Bit\n" "0: SAMPLE03 interrupt mask Disabled,1: SAMPLE03 interrupt mask Enabled"
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bitfld.long 0x00 2. "AD0SPIE2,SAMPLE02 Interrupt Mask Enable Bit\n" "0: SAMPLE02 interrupt mask Disabled,1: SAMPLE02 interrupt mask Enabled"
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newline
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bitfld.long 0x00 1. "AD0SPIE1,SAMPLE01 Interrupt Mask Enable Bit\n" "0: SAMPLE01 interrupt mask Disabled,1: SAMPLE01 interrupt mask Enabled"
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bitfld.long 0x00 0. "AD0SPIE0,SAMPLE00 Interrupt Mask Enable Bit\n" "0: SAMPLE00 interrupt mask Disabled,1: SAMPLE00 interrupt mask Enabled"
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group.long 0x138++0x03
|
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line.long 0x00 "EADC_INTSRC1,A/D Interrupt 1 Source Enable Control Register"
|
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bitfld.long 0x00 15. "AD1SPIE7,SAMPLE17 Interrupt Mask Enable Bit\n" "0: SAMPLE17 interrupt mask Disabled,1: SAMPLE17 interrupt mask Enabled"
|
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bitfld.long 0x00 14. "AD1SPIE6,SAMPLE16 Interrupt Mask Enable Bit\n" "0: SAMPLE16 interrupt mask Disabled,1: SAMPLE16 interrupt mask Enabled"
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newline
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bitfld.long 0x00 13. "AD1SPIE5,SAMPLE15 Interrupt Mask Enable Bit\n" "0: SAMPLE15 interrupt mask Disabled,1: SAMPLE15 interrupt mask Enabled"
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bitfld.long 0x00 12. "AD1SPIE4,SAMPLE14 Interrupt Mask Enable Bit\n" "0: SAMPLE14 interrupt mask Disabled,1: SAMPLE14 interrupt mask Enabled"
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newline
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bitfld.long 0x00 11. "AD1SPIE3,SAMPLE13 Interrupt Mask Enable Bit\n" "0: SAMPLE13 interrupt mask Disabled,1: SAMPLE13 interrupt mask Enabled"
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bitfld.long 0x00 10. "AD1SPIE2,SAMPLE12 Interrupt Mask Enable Bit\n" "0: SAMPLE12 interrupt mask Disabled,1: SAMPLE12 interrupt mask Enabled"
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newline
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bitfld.long 0x00 9. "AD1SPIE1,SAMPLE11 Interrupt Mask Enable Bit\n" "0: SAMPLE11 interrupt mask Disabled,1: SAMPLE11 interrupt mask Enabled"
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bitfld.long 0x00 8. "AD1SPIE0,SAMPLE10 Interrupt Mask Enable Bit\n" "0: SAMPLE10 interrupt mask Disabled,1: SAMPLE10 interrupt mask Enabled"
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newline
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bitfld.long 0x00 7. "AD0SPIE7,SAMPLE07 Interrupt Mask Enable Bit\n" "0: SAMPLE07 interrupt mask Disabled,1: SAMPLE07 interrupt mask Enabled"
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bitfld.long 0x00 6. "AD0SPIE6,SAMPLE06 Interrupt Mask Enable Bit\n" "0: SAMPLE06 interrupt mask Disabled,1: SAMPLE06 interrupt mask Enabled"
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newline
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bitfld.long 0x00 5. "AD0SPIE5,SAMPLE05 Interrupt Mask Enable Bit\n" "0: SAMPLE05 interrupt mask Disabled,1: SAMPLE05 interrupt mask Enabled"
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bitfld.long 0x00 4. "AD0SPIE4,SAMPLE04 Interrupt Mask Enable Bit\n" "0: SAMPLE04 interrupt mask Disabled,1: SAMPLE04 interrupt mask Enabled"
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newline
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bitfld.long 0x00 3. "AD0SPIE3,SAMPLE03 Interrupt Mask Enable Bit\n" "0: SAMPLE03 interrupt mask Disabled,1: SAMPLE03 interrupt mask Enabled"
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bitfld.long 0x00 2. "AD0SPIE2,SAMPLE02 Interrupt Mask Enable Bit\n" "0: SAMPLE02 interrupt mask Disabled,1: SAMPLE02 interrupt mask Enabled"
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bitfld.long 0x00 1. "AD0SPIE1,SAMPLE01 Interrupt Mask Enable Bit\n" "0: SAMPLE01 interrupt mask Disabled,1: SAMPLE01 interrupt mask Enabled"
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bitfld.long 0x00 0. "AD0SPIE0,SAMPLE00 Interrupt Mask Enable Bit\n" "0: SAMPLE00 interrupt mask Disabled,1: SAMPLE00 interrupt mask Enabled"
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group.long 0x13C++0x03
|
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line.long 0x00 "EADC_INTSRC2,A/D Interrupt 2 Source Enable Control Register"
|
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bitfld.long 0x00 15. "AD1SPIE7,SAMPLE17 Interrupt Mask Enable Bit\n" "0: SAMPLE17 interrupt mask Disabled,1: SAMPLE17 interrupt mask Enabled"
|
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bitfld.long 0x00 14. "AD1SPIE6,SAMPLE16 Interrupt Mask Enable Bit\n" "0: SAMPLE16 interrupt mask Disabled,1: SAMPLE16 interrupt mask Enabled"
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newline
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bitfld.long 0x00 13. "AD1SPIE5,SAMPLE15 Interrupt Mask Enable Bit\n" "0: SAMPLE15 interrupt mask Disabled,1: SAMPLE15 interrupt mask Enabled"
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bitfld.long 0x00 12. "AD1SPIE4,SAMPLE14 Interrupt Mask Enable Bit\n" "0: SAMPLE14 interrupt mask Disabled,1: SAMPLE14 interrupt mask Enabled"
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newline
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bitfld.long 0x00 11. "AD1SPIE3,SAMPLE13 Interrupt Mask Enable Bit\n" "0: SAMPLE13 interrupt mask Disabled,1: SAMPLE13 interrupt mask Enabled"
|
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bitfld.long 0x00 10. "AD1SPIE2,SAMPLE12 Interrupt Mask Enable Bit\n" "0: SAMPLE12 interrupt mask Disabled,1: SAMPLE12 interrupt mask Enabled"
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newline
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bitfld.long 0x00 9. "AD1SPIE1,SAMPLE11 Interrupt Mask Enable Bit\n" "0: SAMPLE11 interrupt mask Disabled,1: SAMPLE11 interrupt mask Enabled"
|
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bitfld.long 0x00 8. "AD1SPIE0,SAMPLE10 Interrupt Mask Enable Bit\n" "0: SAMPLE10 interrupt mask Disabled,1: SAMPLE10 interrupt mask Enabled"
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newline
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bitfld.long 0x00 7. "AD0SPIE7,SAMPLE07 Interrupt Mask Enable Bit\n" "0: SAMPLE07 interrupt mask Disabled,1: SAMPLE07 interrupt mask Enabled"
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bitfld.long 0x00 6. "AD0SPIE6,SAMPLE06 Interrupt Mask Enable Bit\n" "0: SAMPLE06 interrupt mask Disabled,1: SAMPLE06 interrupt mask Enabled"
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bitfld.long 0x00 5. "AD0SPIE5,SAMPLE05 Interrupt Mask Enable Bit\n" "0: SAMPLE05 interrupt mask Disabled,1: SAMPLE05 interrupt mask Enabled"
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bitfld.long 0x00 4. "AD0SPIE4,SAMPLE04 Interrupt Mask Enable Bit\n" "0: SAMPLE04 interrupt mask Disabled,1: SAMPLE04 interrupt mask Enabled"
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bitfld.long 0x00 3. "AD0SPIE3,SAMPLE03 Interrupt Mask Enable Bit\n" "0: SAMPLE03 interrupt mask Disabled,1: SAMPLE03 interrupt mask Enabled"
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bitfld.long 0x00 2. "AD0SPIE2,SAMPLE02 Interrupt Mask Enable Bit\n" "0: SAMPLE02 interrupt mask Disabled,1: SAMPLE02 interrupt mask Enabled"
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newline
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bitfld.long 0x00 1. "AD0SPIE1,SAMPLE01 Interrupt Mask Enable Bit\n" "0: SAMPLE01 interrupt mask Disabled,1: SAMPLE01 interrupt mask Enabled"
|
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bitfld.long 0x00 0. "AD0SPIE0,SAMPLE00 Interrupt Mask Enable Bit\n" "0: SAMPLE00 interrupt mask Disabled,1: SAMPLE00 interrupt mask Enabled"
|
|
group.long 0x140++0x03
|
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line.long 0x00 "EADC_INTSRC3,A/D Interrupt 3 Source Enable Control Register"
|
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bitfld.long 0x00 15. "AD1SPIE7,SAMPLE17 Interrupt Mask Enable Bit\n" "0: SAMPLE17 interrupt mask Disabled,1: SAMPLE17 interrupt mask Enabled"
|
|
bitfld.long 0x00 14. "AD1SPIE6,SAMPLE16 Interrupt Mask Enable Bit\n" "0: SAMPLE16 interrupt mask Disabled,1: SAMPLE16 interrupt mask Enabled"
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newline
|
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bitfld.long 0x00 13. "AD1SPIE5,SAMPLE15 Interrupt Mask Enable Bit\n" "0: SAMPLE15 interrupt mask Disabled,1: SAMPLE15 interrupt mask Enabled"
|
|
bitfld.long 0x00 12. "AD1SPIE4,SAMPLE14 Interrupt Mask Enable Bit\n" "0: SAMPLE14 interrupt mask Disabled,1: SAMPLE14 interrupt mask Enabled"
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newline
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bitfld.long 0x00 11. "AD1SPIE3,SAMPLE13 Interrupt Mask Enable Bit\n" "0: SAMPLE13 interrupt mask Disabled,1: SAMPLE13 interrupt mask Enabled"
|
|
bitfld.long 0x00 10. "AD1SPIE2,SAMPLE12 Interrupt Mask Enable Bit\n" "0: SAMPLE12 interrupt mask Disabled,1: SAMPLE12 interrupt mask Enabled"
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newline
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bitfld.long 0x00 9. "AD1SPIE1,SAMPLE11 Interrupt Mask Enable Bit\n" "0: SAMPLE11 interrupt mask Disabled,1: SAMPLE11 interrupt mask Enabled"
|
|
bitfld.long 0x00 8. "AD1SPIE0,SAMPLE10 Interrupt Mask Enable Bit\n" "0: SAMPLE10 interrupt mask Disabled,1: SAMPLE10 interrupt mask Enabled"
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newline
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bitfld.long 0x00 7. "AD0SPIE7,SAMPLE07 Interrupt Mask Enable Bit\n" "0: SAMPLE07 interrupt mask Disabled,1: SAMPLE07 interrupt mask Enabled"
|
|
bitfld.long 0x00 6. "AD0SPIE6,SAMPLE06 Interrupt Mask Enable Bit\n" "0: SAMPLE06 interrupt mask Disabled,1: SAMPLE06 interrupt mask Enabled"
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newline
|
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bitfld.long 0x00 5. "AD0SPIE5,SAMPLE05 Interrupt Mask Enable Bit\n" "0: SAMPLE05 interrupt mask Disabled,1: SAMPLE05 interrupt mask Enabled"
|
|
bitfld.long 0x00 4. "AD0SPIE4,SAMPLE04 Interrupt Mask Enable Bit\n" "0: SAMPLE04 interrupt mask Disabled,1: SAMPLE04 interrupt mask Enabled"
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newline
|
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bitfld.long 0x00 3. "AD0SPIE3,SAMPLE03 Interrupt Mask Enable Bit\n" "0: SAMPLE03 interrupt mask Disabled,1: SAMPLE03 interrupt mask Enabled"
|
|
bitfld.long 0x00 2. "AD0SPIE2,SAMPLE02 Interrupt Mask Enable Bit\n" "0: SAMPLE02 interrupt mask Disabled,1: SAMPLE02 interrupt mask Enabled"
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newline
|
|
bitfld.long 0x00 1. "AD0SPIE1,SAMPLE01 Interrupt Mask Enable Bit\n" "0: SAMPLE01 interrupt mask Disabled,1: SAMPLE01 interrupt mask Enabled"
|
|
bitfld.long 0x00 0. "AD0SPIE0,SAMPLE00 Interrupt Mask Enable Bit\n" "0: SAMPLE00 interrupt mask Disabled,1: SAMPLE00 interrupt mask Enabled"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x144)++0x03
|
|
line.long 0x00 "EADC_AD0TRGEN$1,A/D Trigger Condition for SAMPLE00"
|
|
bitfld.long 0x00 31. "PWM01CEN,PWM0_CH1 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 30. "PWM01PEN,PWM0_CH1 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. "PWM01FEN,PWM0_CH1 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 28. "PWM01REN,PWM0_CH1 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. "PWM00CEN,PWM0_CH0 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 26. "PWM00PEN,PWM0_CH0 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "PWM00FEN,PWM0_CH0 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 24. "PWM00REN,PWM0_CH0 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. "EPWM14CEN,EPWM1_CH4 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 22. "EPWM14PEN,EPWM1_CH4 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "EPWM14FEN,EPWM1_CH4 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 20. "EPWM14REN,EPWM1_CH4 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "EPWM12CEN,EPWM1_CH2 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 18. "EPWM12PEN,EPWM1_CH2 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "EPWM120FEN,EPWM1_CH2 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 16. "EPWM12REN,EPWM1_CH2 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "EPWM10CEN,EPWM1_CH0 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 14. "EPWM10PEN,EPWM1_CH0 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "EPWM10FEN,EPWM1_CH0 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 12. "EPWM10REN,EPWM1_CH0 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "EPWM04CEN,EPWM0_CH4 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 10. "EPWM04PEN,EPWM0_CH4 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "EPWM04FEN,EPWM0_CH4 Falling Rdge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 8. "EPWM04REN,EPWM0_CH4 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "EPWM02CEN,EPWM0_CH2 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 6. "EPWM02PEN,EPWM0_CH2 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "EPWM02FEN,EPWM0_CH2 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 4. "EPWM02REN,EPWM0_CH2 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "EPWM00CEN,EPWM0_CH0 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "EPWM00PEN,EPWM0_CH0 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "EPWM00FEN,EPWM0_CH0 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "EPWM00REN,EPWM0_CH0 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x154)++0x03
|
|
line.long 0x00 "EADC_AD1TRGEN$1,A/D Trigger Condition for SAMPLE10"
|
|
bitfld.long 0x00 31. "PWM01CEN,PWM0_CH1 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 30. "PWM01PEN,PWM0_CH1 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 29. "PWM01FEN,PWM0_CH1 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 28. "PWM01REN,PWM0_CH1 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. "PWM00CEN,PWM0_CH0 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 26. "PWM00PEN,PWM0_CH0 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "PWM00FEN,PWM0_CH0 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 24. "PWM00REN,PWM0_CH0 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. "EPWM14CEN,EPWM1_CH4 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 22. "EPWM14PEN,EPWM1_CH4 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "EPWM14FEN,EPWM1_CH4 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 20. "EPWM14REN,EPWM1_CH4 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "EPWM12CEN,EPWM1_CH2 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 18. "EPWM12PEN,EPWM1_CH2 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "EPWM120FEN,EPWM1_CH2 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 16. "EPWM12REN,EPWM1_CH2 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "EPWM10CEN,EPWM1_CH0 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 14. "EPWM10PEN,EPWM1_CH0 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "EPWM10FEN,EPWM1_CH0 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 12. "EPWM10REN,EPWM1_CH0 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "EPWM04CEN,EPWM0_CH4 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 10. "EPWM04PEN,EPWM0_CH4 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "EPWM04FEN,EPWM0_CH4 Falling Rdge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 8. "EPWM04REN,EPWM0_CH4 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "EPWM02CEN,EPWM0_CH2 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 6. "EPWM02PEN,EPWM0_CH2 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "EPWM02FEN,EPWM0_CH2 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 4. "EPWM02REN,EPWM0_CH2 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "EPWM00CEN,EPWM0_CH0 Center Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "EPWM00PEN,EPWM0_CH0 Period Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "EPWM00FEN,EPWM0_CH0 Falling Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "EPWM00REN,EPWM0_CH0 Rising Edge Trigger Enable Bit\n" "0: Disabled,1: Enabled"
|
|
repeat.end
|
|
tree.end
|
|
tree "EBI"
|
|
base ad:0x40010000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EBI_CTL,External Bus Interface General Control Register"
|
|
bitfld.long 0x00 28.--31. "CSPOLINV,Reverse Chip Select\n" "0: nCS (chip select active low),1: CS (chip select active high),?..."
|
|
bitfld.long 0x00 24.--27. "CRYPTOEN,Encrypt/Decrypt Function Enable Bits (For 4 Individual Chip Select)\n" "0: Encrypt/Decrypt function Disabled,1: Encrypt/Decrypt function Enabled,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock is controlled by MCLKDIV as below:\nNote: Default value of output clock is HCLK/1" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8.\nDefault,4: HCLK/16,5: HCLK/32,?..."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EBI_TCTL0,External Bus Interface Bank0 Timing Control Register"
|
|
bitfld.long 0x00 30. "SEPEN,EBI Bank0 Address/Data Bus Separating Enable Bit\n" "0: Address/Data Bus Separating Disabled,1: Address/Data Bus Separating Enabled"
|
|
bitfld.long 0x00 29. "DW16,EBI Bank0 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
|
|
newline
|
|
bitfld.long 0x00 28. "CSEN,EBI Bank0 Enable Bit\nThis bit is the functional enable bit for EBI.\n" "0: EBI function Disabled,1: EBI function Enabled"
|
|
bitfld.long 0x00 24.--27. "R2R,Bank0 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read idle state is inserted and nCS[0] return to high if R2R is not zero.\n" "0: reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "R2W,Bank0 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write idle state is inserted and nCS[0] return to high if R2W is not zero.\n" "0: reserved,?..."
|
|
bitfld.long 0x00 12.--15. "W2X,Bank0 Idle State Cycle After Write\nWhen write action is finish idle state is inserted and nCS[0] return to high if W2X is not zero.\n" "0: reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TAHD,EBI Bank0 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--7. "TACC,EBI Bank0 Data Access Time\nTACC define data access time (tACC).\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TALE,Bank0 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EBI_TCTL1,External Bus Interface Bank1 Timing Control Register"
|
|
bitfld.long 0x00 30. "SEPEN,EBI Bank1 Address/Data Bus Separating Enable Bit\n" "0: Address/Data Bus Separating Disabled,1: Address/Data Bus Separating Enabled"
|
|
bitfld.long 0x00 29. "DW16,EBI Bank1 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
|
|
newline
|
|
bitfld.long 0x00 28. "CSEN,EBI Bank1 Enable Bit\nThis bit is the functional enable bit for EBI.\n" "0: EBI function Disabled,1: EBI function Enabled"
|
|
bitfld.long 0x00 24.--27. "R2R,Bank1 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read idle state is inserted and nCS[1] return to high if R2R is not zero.\n" "0: reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "R2W,Bank1 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write idle state is inserted and nCS[1] return to high if R2W is not zero.\n" "0: reserved,?..."
|
|
bitfld.long 0x00 12.--15. "W2X,Bank1 Idle State Cycle After Write\nWhen write action is finish idle state is inserted and nCS[1] return to high if W2X is not zero.\n" "0: reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TAHD,EBI Bank1 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--7. "TACC,EBI Bank1 Data Access Time\nTACC define data access time (tACC).\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TALE,Bank1 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n" "0,1,2,3,4,5,6,7"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EBI_TCTL2,External Bus Interface Bank2 Timing Control Register"
|
|
bitfld.long 0x00 30. "SEPEN,EBI Bank2 Address/Data Bus Separating Enable Bit\n" "0: Address/Data Bus Separating Disabled,1: Address/Data Bus Separating Enabled"
|
|
bitfld.long 0x00 29. "DW16,EBI Bank2 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
|
|
newline
|
|
bitfld.long 0x00 28. "CSEN,EBI Bank2 Enable Bit\nThis bit is the functional enable bit for EBI.\n" "0: EBI function Disabled,1: EBI function Enabled"
|
|
bitfld.long 0x00 24.--27. "R2R,Bank2 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read idle state is inserted and nCS[2] return to high if R2R is not 0.\n" "0: Reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. "R2W,Bank2 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write idle state is inserted and nCS[2] return to high if R2W is not 0.\n" "0: Reserved,?..."
|
|
bitfld.long 0x00 12.--15. "W2X,Bank2 Idle State Cycle After Write\nWhen write action is finish idle state is inserted and nCS[2] return to high if W2X is not zero.\n" "0: reserved,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TAHD,EBI Bank2 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--7. "TACC,EBI Bank2 Data Access Time\nTACC define data access time (tACC).\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TALE,Bank2 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "EBI_TCTL3,External Bus Interface Bank3 Timing Control Register"
|
|
bitfld.long 0x00 30. "SEPEN,EBI Bank3 Address/Data Bus Separating Enable Bit\n" "0: Address/Data Bus Separating Disabled,1: Address/Data Bus Separating Enabled"
|
|
bitfld.long 0x00 29. "DW16,EBI Bank3 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
|
|
newline
|
|
bitfld.long 0x00 28. "CSEN,EBI Bank3 Enable Bit\nThis bit is the functional enable bit for EBI.\n" "0: EBI function Disabled,1: EBI function Enabled"
|
|
bitfld.long 0x00 24.--27. "R2R,Bank3 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read idle state is inserted and nCS[3] return to high if R2R is not zero.\n0 : reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 16.--19. "R2W,Bank3 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write idle state is inserted and nCS[3] return to high if R2W is not zero.\n0 : reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. "W2X,Bank3 Idle State Cycle After Write\nWhen write action is finish idle state is inserted and nCS[3] return to high if W2X is not zero.\n0 : reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TAHD,EBI Bank3 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--7. "TACC,EBI Bank3 Data Access Time\nTACC define data access time (tACC).\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "TALE,Bank3 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n" "0,1,2,3,4,5,6,7"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EBI_KEY0,External Bus Interface Crypto Key Word 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Crypto Key Word 0 (key[31:0])"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "EBI_KEY1,External Bus Interface Crypto Key Word 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Crypto Key Word 1 (key[63:32])"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EBI_KEY2,External Bus Interface Crypto Key Word 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Crypto Key Word 2 (key[95:64])"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EBI_KEY3,External Bus Interface Crypto Key Word 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Crypto Key Word 3 (key[127:96])"
|
|
tree.end
|
|
tree "ECAP"
|
|
repeat 2. (list 0. 1.) (list ad:0x400B4000 ad:0x400B5000)
|
|
tree "ECAP$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VAL,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter"
|
|
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "ECAP_HOLD$1,Input Capture Counter Hold Register $1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VAL,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAP_CNT value is latched into the corresponding holding register"
|
|
repeat.end
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ECAP_CNTCMP,Input Capture Counter Compare Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VAL,Input Capture Counter Compare Register\n"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ECAP_CTL0,Input Capture Control Register 0"
|
|
bitfld.long 0x00 29. "CAPEN,Input Capture Timer/Counter Enable Bit\n" "0: Input Capture function Disabled,1: Input Capture function Enabled"
|
|
bitfld.long 0x00 28. "CMPEN,Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP if ECAP_CNT value reaches ECAP_CNTCMP the flag CMPF will be set" "0: The compare function Disabled,1: The compare function Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. "RLDEN,Reload Function Enable Bit \nSetting this bit to enable the reload function" "0: The reload function Disabled,1: The reload function Enabled"
|
|
bitfld.long 0x00 26. "CPTCLR,Input Capture Counter Cleared By Capture Events Control\nIf this bit is set to 1 the capture counter (ECAP_CNT) will be cleared to zero when any one of capture events (CAPF0~3) occurs" "0: Capture events (CAPF0~3) can clear capture..,1: Capture events (CAPF0~3) can clear capture.."
|
|
newline
|
|
bitfld.long 0x00 25. "CMPCLR,Input Capture Counter Cleared By Compare-Match Control\n" "0: Compare-match event (CAMCMPF) can clear..,1: Compare-match event (CAMCMPF) can clear.."
|
|
bitfld.long 0x00 24. "CNTEN,Input Capture Counter Start\nSetting this bit to 1 the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK)" "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
|
|
newline
|
|
bitfld.long 0x00 21. "CMPIEN,CMPF Trigger Input Capture Interrupt Enable Bit\n" "0: The flag CMPF can trigger Input Capture..,1: The flag CMPF can trigger Input Capture.."
|
|
bitfld.long 0x00 20. "OVIEN,OVF Trigger Input Capture Interrupt Enable Bit\n" "0: The flag OVUNF can trigger Input Capture..,1: The flag OVUNF can trigger Input Capture.."
|
|
newline
|
|
bitfld.long 0x00 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Bit\n" "0: The flag CAPF2 can trigger Input Capture..,1: The flag CAPF2 can trigger Input Capture.."
|
|
bitfld.long 0x00 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Bit\n" "0: The flag CAPF1 can trigger Input Capture..,1: The flag CAPF1 can trigger Input Capture.."
|
|
newline
|
|
bitfld.long 0x00 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Bit\n" "0: The flag CAPF0 can trigger Input Capture..,1: The flag CAPF0 can trigger Input Capture.."
|
|
bitfld.long 0x00 12.--13. "CAPSEL2,CAP2 Input Source Selection\n" "0: CAP2 input is from port pin IC2,1: CAP2 input is from signal CPO2 (Analog..,2: CAP2 input is from signal CHX of QEI..,3: CAP2 input is from signal ADCMPOx (ADC.."
|
|
newline
|
|
bitfld.long 0x00 10.--11. "CAPSEL1,CAP1 Input Source Selection\n" "0: CAP1 input is from port pin IC1,1: CAP1 input is from signal CPO1 (Analog..,2: CAP1 input is from signal CHB of QEI..,3: CAP1 input is from signal OPDO1 (OP1 digital.."
|
|
bitfld.long 0x00 8.--9. "CAPSEL0,CAP0 Input Source Selection\n" "0: CAP0 input is from port pin IC0,1: CAP0 input is from signal CPO0 (Analog..,2: CAP0 input is from signal CHA of QEI..,3: CAP0 input is from signal OPDO0 (OP0 digital.."
|
|
newline
|
|
bitfld.long 0x00 6. "CAPEN2,Port Pin IC2 Input To Input Capture Unit Enable Bit\n" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
|
|
bitfld.long 0x00 5. "CAPEN1,Port Pin IC1 Input To Input Capture Unit Enable Bit\n" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "CAPEN0,Port Pin IC0 Input To Input Capture Unit Enable Bit\n" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
|
|
bitfld.long 0x00 3. "CAPNF_DIS,Input Capture Noise Filter Disable Bit\n" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "NFDIS,Noise Filter Clock Pre-Divide Selection\nTo determine the sampling frequency of the Noise Filter clock \n" "0: CAP_CLK,1: CAP_CLK/2,2: CAP_CLK/4,3: CAP_CLK/16"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ECAP_CTL1,Input Capture Control Register 1"
|
|
bitfld.long 0x00 16.--17. "SRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source.\n" "0: CAP_CLK (default),1: CAP0,2: CAP1,3: CAP2"
|
|
bitfld.long 0x00 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[1:0].\n" "0: CAP_CLK/1,1: CAP_CLK/4,2: CAP_CLK/16,3: CAP_CLK/32,4: CAP_CLK/64,5: CAP_CLK/96,6: CAP_CLK/112,7: CAP_CLK/128"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "RLDSEL,ECAP_CNT Reload Trigger Source Selection\n" "0: CAPF0,1: CAPF1,2: CAPF2,?,4: OVF,?..."
|
|
bitfld.long 0x00 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture can detect falling edge change or rising edge change only or one of both edge changes" "0: Detect rising edge,1: Detect falling edge.\nDetect either rising or..,?..."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture can detect falling edge change only rising edge change only or one of both edge change \n" "0: Detect rising edge,1: Detect falling edge.\nDetect either rising or..,?..."
|
|
bitfld.long 0x00 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture can detect falling edge change only rising edge change only or one of both edge change \n" "0: Detect rising edge,1: Detect falling edge.\nDetect either rising or..,?..."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ECAP_STATUS,Input Capture Status Register"
|
|
bitfld.long 0x00 5. "OVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it" "0: No overflow occurs in ECAP_CNT,1: ECAP_CNT overflows"
|
|
bitfld.long 0x00 4. "CMPF,Input Capture Compare-Match Flag\nIf the input capture compare function is enabled the flag is set by hardware while capture counter (ECAP_CNT) up counts and reach to the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it" "0: ECAP_CNT does not match with ECAP_CNTCMP value,1: ECAP_CNT counts to the same as ECAP_CNTCMP.."
|
|
newline
|
|
bitfld.long 0x00 2. "CAPF2,Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input it will set flag CAPF2 to high" "0: No valid edge change is detected at CAP2 input,1: A valid edge change is detected at CAP2 input"
|
|
bitfld.long 0x00 1. "CAPF1,Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input it will set flag CAPF1 to high" "0: No valid edge change is detected at CAP1 input,1: A valid edge change is detected at CAP1 input"
|
|
newline
|
|
bitfld.long 0x00 0. "CAPF0,Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input it will set flag CAPF0 to high" "0: No valid edge change is detected at CAP0 input,1: A valid edge change is detected at CAP0 input"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "EMAC"
|
|
base ad:0x4000B000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EMAC_CAMCTL,CAM Comparison Control Register"
|
|
bitfld.long 0x00 4. "CMPEN,CAM Compare Enable\nThe CMPEN controls the enable of CAM comparison function for destination MAC address recognition" "0: CAM comparison function for destination MAC..,1: CAM comparison function for destination MAC.."
|
|
bitfld.long 0x00 3. "COMPEN,Complement CAM Comparison Enable\nThe COMPEN controls the complement of the CAM comparison result" "0: The CAM comparison result does not complement,1: The CAM comparison result complemented"
|
|
newline
|
|
bitfld.long 0x00 2. "ABP,Accept Broadcast Packet\nThe ABP controls the broadcast packet reception" "0: EMAC receives packet depends on the CAM..,1: EMAC receives all broadcast packets"
|
|
bitfld.long 0x00 1. "AMP,Accept Multicast Packet\nThe AMP controls the multicast packet reception" "0: EMAC receives packet depends on the CAM..,1: EMAC receives all multicast packets"
|
|
newline
|
|
bitfld.long 0x00 0. "AUP,Accept Unicast Packet\nThe AUP controls the unicast packet reception" "0: EMAC receives packet depends on the CAM..,1: EMAC receives all unicast packets"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ECAM_CAMEN,CAM Enable Register"
|
|
bitfld.long 0x00 0. "CAMxEN,CAM Entry X Enable Bit\nThe CAMxEN controls the validation of CAM entry x.\nThe CAM entry 13 14 and 15 are for PAUSE control frame transmission" "0: CAM entry x Disabled,1: CAM entry x Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EMAC_CAM0M,CAM0 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EMAC_CAM0L,CAM0 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "EMAC_CAM1M,CAM1 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EMAC_CAM1L,CAM1 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "EMAC_CAM2M,CAM2 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EMAC_CAM2L,CAM2 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EMAC_CAM3M,CAM3 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "EMAC_CAM3L,CAM3 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "EMAC_CAM4M,CAM4 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "EMAC_CAM4L,CAM4 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "EMAC_CAM5M,CAM5 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EMAC_CAM5L,CAM5 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "EMAC_CAM6M,CAM6 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "EMAC_CAM6L,CAM6 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "EMAC_CAM7M,CAM7 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EMAC_CAM7L,CAM7 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "EMAC_CAM8M,CAM8 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "EMAC_CAM8L,CAM8 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "EMAC_CAM9M,CAM9 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "EMAC_CAM9L,CAM9 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "EMAC_CAM10M,CAM10 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "EMAC_CAM10L,CAM10 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "EMAC_CAM11M,CAM11 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "EMAC_CAM11L,CAM11 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "EMAC_CAM12M,CAM12 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "EMAC_CAM12L,CAM12 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "EMAC_CAM13M,CAM13 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "EMAC_CAM13L,CAM13 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "EMAC_CAM14M,CAM14 Most Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR5,MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR4,MAC Address Byte 4"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MACADDR3,MAC Address Byte 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MACADDR2,MAC Address Byte 2"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "EMAC_CAM14L,CAM14 Least Significant Word Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MACADDR1,MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MACADDR0,MAC Address Byte 0"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "EMAC_CAM15MSB,CAM15 Most Significant Word Register"
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hexmask.long.word 0x00 16.--31. 1. "LENGTH,LENGTH Field Of PAUSE Control Frame\nIn the PAUSE control frame a LENGTH field defined and is 16 h8808"
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hexmask.long.word 0x00 0.--15. 1. "OPCODE,OP Code Field Of PAUSE Control Frame\nIn the PAUSE control frame an op code field defined and is 16 h0001"
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group.long 0x84++0x03
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line.long 0x00 "EMAC_CAM15LSB,CAM15 Least Significant Word Register"
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hexmask.long.byte 0x00 24.--31. 1. "OPERAND,Pause Parameter\nIn the PAUSE control frame an OPERAND field defined and controls how much time the destination Ethernet MAC Controller paused"
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group.long 0x88++0x03
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line.long 0x00 "EMAC_TXDSA,Transmit Descriptor Link List Start Address Register"
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hexmask.long 0x00 0.--31. 1. "TXDSA,Transmit Descriptor Link-List Start Address\nThe TXDSA keeps the start address of transmit descriptor link-list"
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group.long 0x8C++0x03
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line.long 0x00 "EMAC_RXDSA,Receive Descriptor Link List Start Address Register"
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hexmask.long 0x00 0.--31. 1. "RXDSA,Receive Descriptor Link-List Start Address\nThe RXDSA keeps the start address of receive descriptor link-list"
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group.long 0x90++0x03
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line.long 0x00 "EMAC_CTL,MAC Control Register"
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bitfld.long 0x00 24. "RST,Software Reset\nThe RST implements a reset function to make the EMAC return default state" "0: Software reset completed,1: Software reset Enabled"
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bitfld.long 0x00 22. "RMIIEN,RMII Mode Enable\nThis bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII interface or RMII interface" "0: Ethernet MAC controller MII mode Enabled,1: Ethernet MAC controller RMII mode Enabled"
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bitfld.long 0x00 20. "OPMODE,Operation Mode Selection\nThe OPMODE defines that if the EMAC is operating on 10M or 100M bps mode" "0: EMAC operates in 10Mbps mode,1: EMAC operates in 100Mbps mode"
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bitfld.long 0x00 19. "RMIIRXCTL,RMII RX Control\nThe RMIIRXCTL control the receive data sample in RMII mode" "0: RMII RX control disabled,1: RMII RX control enabled"
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bitfld.long 0x00 18. "FUDUP,Full Duplex Mode Selection\nThe FUDUP controls that if EMAC is operating on full or half duplex mode.\n" "0: EMAC operates in half duplex mode,1: EMAC operates in full duplex mode"
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bitfld.long 0x00 17. "SQECHKEN,SQE Checking Enable\nThe SQECHKEN controls the enable of SQE checking" "0: SQE checking Disabled while EMAC is operating..,1: SQE checking Enabled while EMAC is operating.."
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bitfld.long 0x00 16. "SDPZ,Send PAUSE Frame\nThe SDPZ controls the PAUSE control frame transmission.\nIf S/W wants to send a PAUSE control frame out the CAM entry 13 14 and 15 must be configured first and the corresponding CAM enable bit of CAMEN register also must be set" "0: PAUSE control frame transmission completed,1: PAUSE control frame transmission Enabled"
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bitfld.long 0x00 9. "NODEF,No Deferral\nThe NODEF controls the enable of deferral exceed counter" "0: The deferral exceed counter Enabled,1: The deferral exceed counter Disabled"
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bitfld.long 0x00 8. "TXON,Frame Transmission ON\nThe TXON controls the normal packet transmission of EMAC" "0: Packet transmission process stopped,1: Packet transmission process started"
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bitfld.long 0x00 6. "WOLEN,Wake On LAN Enable\nThe WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet is Magic Packet and wakeup system from Power-down mode.\nIf incoming packet was a Magic Packet and the system was in.." "0: Wake-up by Magic Packet function Disabled,1: Wake-up by Magic Packet function Enabled"
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bitfld.long 0x00 5. "STRIPCRC,Strip CRC Checksum\nThe STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum" "0: The 4 bytes CRC checksum is included in..,1: The 4 bytes CRC checksum is excluded in.."
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bitfld.long 0x00 4. "AEP,Accept CRC Error Packet\nThe AEP controls the EMAC accepts or drops the CRC error packet" "0: Ethernet MAC controller dropped the CRC error..,1: Ethernet MAC controller received the CRC.."
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bitfld.long 0x00 3. "ACP,Accept Control Packet\nThe ACP controls the control frame reception" "0: Ethernet MAC controller dropped the control..,1: Ethernet MAC controller received the control.."
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bitfld.long 0x00 2. "ARP,Accept Runt Packet\nThe ARP controls the runt packet which length is less than 64 bytes reception" "0: Ethernet MAC controller dropped the runt packet,1: Ethernet MAC controller received the runt.."
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bitfld.long 0x00 1. "ALP,Accept Long Packet\nThe ALP controls the long packet which packet length is greater than 1518 bytes reception" "0: Ethernet MAC controller dropped the long packet,1: Ethernet MAC controller received the long.."
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bitfld.long 0x00 0. "RXON,Frame Reception ON\nThe RXON controls the normal packet reception of EMAC" "0: Packet reception process stopped,1: Packet reception process started"
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group.long 0x94++0x03
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line.long 0x00 "EMAC_MIIMDAT,MII Management Data Register"
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hexmask.long.word 0x00 0.--15. 1. "DATA,MII Management Data\nThe DATA is the 16 bits data that will be written into the registers of external PHY for MII Management write command or the data from the registers of external PHY for MII Management read command"
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group.long 0x98++0x03
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line.long 0x00 "EMAC_MIIMCTL,MII Management Control and Address Register"
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bitfld.long 0x00 19. "MDCON,MDC Clock ON\nThe MDC controls the MDC clock generation" "0: MDC clock off,1: MDC clock on"
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bitfld.long 0x00 18. "PREAMSP,Preamble Suppress\nThe PREAMSP controls the preamble field generation of MII management frame" "0: Preamble field generation of MII management..,1: Preamble field generation of MII management.."
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bitfld.long 0x00 17. "BUSY,Busy Bit\nThe BUSY controls the enable of the MII management frame generation" "0: MII management command generation finished,1: MII management command generation Enabled"
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bitfld.long 0x00 16. "WRITE,Write Command\nThe Write defines the MII management command is a read or write.\n" "0: MII management command is a read command,1: MII management command is a write command"
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bitfld.long 0x00 8.--12. "PHYADDR,PHY Address\nThe PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "PHYREG,PHY Register Address\nThe PHYREG keeps the address to indicate which register of external PHY is the target of the MII management command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x9C++0x03
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line.long 0x00 "EMAC_FIFOCTL,FIFO Threshold Control Register"
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bitfld.long 0x00 20.--21. "BURSTLEN,DMA Burst Length\nThis defines the burst length of AHB bus cycle while EMAC accesses system memory.\n" "0: 16 words,1: 16 words,2: 8 words,3: 4 words"
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bitfld.long 0x00 8.--9. "TXFIFOTH,TXFIFO Low Threshold\nThe TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system memory and TXFIFO" "0: Undefined,1: TXFIFO low threshold is 64B and high..,2: TXFIFO low threshold is 80B and high..,3: TXFIFO low threshold is 96B and high.."
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bitfld.long 0x00 0.--1. "RXFIFOTH,RXFIFO Low Threshold\nThe RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO and system memory" "0: Depend on the burst length setting,1: RXFIFO high threshold is 64B and low..,2: RXFIFO high threshold is 128B and low..,3: RXFIFO high threshold is 192B and low.."
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wgroup.long 0xA0++0x03
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line.long 0x00 "EMAC_TXST,Transmit Start Demand Register"
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hexmask.long 0x00 0.--31. 1. "TXST,Transmit Start Demand\nIf the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted"
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wgroup.long 0xA4++0x03
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line.long 0x00 "EMAC_RXST,Receive Start Demand Register"
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hexmask.long 0x00 0.--31. 1. "RXST,Receive Start Demand\nIf the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted"
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group.long 0xA8++0x03
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line.long 0x00 "EMAC_MRFL,Maximum Receive Frame Control Register"
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hexmask.long.word 0x00 0.--15. 1. "MRFL,Maximum Receive Frame Length\nThe MRFL defines the maximum frame length for received frame"
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group.long 0xAC++0x03
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line.long 0x00 "EMAC_INTEN,MAC Interrupt Enable Register"
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bitfld.long 0x00 28. "TSALMIEN,Time Stamp Alarm Interrupt Enable Bit\nThe TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation" "0: TXTSALMIF (EMAC_INTSTS[28]) trigger TX..,1: TXTSALMIF (EMAC_INTSTS[28]) trigger TX.."
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bitfld.long 0x00 24. "TXBEIEN,Transmit Bus Error Interrupt Enable Bit\nThe TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation" "0: TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt..,1: TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt.."
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bitfld.long 0x00 23. "TDUIEN,Transmit Descriptor Unavailable Interrupt Enable Bit\nThe TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation" "0: TDUIF (EMAC_INTSTS[23]) trigger TX interrupt..,1: TDUIF (EMAC_INTSTS[23]) trigger TX interrupt.."
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bitfld.long 0x00 22. "LCIEN,Late Collision Interrupt Enable Bit\nThe LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation" "0: LCIF (EMAC_INTSTS[22]) trigger TX interrupt..,1: LCIF (EMAC_INTSTS[22]) trigger TX interrupt.."
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bitfld.long 0x00 21. "TXABTIEN,Transmit Abort Interrupt Enable Bit\nThe TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation" "0: TXABTIF (EMAC_INTSTS[21]) trigger TX..,1: TXABTIF (EMAC_INTSTS[21]) trigger TX.."
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bitfld.long 0x00 20. "NCSIEN,No Carrier Sense Interrupt Enable Bit\nThe NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation" "0: NCSIF (EMAC_INTSTS[20]) trigger TX interrupt..,1: NCSIF (EMAC_INTSTS[20]) trigger TX interrupt.."
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bitfld.long 0x00 19. "EXDEFIEN,Defer Exceed Interrupt Enable Bit\nThe EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation" "0: EXDEFIF (EMAC_INTSTS[19]) trigger TX..,1: EXDEFIF (EMAC_INTSTS[19]) trigger TX.."
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bitfld.long 0x00 18. "TXCPIEN,Transmit Completion Interrupt Enable Bit\nThe TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation" "0: TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt..,1: TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt.."
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bitfld.long 0x00 17. "TXUDIEN,Transmit FIFO Underflow Interrupt Enable Bit\nThe TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation" "0: TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled,1: TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled"
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bitfld.long 0x00 16. "TXIEN,Transmit Interrupt Enable Bit\nThe TXIEN controls the TX interrupt generation.\nIf TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high EMAC generates the TX interrupt to CPU" "0: TXIF (EMAC_INTSTS[16]) is masked and TX..,1: TXIF (EMAC_INTSTS[16]) is not masked and TX.."
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bitfld.long 0x00 15. "WOLIEN,Wake On LAN Interrupt Enable\nThe WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation" "0: WOLIF (EMAC_INTSTS[15]) trigger RX interrupt..,1: WOLIF (EMAC_INTSTS[15]) trigger RX interrupt.."
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bitfld.long 0x00 14. "CFRIEN,Control Frame Receive Interrupt Enable Bit\nThe CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation" "0: CFRIF (EMAC_INTSTS[14]) trigger RX interrupt..,1: CFRIF (EMAC_INTSTS[14]) trigger RX interrupt.."
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bitfld.long 0x00 11. "RXBEIEN,Receive Bus Error Interrupt Enable Bit\nThe RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation" "0: RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt..,1: RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt.."
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bitfld.long 0x00 10. "RDUIEN,Receive Descriptor Unavailable Interrupt Enable Bit\nThe RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation" "0: RDUIF (EMAC_INTSTS[10]) trigger RX interrupt..,1: RDUIF (EMAC_INTSTS[10]) trigger RX interrupt.."
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bitfld.long 0x00 9. "DENIEN,DMA Early Notification Interrupt Enable Bit\nThe DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation" "0: TDENIF (EMAC_INTSTS[9]) trigger RX interrupt..,1: TDENIF (EMAC_INTSTS[9]) trigger RX interrupt.."
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bitfld.long 0x00 8. "MFLEIEN,Maximum Frame Length Exceed Interrupt Enable\nThe MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation" "0: MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt..,1: MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt.."
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bitfld.long 0x00 7. "MPCOVIEN,Miss Packet Counter Overrun Interrupt Enable\nThe MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation" "0: MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt..,1: MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt.."
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bitfld.long 0x00 6. "RPIEN,Runt Packet Interrupt Enable Bit\nThe RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation" "0: RPIF (EMAC_INTSTS[6]) trigger RX interrupt..,1: RPIF (EMAC_INTSTS[6]) trigger RX interrupt.."
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bitfld.long 0x00 5. "ALIEIEN,Alignment Error Interrupt Enable Bit\nThe ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation" "0: ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt..,1: ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt.."
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bitfld.long 0x00 4. "RXGDIEN,Receive Good Interrupt Enable Bit\nThe RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation" "0: RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt..,1: RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt.."
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bitfld.long 0x00 3. "LPIEN,Long Packet Interrupt Enable\nThe LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation" "0: LPIF (EMAC_INTSTS[3]) trigger RX interrupt..,1: LPIF (EMAC_INTSTS[3]) trigger RX interrupt.."
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bitfld.long 0x00 2. "RXOVIEN,Receive FIFO Overflow Interrupt Enable Bit\nThe RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation" "0: RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt..,1: RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt.."
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bitfld.long 0x00 1. "CRCEIEN,CRC Error Interrupt Enable Bit\nThe CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation" "0: CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt..,1: CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt.."
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bitfld.long 0x00 0. "RXIEN,Receive Interrupt Enable Bit\nThe RXIEN controls the RX interrupt generation.\nIf RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high EMAC generates the RX interrupt to CPU" "0: RXIF (EMAC_INTSTS[0]) is masked and RX..,1: RXIF (EMAC_INTSTS[0]) is not masked and RX.."
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group.long 0xB0++0x03
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line.long 0x00 "EMAC_INTSTS,MAC Interrupt Status Register"
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bitfld.long 0x00 28. "TSALMIF,Time Stamp Alarm Interrupt\nThe TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and EMAC_TSSUBSEC register value equals to register EMAC_TSMLSR.\nIf TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled the.." "0: EMAC_TSSEC did not equal EMAC_ALMSEC or..,1: EMAC_TSSEC equals EMAC_ALMSEC and.."
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bitfld.long 0x00 24. "TXBEIF,Transmit Bus Error Interrupt\nThe TXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through TXDMA during packet transmission process" "0: No ERROR response is received,1: ERROR response is received"
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bitfld.long 0x00 23. "TDUIF,Transmit Descriptor Unavailable Interrupt\nThe TDUIF high indicates that there is no available TX descriptor for packet transmission and TXDMA will stay at Halt state" "0: TX descriptor is available,1: TX descriptor is unavailable"
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bitfld.long 0x00 22. "LCIF,Late Collision Interrupt\nThe LCIF high indicates the collision occurred in the outside of 64 bytes collision window" "0: No collision occurred in the outside of 64..,1: Collision occurred in the outside of 64 bytes.."
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bitfld.long 0x00 21. "TXABTIF,Transmit Abort Interrupt\nThe TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission and then the transmission process for this packet is aborted" "0: Packet does not incur 16 consecutive..,1: Packet incurred 16 consecutive collisions.."
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bitfld.long 0x00 20. "NCSIF,No Carrier Sense Interrupt\nThe NCSIF high indicates the MII I/F signal CRS does not active at the start of or during the packet transmission" "0: CRS signal actives correctly,1: CRS signal does not active at the start of or.."
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bitfld.long 0x00 19. "EXDEFIF,Defer Exceed Interrupt\nThe EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps mode or 3.2768ms on 10Mbps mode" "0: Frame waiting for transmission has not..,1: Frame waiting for transmission has deferred.."
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bitfld.long 0x00 18. "TXCPIF,Transmit Completion Interrupt\nThe TXCPIF indicates the packet transmission has completed correctly.\nIf the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled the TXIF will be high" "0: The packet transmission not completed,1: The packet transmission has completed"
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bitfld.long 0x00 17. "TXUDIF,Transmit FIFO Underflow Interrupt\nThe TXUDIF high indicates the TXFIFO underflow occurred during packet transmission" "0: No TXFIFO underflow occurred during packet..,1: TXFIFO underflow occurred during packet.."
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bitfld.long 0x00 16. "TXIF,Transmit Interrupt\nThe TXIF indicates the TX interrupt status.\nIf TXIF high and its corresponding enable bit TXIEN (EMAC_INTEN[16]) is also high indicates the EMAC generates TX interrupt to CPU" "0: No status bit in EMAC_INTSTS[28:17] is set or..,1: At least one status in EMAC_INTSTS[28:17] is.."
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bitfld.long 0x00 15. "WOLIF,Wake On LAN Interrupt Flag\nThe WOLIF high indicates EMAC receives a Magic Packet" "0: The EMAC does not receive the Magic Packet,1: The EMAC receives a Magic Packet"
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bitfld.long 0x00 14. "CFRIF,Control Frame Receive Interrupt\nThe CFRIF high indicates EMAC receives a flow control frame" "0: The EMAC does not receive the flow control..,1: The EMAC receives a flow control frame"
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bitfld.long 0x00 11. "RXBEIF,Receive Bus Error Interrupt\nThe RXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through RXDMA during packet reception process" "0: No ERROR response is received,1: ERROR response is received"
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bitfld.long 0x00 10. "RDUIF,Receive Descriptor Unavailable Interrupt\nThe RDUIF high indicates that there is no available RX descriptor for packet reception and RXDMA will stay at Halt state" "0: RX descriptor is available,1: RX descriptor is unavailable"
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bitfld.long 0x00 9. "DENIF,DMA Early Notification Interrupt\nThe DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.\nIf the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled the RXIF will be high" "0: The LENGTH field of incoming packet has not..,1: The LENGTH field of incoming packet has.."
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bitfld.long 0x00 8. "MFLEIF,Maximum Frame Length Exceed Interrupt Flag\nThe MFLEIF high indicates the length of the incoming packet has exceeded the length limitation configured in DMARFC register and the incoming packet is dropped" "0: The length of the incoming packet does not..,1: The length of the incoming packet has.."
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bitfld.long 0x00 7. "MPCOVIF,Missed Packet Counter Overrun Interrupt Flag\nThe MPCOVIF high indicates the MPCNT Missed Packet Count has overflow" "0: The MPCNT has not rolled over yet,1: The MPCNT has rolled over yet"
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bitfld.long 0x00 6. "RPIF,Runt Packet Interrupt\nThe RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped" "0: The incoming frame is not a short frame or..,1: The incoming frame is a short frame and dropped"
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bitfld.long 0x00 5. "ALIEIF,Alignment Error Interrupt\nThe ALIEIF high indicates the length of the incoming frame is not a multiple of byte" "0: The frame length is a multiple of byte,1: The frame length is not a multiple of byte"
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bitfld.long 0x00 4. "RXGDIF,Receive Good Interrupt\nThe RXGDIF high indicates the frame reception has completed.\nIf the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled the RXIF will be high" "0: The frame reception has not complete yet,1: The frame reception has completed"
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bitfld.long 0x00 3. "LPIF,Long Packet Interrupt Flag\nThe LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped" "0: The incoming frame is not a long frame or S/W..,1: The incoming frame is a long frame and dropped"
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bitfld.long 0x00 2. "RXOVIF,Receive FIFO Overflow Interrupt\nThe RXOVIF high indicates the RXFIFO overflow occurred during packet reception" "0: No RXFIFO overflow occurred during packet..,1: RXFIFO overflow occurred during packet.."
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bitfld.long 0x00 1. "CRCEIF,CRC Error Interrupt\nThe CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped" "0: The frame does not incur CRC error,1: The frame incurred CRC error"
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bitfld.long 0x00 0. "RXIF,Receive Interrupt\nThe RXIF indicates the RX interrupt status.\nIf RXIF high and its corresponding enable bit RXIEN (EMAC_INTEN[0]) is also high indicates the EMAC generates RX interrupt to CPU" "0: No status bit in EMAC_INTSTS[15:1] is set or..,1: At least one status in EMAC_INTSTS[15:1] is.."
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group.long 0xB4++0x03
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line.long 0x00 "EMAC_GENSTS,MAC General Status Register"
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bitfld.long 0x00 12. "RPSTS,Remote Pause Status\nThe RPSTS indicates that remote pause counter down counting actives.\nAfter Ethernet MAC controller sent PAUSE frame out successfully it starts the remote pause counter down counting" "0: Remote pause counter down counting done,1: Remote pause counter down counting actives"
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bitfld.long 0x00 11. "TXHALT,Transmission Halted\nThe TXHALT high indicates the next normal packet transmission process will be halted because the bit TXON (EMAC_CTL[8]) is disabled be S/W.\n" "0: Next normal packet transmission process will..,1: Next normal packet transmission process will.."
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bitfld.long 0x00 10. "SQE,Signal Quality Error\nThe SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode" "0: No SQE error found at end of packet..,1: SQE error found at end of packet transmission"
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bitfld.long 0x00 9. "TXPAUSED,Transmission Paused\nThe TXPAUSED high indicates the next normal packet transmission process will be paused temporally because EMAC received a PAUSE control frame.\n" "0: Next normal packet transmission process will..,1: Next normal packet transmission process will.."
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bitfld.long 0x00 8. "DEF,Deferred Transmission\nThe DEF high indicates the packet transmission has deferred once" "0: Packet transmission does not defer,1: Packet transmission has deferred once"
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bitfld.long 0x00 4.--7. "COLCNT,Collision Count\nThe COLCNT indicates that how many collisions occurred consecutively during a packet transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2. "RXFFULL,RXFIFO Full\nThe RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO and the following incoming packet will be dropped.\n" "0: The RXFIFO is not full,1: The RXFIFO is full and the following incoming.."
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bitfld.long 0x00 1. "RXHALT,Receive Halted\nThe RXHALT high indicates the next normal packet reception process will be halted because the bit RXON of MCMDR is disabled be S/W.\n" "0: Next normal packet reception process will go on,1: Next normal packet reception process will be.."
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bitfld.long 0x00 0. "CFR,Control Frame Received\nThe CFRIF high indicates EMAC receives a flow control frame" "0: The EMAC does not receive the flow control..,1: The EMAC receives a flow control frame"
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group.long 0xB8++0x03
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line.long 0x00 "EMAC_MPCNT,Missed Packet Count Register"
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hexmask.long.word 0x00 0.--15. 1. "MPCNT,Miss Packet Count\nThe MPCNT indicates the number of packets that were dropped due to various types of receive errors"
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rgroup.long 0xBC++0x03
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line.long 0x00 "EMAC_RPCNT,MAC Receive Pause Count Register"
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|
hexmask.long.word 0x00 0.--15. 1. "RPCNT,MAC Receive Pause Count\nThe RPCNT keeps the OPERAND field of the PAUSE control frame"
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group.long 0xC8++0x03
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line.long 0x00 "EMAC_FRSTS,DMA Receive Frame Status Register"
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hexmask.long.word 0x00 0.--15. 1. "RXFLT,Receive Frame LENGTH\nThe RXFLT keeps the LENGTH field of each incoming Ethernet packet"
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rgroup.long 0xCC++0x03
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line.long 0x00 "EMAC_CTXDSA,Current Transmit Descriptor Start Address Register"
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hexmask.long 0x00 0.--31. 1. "CTXDSA,Current Transmit Descriptor Start Address\nThe CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently"
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rgroup.long 0xD0++0x03
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line.long 0x00 "EMAC_CTXBSA,Current Transmit Buffer Start Address Register"
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hexmask.long 0x00 0.--31. 1. "CTXBSA,Current Transmit Buffer Start Address\nThe CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently"
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|
rgroup.long 0xD4++0x03
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line.long 0x00 "EMAC_CRXDSA,Current Receive Descriptor Start Address Register"
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hexmask.long 0x00 0.--31. 1. "CRXDSA,Current Receive Descriptor Start Address\nThe CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently"
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rgroup.long 0xD8++0x03
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line.long 0x00 "EMAC_CRXBSA,Current Receive Buffer Start Address Register"
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hexmask.long 0x00 0.--31. 1. "CRXBSA,Current Receive Buffer Start Address\nThe CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently"
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group.long 0x100++0x03
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line.long 0x00 "EMAC_TSCTL,Time Stamp Control Register"
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bitfld.long 0x00 5. "TSALMEN,Time Stamp Alarm Enable Bit\nSet this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.\n" "0: Alarm disabled when EMAC_TSSEC equals to..,1: Alarm enabled when EMAC_TSSEC equals to.."
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bitfld.long 0x00 3. "TSUPDATE,Time Stamp Counter Time Update Enable Bit\nSet this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stamp counter.\nAfter the add operation finished Ethernet MAC controller clear this.." "0: No action,1: EMAC_UPDSEC updated to EMAC_TSSEC and.."
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bitfld.long 0x00 2. "TSMODE,Time Stamp Fine Update Enable Bit\nThis bit chooses the time stamp counter update mode.\n" "0: Time stamp counter is in coarse update mode,1: Time stamp counter is in fine update mode"
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bitfld.long 0x00 1. "TSIEN,Time Stamp Counter Initialization Enable Bit\nSet this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stampe counter.\nAfter the load operation finished Ethernet MAC controller clear.." "0: Time stamp counter initialization done,1: Time stamp counter initialization Enabled"
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bitfld.long 0x00 0. "TSEN,Time Stamp Function Enable Bit\nThis bit controls if the IEEE 1588 PTP time stamp function is enabled or not.\nSet this bit high to enable IEEE 1588 PTP time stamp function while set this bit low to disable IEEE 1588 PTP time stamp function.\n" "0: I EEE 1588 PTP time stamp function Disabled,1: IEEE 1588 PTP time stamp function Enabled"
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rgroup.long 0x110++0x03
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line.long 0x00 "EMAC_TSSEC,Time Stamp Counter Second Register"
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hexmask.long 0x00 0.--31. 1. "SEC,Time Stamp Counter Second\nThis register reflects the bit [63:32] value of 64-bit reference timing counter"
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rgroup.long 0x114++0x03
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line.long 0x00 "EMAC_TSSUBSEC,Time Stamp Counter Sub Second Register"
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hexmask.long 0x00 0.--31. 1. "SUBSEC,Time Stamp Counter Sub-Second\nThis register reflects the bit [31:0] value of 64-bit reference timing counter"
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group.long 0x118++0x03
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line.long 0x00 "EMAC_TSINC,Time Stamp Increment Register"
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hexmask.long.byte 0x00 0.--7. 1. "CNTINC,Time Stamp Counter Increment\nTime stamp counter increment value.\nIf TSEN (EMAC_TSCTL[0]) is high EMAC adds EMAC_TSSUBSEC with this 8-bit value every time when it wants to increase the EMAC_TSSUBSEC value"
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group.long 0x11C++0x03
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line.long 0x00 "EMAC_TSADDEND,Time Stamp Addend Register"
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hexmask.long 0x00 0.--31. 1. "ADDEND,Time Stamp Counter Addend\nThis register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.\nIf TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high EMAC increases accumulator with this 32-bit value in each HCLK"
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group.long 0x120++0x03
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line.long 0x00 "EMAC_UPDSEC,Time Stamp Update Second Register"
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hexmask.long 0x00 0.--31. 1. "SEC,Time Stamp Counter Second Update\nWhen TSIEN (EMAC_TSCTL[1]) is high"
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group.long 0x124++0x03
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line.long 0x00 "EMAC_UPDSUBSEC,Time Stamp Update Sub Second Register"
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hexmask.long 0x00 0.--31. 1. "SUBSEC,Time Stamp Counter Sub-Second Update\nWhen TSIEN (EMAC_TSCTL[1]) is high"
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group.long 0x128++0x03
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line.long 0x00 "EMAC_ALMSEC,Time Stamp Alarm Second Register"
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hexmask.long 0x00 0.--31. 1. "SEC,Time Stamp Counter Second Alarm\nTime stamp counter second part alarm value.\nThis value is only useful when ALMEN (EMAC_TSCTL[5]) high"
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group.long 0x12C++0x03
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line.long 0x00 "EMAC_ALMSUBSEC,Time Stamp Alarm Sub Second Register"
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hexmask.long 0x00 0.--31. 1. "SUBSEC,Time Stamp Counter Sub-Second Alarm\nTime stamp counter sub-second part alarm value.\nThis value is only useful when ALMEN (EMAC_TSCTL[5]) high"
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tree.end
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tree "EPWM"
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tree "EPWM0"
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base ad:0x4005C000
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group.long 0x00++0x03
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line.long 0x00 "EPWM_CTL,PWM Control Register"
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bitfld.long 0x00 31. "CTRLD,Center Reload Mode Enable Bit\nThis bit only work when EPWM operation at center aligned mode" "0: EPWM reload compare register at the period..,1: EPWM reload compare register at the center.."
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bitfld.long 0x00 29. "BRK1NFDIS,PWM Brake 1 Noise Filter Disable Bit\n" "0: Noise filter of PWM Brake 1 Enabled,1: Noise filter of PWM Brake 1 Disabled"
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bitfld.long 0x00 28. "BRK0NFDIS,PWM Brake 0 Noise Filter Disable Bit\n" "0: Noise filter of PWM Brake 0 Enabled,1: Noise filter of PWM Brake 0 Disabled"
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bitfld.long 0x00 27. "LVDBKEN,Low-Level Detection Trigger PWM Brake Function 1 Enable Bit\n" "0: Brake Function 1 triggered by Low-level..,1: Brake Function 1 triggered by Low-level.."
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bitfld.long 0x00 26. "CPO2BKEN,CPO2 Digital Output As Brake 0 Source Enable Bit\n" "0: CPO2 as one brake source in Brake 0 Disabled,1: CPO2 as one brake source in Brake 0 Enabled"
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bitfld.long 0x00 25. "CPO1BKEN,CPO1 Digital Output As Brake 0 Source Enable Bit\n" "0: CPO1 as one brake source in Brake 0 Disabled,1: CPO1 as one brake source in Brake 0 Enabled"
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bitfld.long 0x00 24. "CPO0BKEN,CPO0 Digital Output As Brake0 Source Enable Bit\n" "0: CPO0 as one brake source in Brake 0 Disabled,1: CPO0 as one brake source in Brake 0 Enabled"
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bitfld.long 0x00 22.--23. "BRK1NFSEL,Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/16"
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bitfld.long 0x00 20.--21. "BRK0NFSEL,Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/16"
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bitfld.long 0x00 18.--19. "BRK1SEL,Brake Function 1 Source Selection\n" "0: From external pin BKPx1 (x=0~1 for unit0~1),1: From analog comparator 0 output (CPO0),2: From analog comparator 1 output (CPO1),3: From analog comparator 2 output (CPO2)"
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bitfld.long 0x00 17. "BRKP1EN,BKPx1 Pin Trigger Brake Function Enable Bit\n" "0: PWMx Brake Function 1 Disabled,1: PWMx Brake Function 1 Enabled"
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bitfld.long 0x00 16. "BRKP0EN,BKPx0 Pin Trigger Brake Function0 Enable Bit\n" "0: PWMx Brake Function 0 Disabled,1: PWMx Brake Function 0 Enabled"
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bitfld.long 0x00 15. "BRKP1INV,Inverse BKP1 State\n" "0: The state of pin BKPx1 is passed to the..,1: The inversed state of pin BKPx1 is passed to.."
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bitfld.long 0x00 14. "BRKP0INV,Inverse BKP0 State\n" "0: The state of pin BKPx0 is passed to the..,1: The inversed state of pin BKPx0 is passed to.."
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bitfld.long 0x00 13. "GROUPEN,Group Bit\n" "0: The signals timing of EPWM_CMPDAT0..,1: Unify the signals timing of EPWM_CMPDAT0.."
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bitfld.long 0x00 12. "CNTTYPE,PWM Aligned Type Selection\n" "0: Edge-aligned type,1: Centre-aligned type"
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bitfld.long 0x00 11. "CNTCLR,Clear PWM Counter Control\nNote: It is automatically cleared by hardware" "?,1: Clear 16-bit PWM counter to 000H"
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bitfld.long 0x00 9. "PINV,Inverse PWM Comparator Output\nWhen PINV is set to high the PWM comparator output signals will be inversed therefore the PWM Duty (in percentage) is changed to (1-Duty) before PINV is set to high.\n" "0: Not inverse PWM comparator output,1: Inverse PWM comparator output"
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bitfld.long 0x00 8. "INTTYPE,PWM Interrupt Type Selection\nNote: This bit is effective when PWM in central align mode only" "0: PIF will be set if PWM counter underflow,1: PIF will be set if PWM counter matches.."
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bitfld.long 0x00 7. "CNTEN,Start CNTEN Control\n" "0: The PWM stops running,1: The PWM counter starts running"
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bitfld.long 0x00 6. "LOAD,Re-Load PWM Period Registers (EPWM_PERIOD) And PWM Compare Registers (EPWM_CMPDAT0~4) Control \nNote: This bit is software write hardware clear and always read zero" "0: No action if written with 0,1: Hardware will update the value of PWM period.."
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bitfld.long 0x00 5. "BRKIEN,Brake0 And Brak1 Interrupt Enable Bit\n" "0: Disabling flags BRKIF0 and BRKIF1 to trigger..,1: Enabling flags BRKIF0 and BRKIF1 can trigger.."
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bitfld.long 0x00 4. "PWMIEN,PWM Interrupt Enable Bit\n" "0: Disabling flag PIF to trigger PWM interrupt,1: Enabling flag PIF can trigger PWM interrupt"
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bitfld.long 0x00 2.--3. "CLKDIV,PWM Clock Pre-Divider Selection\n" "0: PWM clock = EPWM_CLK,1: PWM clock = EPWM_CLK/2,2: PWM clock = EPWM_CLK/4,3: PWM clock = EPWM_CLK/16"
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bitfld.long 0x00 0.--1. "MODE,PWM Mode Selection\n" "0: Independent mode,1: Pair/Complementary mode,2: Synchronized mode,3: Reserved"
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group.long 0x04++0x03
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line.long 0x00 "EPWM_STATUS,PWM Status Register"
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rbitfld.long 0x00 25. "BRK1STS,Brake 1 Status (Read Only)\n" "0: PWM had been out of Brake 1 state,1: PWM is in Brake 1 state"
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rbitfld.long 0x00 24. "BRK0STS,Brake 0 Status (Read Only)\n" "0: PWM had been out of Brake 0 state,1: PWM is in Brake 0 state"
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bitfld.long 0x00 8. "BRK0LOCK,PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to it" "0: Brake 0 state is released,1: When PWM Brake detects a falling signal at.."
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bitfld.long 0x00 6. "EIF4,PWMx_CH4 Edge Flag\nNote: This bit must be cleared by writing 1 to it" "0: The PWMx_CH4 doesn't toggle,1: Hardware will set this flag to high at the.."
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bitfld.long 0x00 5. "EIF2,PWMx_CH2 Edge Flag\nNote: This bit must be cleared by writing 1 to it" "0: The PWMx_CH2 doesn't toggle,1: Hardware will set this flag to high at the.."
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bitfld.long 0x00 4. "EIF0,PWMx_CH0 Edge Flag\nNote: This bit must be cleared by writing 1 to it" "0: The PWMx_CH0 doesn't toggle,1: Hardware will set this flag to high at the.."
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bitfld.long 0x00 2. "PIF,PWM Period Flag\nNote: This bit must be cleared by writing 1 to it" "0: PWM Counter has not up counted to the value..,1: Hardware will set this flag to high at the.."
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bitfld.long 0x00 1. "BRKIF1,PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to it" "0: PWM Brake 1 is able to poll falling signal at..,1: When PWM Brake 1 detects a falling signal at.."
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bitfld.long 0x00 0. "BRKIF0,PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to it" "0: PWM Brake 0 is able to poll falling signal at..,1: When PWM Brake 0 detects a falling signal at.."
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group.long 0x08++0x03
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line.long 0x00 "EPWM_PERIOD,PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nEdge aligned:\n"
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group.long 0x0C++0x03
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line.long 0x00 "EPWM_CMPDAT0,EPWM_CMPDAT0 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Duty Register\nEdge aligned:\n"
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group.long 0x10++0x03
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line.long 0x00 "EPWM_CMPDAT2,EPWM_CMPDAT2 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Duty Register\nEdge aligned:\n"
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group.long 0x14++0x03
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line.long 0x00 "EPWM_CMPDAT4,EPWM_CMPDAT4 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Duty Register\nEdge aligned:\n"
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group.long 0x18++0x03
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line.long 0x00 "EPWM_MSKEN,PWM Mask Mode Enable Control Register"
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bitfld.long 0x00 0.--5. "MSKEN,PWM Mask Enable Bits\nThe PWM generator signal will be masked when this bit is enabled" "0: PWM generator signal is output to next stage,1: PWM generator signal is masked and..,?..."
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group.long 0x1C++0x03
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line.long 0x00 "EPWM_MSK,PWM Mask Mode Data Register"
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bitfld.long 0x00 0.--5. "MSKDAT,PWM Mask Data Bit\n" "0: Output logic low to EPWM_CHn,1: Output logic high to EPWM_CHn,?..."
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group.long 0x20++0x03
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line.long 0x00 "EPWM_ASYMCMP0,Asymmetric EPWM_CMPDAT0 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,Asymmetric PWM Duty Register\nWhen the asymmetric PWM function is enabled this 16-bit field determines the second time compared value after PWM counter has matched with EPWM_CMPDATx in the first half PWM cycle"
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group.long 0x24++0x03
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line.long 0x00 "EPWM_ASYMCMP2,Asymmetric EPWM_CMPDAT2 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,Asymmetric PWM Duty Register\nWhen the asymmetric PWM function is enabled this 16-bit field determines the second time compared value after PWM counter has matched with EPWM_CMPDATx in the first half PWM cycle"
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group.long 0x28++0x03
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line.long 0x00 "EPWM_ASYMCMP4,Asymmetric EPWM_CMPDAT4 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,Asymmetric PWM Duty Register\nWhen the asymmetric PWM function is enabled this 16-bit field determines the second time compared value after PWM counter has matched with EPWM_CMPDATx in the first half PWM cycle"
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group.long 0x2C++0x03
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line.long 0x00 "EPWM_DTCTL,PWM Dead-time Control Register"
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bitfld.long 0x00 18. "DTEN4,Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH4 PWM_CH5)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair..,1: Dead-time insertion Enabled on the pin pair.."
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bitfld.long 0x00 17. "DTEN2,Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH2 PWM_CH3)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair..,1: Dead-time insertion Enabled on the pin pair.."
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bitfld.long 0x00 16. "DTEN0,Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH0 PWM_CH1)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair..,1: Dead-time insertion Enabled on the pin pair.."
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hexmask.long.word 0x00 0.--10. 1. "DTCNT,Dead-Time Counter\nThe dead-time can be calculated from the following formula: \n"
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group.long 0x30++0x03
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line.long 0x00 "EPWM_BRKOUT,PWM Brake Output"
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bitfld.long 0x00 0.--5. "BRKOUT,PWM Brake Output\nWhen PWM Brake is asserted the PWM_CH0~5 output state before polarity control will follow bit0~5 setting respectively.\n" "0: The PWM_CHn output before polarity control is..,1: The PWM_CHn output before polarity control is..,?..."
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group.long 0x34++0x03
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line.long 0x00 "EPWM_NPCTL,PWM Negative Polarity Control"
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bitfld.long 0x00 0.--5. "NEGPOLAR,PWM Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n" "0: PWM_CHn output is active high,1: PWM_CHn output is active low,?..."
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group.long 0x38++0x03
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line.long 0x00 "EPWM_ASYMCTL,Asymmetric PWM Control Register"
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bitfld.long 0x00 24.--25. "ASYMMODE4,Asymmetric PWMx_CH4 Reload Mode Setting\n" "0: 1,1: 1,2: 1,3: Reserved"
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bitfld.long 0x00 16.--17. "ASYMMODE2,Asymmetric PWMx_CH2 Reload Mode Setting\n" "0: 1,1: 1,2: 1,3: Reserved"
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newline
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bitfld.long 0x00 8.--9. "ASYMMODE0,Asymmetric PWMx_CH0 Reload Mode Setting\n" "0: 1,1: 1,2: 1,3: Reserved"
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bitfld.long 0x00 0. "ASYMEN,Asymmetric PWM Enable Bit\nNote: This control bit is only valid when PWM module is set in Centre-aligned mode" "0: Asymmetric PWM function Disabled,1: Asymmetric PWM function Enabled"
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group.long 0x3C++0x03
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line.long 0x00 "EPWM_PERIODCNT,PIF Compared Counter"
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bitfld.long 0x00 0.--3. "PERIODCNT,PIF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PIF to request the PWM period interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x40++0x03
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line.long 0x00 "EPWM_EINTCTL,PWM Edge Interrupt Control Register"
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bitfld.long 0x00 10. "EINTTYPE4,PWMx4 Edge Interrupt Type\n" "0: EIF4 will be set if falling edge is detected..,1: EIF4 will be set if rising edge is detected.."
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bitfld.long 0x00 9. "EINTTYPE2,PWMx2 Edge Interrupt Type\n" "0: EIF2 will be set if falling edge is detected..,1: EIF2 will be set if rising edge is detected.."
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bitfld.long 0x00 8. "EINTTYPE0,PWMx0 Edge Interrupt Type\n" "0: EIF0 will be set if falling edge is detected..,1: EIF0 will be set if rising edge is detected.."
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bitfld.long 0x00 2. "EDGEIEN4,PWMx4 Edge Interrupt Enable Bit\n" "0: Disable flag EIF4 to trigger PWM interrupt,1: Enabling flag EIF4 can trigger PWM interrupt"
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bitfld.long 0x00 1. "EDGEIEN2,PWMx2 Edge Interrupt Enable Bit\n" "0: Disabling flag EIF2 can trigger PWM interrupt,1: Enabling flag EIF2 can trigger PWM interrupt"
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bitfld.long 0x00 0. "EDGEIEN0,PWMx0 Edge Interrupt Enable Bit\n" "0: Disabling flag EIF0 to trigger PWM interrupt,1: Enabling flag EIF0 can trigger PWM interrupt"
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group.long 0x44++0x03
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line.long 0x00 "EPWM_OUTEN0,PWM Output Enable Control Register"
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bitfld.long 0x00 1. "ODDOUTEN,PWM Odd Ports Output Enable Bit\n" "0: PWM odd ports output Disabled (PWM even ports..,1: PWM odd ports output Enabled"
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bitfld.long 0x00 0. "EVENOUTEN,PWM Even Ports Output Enable Bit\n" "0: PWM even ports output Disabled (PWM even..,1: PWM even ports output Enabled"
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tree.end
|
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tree "EPWM1"
|
|
base ad:0x4005D000
|
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group.long 0x00++0x03
|
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line.long 0x00 "EPWM_CTL,PWM Control Register"
|
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bitfld.long 0x00 31. "CTRLD,Center Reload Mode Enable Bit\nThis bit only work when EPWM operation at center aligned mode" "0: EPWM reload compare register at the period..,1: EPWM reload compare register at the center.."
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bitfld.long 0x00 29. "BRK1NFDIS,PWM Brake 1 Noise Filter Disable Bit\n" "0: Noise filter of PWM Brake 1 Enabled,1: Noise filter of PWM Brake 1 Disabled"
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bitfld.long 0x00 28. "BRK0NFDIS,PWM Brake 0 Noise Filter Disable Bit\n" "0: Noise filter of PWM Brake 0 Enabled,1: Noise filter of PWM Brake 0 Disabled"
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bitfld.long 0x00 27. "LVDBKEN,Low-Level Detection Trigger PWM Brake Function 1 Enable Bit\n" "0: Brake Function 1 triggered by Low-level..,1: Brake Function 1 triggered by Low-level.."
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bitfld.long 0x00 26. "CPO2BKEN,CPO2 Digital Output As Brake 0 Source Enable Bit\n" "0: CPO2 as one brake source in Brake 0 Disabled,1: CPO2 as one brake source in Brake 0 Enabled"
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bitfld.long 0x00 25. "CPO1BKEN,CPO1 Digital Output As Brake 0 Source Enable Bit\n" "0: CPO1 as one brake source in Brake 0 Disabled,1: CPO1 as one brake source in Brake 0 Enabled"
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bitfld.long 0x00 24. "CPO0BKEN,CPO0 Digital Output As Brake0 Source Enable Bit\n" "0: CPO0 as one brake source in Brake 0 Disabled,1: CPO0 as one brake source in Brake 0 Enabled"
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bitfld.long 0x00 22.--23. "BRK1NFSEL,Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/16"
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bitfld.long 0x00 20.--21. "BRK0NFSEL,Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/16"
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bitfld.long 0x00 18.--19. "BRK1SEL,Brake Function 1 Source Selection\n" "0: From external pin BKPx1 (x=0~1 for unit0~1),1: From analog comparator 0 output (CPO0),2: From analog comparator 1 output (CPO1),3: From analog comparator 2 output (CPO2)"
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bitfld.long 0x00 17. "BRKP1EN,BKPx1 Pin Trigger Brake Function Enable Bit\n" "0: PWMx Brake Function 1 Disabled,1: PWMx Brake Function 1 Enabled"
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bitfld.long 0x00 16. "BRKP0EN,BKPx0 Pin Trigger Brake Function0 Enable Bit\n" "0: PWMx Brake Function 0 Disabled,1: PWMx Brake Function 0 Enabled"
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bitfld.long 0x00 15. "BRKP1INV,Inverse BKP1 State\n" "0: The state of pin BKPx1 is passed to the..,1: The inversed state of pin BKPx1 is passed to.."
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bitfld.long 0x00 14. "BRKP0INV,Inverse BKP0 State\n" "0: The state of pin BKPx0 is passed to the..,1: The inversed state of pin BKPx0 is passed to.."
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bitfld.long 0x00 13. "GROUPEN,Group Bit\n" "0: The signals timing of EPWM_CMPDAT0..,1: Unify the signals timing of EPWM_CMPDAT0.."
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bitfld.long 0x00 12. "CNTTYPE,PWM Aligned Type Selection\n" "0: Edge-aligned type,1: Centre-aligned type"
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bitfld.long 0x00 11. "CNTCLR,Clear PWM Counter Control\nNote: It is automatically cleared by hardware" "?,1: Clear 16-bit PWM counter to 000H"
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bitfld.long 0x00 9. "PINV,Inverse PWM Comparator Output\nWhen PINV is set to high the PWM comparator output signals will be inversed therefore the PWM Duty (in percentage) is changed to (1-Duty) before PINV is set to high.\n" "0: Not inverse PWM comparator output,1: Inverse PWM comparator output"
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bitfld.long 0x00 8. "INTTYPE,PWM Interrupt Type Selection\nNote: This bit is effective when PWM in central align mode only" "0: PIF will be set if PWM counter underflow,1: PIF will be set if PWM counter matches.."
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bitfld.long 0x00 7. "CNTEN,Start CNTEN Control\n" "0: The PWM stops running,1: The PWM counter starts running"
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bitfld.long 0x00 6. "LOAD,Re-Load PWM Period Registers (EPWM_PERIOD) And PWM Compare Registers (EPWM_CMPDAT0~4) Control \nNote: This bit is software write hardware clear and always read zero" "0: No action if written with 0,1: Hardware will update the value of PWM period.."
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bitfld.long 0x00 5. "BRKIEN,Brake0 And Brak1 Interrupt Enable Bit\n" "0: Disabling flags BRKIF0 and BRKIF1 to trigger..,1: Enabling flags BRKIF0 and BRKIF1 can trigger.."
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bitfld.long 0x00 4. "PWMIEN,PWM Interrupt Enable Bit\n" "0: Disabling flag PIF to trigger PWM interrupt,1: Enabling flag PIF can trigger PWM interrupt"
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bitfld.long 0x00 2.--3. "CLKDIV,PWM Clock Pre-Divider Selection\n" "0: PWM clock = EPWM_CLK,1: PWM clock = EPWM_CLK/2,2: PWM clock = EPWM_CLK/4,3: PWM clock = EPWM_CLK/16"
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bitfld.long 0x00 0.--1. "MODE,PWM Mode Selection\n" "0: Independent mode,1: Pair/Complementary mode,2: Synchronized mode,3: Reserved"
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group.long 0x04++0x03
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line.long 0x00 "EPWM_STATUS,PWM Status Register"
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rbitfld.long 0x00 25. "BRK1STS,Brake 1 Status (Read Only)\n" "0: PWM had been out of Brake 1 state,1: PWM is in Brake 1 state"
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rbitfld.long 0x00 24. "BRK0STS,Brake 0 Status (Read Only)\n" "0: PWM had been out of Brake 0 state,1: PWM is in Brake 0 state"
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bitfld.long 0x00 8. "BRK0LOCK,PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to it" "0: Brake 0 state is released,1: When PWM Brake detects a falling signal at.."
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bitfld.long 0x00 6. "EIF4,PWMx_CH4 Edge Flag\nNote: This bit must be cleared by writing 1 to it" "0: The PWMx_CH4 doesn't toggle,1: Hardware will set this flag to high at the.."
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bitfld.long 0x00 5. "EIF2,PWMx_CH2 Edge Flag\nNote: This bit must be cleared by writing 1 to it" "0: The PWMx_CH2 doesn't toggle,1: Hardware will set this flag to high at the.."
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bitfld.long 0x00 4. "EIF0,PWMx_CH0 Edge Flag\nNote: This bit must be cleared by writing 1 to it" "0: The PWMx_CH0 doesn't toggle,1: Hardware will set this flag to high at the.."
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bitfld.long 0x00 2. "PIF,PWM Period Flag\nNote: This bit must be cleared by writing 1 to it" "0: PWM Counter has not up counted to the value..,1: Hardware will set this flag to high at the.."
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bitfld.long 0x00 1. "BRKIF1,PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to it" "0: PWM Brake 1 is able to poll falling signal at..,1: When PWM Brake 1 detects a falling signal at.."
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bitfld.long 0x00 0. "BRKIF0,PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to it" "0: PWM Brake 0 is able to poll falling signal at..,1: When PWM Brake 0 detects a falling signal at.."
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group.long 0x08++0x03
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line.long 0x00 "EPWM_PERIOD,PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nEdge aligned:\n"
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group.long 0x0C++0x03
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line.long 0x00 "EPWM_CMPDAT0,EPWM_CMPDAT0 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Duty Register\nEdge aligned:\n"
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group.long 0x10++0x03
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line.long 0x00 "EPWM_CMPDAT2,EPWM_CMPDAT2 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Duty Register\nEdge aligned:\n"
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group.long 0x14++0x03
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line.long 0x00 "EPWM_CMPDAT4,EPWM_CMPDAT4 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Duty Register\nEdge aligned:\n"
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group.long 0x18++0x03
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line.long 0x00 "EPWM_MSKEN,PWM Mask Mode Enable Control Register"
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bitfld.long 0x00 0.--5. "MSKEN,PWM Mask Enable Bits\nThe PWM generator signal will be masked when this bit is enabled" "0: PWM generator signal is output to next stage,1: PWM generator signal is masked and..,?..."
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group.long 0x1C++0x03
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line.long 0x00 "EPWM_MSK,PWM Mask Mode Data Register"
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bitfld.long 0x00 0.--5. "MSKDAT,PWM Mask Data Bit\n" "0: Output logic low to EPWM_CHn,1: Output logic high to EPWM_CHn,?..."
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group.long 0x20++0x03
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line.long 0x00 "EPWM_ASYMCMP0,Asymmetric EPWM_CMPDAT0 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,Asymmetric PWM Duty Register\nWhen the asymmetric PWM function is enabled this 16-bit field determines the second time compared value after PWM counter has matched with EPWM_CMPDATx in the first half PWM cycle"
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group.long 0x24++0x03
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line.long 0x00 "EPWM_ASYMCMP2,Asymmetric EPWM_CMPDAT2 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,Asymmetric PWM Duty Register\nWhen the asymmetric PWM function is enabled this 16-bit field determines the second time compared value after PWM counter has matched with EPWM_CMPDATx in the first half PWM cycle"
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group.long 0x28++0x03
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line.long 0x00 "EPWM_ASYMCMP4,Asymmetric EPWM_CMPDAT4 Duty Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,Asymmetric PWM Duty Register\nWhen the asymmetric PWM function is enabled this 16-bit field determines the second time compared value after PWM counter has matched with EPWM_CMPDATx in the first half PWM cycle"
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group.long 0x2C++0x03
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line.long 0x00 "EPWM_DTCTL,PWM Dead-time Control Register"
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bitfld.long 0x00 18. "DTEN4,Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH4 PWM_CH5)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair..,1: Dead-time insertion Enabled on the pin pair.."
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bitfld.long 0x00 17. "DTEN2,Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH2 PWM_CH3)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair..,1: Dead-time insertion Enabled on the pin pair.."
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bitfld.long 0x00 16. "DTEN0,Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH0 PWM_CH1)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair..,1: Dead-time insertion Enabled on the pin pair.."
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hexmask.long.word 0x00 0.--10. 1. "DTCNT,Dead-Time Counter\nThe dead-time can be calculated from the following formula: \n"
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group.long 0x30++0x03
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line.long 0x00 "EPWM_BRKOUT,PWM Brake Output"
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bitfld.long 0x00 0.--5. "BRKOUT,PWM Brake Output\nWhen PWM Brake is asserted the PWM_CH0~5 output state before polarity control will follow bit0~5 setting respectively.\n" "0: The PWM_CHn output before polarity control is..,1: The PWM_CHn output before polarity control is..,?..."
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group.long 0x34++0x03
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line.long 0x00 "EPWM_NPCTL,PWM Negative Polarity Control"
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bitfld.long 0x00 0.--5. "NEGPOLAR,PWM Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n" "0: PWM_CHn output is active high,1: PWM_CHn output is active low,?..."
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group.long 0x38++0x03
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line.long 0x00 "EPWM_ASYMCTL,Asymmetric PWM Control Register"
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bitfld.long 0x00 24.--25. "ASYMMODE4,Asymmetric PWMx_CH4 Reload Mode Setting\n" "0: 1,1: 1,2: 1,3: Reserved"
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bitfld.long 0x00 16.--17. "ASYMMODE2,Asymmetric PWMx_CH2 Reload Mode Setting\n" "0: 1,1: 1,2: 1,3: Reserved"
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bitfld.long 0x00 8.--9. "ASYMMODE0,Asymmetric PWMx_CH0 Reload Mode Setting\n" "0: 1,1: 1,2: 1,3: Reserved"
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bitfld.long 0x00 0. "ASYMEN,Asymmetric PWM Enable Bit\nNote: This control bit is only valid when PWM module is set in Centre-aligned mode" "0: Asymmetric PWM function Disabled,1: Asymmetric PWM function Enabled"
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group.long 0x3C++0x03
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line.long 0x00 "EPWM_PERIODCNT,PIF Compared Counter"
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bitfld.long 0x00 0.--3. "PERIODCNT,PIF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PIF to request the PWM period interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x40++0x03
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line.long 0x00 "EPWM_EINTCTL,PWM Edge Interrupt Control Register"
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bitfld.long 0x00 10. "EINTTYPE4,PWMx4 Edge Interrupt Type\n" "0: EIF4 will be set if falling edge is detected..,1: EIF4 will be set if rising edge is detected.."
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bitfld.long 0x00 9. "EINTTYPE2,PWMx2 Edge Interrupt Type\n" "0: EIF2 will be set if falling edge is detected..,1: EIF2 will be set if rising edge is detected.."
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bitfld.long 0x00 8. "EINTTYPE0,PWMx0 Edge Interrupt Type\n" "0: EIF0 will be set if falling edge is detected..,1: EIF0 will be set if rising edge is detected.."
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bitfld.long 0x00 2. "EDGEIEN4,PWMx4 Edge Interrupt Enable Bit\n" "0: Disable flag EIF4 to trigger PWM interrupt,1: Enabling flag EIF4 can trigger PWM interrupt"
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newline
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bitfld.long 0x00 1. "EDGEIEN2,PWMx2 Edge Interrupt Enable Bit\n" "0: Disabling flag EIF2 can trigger PWM interrupt,1: Enabling flag EIF2 can trigger PWM interrupt"
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bitfld.long 0x00 0. "EDGEIEN0,PWMx0 Edge Interrupt Enable Bit\n" "0: Disabling flag EIF0 to trigger PWM interrupt,1: Enabling flag EIF0 can trigger PWM interrupt"
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group.long 0x44++0x03
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line.long 0x00 "EPWM_OUTEN0,PWM Output Enable Control Register"
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bitfld.long 0x00 1. "ODDOUTEN,PWM Odd Ports Output Enable Bit\n" "0: PWM odd ports output Disabled (PWM even ports..,1: PWM odd ports output Enabled"
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bitfld.long 0x00 0. "EVENOUTEN,PWM Even Ports Output Enable Bit\n" "0: PWM even ports output Disabled (PWM even..,1: PWM even ports output Enabled"
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tree.end
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tree.end
|
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tree "FMC"
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base ad:0x4000C000
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group.long 0x00++0x03
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line.long 0x00 "FMC_ISPCTL,ISP Control Register"
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bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is.." "0,1"
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bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\n" "0: LDROM cannot be updated,1: LDROM can be updated"
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bitfld.long 0x00 4. "CFGUEN,Config-Bits Update By ISP Enable Bit (Write Protect)\n" "0: ISP Disabled to update config-bits,1: ISP Enabled to update config-bits"
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bitfld.long 0x00 3. "APUEN,APROM Update Enable Bit (Write Protect)\n" "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in.."
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bitfld.long 0x00 1. "BS,Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively" "0: Boot from APROM,1: Boot from LDROM"
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bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect)\nISP function enable bit" "0: ISP function Disabled,1: ISP function Enabled"
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group.long 0x04++0x03
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line.long 0x00 "FMC_ISPADDR,ISP Address Register"
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hexmask.long 0x00 0.--31. 1. "ISPADDR,ISP Address\nThe NUC442/NUC472 series is equipped with an embedded flash and supports word program only"
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group.long 0x08++0x03
|
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line.long 0x00 "FMC_ISPDAT,ISP Data Register"
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hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation"
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group.long 0x0C++0x03
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line.long 0x00 "FMC_ISPCMD,ISP Command Register"
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bitfld.long 0x00 0.--5. "CMD,ISP Command\nPlease check the table below for ISP commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x10++0x03
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line.long 0x00 "FMC_ISPTRG,ISP Trigger Register"
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bitfld.long 0x00 0. "ISPGO,ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the protected bit It means programming this bit needs to write 59h 16h 88h to address.." "0: ISP operation is finished,1: ISP is progressed"
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rgroup.long 0x14++0x03
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line.long 0x00 "FMC_DFBA,Data Flash Base Address"
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hexmask.long 0x00 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates data flash start address"
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group.long 0x18++0x03
|
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line.long 0x00 "FMC_FTCTL,Flash Access Time Control Register"
|
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bitfld.long 0x00 4.--6. "FOM,Frequency Optimization Mode (Write Protect)\n" "0,1,2,3,4,5,6,7"
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rgroup.long 0x40++0x03
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line.long 0x00 "FMC_ISPSTS,ISP Status Register"
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bitfld.long 0x00 26. "CFGCRCF,User-Configuration CRC Check Flag (Read Only)\nThis bit is set by hardware when detecting CONFIG CRC checksum is error\n" "0: CONFIG CRC checksum is OK,1: CONFIG CRC checksum error and force chip into.."
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hexmask.long.word 0x00 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_07FF is mapping to address {VECMAP[11:2] 11'h000} ~ {VECMAP[11:2] 11'h7FF}\nVECMAP[1:0] is needed to set 0"
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bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Read Only)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed.." "0,1"
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bitfld.long 0x00 1.--2. "CBS,Chip Boot Selection Mode This CBS field is just a copy of User-Configuration Config0 CBS[7:6]" "0,1,2,3"
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newline
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bitfld.long 0x00 0. "ISPBUSY,ISP Busy Flag\n" "0: ISP operation is finished,1: ISP is progressed"
|
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group.long 0x80++0x03
|
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line.long 0x00 "FMC_MPDAT0,ISP Multi-word Program Data0 Register"
|
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hexmask.long 0x00 0.--31. 1. "ISPDAT0,ISP Data 0\nThis register is the first 32-bit data for 32b/64b/multi-word program and it is also the mirror of FMC_ISPDAT register both registers keep the same data"
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group.long 0x84++0x03
|
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line.long 0x00 "FMC_MPDAT1,ISP Multi-word Program Data1 Register"
|
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hexmask.long 0x00 0.--31. 1. "ISPDAT1,ISP Data 1\nThis register is the second 32-bit data for 32b/64b/multi-word program"
|
|
group.long 0x88++0x03
|
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line.long 0x00 "FMC_MPDAT2,ISP Multi-word Program Data2 Register"
|
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hexmask.long 0x00 0.--31. 1. "ISPDAT2,ISP Data 2\nThis register is the third 32-bit data for 32b/64b/multi-word program"
|
|
group.long 0x8C++0x03
|
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line.long 0x00 "FMC_MPDAT3,ISP Multi-word Program Data3 Register"
|
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hexmask.long 0x00 0.--31. 1. "ISPDAT3,ISP Data 3\nThis register is the fourth 32-bit data for 32b/64b/multi-word program"
|
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rgroup.long 0xC0++0x03
|
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line.long 0x00 "FMC_MPSTS,ISP Multi-word Program Status Register"
|
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bitfld.long 0x00 7. "D3,ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 is programmed to flash complete.\n" "0: FMC_MPDAT3 register is empty or program to..,1: FMC_MPDAT3 register has been written and not.."
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bitfld.long 0x00 6. "D2,ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 is programmed to flash complete.\n" "0: FMC_MPDAT2 register is empty or program to..,1: FMC_MPDAT2 register has been written and not.."
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bitfld.long 0x00 5. "D1,ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 is programmed to flash complete.\n" "0: FMC_MPDAT1 register is empty or program to..,1: FMC_MPDAT1 register has been written and not.."
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bitfld.long 0x00 4. "D0,ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 is programmed to flash complete.\n" "0: FMC_MPDAT0 register is empty or program to..,1: FMC_ISPDAT0 register has been written and not.."
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newline
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bitfld.long 0x00 2. "ISPFF,ISP Fail Flag (Read Only)\nThis bit is set when ISP Multi-Word Program operation failed" "0,1"
|
|
bitfld.long 0x00 0. "MPBUSY,ISP Multi-Word Program Busy Flag (Read Only)\n" "0: ISP Multi-Word Program operation is aborted..,1: ISP Multi-Word Program operation is progressed"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "FMC_MPADDR,ISP Multi-word Program Address Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "MPADDR,ISP Multi-Word Program Address Status\nMPADDR is the address of ISP Multi-Word Program operation when MPBUSY flag is 1"
|
|
tree.end
|
|
tree "GPIO"
|
|
base ad:0x40004000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PA_MODE,PA I/O Mode Control"
|
|
bitfld.long 0x00 30.--31. "MODE15,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PA_DINOFF,PA Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 30. "DINOFF14,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 29. "DINOFF13,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 28. "DINOFF12,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 27. "DINOFF11,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 26. "DINOFF10,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 25. "DINOFF9,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 24. "DINOFF8,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 23. "DINOFF7,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 22. "DINOFF6,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 21. "DINOFF5,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 20. "DINOFF4,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 19. "DINOFF3,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 18. "DINOFF2,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 17. "DINOFF1,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 16. "DINOFF0,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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group.long 0x08++0x03
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line.long 0x00 "PA_DOUT,PA Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 14. "DOUT14,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 13. "DOUT13,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 12. "DOUT12,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 11. "DOUT11,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 10. "DOUT10,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 9. "DOUT9,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 8. "DOUT8,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 7. "DOUT7,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 6. "DOUT6,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 5. "DOUT5,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 4. "DOUT4,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 3. "DOUT3,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 2. "DOUT2,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 1. "DOUT1,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 0. "DOUT0,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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group.long 0x0C++0x03
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line.long 0x00 "PA_DATMSK,PA Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 14. "DATMSK14,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 13. "DATMSK13,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 12. "DATMSK12,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 11. "DATMSK11,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 10. "DATMSK10,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 9. "DATMSK9,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 8. "DATMSK8,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 7. "DATMSK7,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 6. "DATMSK6,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 5. "DATMSK5,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 4. "DATMSK4,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 3. "DATMSK3,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 2. "DATMSK2,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 1. "DATMSK1,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 0. "DATMSK0,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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rgroup.long 0x10++0x03
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line.long 0x00 "PA_PIN,PA Pin Value"
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bitfld.long 0x00 15. "PIN15,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PA_DBEN,PA De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 14. "DBEN14,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 13. "DBEN13,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 12. "DBEN12,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 11. "DBEN11,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 10. "DBEN10,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 9. "DBEN9,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 8. "DBEN8,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 7. "DBEN7,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 6. "DBEN6,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 5. "DBEN5,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 4. "DBEN4,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 3. "DBEN3,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 2. "DBEN2,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 1. "DBEN1,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 0. "DBEN0,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PA_INTTYPE,PA Interrupt Trigger Type Register"
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bitfld.long 0x00 15. "TYPE15,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 14. "TYPE14,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 13. "TYPE13,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 12. "TYPE12,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 11. "TYPE11,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 10. "TYPE10,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 9. "TYPE9,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 8. "TYPE8,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 7. "TYPE7,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 6. "TYPE6,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 5. "TYPE5,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 4. "TYPE4,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 3. "TYPE3,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 2. "TYPE2,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 1. "TYPE1,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 0. "TYPE0,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PA_INTEN,PA Interrupt Enable"
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bitfld.long 0x00 31. "RHIEN15,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 30. "RHIEN14,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 29. "RHIEN13,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 28. "RHIEN12,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 27. "RHIEN11,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 26. "RHIEN10,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 25. "RHIEN9,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 24. "RHIEN8,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 23. "RHIEN7,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 22. "RHIEN6,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 21. "RHIEN5,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 20. "RHIEN4,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 19. "RHIEN3,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 18. "RHIEN2,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 17. "RHIEN1,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 16. "RHIEN0,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 15. "FLIEN15,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 14. "FLIEN14,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 13. "FLIEN13,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 12. "FLIEN12,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 11. "FLIEN11,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 10. "FLIEN10,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 9. "FLIEN9,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 8. "FLIEN8,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 7. "FLIEN7,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 6. "FLIEN6,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 5. "FLIEN5,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 4. "FLIEN4,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 3. "FLIEN3,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 2. "FLIEN2,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 1. "FLIEN1,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 0. "FLIEN0,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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group.long 0x20++0x03
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line.long 0x00 "PA_INTSRC,PA Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 14. "INTSRC14,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 13. "INTSRC13,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 12. "INTSRC12,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 11. "INTSRC11,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 10. "INTSRC10,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 9. "INTSRC9,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 8. "INTSRC8,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 7. "INTSRC7,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 6. "INTSRC6,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 5. "INTSRC5,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 4. "INTSRC4,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 3. "INTSRC3,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 2. "INTSRC2,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 1. "INTSRC1,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 0. "INTSRC0,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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group.long 0x24++0x03
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line.long 0x00 "PA_SMTEN,PA Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PA_SLEWCTL,PA High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 13. "HSREN13,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 11. "HSREN11,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 9. "HSREN9,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 7. "HSREN7,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 5. "HSREN5,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 3. "HSREN3,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 1. "HSREN1,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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group.long 0x40++0x03
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line.long 0x00 "PB_MODE,PB I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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group.long 0x44++0x03
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line.long 0x00 "PB_DINOFF,PB Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 30. "DINOFF14,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 29. "DINOFF13,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 28. "DINOFF12,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 27. "DINOFF11,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 26. "DINOFF10,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 25. "DINOFF9,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 24. "DINOFF8,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 23. "DINOFF7,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 22. "DINOFF6,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 21. "DINOFF5,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 20. "DINOFF4,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 19. "DINOFF3,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 18. "DINOFF2,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 17. "DINOFF1,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 16. "DINOFF0,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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group.long 0x48++0x03
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line.long 0x00 "PB_DOUT,PB Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 14. "DOUT14,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 13. "DOUT13,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 12. "DOUT12,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 11. "DOUT11,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 10. "DOUT10,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 9. "DOUT9,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 8. "DOUT8,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 7. "DOUT7,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 6. "DOUT6,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 5. "DOUT5,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 4. "DOUT4,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 3. "DOUT3,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 2. "DOUT2,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 1. "DOUT1,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 0. "DOUT0,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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group.long 0x4C++0x03
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line.long 0x00 "PB_DATMSK,PB Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 14. "DATMSK14,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 13. "DATMSK13,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 12. "DATMSK12,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 11. "DATMSK11,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 10. "DATMSK10,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 9. "DATMSK9,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 8. "DATMSK8,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 7. "DATMSK7,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 6. "DATMSK6,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 5. "DATMSK5,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 4. "DATMSK4,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 3. "DATMSK3,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 2. "DATMSK2,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 1. "DATMSK1,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 0. "DATMSK0,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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group.long 0x50++0x03
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line.long 0x00 "PB_PIN,PB Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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group.long 0x54++0x03
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line.long 0x00 "PB_DBEN,PB De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 14. "DBEN14,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 13. "DBEN13,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 12. "DBEN12,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 11. "DBEN11,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 10. "DBEN10,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 9. "DBEN9,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 8. "DBEN8,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 7. "DBEN7,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 6. "DBEN6,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 5. "DBEN5,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 4. "DBEN4,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 3. "DBEN3,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 2. "DBEN2,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 1. "DBEN1,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 0. "DBEN0,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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group.long 0x58++0x03
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line.long 0x00 "PB_INTTYPE,PB Interrupt Trigger Type Register"
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bitfld.long 0x00 15. "TYPE15,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 14. "TYPE14,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 13. "TYPE13,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 12. "TYPE12,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 11. "TYPE11,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 10. "TYPE10,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 9. "TYPE9,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 8. "TYPE8,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 7. "TYPE7,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 6. "TYPE6,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 5. "TYPE5,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 4. "TYPE4,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 3. "TYPE3,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 2. "TYPE2,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 1. "TYPE1,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 0. "TYPE0,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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group.long 0x5C++0x03
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line.long 0x00 "PB_INTEN,PB Interrupt Enable"
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bitfld.long 0x00 31. "RHIEN15,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 30. "RHIEN14,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 29. "RHIEN13,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 28. "RHIEN12,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 27. "RHIEN11,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 26. "RHIEN10,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 25. "RHIEN9,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 24. "RHIEN8,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 23. "RHIEN7,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 22. "RHIEN6,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 21. "RHIEN5,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 20. "RHIEN4,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 19. "RHIEN3,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 18. "RHIEN2,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 17. "RHIEN1,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 16. "RHIEN0,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 15. "FLIEN15,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 14. "FLIEN14,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 13. "FLIEN13,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 12. "FLIEN12,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 11. "FLIEN11,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 10. "FLIEN10,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 9. "FLIEN9,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 8. "FLIEN8,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 7. "FLIEN7,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 6. "FLIEN6,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 5. "FLIEN5,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 4. "FLIEN4,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 3. "FLIEN3,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 2. "FLIEN2,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 1. "FLIEN1,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 0. "FLIEN0,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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group.long 0x60++0x03
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line.long 0x00 "PB_INTSRC,PB Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 14. "INTSRC14,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 13. "INTSRC13,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 12. "INTSRC12,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 11. "INTSRC11,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 10. "INTSRC10,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 9. "INTSRC9,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 8. "INTSRC8,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 7. "INTSRC7,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 6. "INTSRC6,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 5. "INTSRC5,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 4. "INTSRC4,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 3. "INTSRC3,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 2. "INTSRC2,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 1. "INTSRC1,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 0. "INTSRC0,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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group.long 0x64++0x03
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line.long 0x00 "PB_SMTEN,PB Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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group.long 0x68++0x03
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line.long 0x00 "PB_SLEWCTL,PB High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 13. "HSREN13,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 11. "HSREN11,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 9. "HSREN9,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 7. "HSREN7,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 5. "HSREN5,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 3. "HSREN3,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 1. "HSREN1,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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group.long 0x80++0x03
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line.long 0x00 "PC_MODE,PC I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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group.long 0x84++0x03
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line.long 0x00 "PC_DINOFF,PC Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 30. "DINOFF14,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 29. "DINOFF13,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 28. "DINOFF12,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 27. "DINOFF11,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 26. "DINOFF10,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 25. "DINOFF9,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 24. "DINOFF8,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 23. "DINOFF7,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 22. "DINOFF6,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 21. "DINOFF5,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 20. "DINOFF4,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 19. "DINOFF3,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 18. "DINOFF2,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 17. "DINOFF1,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 16. "DINOFF0,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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group.long 0x88++0x03
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line.long 0x00 "PC_DOUT,PC Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 14. "DOUT14,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 13. "DOUT13,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 12. "DOUT12,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 11. "DOUT11,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 10. "DOUT10,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 9. "DOUT9,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 8. "DOUT8,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 7. "DOUT7,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 6. "DOUT6,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 5. "DOUT5,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 4. "DOUT4,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 3. "DOUT3,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 2. "DOUT2,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 1. "DOUT1,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 0. "DOUT0,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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group.long 0x8C++0x03
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line.long 0x00 "PC_DATMSK,PC Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 14. "DATMSK14,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 13. "DATMSK13,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 12. "DATMSK12,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 11. "DATMSK11,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 10. "DATMSK10,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 9. "DATMSK9,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 8. "DATMSK8,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 7. "DATMSK7,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 6. "DATMSK6,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 5. "DATMSK5,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 4. "DATMSK4,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 3. "DATMSK3,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 2. "DATMSK2,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 1. "DATMSK1,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 0. "DATMSK0,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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group.long 0x90++0x03
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line.long 0x00 "PC_PIN,PC Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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group.long 0x94++0x03
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line.long 0x00 "PC_DBEN,PC De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 14. "DBEN14,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 13. "DBEN13,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 12. "DBEN12,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 11. "DBEN11,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 10. "DBEN10,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 9. "DBEN9,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 8. "DBEN8,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 7. "DBEN7,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 6. "DBEN6,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 5. "DBEN5,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 4. "DBEN4,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 3. "DBEN3,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 2. "DBEN2,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 1. "DBEN1,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 0. "DBEN0,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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group.long 0x98++0x03
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line.long 0x00 "PC_INTTYPE,PC Interrupt Trigger Type Register"
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bitfld.long 0x00 15. "TYPE15,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 14. "TYPE14,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 13. "TYPE13,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 12. "TYPE12,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 11. "TYPE11,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 10. "TYPE10,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 9. "TYPE9,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 8. "TYPE8,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 7. "TYPE7,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 6. "TYPE6,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 5. "TYPE5,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 4. "TYPE4,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 3. "TYPE3,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 2. "TYPE2,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 1. "TYPE1,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 0. "TYPE0,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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group.long 0x9C++0x03
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line.long 0x00 "PC_INTEN,PC Interrupt Enable"
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bitfld.long 0x00 31. "RHIEN15,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 30. "RHIEN14,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 29. "RHIEN13,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 28. "RHIEN12,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 27. "RHIEN11,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 26. "RHIEN10,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 25. "RHIEN9,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 24. "RHIEN8,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 23. "RHIEN7,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 22. "RHIEN6,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 21. "RHIEN5,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 20. "RHIEN4,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 19. "RHIEN3,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 18. "RHIEN2,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 17. "RHIEN1,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 16. "RHIEN0,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 15. "FLIEN15,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 14. "FLIEN14,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 13. "FLIEN13,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 12. "FLIEN12,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 11. "FLIEN11,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 10. "FLIEN10,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 9. "FLIEN9,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 8. "FLIEN8,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 7. "FLIEN7,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 6. "FLIEN6,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 5. "FLIEN5,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 4. "FLIEN4,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 3. "FLIEN3,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 2. "FLIEN2,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 1. "FLIEN1,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 0. "FLIEN0,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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group.long 0xA0++0x03
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line.long 0x00 "PC_INTSRC,PC Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 14. "INTSRC14,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 13. "INTSRC13,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 12. "INTSRC12,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 11. "INTSRC11,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 10. "INTSRC10,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 9. "INTSRC9,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 8. "INTSRC8,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 7. "INTSRC7,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 6. "INTSRC6,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 5. "INTSRC5,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 4. "INTSRC4,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 3. "INTSRC3,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 2. "INTSRC2,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 1. "INTSRC1,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 0. "INTSRC0,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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group.long 0xA4++0x03
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line.long 0x00 "PC_SMTEN,PC Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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group.long 0xA8++0x03
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line.long 0x00 "PC_SLEWCTL,PC High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 13. "HSREN13,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 11. "HSREN11,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 9. "HSREN9,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 7. "HSREN7,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 5. "HSREN5,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 3. "HSREN3,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 1. "HSREN1,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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group.long 0xC0++0x03
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line.long 0x00 "PD_MODE,PD I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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group.long 0xC4++0x03
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line.long 0x00 "PD_DINOFF,PD Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 30. "DINOFF14,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 29. "DINOFF13,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 28. "DINOFF12,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 27. "DINOFF11,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 26. "DINOFF10,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 25. "DINOFF9,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 24. "DINOFF8,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 23. "DINOFF7,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 22. "DINOFF6,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 21. "DINOFF5,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 20. "DINOFF4,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 19. "DINOFF3,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 18. "DINOFF2,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 17. "DINOFF1,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 16. "DINOFF0,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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group.long 0xC8++0x03
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line.long 0x00 "PD_DOUT,PD Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 14. "DOUT14,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 13. "DOUT13,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 12. "DOUT12,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 11. "DOUT11,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 10. "DOUT10,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 9. "DOUT9,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 8. "DOUT8,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 7. "DOUT7,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 6. "DOUT6,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 5. "DOUT5,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 4. "DOUT4,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 3. "DOUT3,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 2. "DOUT2,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 1. "DOUT1,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 0. "DOUT0,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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group.long 0xCC++0x03
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line.long 0x00 "PD_DATMSK,PD Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 14. "DATMSK14,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 13. "DATMSK13,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 12. "DATMSK12,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 11. "DATMSK11,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 10. "DATMSK10,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 9. "DATMSK9,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 8. "DATMSK8,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 7. "DATMSK7,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 6. "DATMSK6,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 5. "DATMSK5,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 4. "DATMSK4,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 3. "DATMSK3,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 2. "DATMSK2,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 1. "DATMSK1,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 0. "DATMSK0,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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group.long 0xD0++0x03
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line.long 0x00 "PD_PIN,PD Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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group.long 0xD4++0x03
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line.long 0x00 "PD_DBEN,PD De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 14. "DBEN14,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 13. "DBEN13,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 12. "DBEN12,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 11. "DBEN11,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 10. "DBEN10,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 9. "DBEN9,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 8. "DBEN8,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 7. "DBEN7,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 6. "DBEN6,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 5. "DBEN5,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 4. "DBEN4,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 3. "DBEN3,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 2. "DBEN2,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 1. "DBEN1,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 0. "DBEN0,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "PD_INTTYPE,PD Interrupt Trigger Type Register"
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bitfld.long 0x00 15. "TYPE15,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 14. "TYPE14,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 13. "TYPE13,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 12. "TYPE12,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 11. "TYPE11,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 10. "TYPE10,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 9. "TYPE9,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 8. "TYPE8,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 7. "TYPE7,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 6. "TYPE6,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 5. "TYPE5,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 4. "TYPE4,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 3. "TYPE3,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 2. "TYPE2,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 1. "TYPE1,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 0. "TYPE0,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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group.long 0xDC++0x03
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line.long 0x00 "PD_INTEN,PD Interrupt Enable"
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bitfld.long 0x00 31. "RHIEN15,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 30. "RHIEN14,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 29. "RHIEN13,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 28. "RHIEN12,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 27. "RHIEN11,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 26. "RHIEN10,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 25. "RHIEN9,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 24. "RHIEN8,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 23. "RHIEN7,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 22. "RHIEN6,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 21. "RHIEN5,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 20. "RHIEN4,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 19. "RHIEN3,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 18. "RHIEN2,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 17. "RHIEN1,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 16. "RHIEN0,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 15. "FLIEN15,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 14. "FLIEN14,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 13. "FLIEN13,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 12. "FLIEN12,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 11. "FLIEN11,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 10. "FLIEN10,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 9. "FLIEN9,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 8. "FLIEN8,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 7. "FLIEN7,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 6. "FLIEN6,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 5. "FLIEN5,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 4. "FLIEN4,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 3. "FLIEN3,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 2. "FLIEN2,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 1. "FLIEN1,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 0. "FLIEN0,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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group.long 0xE0++0x03
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line.long 0x00 "PD_INTSRC,PD Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 14. "INTSRC14,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 13. "INTSRC13,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 12. "INTSRC12,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 11. "INTSRC11,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 10. "INTSRC10,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 9. "INTSRC9,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 8. "INTSRC8,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 7. "INTSRC7,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 6. "INTSRC6,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 5. "INTSRC5,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 4. "INTSRC4,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 3. "INTSRC3,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 2. "INTSRC2,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 1. "INTSRC1,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 0. "INTSRC0,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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group.long 0xE4++0x03
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line.long 0x00 "PD_SMTEN,PD Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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group.long 0xE8++0x03
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line.long 0x00 "PD_SLEWCTL,PD High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 13. "HSREN13,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 11. "HSREN11,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 9. "HSREN9,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 7. "HSREN7,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 5. "HSREN5,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 3. "HSREN3,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 1. "HSREN1,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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group.long 0x100++0x03
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line.long 0x00 "PE_MODE,PE I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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group.long 0x104++0x03
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line.long 0x00 "PE_DINOFF,PE Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 30. "DINOFF14,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 29. "DINOFF13,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 28. "DINOFF12,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 27. "DINOFF11,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 26. "DINOFF10,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 25. "DINOFF9,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 24. "DINOFF8,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 23. "DINOFF7,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 22. "DINOFF6,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 21. "DINOFF5,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 20. "DINOFF4,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 19. "DINOFF3,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 18. "DINOFF2,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 17. "DINOFF1,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 16. "DINOFF0,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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group.long 0x108++0x03
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line.long 0x00 "PE_DOUT,PE Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 14. "DOUT14,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 13. "DOUT13,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 12. "DOUT12,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 11. "DOUT11,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 10. "DOUT10,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 9. "DOUT9,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 8. "DOUT8,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 7. "DOUT7,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 6. "DOUT6,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 5. "DOUT5,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 4. "DOUT4,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 3. "DOUT3,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 2. "DOUT2,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 1. "DOUT1,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 0. "DOUT0,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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group.long 0x10C++0x03
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line.long 0x00 "PE_DATMSK,PE Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 14. "DATMSK14,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 13. "DATMSK13,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 12. "DATMSK12,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 11. "DATMSK11,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 10. "DATMSK10,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 9. "DATMSK9,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 8. "DATMSK8,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 7. "DATMSK7,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 6. "DATMSK6,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 5. "DATMSK5,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 4. "DATMSK4,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 3. "DATMSK3,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 2. "DATMSK2,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 1. "DATMSK1,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 0. "DATMSK0,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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group.long 0x110++0x03
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line.long 0x00 "PE_PIN,PE Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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group.long 0x114++0x03
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line.long 0x00 "PE_DBEN,PE De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 14. "DBEN14,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 13. "DBEN13,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 12. "DBEN12,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 11. "DBEN11,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 10. "DBEN10,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 9. "DBEN9,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 8. "DBEN8,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 7. "DBEN7,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 6. "DBEN6,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 5. "DBEN5,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 4. "DBEN4,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 3. "DBEN3,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 2. "DBEN2,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 1. "DBEN1,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 0. "DBEN0,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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group.long 0x118++0x03
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line.long 0x00 "PE_INTTYPE,PE Interrupt Trigger Type Register"
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bitfld.long 0x00 15. "TYPE15,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 14. "TYPE14,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 13. "TYPE13,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 12. "TYPE12,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 11. "TYPE11,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 10. "TYPE10,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 9. "TYPE9,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 8. "TYPE8,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 7. "TYPE7,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 6. "TYPE6,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 5. "TYPE5,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 4. "TYPE4,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 3. "TYPE3,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 2. "TYPE2,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 1. "TYPE1,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 0. "TYPE0,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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group.long 0x11C++0x03
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line.long 0x00 "PE_INTEN,PE Interrupt Enable"
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bitfld.long 0x00 31. "RHIEN15,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 30. "RHIEN14,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 29. "RHIEN13,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 28. "RHIEN12,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 27. "RHIEN11,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 26. "RHIEN10,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 25. "RHIEN9,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 24. "RHIEN8,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 23. "RHIEN7,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 22. "RHIEN6,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 21. "RHIEN5,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 20. "RHIEN4,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 19. "RHIEN3,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 18. "RHIEN2,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 17. "RHIEN1,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 16. "RHIEN0,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 15. "FLIEN15,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 14. "FLIEN14,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 13. "FLIEN13,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 12. "FLIEN12,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 11. "FLIEN11,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 10. "FLIEN10,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 9. "FLIEN9,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 8. "FLIEN8,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 7. "FLIEN7,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 6. "FLIEN6,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 5. "FLIEN5,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 4. "FLIEN4,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 3. "FLIEN3,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 2. "FLIEN2,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 1. "FLIEN1,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 0. "FLIEN0,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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group.long 0x120++0x03
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line.long 0x00 "PE_INTSRC,PE Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 14. "INTSRC14,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 13. "INTSRC13,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 12. "INTSRC12,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 11. "INTSRC11,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 10. "INTSRC10,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 9. "INTSRC9,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 8. "INTSRC8,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 7. "INTSRC7,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 6. "INTSRC6,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 5. "INTSRC5,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 4. "INTSRC4,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 3. "INTSRC3,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 2. "INTSRC2,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 1. "INTSRC1,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 0. "INTSRC0,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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group.long 0x124++0x03
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line.long 0x00 "PE_SMTEN,PE Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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group.long 0x128++0x03
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line.long 0x00 "PE_SLEWCTL,PE High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 13. "HSREN13,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 11. "HSREN11,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 9. "HSREN9,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 7. "HSREN7,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 5. "HSREN5,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 3. "HSREN3,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 1. "HSREN1,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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group.long 0x140++0x03
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line.long 0x00 "PF_MODE,PF I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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group.long 0x144++0x03
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line.long 0x00 "PF_DINOFF,PF Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 30. "DINOFF14,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 29. "DINOFF13,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 28. "DINOFF12,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 27. "DINOFF11,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 26. "DINOFF10,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 25. "DINOFF9,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 24. "DINOFF8,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 23. "DINOFF7,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 22. "DINOFF6,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 21. "DINOFF5,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 20. "DINOFF4,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 19. "DINOFF3,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 18. "DINOFF2,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 17. "DINOFF1,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 16. "DINOFF0,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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group.long 0x148++0x03
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line.long 0x00 "PF_DOUT,PF Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 14. "DOUT14,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 13. "DOUT13,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 12. "DOUT12,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 11. "DOUT11,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 10. "DOUT10,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 9. "DOUT9,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 8. "DOUT8,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 7. "DOUT7,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 6. "DOUT6,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 5. "DOUT5,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 4. "DOUT4,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 3. "DOUT3,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 2. "DOUT2,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 1. "DOUT1,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 0. "DOUT0,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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group.long 0x14C++0x03
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line.long 0x00 "PF_DATMSK,PF Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 14. "DATMSK14,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 13. "DATMSK13,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 12. "DATMSK12,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 11. "DATMSK11,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 10. "DATMSK10,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 9. "DATMSK9,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 8. "DATMSK8,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 7. "DATMSK7,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 6. "DATMSK6,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 5. "DATMSK5,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 4. "DATMSK4,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 3. "DATMSK3,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 2. "DATMSK2,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 1. "DATMSK1,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 0. "DATMSK0,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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group.long 0x150++0x03
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line.long 0x00 "PF_PIN,PF Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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group.long 0x154++0x03
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line.long 0x00 "PF_DBEN,PF De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 14. "DBEN14,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 13. "DBEN13,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 12. "DBEN12,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 11. "DBEN11,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 10. "DBEN10,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 9. "DBEN9,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 8. "DBEN8,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 7. "DBEN7,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 6. "DBEN6,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 5. "DBEN5,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 4. "DBEN4,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 3. "DBEN3,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 2. "DBEN2,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 1. "DBEN1,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 0. "DBEN0,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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group.long 0x158++0x03
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line.long 0x00 "PF_INTTYPE,PF Interrupt Trigger Type Register"
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bitfld.long 0x00 15. "TYPE15,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 14. "TYPE14,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 13. "TYPE13,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 12. "TYPE12,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 11. "TYPE11,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 10. "TYPE10,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 9. "TYPE9,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 8. "TYPE8,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 7. "TYPE7,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 6. "TYPE6,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 5. "TYPE5,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 4. "TYPE4,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 3. "TYPE3,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 2. "TYPE2,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 1. "TYPE1,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 0. "TYPE0,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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group.long 0x15C++0x03
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line.long 0x00 "PF_INTEN,PF Interrupt Enable"
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bitfld.long 0x00 31. "RHIEN15,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 30. "RHIEN14,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 29. "RHIEN13,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 28. "RHIEN12,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 27. "RHIEN11,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 26. "RHIEN10,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 25. "RHIEN9,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 24. "RHIEN8,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 23. "RHIEN7,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 22. "RHIEN6,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 21. "RHIEN5,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 20. "RHIEN4,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 19. "RHIEN3,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 18. "RHIEN2,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 17. "RHIEN1,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 16. "RHIEN0,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 15. "FLIEN15,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 14. "FLIEN14,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 13. "FLIEN13,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 12. "FLIEN12,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 11. "FLIEN11,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 10. "FLIEN10,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 9. "FLIEN9,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 8. "FLIEN8,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 7. "FLIEN7,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 6. "FLIEN6,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 5. "FLIEN5,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 4. "FLIEN4,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 3. "FLIEN3,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 2. "FLIEN2,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 1. "FLIEN1,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 0. "FLIEN0,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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group.long 0x160++0x03
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line.long 0x00 "PF_INTSRC,PF Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 14. "INTSRC14,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 13. "INTSRC13,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 12. "INTSRC12,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 11. "INTSRC11,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 10. "INTSRC10,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 9. "INTSRC9,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 8. "INTSRC8,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 7. "INTSRC7,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 6. "INTSRC6,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 5. "INTSRC5,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 4. "INTSRC4,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 3. "INTSRC3,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 2. "INTSRC2,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 1. "INTSRC1,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 0. "INTSRC0,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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group.long 0x164++0x03
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line.long 0x00 "PF_SMTEN,PF Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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group.long 0x168++0x03
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line.long 0x00 "PF_SLEWCTL,PF High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 13. "HSREN13,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 11. "HSREN11,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 9. "HSREN9,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 7. "HSREN7,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 5. "HSREN5,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 3. "HSREN3,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 1. "HSREN1,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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group.long 0x180++0x03
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line.long 0x00 "PG_MODE,PG I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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group.long 0x184++0x03
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line.long 0x00 "PG_DINOFF,PG Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 30. "DINOFF14,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 29. "DINOFF13,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 28. "DINOFF12,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 27. "DINOFF11,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 26. "DINOFF10,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 25. "DINOFF9,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 24. "DINOFF8,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 23. "DINOFF7,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 22. "DINOFF6,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 21. "DINOFF5,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 20. "DINOFF4,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 19. "DINOFF3,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 18. "DINOFF2,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 17. "DINOFF1,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 16. "DINOFF0,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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group.long 0x188++0x03
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line.long 0x00 "PG_DOUT,PG Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 14. "DOUT14,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 13. "DOUT13,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 12. "DOUT12,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 11. "DOUT11,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 10. "DOUT10,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 9. "DOUT9,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 8. "DOUT8,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 7. "DOUT7,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 6. "DOUT6,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 5. "DOUT5,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 4. "DOUT4,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 3. "DOUT3,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 2. "DOUT2,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 1. "DOUT1,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 0. "DOUT0,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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group.long 0x18C++0x03
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line.long 0x00 "PG_DATMSK,PG Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 14. "DATMSK14,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 13. "DATMSK13,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 12. "DATMSK12,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 11. "DATMSK11,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 10. "DATMSK10,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 9. "DATMSK9,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 8. "DATMSK8,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 7. "DATMSK7,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 6. "DATMSK6,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 5. "DATMSK5,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 4. "DATMSK4,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 3. "DATMSK3,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 2. "DATMSK2,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 1. "DATMSK1,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 0. "DATMSK0,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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group.long 0x190++0x03
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line.long 0x00 "PG_PIN,PG Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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group.long 0x194++0x03
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line.long 0x00 "PG_DBEN,PG De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 14. "DBEN14,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 13. "DBEN13,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 12. "DBEN12,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 11. "DBEN11,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 10. "DBEN10,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 9. "DBEN9,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 8. "DBEN8,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 7. "DBEN7,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 6. "DBEN6,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 5. "DBEN5,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 4. "DBEN4,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 3. "DBEN3,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 2. "DBEN2,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 1. "DBEN1,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 0. "DBEN0,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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group.long 0x198++0x03
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line.long 0x00 "PG_INTTYPE,PG Interrupt Trigger Type Register"
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bitfld.long 0x00 15. "TYPE15,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 14. "TYPE14,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 13. "TYPE13,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 12. "TYPE12,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 11. "TYPE11,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 10. "TYPE10,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 9. "TYPE9,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 8. "TYPE8,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 7. "TYPE7,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 6. "TYPE6,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 5. "TYPE5,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 4. "TYPE4,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 3. "TYPE3,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 2. "TYPE2,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 1. "TYPE1,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 0. "TYPE0,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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group.long 0x19C++0x03
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line.long 0x00 "PG_INTEN,PG Interrupt Enable"
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bitfld.long 0x00 31. "RHIEN15,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 30. "RHIEN14,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 29. "RHIEN13,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 28. "RHIEN12,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 27. "RHIEN11,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 26. "RHIEN10,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 25. "RHIEN9,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 24. "RHIEN8,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 23. "RHIEN7,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 22. "RHIEN6,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 21. "RHIEN5,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 20. "RHIEN4,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 19. "RHIEN3,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 18. "RHIEN2,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 17. "RHIEN1,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 16. "RHIEN0,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 15. "FLIEN15,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 14. "FLIEN14,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 13. "FLIEN13,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 12. "FLIEN12,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 11. "FLIEN11,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 10. "FLIEN10,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 9. "FLIEN9,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 8. "FLIEN8,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 7. "FLIEN7,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 6. "FLIEN6,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 5. "FLIEN5,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 4. "FLIEN4,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 3. "FLIEN3,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 2. "FLIEN2,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 1. "FLIEN1,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 0. "FLIEN0,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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group.long 0x1A0++0x03
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line.long 0x00 "PG_INTSRC,PG Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 14. "INTSRC14,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 13. "INTSRC13,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 12. "INTSRC12,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 11. "INTSRC11,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 10. "INTSRC10,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 9. "INTSRC9,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 8. "INTSRC8,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 7. "INTSRC7,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 6. "INTSRC6,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 5. "INTSRC5,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 4. "INTSRC4,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 3. "INTSRC3,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 2. "INTSRC2,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 1. "INTSRC1,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 0. "INTSRC0,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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group.long 0x1A4++0x03
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line.long 0x00 "PG_SMTEN,PG Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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group.long 0x1A8++0x03
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line.long 0x00 "PG_SLEWCTL,PG High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 13. "HSREN13,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 11. "HSREN11,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 9. "HSREN9,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 7. "HSREN7,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 5. "HSREN5,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 3. "HSREN3,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 1. "HSREN1,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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group.long 0x1C0++0x03
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line.long 0x00 "PH_MODE,PH I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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group.long 0x1C4++0x03
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line.long 0x00 "PH_DINOFF,PH Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 30. "DINOFF14,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 29. "DINOFF13,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 28. "DINOFF12,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 27. "DINOFF11,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 26. "DINOFF10,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 25. "DINOFF9,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 24. "DINOFF8,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 23. "DINOFF7,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 22. "DINOFF6,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 21. "DINOFF5,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 20. "DINOFF4,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 19. "DINOFF3,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 18. "DINOFF2,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 17. "DINOFF1,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 16. "DINOFF0,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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group.long 0x1C8++0x03
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line.long 0x00 "PH_DOUT,PH Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 14. "DOUT14,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 13. "DOUT13,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 12. "DOUT12,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 11. "DOUT11,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 10. "DOUT10,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 9. "DOUT9,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 8. "DOUT8,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 7. "DOUT7,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 6. "DOUT6,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 5. "DOUT5,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 4. "DOUT4,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 3. "DOUT3,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 2. "DOUT2,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 1. "DOUT1,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 0. "DOUT0,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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group.long 0x1CC++0x03
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line.long 0x00 "PH_DATMSK,PH Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 14. "DATMSK14,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 13. "DATMSK13,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 12. "DATMSK12,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 11. "DATMSK11,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 10. "DATMSK10,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 9. "DATMSK9,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 8. "DATMSK8,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 7. "DATMSK7,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 6. "DATMSK6,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 5. "DATMSK5,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 4. "DATMSK4,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 3. "DATMSK3,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 2. "DATMSK2,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 1. "DATMSK1,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 0. "DATMSK0,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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group.long 0x1D0++0x03
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line.long 0x00 "PH_PIN,PH Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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group.long 0x1D4++0x03
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line.long 0x00 "PH_DBEN,PH De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 14. "DBEN14,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 13. "DBEN13,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 12. "DBEN12,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 11. "DBEN11,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 10. "DBEN10,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 9. "DBEN9,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 8. "DBEN8,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 7. "DBEN7,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 6. "DBEN6,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 5. "DBEN5,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 4. "DBEN4,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 3. "DBEN3,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 2. "DBEN2,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 1. "DBEN1,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 0. "DBEN0,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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group.long 0x1D8++0x03
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line.long 0x00 "PH_INTTYPE,PH Interrupt Trigger Type Register"
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bitfld.long 0x00 15. "TYPE15,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 14. "TYPE14,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 13. "TYPE13,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 12. "TYPE12,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 11. "TYPE11,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 10. "TYPE10,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 9. "TYPE9,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 8. "TYPE8,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 7. "TYPE7,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 6. "TYPE6,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 5. "TYPE5,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 4. "TYPE4,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 3. "TYPE3,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 2. "TYPE2,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 1. "TYPE1,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 0. "TYPE0,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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group.long 0x1DC++0x03
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line.long 0x00 "PH_INTEN,PH Interrupt Enable"
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bitfld.long 0x00 31. "RHIEN15,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 30. "RHIEN14,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 29. "RHIEN13,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 28. "RHIEN12,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 27. "RHIEN11,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 26. "RHIEN10,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 25. "RHIEN9,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 24. "RHIEN8,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 23. "RHIEN7,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 22. "RHIEN6,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 21. "RHIEN5,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 20. "RHIEN4,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 19. "RHIEN3,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 18. "RHIEN2,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 17. "RHIEN1,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 16. "RHIEN0,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 15. "FLIEN15,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 14. "FLIEN14,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 13. "FLIEN13,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 12. "FLIEN12,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 11. "FLIEN11,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 10. "FLIEN10,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 9. "FLIEN9,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 8. "FLIEN8,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 7. "FLIEN7,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 6. "FLIEN6,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 5. "FLIEN5,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 4. "FLIEN4,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 3. "FLIEN3,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 2. "FLIEN2,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 1. "FLIEN1,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 0. "FLIEN0,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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group.long 0x1E0++0x03
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line.long 0x00 "PH_INTSRC,PH Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 14. "INTSRC14,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 13. "INTSRC13,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 12. "INTSRC12,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 11. "INTSRC11,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 10. "INTSRC10,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 9. "INTSRC9,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 8. "INTSRC8,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 7. "INTSRC7,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 6. "INTSRC6,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 5. "INTSRC5,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 4. "INTSRC4,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 3. "INTSRC3,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 2. "INTSRC2,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 1. "INTSRC1,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 0. "INTSRC0,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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group.long 0x1E4++0x03
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line.long 0x00 "PH_SMTEN,PH Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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group.long 0x1E8++0x03
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line.long 0x00 "PH_SLEWCTL,PH High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 13. "HSREN13,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 11. "HSREN11,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 9. "HSREN9,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 7. "HSREN7,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 5. "HSREN5,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 3. "HSREN3,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 1. "HSREN1,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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group.long 0x200++0x03
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line.long 0x00 "PI_MODE,PI I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port N Bit M I/O Mode Control\nDetermine the I/O mode of port n bit m.\n" "0: INPUT only mode,1: OUTPUT mode,2: Open-drain mode,3: Quasi-bidirectional mode"
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group.long 0x204++0x03
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line.long 0x00 "PI_DINOFF,PI Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 30. "DINOFF14,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 29. "DINOFF13,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 28. "DINOFF12,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 27. "DINOFF11,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 26. "DINOFF10,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 25. "DINOFF9,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 24. "DINOFF8,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 23. "DINOFF7,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 22. "DINOFF6,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 21. "DINOFF5,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 20. "DINOFF4,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 19. "DINOFF3,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 18. "DINOFF2,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 17. "DINOFF1,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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bitfld.long 0x00 16. "DINOFF0,Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin" "0: Digital input path Enabled,1: Digital input path Disabled (Digital input is.."
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group.long 0x208++0x03
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line.long 0x00 "PI_DOUT,PI Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 14. "DOUT14,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 13. "DOUT13,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 12. "DOUT12,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 11. "DOUT11,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 10. "DOUT10,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 9. "DOUT9,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 8. "DOUT8,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 7. "DOUT7,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 6. "DOUT6,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 5. "DOUT5,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 4. "DOUT4,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 3. "DOUT3,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 2. "DOUT2,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 1. "DOUT1,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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bitfld.long 0x00 0. "DOUT0,Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output open-drain or Quasi-bidirectional mode.\n" "0: Drive port n bit m high low,1: Drive port n bit m high level"
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group.long 0x20C++0x03
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line.long 0x00 "PI_DATMSK,PI Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 14. "DATMSK14,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 13. "DATMSK13,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 12. "DATMSK12,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 11. "DATMSK11,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 10. "DATMSK10,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 9. "DATMSK9,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 8. "DATMSK8,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 7. "DATMSK7,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 6. "DATMSK6,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 5. "DATMSK5,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 4. "DATMSK4,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 3. "DATMSK3,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 2. "DATMSK2,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 1. "DATMSK1,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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bitfld.long 0x00 0. "DATMSK0,Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]" "0: Pn_DOUT[m] bit writing is valid,1: Pn_DOUT[m] bit writing is ignored"
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group.long 0x210++0x03
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line.long 0x00 "PI_PIN,PI Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin" "0,1"
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group.long 0x214++0x03
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line.long 0x00 "PI_DBEN,PI De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 14. "DBEN14,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 13. "DBEN13,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 12. "DBEN12,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 11. "DBEN11,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 10. "DBEN10,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 9. "DBEN9,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 8. "DBEN8,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 7. "DBEN7,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 6. "DBEN6,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 5. "DBEN5,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 4. "DBEN4,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 3. "DBEN3,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 2. "DBEN2,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 1. "DBEN1,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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bitfld.long 0x00 0. "DBEN0,Port N Bit M Input De-Bounce Enable\nDBEN[m] is used to enable the de-bounce function for each corresponding bit" "0: Port n bit m input de-bounce Disabled,1: Port n bit m input de-bounce Enabled"
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group.long 0x218++0x03
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line.long 0x00 "PI_INTTYPE,PI Interrupt Trigger Type Register"
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bitfld.long 0x00 15. "TYPE15,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 14. "TYPE14,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 13. "TYPE13,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 12. "TYPE12,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 11. "TYPE11,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 10. "TYPE10,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 9. "TYPE9,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 8. "TYPE8,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 7. "TYPE7,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 6. "TYPE6,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 5. "TYPE5,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 4. "TYPE4,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 3. "TYPE3,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 2. "TYPE2,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 1. "TYPE1,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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bitfld.long 0x00 0. "TYPE0,Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge" "0: Edge triggered interrupt,1: Level triggered interrupt"
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group.long 0x21C++0x03
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line.long 0x00 "PI_INTEN,PI Interrupt Enable"
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bitfld.long 0x00 31. "RHIEN15,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 30. "RHIEN14,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 29. "RHIEN13,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 28. "RHIEN12,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 27. "RHIEN11,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 26. "RHIEN10,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 25. "RHIEN9,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 24. "RHIEN8,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 23. "RHIEN7,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 22. "RHIEN6,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 21. "RHIEN5,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 20. "RHIEN4,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 19. "RHIEN3,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 18. "RHIEN2,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 17. "RHIEN1,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 16. "RHIEN0,Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m high-level or rising edge..,1: Port n bit m high-level or rising edge.."
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bitfld.long 0x00 15. "FLIEN15,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 14. "FLIEN14,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 13. "FLIEN13,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 12. "FLIEN12,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 11. "FLIEN11,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 10. "FLIEN10,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 9. "FLIEN9,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 8. "FLIEN8,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 7. "FLIEN7,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 6. "FLIEN6,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 5. "FLIEN5,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 4. "FLIEN4,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 3. "FLIEN3,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 2. "FLIEN2,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 1. "FLIEN1,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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bitfld.long 0x00 0. "FLIEN0,Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n" "0: Port n bit m low-level or falling edge..,1: Port n bit m low-level or falling edge.."
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group.long 0x220++0x03
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line.long 0x00 "PI_INTSRC,PI Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 14. "INTSRC14,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 13. "INTSRC13,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 12. "INTSRC12,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 11. "INTSRC11,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 10. "INTSRC10,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 9. "INTSRC9,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 8. "INTSRC8,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 7. "INTSRC7,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 6. "INTSRC6,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 5. "INTSRC5,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 4. "INTSRC4,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 3. "INTSRC3,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 2. "INTSRC2,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 1. "INTSRC1,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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bitfld.long 0x00 0. "INTSRC0,Port N Bit M Interrupt Trigger Source Indicator\nRead:\n" "0: No interrupt at Port n.\nNo effect,1: Port n bit m generate an interrupt.\nClear.."
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group.long 0x224++0x03
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line.long 0x00 "PI_SMTEN,PI Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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|
newline
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bitfld.long 0x00 1. "SMTEN1,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port N Bit M Input Schmitt Trigger Enable Bit\n" "0: P I/O input Schmitt Trigger function Disabled,1: P I/O input Schmitt Trigger function Enabled"
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group.long 0x228++0x03
|
|
line.long 0x00 "PI_SLEWCTL,PI High Slew Rate Control"
|
|
bitfld.long 0x00 15. "HSREN15,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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|
newline
|
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bitfld.long 0x00 13. "HSREN13,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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|
newline
|
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bitfld.long 0x00 11. "HSREN11,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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|
newline
|
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bitfld.long 0x00 9. "HSREN9,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
|
|
newline
|
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bitfld.long 0x00 7. "HSREN7,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
|
|
newline
|
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bitfld.long 0x00 5. "HSREN5,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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|
newline
|
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bitfld.long 0x00 3. "HSREN3,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
|
|
newline
|
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bitfld.long 0x00 1. "HSREN1,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port N Bit M High Slew Rate Control\n" "0: P I/O output with basic slew rate,1: P I/O output with higher slew rate"
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group.long 0x440++0x03
|
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line.long 0x00 "GPIO_DBCTL,Interrupt De-bounce Control"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock On Mode\nSetting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled.\n" "0: Disable the clock if the all port interrupts..,1: Interrupt generated circuit clock always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-Bounce Counter Clock Source Selection\n" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the.."
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|
newline
|
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-Bounce Sampling Cycle Selection\n" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
|
|
group.long 0x800++0x03
|
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line.long 0x00 "PA0_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
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group.long 0x804++0x03
|
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line.long 0x00 "PA1_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
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group.long 0x808++0x03
|
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line.long 0x00 "PA2_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
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group.long 0x80C++0x03
|
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line.long 0x00 "PA3_PDIO,GPIO PA.n Pin Data Input/Output"
|
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bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
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|
group.long 0x810++0x03
|
|
line.long 0x00 "PA4_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
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group.long 0x814++0x03
|
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line.long 0x00 "PA5_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
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|
group.long 0x818++0x03
|
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line.long 0x00 "PA6_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
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|
group.long 0x81C++0x03
|
|
line.long 0x00 "PA7_PDIO,GPIO PA.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
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|
group.long 0x820++0x03
|
|
line.long 0x00 "PA8_PDIO,GPIO PA.n Pin Data Input/Output"
|
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bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
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|
group.long 0x824++0x03
|
|
line.long 0x00 "PA9_PDIO,GPIO PA.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
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|
group.long 0x828++0x03
|
|
line.long 0x00 "PA10_PDIO,GPIO PA.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
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|
group.long 0x82C++0x03
|
|
line.long 0x00 "PA11_PDIO,GPIO PA.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "PA12_PDIO,GPIO PA.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "PA13_PDIO,GPIO PA.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "PA14_PDIO,GPIO PA.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "PA15_PDIO,GPIO PA.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "PB0_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "PB1_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "PB2_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "PB3_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "PB4_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "PB5_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "PB6_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x85C++0x03
|
|
line.long 0x00 "PB7_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "PB8_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x864++0x03
|
|
line.long 0x00 "PB9_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "PB10_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x86C++0x03
|
|
line.long 0x00 "PB11_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "PB12_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x874++0x03
|
|
line.long 0x00 "PB13_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "PB14_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x87C++0x03
|
|
line.long 0x00 "PB15_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "PC0_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "PC1_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "PC2_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x88C++0x03
|
|
line.long 0x00 "PC3_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "PC4_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "PC5_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "PC6_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x89C++0x03
|
|
line.long 0x00 "PC7_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "PC8_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8A4++0x03
|
|
line.long 0x00 "PC9_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "PC10_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8AC++0x03
|
|
line.long 0x00 "PC11_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "PC12_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8B4++0x03
|
|
line.long 0x00 "PC13_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "PC14_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8BC++0x03
|
|
line.long 0x00 "PC15_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "PD0_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8C4++0x03
|
|
line.long 0x00 "PD1_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "PD2_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8CC++0x03
|
|
line.long 0x00 "PD3_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "PD4_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8D4++0x03
|
|
line.long 0x00 "PD5_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "PD6_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8DC++0x03
|
|
line.long 0x00 "PD7_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "PD8_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8E4++0x03
|
|
line.long 0x00 "PD9_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "PD10_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8EC++0x03
|
|
line.long 0x00 "PD11_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "PD12_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8F4++0x03
|
|
line.long 0x00 "PD13_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "PD14_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x8FC++0x03
|
|
line.long 0x00 "PD15_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "PE0_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x904++0x03
|
|
line.long 0x00 "PE1_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "PE2_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x90C++0x03
|
|
line.long 0x00 "PE3_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "PE4_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x914++0x03
|
|
line.long 0x00 "PE5_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "PE6_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x91C++0x03
|
|
line.long 0x00 "PE7_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "PE8_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x924++0x03
|
|
line.long 0x00 "PE9_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "PE10_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x92C++0x03
|
|
line.long 0x00 "PE11_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "PE12_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x934++0x03
|
|
line.long 0x00 "PE13_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "PE14_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x93C++0x03
|
|
line.long 0x00 "PE15_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "PF0_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x944++0x03
|
|
line.long 0x00 "PF1_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "PF2_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x94C++0x03
|
|
line.long 0x00 "PF3_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "PF4_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x954++0x03
|
|
line.long 0x00 "PF5_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "PF6_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x95C++0x03
|
|
line.long 0x00 "PF7_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "PF8_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x964++0x03
|
|
line.long 0x00 "PF9_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "PF10_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x96C++0x03
|
|
line.long 0x00 "PF11_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "PF12_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x974++0x03
|
|
line.long 0x00 "PF13_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "PF14_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x97C++0x03
|
|
line.long 0x00 "PF15_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "PG0_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x984++0x03
|
|
line.long 0x00 "PG1_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "PG2_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x98C++0x03
|
|
line.long 0x00 "PG3_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "PG4_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x994++0x03
|
|
line.long 0x00 "PG5_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "PG6_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x99C++0x03
|
|
line.long 0x00 "PG7_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "PG8_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9A4++0x03
|
|
line.long 0x00 "PG9_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "PG10_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9AC++0x03
|
|
line.long 0x00 "PG11_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "PG12_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9B4++0x03
|
|
line.long 0x00 "PG13_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "PG14_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9BC++0x03
|
|
line.long 0x00 "PG15_PDIO,GPIO PG.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "PH0_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9C4++0x03
|
|
line.long 0x00 "PH1_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "PH2_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9CC++0x03
|
|
line.long 0x00 "PH3_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "PH4_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9D4++0x03
|
|
line.long 0x00 "PH5_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "PH6_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9DC++0x03
|
|
line.long 0x00 "PH7_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "PH8_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9E4++0x03
|
|
line.long 0x00 "PH9_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "PH10_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9EC++0x03
|
|
line.long 0x00 "PH11_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "PH12_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9F4++0x03
|
|
line.long 0x00 "PH13_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9F8++0x03
|
|
line.long 0x00 "PH14_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0x9FC++0x03
|
|
line.long 0x00 "PH15_PDIO,GPIO PH.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "PI0_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "PI1_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "PI2_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "PI3_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "PI4_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "PI5_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "PI6_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "PI7_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "PI8_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "PI9_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "PI10_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "PI11_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "PI12_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "PI13_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "PI14_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
group.long 0xA3C++0x03
|
|
line.long 0x00 "PI15_PDIO,GPIO PI.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,Port N Bit M (PDIO) Value\nWrite:\nFor example a writing of PA0 reflects the value of bit PA_DOUT[0] a reading returns the value of PA_PIN[0]" "0: Clear PDIO port latch to output low.\nPort..,1: Set PDIO port latch to output high.\nPort pin.."
|
|
tree.end
|
|
tree "I2C"
|
|
repeat 5. (list 0. 1. 2. 3. 4.) (list ad:0x40080000 ad:0x40081000 ad:0x40082000 ad:0x40083000 ad:0x40084000)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C_CTL,I2C Control Register"
|
|
bitfld.long 0x00 7. "INTEN,I2C Interrupt Enable Bit\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
|
bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register the SI flag is set by hardware and if bit INTEN (I2C_CTL [7]) is set the I2C interrupt is requested" "0,1"
|
|
bitfld.long 0x00 2. "AA,Assert Acknowledge Control\n" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C_DAT,I2C Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of I2C serial port"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status Bits\nThe status register of I2C:\nThe three least significant bits are always 0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIVIDER,I2C Clock Divided Bits\nNote: The minimum value of DIVIDER is 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
|
|
bitfld.long 0x00 2. "TOCEN,Time-Out Counter Enable Bit\nWhen Enabled the 14-bit time-out counter will start counting when SI (I2C_CTL[3]) is clear" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 1. "TOCDIV4,Time-Out Counter Input Clock Divided By 4\nWhen Enabled The time-out period is extend 4 times" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TOIF,Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN (I2C_CTL[7])) is set to 1.\nNote: Write 1 to clear this bit" "0,1"
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "I2C_ADDR$1,I2C Slave Address Register $1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "I2C_ADDRMSK$1,I2C Slave Address Mask Register $1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDRMSK,I2C Address Mask Bits\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
repeat.end
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
|
|
bitfld.long 0x00 0. "WKEN,I2C Wake-Up Enable Bit\n" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WKIF,I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit" "0: No wake up occurred,1: Wake up from Power-down mode"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "I2S"
|
|
base ad:0x40048000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2S_CTL,I2S Control Register"
|
|
bitfld.long 0x00 24. "PCMEN,PCM Interface Enable Bit\n" "0: I2S Interface,1: PCM Interface"
|
|
bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit\n" "0: Receives right channel data when monaural..,1: Receives left channel data when monaural.."
|
|
newline
|
|
bitfld.long 0x00 21. "RXPDMAEN,Receive DMA Enable Bit\nNote: When RX DMA is enabled I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty" "0: RX DMA Disabled,1: RX DMA Enabled"
|
|
bitfld.long 0x00 20. "TXPDMAEN,Transmit DMA Enable Bit\nNote: When TX DMA is enables I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full" "0: TX DMA Disabled,1: TX DMA Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. "RXCLR,Clear Receive FIFO\nNote1: Write 1 to clear receive FIFO internal pointer is reset to FIFO start point and RXCNT (I2S_STATUS[27:24]) returns 0 and receive FIFO becomes empty.\nNote2: This bit is cleared by hardware automatically read it return zero" "0: No Effect,1: Clear RX FIFO"
|
|
bitfld.long 0x00 18. "TXCLR,Clear Transmit FIFO\nNote1: Write 1 to clear transmit FIFO internal pointer is reset to FIFO start point and TXCNT(I2S_STATUS[31:28]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed" "0: No Effect,1: Clear TX FIFO"
|
|
newline
|
|
bitfld.long 0x00 17. "LZCEN,Left Channel Zero-Cross Detect Enable Bit\nNote1: If this bit is set to 1 when left channel data sign bit change or next shift data bits are all zero then LZCIF(I2S_STATUS[23]) flag is set to 1.\nNote2: If LZCIF Flag is set to 1 the left channel.." "0: Left channel zero-cross detect Disabled,1: Left channel zero-cross detect Enabled"
|
|
bitfld.long 0x00 16. "RZCEN,Right Channel Zero-Cross Detection Enable Bit\nNote1: If this bit is set to 1 when right channel data sign bit change or next shift data bits are all zero then RZCIF(I2S_STATUS[22]) flag is set to 1.\nNote2: If RZCIF Flag is set to 1 the right.." "0: Right channel zero-cross detect Disabled,1: Right channel zero-cross detect Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nNote: If the external crystal clock in NuMicro( NUC442/NUC472 series is frequency 2*N*256fs software can program MCLKDIV(I2S_CLKDIV[5:0]) to get 256fs clock to audio codec chip" "0: Master clock Disabled,1: Master clock Enabled"
|
|
bitfld.long 0x00 12.--14. "RXTH,Receive FIFO Threshold Level\nNote: When received data word(s) in buffer is equal to or higher than threshold level then RXTHIF flag is set" "0: 1 word data in receive FIFO,1: 2 word data in receive FIFO,2: 3 word data in receive FIFO,3: 4 word data in receive FIFO,4: 5 word data in receive FIFO,5: 6 word data in receive FIFO,6: 7 word data in receive FIFO,7: 8 word data in receive FIFO"
|
|
newline
|
|
bitfld.long 0x00 9.--11. "TXTH,Transmit FIFO Threshold Level\nNote: If remain data word(s) in transmit FIFO is the same or less than threshold level then TXTHIF flag is set" "0: 0 word data in transmit FIFO,1: 1 word data in transmit FIFO,2: 2 words data in transmit FIFO,3: 3 words data in transmit FIFO,4: 4 words data in transmit FIFO,5: 5 words data in transmit FIFO,6: 6 words data in transmit FIFO,7: 7 words data in transmit FIFO"
|
|
bitfld.long 0x00 8. "SLAVE,Slave Mode Enable Bit\nNote: I2S can operate as master or slave" "0: Master mode,1: Slave mode"
|
|
newline
|
|
bitfld.long 0x00 7. "FORMAT,Data Format Selection\n" "0: I2S data format.\nPCM mode A,1: MSB justified data format.\nPCM mode B"
|
|
bitfld.long 0x00 6. "MONO,Monaural Data Control\nNote: when chip records data only right channel data will be saved if monaural format is select" "0: Data is stereo format,1: Data is monaural format"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "WDWIDTH,Word Width\n" "0: data is 8-bit,1: data is 16-bit,2: data is 24-bit,3: data is 32-bit"
|
|
bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit\n" "0: Transmit data is shifted from buffer,1: Transmit zero data"
|
|
newline
|
|
bitfld.long 0x00 2. "RXEN,Receive Enable Bit\n" "0: Data receiving Disabled,1: Data receiving Enabled"
|
|
bitfld.long 0x00 1. "TXEN,Transmit Enable Bit\n" "0: Data transmission Disabled,1: Data transmission Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\n" "0: Disabled,1: Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2S_CLKDIV,I2S Clock Divider Register"
|
|
hexmask.long.word 0x00 8.--16. 1. "BCLKDIV,Bit Clock Divider\nIf I2S operates in Master mode bit clock is provided by the NuMicro( NUC442/NUC472 series. Software can program these bits to generate sampling rate clock frequency.\nNote: F_BCLK is the frequency of BCLK and F_I2SCLK is the.."
|
|
bitfld.long 0x00 0.--5. "MCLKDIV,Master Clock Divider\nIf chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2S_IEN,I2S Interrupt Enable Register"
|
|
bitfld.long 0x00 12. "LZCIEN,Left Channel Zero-Cross Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and left channel zero-cross" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 11. "RZCIEN,Right Channel Zero-Cross Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and right channel zero-cross" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "TXTHIEN,Transmit FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH(I2S_CTL[11:9])" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 9. "TXOVIEN,Transmit FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and TXOVIF(I2S_STATUS[17]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "TXUDIEN,Transmit FIFO Underflow Interrupt Enable Bit\nNote: Interrupt occur if this bit is set to 1 and TXUDIF(I2S_STATUS[16]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Level Interrupt Enable Bit\nNote: When data word in receive FIFO is equal or higher than RXTH(I2S_CTL[14:12]) and the RXTHIF bit is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RXOVIEN,Receive FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and RXOVIF(I2S_STATUS[9]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 0. "RXUDIEN,Receive FIFO Underflow Interrupt E Enable Bit\nNote: If software reads receive FIFO when it is empty then RXUDIF(I2S_STATUS[8]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2S_STATUS,I2S Status Register"
|
|
rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Level (Read Only)\nThese bits indicate word number in transmit FIFO\n" "0: No data,1: 1 word in transmit FIFO,?,?,?,?,?,?,8: 8 words in transmit FIFO,?..."
|
|
rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Level (Read Only)\nThese bits indicate word number in receive FIFO\n" "0: No data,1: 1 word in receive FIFO,?,?,?,?,?,?,8: 8 words in receive FIFO,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "LZCIF,Left Channel Zero-Cross Flag\nIt indicates left channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0" "0: No zero-cross,1: Left channel zero-cross is detected"
|
|
bitfld.long 0x00 22. "RZCIF,Right Channel Zero-Cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0" "0: No zero-cross,1: Right channel zero-cross is detected"
|
|
newline
|
|
rbitfld.long 0x00 21. "TXBUSY,Transmit Busy (Read Only)\nNote: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out" "0: Transmit shift buffer is empty,1: Transmit shift buffer is busy"
|
|
rbitfld.long 0x00 20. "TXEMPTY,Transmit FIFO Empty (Read Only)\nThis bit reflect data word number in transmit FIFO is zero\n" "0: Not empty,1: Empty"
|
|
newline
|
|
rbitfld.long 0x00 19. "TXFULL,Transmit FIFO Full (Read Only)\nThis bit reflect data word number in transmit FIFO is 8\n" "0: Not full,1: Full"
|
|
rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Flag (Read Only)\nNote: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH(I2S_CTL[11:9]) the TXTHIF bit becomes to 1" "0: Data word(s) in FIFO is higher than threshold..,1: Data word(s) in FIFO is equal or lower than.."
|
|
newline
|
|
bitfld.long 0x00 17. "TXOVIF,Transmit FIFO Overflow Flag\nNote1: Write data to transmit FIFO when it is full and this bit set to 1\nNote2: Write 1 to clear this bit to 0" "0: No overflow,1: Overflow"
|
|
bitfld.long 0x00 16. "TXUDIF,Transmit FIFO Underflow Flag\nNote1: When transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nNote2: Write 1 to clear this bit to 0" "0: No underflow,1: Underflow"
|
|
newline
|
|
rbitfld.long 0x00 12. "RXEMPTY,Receive FIFO Empty (Read Only)\nNote: This bit reflects data words number in receive FIFO is zero" "0: Not empty,1: Empty"
|
|
rbitfld.long 0x00 11. "RXFULL,Receive FIFO Full (Read Only)\nNote: This bit reflects data words number in receive FIFO is 8" "0: Not full,1: Full"
|
|
newline
|
|
rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Flag (Read Only)\nNote: When data word(s) in receive FIFO is equal or higher than threshold value set in RXTH(I2S_CTL[14:12]) the RXTHIF bit becomes to 1" "0: Data word(s) in FIFO is lower than threshold..,1: Data word(s) in FIFO is equal or higher than.."
|
|
bitfld.long 0x00 9. "RXOVIF,Receive FIFO Overflow Flag\nNote1: When receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1 data in 1st buffer is overwrote.\nNote2: Write 1 to clear this bit to 0" "0: No overflow occur,1: Overflow occur"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUDIF,Receive FIFO Underflow Flag\nNote1: When receive FIFO is empty and software reads the receive FIFO again" "0: No underflow occur,1: Underflow occur"
|
|
rbitfld.long 0x00 3. "RIGHT,Right Channel (Read Only)\nNote: This bit indicate current transmit data is belong to right channel" "0: Left channel,1: Right channel"
|
|
newline
|
|
rbitfld.long 0x00 2. "TXIF,I2S Transmit Interrupt (Read Only)\n" "0: No transmit interrupt,1: Transmit interrupt"
|
|
rbitfld.long 0x00 1. "RXIF,I2S Receive Interrupt (Read Only)\n" "0: No receive interrupt,1: Receive interrupt"
|
|
newline
|
|
rbitfld.long 0x00 0. "I2SIF,I2S Interrupt Flag (Read Only)\nNote: It is wire-OR of TXIF and RXIF bits" "0: No I2S interrupt,1: I2S interrupt"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "I2S_TX,I2S Transmit FIFO Register"
|
|
hexmask.long 0x00 0.--31. 1. "TX,Transmit FIFO Bits\nI2S contains 8 words (8x32 bit) data buffer for data transmit"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "I2S_RX,I2S Receive FIFO Register"
|
|
hexmask.long 0x00 0.--31. 1. "RX,Receive FIFO Bits\nI2S contains 8 words (8x32 bit) data buffer for data receive"
|
|
tree.end
|
|
tree "NMI"
|
|
base ad:0x40000300
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NMIEN,NMI Source Interrupt Enable Control Register"
|
|
bitfld.long 0x00 15. "EINT7,External Interrupt 7 NMI Source Enable\n" "0: External interrupt 7 NMI source Disabled,1: External interrupt 7 NMI source Enabled"
|
|
bitfld.long 0x00 14. "EINT6,External Interrupt 6 NMI Source Enable\n" "0: External interrupt 6 NMI source Disabled,1: External interrupt 6 NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "EINT5,External Interrupt 5 NMI Source Enable\n" "0: External interrupt 5 NMI source Disabled,1: External interrupt 5 NMI source Enabled"
|
|
bitfld.long 0x00 12. "EINT4,External Interrupt 4 NMI Source Enable\n" "0: External interrupt 4 NMI source Disabled,1: External interrupt 4 NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "EINT3,External Interrupt 3 NMI Source Enable\n" "0: External interrupt 3 NMI source Disabled,1: External interrupt 3 NMI source Enabled"
|
|
bitfld.long 0x00 10. "EINT2,External Interrupt 2 NMI Source Enable\n" "0: External interrupt 2 NMI source Disabled,1: External interrupt 2 NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "EINT1,External Interrupt 1 NMI Source Enable\n" "0: External interrupt 1 NMI source Disabled,1: External interrupt 1 NMI source Enabled"
|
|
bitfld.long 0x00 8. "EINT0,External Interrupt 0 NMI Source Enable\n" "0: External interrupt 0 NMI source Disabled,1: External interrupt 0 NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "TAMPER,TAMPER_INT NMI Source Enable\n" "0: Backup register tamper detected interrupt.NMI..,1: Backup register tamper detected interrupt.NMI.."
|
|
bitfld.long 0x00 6. "RTC,RTC NMI Source Enable\n" "0: RTC NMI source Disabled,1: RTC NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected NMI Source Enable\n" "0: Clock fail detected interrupt NMI source..,1: Clock fail detected interrupt NMI source.."
|
|
bitfld.long 0x00 3. "SRAMFAIL,SRAM ParityCheck Error NMI Source Enable\n" "0: SRAM parity check error NMI source Disabled,1: SRAM parity check error NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "PWRWK,Power-down Mode Wake-up NMI Source Enable\n" "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled"
|
|
bitfld.long 0x00 1. "IRC,IRC TRIM NMI Source Enable\n" "0: IRC TRIM NMI source Disabled,1: IRC TRIM NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "BOD,BOD NMI Source Enable\n" "0: BOD NMI source Disabled,1: BOD NMI source Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "NMISTS,NMI Source Interrupt Status Register"
|
|
bitfld.long 0x00 15. "EINT7,External Interrupt 7 Interrupt Flag (Read Only)\n" "0: External Interrupt 7 interrupt is deasserted,1: External Interrupt 7 interrupt is asserted"
|
|
bitfld.long 0x00 14. "EINT6,External Interrupt 6 Interrupt Flag (Read Only)\n" "0: External Interrupt 6 interrupt is deasserted,1: External Interrupt 6 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 13. "EINT5,External Interrupt 5 Interrupt Flag (Read Only)\n" "0: External Interrupt 5 interrupt is deasserted,1: External Interrupt 5 interrupt is asserted"
|
|
bitfld.long 0x00 12. "EINT4,External Interrupt 4 Interrupt Flag (Read Only)\n" "0: External Interrupt 4 interrupt is deasserted,1: External Interrupt 4 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 11. "EINT3,External Interrupt 3 Interrupt Flag (Read Only)\n" "0: External Interrupt 3 interrupt is deasserted,1: External Interrupt 3 interrupt is asserted"
|
|
bitfld.long 0x00 10. "EINT2,External Interrupt 2 Interrupt Flag (Read Only)\n" "0: External Interrupt 2 interrupt is deasserted,1: External Interrupt 2 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 9. "EINT1,External Interrupt 1 Interrupt Flag (Read Only)\n" "0: External Interrupt 1 interrupt is deasserted,1: External Interrupt 1 interrupt is asserted"
|
|
bitfld.long 0x00 8. "EINT0,External Interrupt 0 Interrupt Flag (Read Only)\n" "0: External Interrupt 0 interrupt is deasserted,1: External Interrupt 0 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 7. "TAMPER,TAMPER_INT Interrupt Flag (Read Only)\n" "0: Backup register tamper detected interrupt is..,1: Backup register tamper detected interrupt is.."
|
|
bitfld.long 0x00 6. "RTC,RTC Interrupt Flag (Read Only)\n" "0: RTC interrupt is deasserted,1: RTC interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected Interrupt Flag (Read Only)\n" "0: Clock fail detected interrupt is deasserted,1: Clock fail detected interrupt is asserted"
|
|
bitfld.long 0x00 3. "SRAMFAIL,SRAM ParityCheck Error Interrupt Flag (Read Only)\n" "0: SRAM parity check error interrupt is deasserted,1: SRAM parity check error interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 2. "PWRWK,Power-down Mode Wake-up Interrupt Flag (Read Only)\n" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted"
|
|
bitfld.long 0x00 1. "IRC,IRC TRIM Interrupt Flag (Read Only)\n" "0: HIRC TRIM interrupt is deasserted,1: HIRC TRIM interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 0. "BOD,BOD Interrupt Flag (Read Only)\n" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted"
|
|
tree.end
|
|
tree "NVIC"
|
|
base ad:0xE000E100
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x0 0x4 0x8 0xC 0x10 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "NVIC_ISER$1,IRQ0 ~ IRQ159 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts and show which interrupts are enabled\nWrite:\n"
|
|
repeat.end
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x0 0x4 0x8 0xC 0x10 )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "NVIC_ICER$1,IRQ0 ~ IRQ159 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt Clear Enable Control\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts and show which interrupts are enabled.\nWrite:\n"
|
|
repeat.end
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "NVIC_ISPR$1,IRQ0 ~ IRQ159 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-Pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state and show which interrupts are pending\nWrite:\n"
|
|
repeat.end
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "NVIC_ICPR$1,IRQ0 ~ IRQ159 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRPEND,Interrupt Clear-Pending\nThe NVIC_ICPR0-NCVIC_ICPR3 registers remove the pending state from interrupts and show which interrupts are pending\nWrite:\n"
|
|
repeat.end
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C 0x10 )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "NVIC_IABR$1,IRQ0 ~ IRQ159 Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active"
|
|
repeat.end
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x300)++0x03
|
|
line.long 0x00 "NVIC_IPR$1,IRQ0 ~ IRQ159 Interrupt Priority Control Register"
|
|
bitfld.long 0x00 28.--31. "PRI_4n3,Priority Of IRQ_4n+3\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "PRI_4n2,Priority Of IRQ_4n+2\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PRI_4n1,Priority Of IRQ_4n+1\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "PRI_4n0,Priority Of IRQ_4n+0\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x340)++0x03
|
|
line.long 0x00 "NVIC_IPR$1,IRQ0 ~ IRQ159 Interrupt Priority Control Register"
|
|
bitfld.long 0x00 28.--31. "PRI_4n3,Priority Of IRQ_4n+3\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. "PRI_4n2,Priority Of IRQ_4n+2\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PRI_4n1,Priority Of IRQ_4n+1\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. "PRI_4n0,Priority Of IRQ_4n+0\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0xE00++0x03
|
|
line.long 0x00 "NVIC_STIR,Software Trigger Interrupt Registers"
|
|
hexmask.long.word 0x00 0.--8. 1. "INTID,Interrupt ID\nWrite to the STIR To Generate An Interrupt from Software\nWhen the USERSETMPEND bit in the SCR is set to 1 unprivileged software can access the STIR\nInterrupt ID of the interrupt to trigger in the range 0-63"
|
|
tree.end
|
|
tree "OPS"
|
|
base ad:0x40046000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "OPA_CTL,OP Amplifier Control Register"
|
|
bitfld.long 0x00 9. "OPAIE1,OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit\nOPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state in the meanwhile if OPAIE1 is set to 1 a.." "0: OP Amplifier 1 digital output interrupt..,1: OP Amplifier 1 digital output interrupt.."
|
|
bitfld.long 0x00 8. "OPAIE0,OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit\nThe OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state in the meanwhile if OPAIE0 is set to 1 a.." "0: OP Amplifier 0 digital output interrupt..,1: OP Amplifier 0 digital output interrupt.."
|
|
newline
|
|
bitfld.long 0x00 5. "OPSMTEN1,OP Amplifier 1 Schmitt Trigger Non-Inverting Buffer Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 4. "OPSMTEN0,OP Amplifier 0 Schmitt Trigger Non-Inverting Buffer Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "OPEN1,OP Amplifier 1 Enable Bit\nNote: OP Amplifier 1 output needs wait stable 20 s after OPEN1 is first set" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "OPEN0,OP Amplifier 0 Enable Bit\nNote: OP Amplifier 0 output needs wait stable 20 s after OPEN0 is first set" "0: Disabled,1: Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OPA_STATUS,OP Amplifier Status Register"
|
|
bitfld.long 0x00 5. "OPDF1,OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag\nOPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state" "0,1"
|
|
bitfld.long 0x00 4. "OPDF0,OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag\nOPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "OPDO1,OP Amplifier 1 Digital Output\n" "0,1"
|
|
bitfld.long 0x00 0. "OPDO0,OP Amplifier 0 Digital Output\n" "0,1"
|
|
tree.end
|
|
tree "OTG"
|
|
base ad:0x4004D000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "OTG_CTL,OTG Control Register"
|
|
bitfld.long 0x00 8. "WKEN,OTG Wake-Up Enable Bit\n" "0: OTG ID pin status change wake-up Disabled,1: OTG ID pin status change wake-up Enabled"
|
|
bitfld.long 0x00 7. "PDEVCKON,Force OTG PHY Output Clock To USB Device\nIf software configures OTG controller as OTG device and OTG device as A-device OTG controller will output OTG PHY clock (30 MHz) to USB device only when OTG device as A-peripheral" "0: USB device clock is available only when OTG..,1: Force output OTG PHY clock to USB device"
|
|
newline
|
|
bitfld.long 0x00 4. "OTGEN,OTG Function Enable Bit\nIf USB is configured as OTG device this bit must set high.\n" "0: OTG function Disabled,1: OTG function Enabled"
|
|
bitfld.long 0x00 2. "HNPREQEN,OTG B-Device HNP Enable/Request\nSet this bit to TRUE after the OTG A-device successfully sends a SetFeature(b_hnp_enable) command to the OTG B-device This bit will be cleared automatically when a bus reset or SESS_VLD goes from TRUE to FALSE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "BUSREQ,OTG A-Device Bus Request\nIf user application of an OTG A-device wants to do data transfers via USB bus set this bit to high Otherwise if user application won't use the bus any more set this bit low" "0,1"
|
|
bitfld.long 0x00 0. "VBUSDROP,Drop The VUSB Bus\nIf user application running on this OTG A-device wants to conserve power consumption set this bit to high When set this bit to TRUE BUSREQ shall be cleared as well.\n" "0: Did Not drop the VBUS and keep going on USB..,1: Drop the VBUS to conserve power consumption"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTG_PHYCTL,OTG PHY Control Register"
|
|
bitfld.long 0x00 9. "OTGPHYEN,OTG PHY Enable Control when Device Configured as OTG-Device\nWhen device is configured as OTG-device hardware will not enable OTG PHY automatically" "0: OTG PHY Disabled,1: OTG PHY Enabled"
|
|
bitfld.long 0x00 8. "PHYCLK,PHY Input Clock Selection\n" "0: PHY input clock is12 MHz,1: PHY input clock is 24 MHz"
|
|
newline
|
|
bitfld.long 0x00 7. "IDDETEN,ID Detection Enable\n" "0: Sampling on ID pin Enabled,1: Sampling on ID pin Disabled"
|
|
bitfld.long 0x00 6. "VBENPOL,Off-Chip USB VBUS Power Enable Polarity\nThe OTG controller will enable off-chip USB VBUS LDO to provide VBUS power when need" "0: The polarity of enabling off-chip USB VBUS..,1: The polarity of enabling off-chip USB VBUS.."
|
|
newline
|
|
bitfld.long 0x00 5. "VBSTSPOL,Off-Chip USB VBUS Power Status Polarity\nThe polarity of off-chip USB VBUS LDO valid depends on the selected component" "0: The polarity of off-chip USB VBUS LDO valid..,1: The polarity of off-chip USB VBUS LDO valid.."
|
|
bitfld.long 0x00 2. "DMPDEN," "?,1: 15 k resistor pull-down on D- pin Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "DPPDEN," "?,1: 15 k resistor pull-down on D+ pin Enabled"
|
|
bitfld.long 0x00 0. "SWPDEN,Software Control Pull-Down On Data Lines Enable Bit\nNote: Software must set this bit high before controlling DPPDEN and DMPDEN" "0: Pull-down resistors on data lines is..,1: Pull-down resistors on data lines is.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OTG_INTEN,OTG Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "SRPDETIEN,SRP Detected Interrupt Enable Bit\n" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 11. "SECHGIEN,SESSEND Status Changed Interrupt Enable Bit \n" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "VBCHGIEN,VBVALID Status Changed Interrupt Enable Bit\n" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 9. "AVLDCHGIEN,A-Device Session Valid Status Change (From High To Low Or From Low To High) Interrupt Enable Bit\n" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "BVLDCHGIEN,B-Device Session Valid Status Change (From High To Low Or From Low To High) Interrupt Enable Bit\n" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 7. "HOSTIEN,Act As Host Interrupt Enable Bit\n" "0: This device as a host interrupt Disabled,1: This device as a host interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "PDEVIEN,Act As Peripheral Interrupt Enable Bit\n" "0: This device as a peripheral interrupt Disabled,1: This device as a peripheral interrupt Enabled"
|
|
bitfld.long 0x00 5. "IDCHGIEN,IDSTS Changed Interrupt Enable \n" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "GOIDLEIEN,OTG Device Goes IDLE State Interrupt Enable Bit\nNote: Going to idle state means going to a_idle or b_idle state" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 3. "HNPFIEN,HNP Fail Interrupt Enable Bit\n" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "SRPFIEN,SRP Fail Interrupt Enable Bit\n" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 1. "VBEIEN,VBUS Error Interrupt Enable Bit\nNote: VBUS error means going to a_vbus_err state" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ROLECHGIEN,Role(Host Or Peripheral) Changed Interrupt Enable Bit\n" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OTG_INTSTS,OTG Interrupt Status Register"
|
|
bitfld.long 0x00 13. "SRPDETIF,SRP Detected Interrupt Status\nNote: Write 1 to clear this status" "0: SRP not detected,1: SRP detected"
|
|
bitfld.long 0x00 11. "SECHGIF,SESSEND State Change Interrupt Status\nNote: Write 1 to clear this flag" "0: Session end not toggled,1: SESSEND from high to low or from low to high"
|
|
newline
|
|
bitfld.long 0x00 10. "VBCHGIF,VBVALID State Change Interrupt Status\nNote: Write 1 to clear this flag" "0: VBUS_VLD not toggled,1: VBUS_VLD from high to low or from low to high"
|
|
bitfld.long 0x00 9. "AVLDCHGIF,A-Device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this flag" "0: AVLD not toggled,1: AVLD from high to low or low to high"
|
|
newline
|
|
bitfld.long 0x00 8. "BVLDCHGIF,B-Device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status" "0: BVLD not toggled,1: BVLD from high to low or low to high"
|
|
bitfld.long 0x00 7. "HOSTIF,Act As Host Interrupt Status\nNote: Write 1 to clear this flag" "0: This device does not act as a host,1: This device acts as a host"
|
|
newline
|
|
bitfld.long 0x00 6. "PDEVIF,Act As Peripheral Interrupt Status\nNote: Write 1 to clear this flag" "0: This device does not act as a peripheral,1: This device acts as a peripheral"
|
|
bitfld.long 0x00 5. "IDCHGIF,ID State Change Interrupt Status\nNote1: BUSREQ (OTG_CTL[1]) will be cleared when IDDIG is high.\nNote2: Write 1 to clear this flag" "0: IDSTS not toggled,1: IDSTS from high to low or from low to high"
|
|
newline
|
|
bitfld.long 0x00 4. "GOIDLEIF,OTG Device Goes IDLE Interrupt Status\nFlag is set if the OTG device transfers from non-idle state to idle state" "0: OTG device does not go back to idle..,1: OTG device go back to idle state(a_idle or.."
|
|
bitfld.long 0x00 3. "HNPFIF,HNP Fail Interrupt Status\nWhen A-device has granted B-device to be host and USB bus in SE0 state this bit will be set in specified interval (b_ase0_brst_tmr defined in OTG spec. specification) A-device does not signal connect signal.\nNote:.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "SRPFIF,SRP Fail Interrupt Status\nAfter initiating SRP an OTG B-device will wait at least TB_SRP_FAIL min defined in OTG specification for the OTG A-device respond This flag is set when the OTG B-device didn't get the response from the remote A-device.." "0,1"
|
|
bitfld.long 0x00 1. "VBEIF,VBUS Error Interrupt Status\nThis flag will be set in one of two conditions \nOne case is that voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A device starting to drive" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ROLECHGIF,OTG Role Change Interrupt Status\nThis flag is set when the role of an OTG device changed from a host to a peripheral or changed from a peripheral to a host\nNote: Write 1 to clear this flag" "0,1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "OTG_STATUS,Functional Status Register"
|
|
bitfld.long 0x00 5. "VBUSVLD,VBUS Valid Status\n" "0: VBUS 4.4V,1: VBUS 4.75V"
|
|
bitfld.long 0x00 4. "AVLD,A-Device Session Valid Status\n" "0: VBUS 0.8V,1: VBUS 2V"
|
|
newline
|
|
bitfld.long 0x00 3. "BVLD,B-Device Session Valid Status\n" "0: VBUS 0.8V,1: VBUS 4V"
|
|
bitfld.long 0x00 2. "SESSEND,Session End Status \n" "0: VBUS 0.8V,1: VBUS 0.2V"
|
|
newline
|
|
bitfld.long 0x00 1. "IDSTS,ID Pin State Of Mini-B/Micro-Plug\n" "0: Mini-A/Micro-A plug is attached,1: Mini-B/Micro-B plug is attached"
|
|
bitfld.long 0x00 0. "OVERCUR,Overcurrent Condition\nThe voltage on VBUS cannot reach a minimum VBUS valid threshold 4.4V minimum within a maximum time of 100ms after OTG A device starting to drive\n" "0: OTG A-device drives VBUS successfully,1: Overcurrent condition occurred"
|
|
tree.end
|
|
tree "PDMA"
|
|
base ad:0x40008000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDMA_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel 0"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDMA_DSCT0_ENDSA,End Source Address Register of PDMA Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PDMA_DSCT0_ENDDA,End Destination Address Register of PDMA Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PDMA_DSCT0_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 0"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PDMA_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel 1"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDMA_DSCT1_ENDSA,End Source Address Register of PDMA Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PDMA_DSCT1_ENDDA,End Destination Address Register of PDMA Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PDMA_DSCT1_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 1"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PDMA_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel 2"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PDMA_DSCT2_ENDSA,End Source Address Register of PDMA Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PDMA_DSCT2_ENDDA,End Destination Address Register of PDMA Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PDMA_DSCT2_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 2"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
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|
group.long 0x30++0x03
|
|
line.long 0x00 "PDMA_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel 3"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
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|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
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|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
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|
newline
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|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
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|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
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|
newline
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bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
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|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
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|
group.long 0x34++0x03
|
|
line.long 0x00 "PDMA_DSCT3_ENDSA,End Source Address Register of PDMA Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PDMA_DSCT3_ENDDA,End Destination Address Register of PDMA Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PDMA_DSCT3_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 3"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
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|
group.long 0x40++0x03
|
|
line.long 0x00 "PDMA_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel 4"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
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|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
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|
newline
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|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
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|
newline
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bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
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|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
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|
group.long 0x44++0x03
|
|
line.long 0x00 "PDMA_DSCT4_ENDSA,End Source Address Register of PDMA Channel 4"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PDMA_DSCT4_ENDDA,End Destination Address Register of PDMA Channel 4"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PDMA_DSCT4_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 4"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PDMA_DSCT5_CTL,Descriptor Table Control Register of PDMA Channel 5"
|
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hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
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bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
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newline
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bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
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|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
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newline
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bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
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|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
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|
group.long 0x54++0x03
|
|
line.long 0x00 "PDMA_DSCT5_ENDSA,End Source Address Register of PDMA Channel 5"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PDMA_DSCT5_ENDDA,End Destination Address Register of PDMA Channel 5"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PDMA_DSCT5_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 5"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PDMA_DSCT6_CTL,Descriptor Table Control Register of PDMA Channel 6"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
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bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
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|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
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|
newline
|
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bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
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|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PDMA_DSCT6_ENDSA,End Source Address Register of PDMA Channel 6"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PDMA_DSCT6_ENDDA,End Destination Address Register of PDMA Channel 6"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PDMA_DSCT6_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 6"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PDMA_DSCT7_CTL,Descriptor Table Control Register of PDMA Channel 7"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
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|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
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|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PDMA_DSCT7_ENDSA,End Source Address Register of PDMA Channel 7"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PDMA_DSCT7_ENDDA,End Destination Address Register of PDMA Channel 7"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PDMA_DSCT7_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 7"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PDMA_DSCT8_CTL,Descriptor Table Control Register of PDMA Channel 8"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
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|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PDMA_DSCT8_ENDSA,End Source Address Register of PDMA Channel 8"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PDMA_DSCT8_ENDDA,End Destination Address Register of PDMA Channel 8"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PDMA_DSCT8_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 8"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PDMA_DSCT9_CTL,Descriptor Table Control Register of PDMA Channel 9"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PDMA_DSCT9_ENDSA,End Source Address Register of PDMA Channel 9"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PDMA_DSCT9_ENDDA,End Destination Address Register of PDMA Channel 9"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "PDMA_DSCT9_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 9"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PDMA_DSCT10_CTL,Descriptor Table Control Register of PDMA Channel 10"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
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|
group.long 0xA4++0x03
|
|
line.long 0x00 "PDMA_DSCT10_ENDSA,End Source Address Register of PDMA Channel 10"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PDMA_DSCT10_ENDDA,End Destination Address Register of PDMA Channel 10"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PDMA_DSCT10_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 10"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PDMA_DSCT11_CTL,Descriptor Table Control Register of PDMA Channel 11"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
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|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
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|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
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|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
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|
newline
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|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
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|
newline
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bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
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|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
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|
group.long 0xB4++0x03
|
|
line.long 0x00 "PDMA_DSCT11_ENDSA,End Source Address Register of PDMA Channel 11"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PDMA_DSCT11_ENDDA,End Destination Address Register of PDMA Channel 11"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "PDMA_DSCT11_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 11"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "PDMA_DSCT12_CTL,Descriptor Table Control Register of PDMA Channel 12"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
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|
newline
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|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
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|
newline
|
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bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
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|
group.long 0xC4++0x03
|
|
line.long 0x00 "PDMA_DSCT12_ENDSA,End Source Address Register of PDMA Channel 12"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PDMA_DSCT12_ENDDA,End Destination Address Register of PDMA Channel 12"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "PDMA_DSCT12_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 12"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "PDMA_DSCT13_CTL,Descriptor Table Control Register of PDMA Channel 13"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
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|
newline
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|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
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|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
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|
newline
|
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bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
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|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
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|
group.long 0xD4++0x03
|
|
line.long 0x00 "PDMA_DSCT13_ENDSA,End Source Address Register of PDMA Channel 13"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PDMA_DSCT13_ENDDA,End Destination Address Register of PDMA Channel 13"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "PDMA_DSCT13_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 13"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "PDMA_DSCT14_CTL,Descriptor Table Control Register of PDMA Channel 14"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
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|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
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|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PDMA_DSCT14_ENDSA,End Source Address Register of PDMA Channel 14"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "PDMA_DSCT14_ENDDA,End Destination Address Register of PDMA Channel 14"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "PDMA_DSCT14_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 14"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "PDMA_DSCT15_CTL,Descriptor Table Control Register of PDMA Channel 15"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection" "0: 8 bits for every transfer item,1: 16 bits for every transfer item,2: 32 bits for every transfer item,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size\n" "?,?,?,3: No Increment (Fixed Address.)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size" "0: 128 transfers,1: 64 transfers,2: 32 transfers,3: 16 transfers,4: 8 transfers,5: 4 transfers,6: 2 transfers,7: 1 transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Request Type\n" "0: Burst request type,1: Single request type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table user must check if the descriptor table is complete" "0: Stop Mode,1: Basic Mode,2: Scatter-Gather Mode,?..."
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "PDMA_DSCT15_ENDSA,End Source Address Register of PDMA Channel 15"
|
|
hexmask.long 0x00 0.--31. 1. "ENDSA,PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000 the transfer count is 0x100 and the source address increment is word this field must be filled.."
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PDMA_DSCT15_ENDDA,End Destination Address Register of PDMA Channel 15"
|
|
hexmask.long 0x00 0.--31. 1. "ENDDA,PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000 the transfer count is 0x100 and the destination address increment is word this.."
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "PDMA_DSCT15_NEXT,Scatter-gather Descriptor Table Offset Address of PDMA Channel 15"
|
|
hexmask.long.word 0x00 2.--15. 1. "NEXT,PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is.."
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "PDMA_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA External Current Descriptor Address Bits\nThis field indicates a 32-bit current external descriptor address of PDMA.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external descriptor address"
|
|
repeat 15. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
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|
group.long ($2+0x104)++0x03
|
|
line.long 0x00 "PDMA_CURSCAT$1,Current Scatter-gather Descriptor Table Address of PDMA Channel $1"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA External Current Descriptor Address Bits\nThis field indicates a 32-bit current external descriptor address of PDMA.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external descriptor address"
|
|
repeat.end
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PDMA_CHCTL,PDMA Channel Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CHEN,PDMA Channel Enable Control Bit[X]\nSet this bit to 1 to enable PDMA[x] operation"
|
|
wgroup.long 0x404++0x03
|
|
line.long 0x00 "PDMA_STOP,PDMA Stop Transfer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "STOP,PDMA Stop Transfer Bit [X]\nUser can stop the PDMA transfer by software reset (writing all '1' to PDMA_STOP register) or by PDMA_STOP register.\nThe difference between software reset and PDMA_STOP register is when software set software reset the.."
|
|
wgroup.long 0x408++0x03
|
|
line.long 0x00 "PDMA_SWREQ,PDMA Software Request Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "SWREQ,PDMA Software Request Bit [X]\nSet this bit to 1 to generate a software request to PDMA [x].\nNote1: This field is Write-Only"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "PDMA_TRGSTS,PDMA Request Active Flag Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "REQSTS,PDMA Request Active Flag [X]\nThis flag indicates whether channel[x] have a request or not.\nNote1: The request may come from software request (SWREQ) or peripheral request.\nNote2: When PDMA finishes channel transfer this bit will be cleared.."
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "PDMA_PRISET,PDMA Fixed Priority Setting Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "FPRISET,PDMA Fixed Priority Setting Bit[X]\nSet this bit to 1 to enable fix priority level.\nThe PDMA channel priority is shown in the following table"
|
|
wgroup.long 0x414++0x03
|
|
line.long 0x00 "PDMA_PRICLR,PDMA Fixed Priority Clear Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "FPRICLR,PDMA Fix Priority Clear Bit\nSet this bit to 1 to clear fixed priority level.\nNote: This field is Write-Only and software can indicate the channel priority by reading PDMA_PRISET register"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "PDMA_INTEN,PDMA Interrupt Enable Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "INTEN,PDMA Interrupt Enable\nThis field is used for enabling PDMA channel[x] interrupt.\n"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "PDMA_INTSTS,PDMA Interrupt Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "ABTIF,PDMA Target Abort Status Flag\nThis bit indicates which PDMA has target abort error \nNote: This field is read only but software can write 1 to clear it"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "PDMA_ABTSTS,PDMA Read/Write Target Abort Flag Register"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "PDMA_TDSTS,PDMA Transfer Done Flag Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TDIF,Transfer Done Flag\nThis bit indicates which PDMA channel has finished transmission.\nNote: This field is read only but software can write 1 to clear"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "PDMA_SCATSTS,PDMA Scatter-gather Transfer Done Flag Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TEMPTYF,Table Empty Flag\nThis bit indicates which PDMA channel table has finished transmission and the operation mode is Stop mode \nNote: This field is read only but software can write 1 to clear"
|
|
rgroup.long 0x42C++0x03
|
|
line.long 0x00 "PDMA_TACTSTS,PDMA Transfer on Active Flag Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXACTF,Transfer On Active Flag\nThis bit indicates which PDMA channel is on active.\n"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "PDMA_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SCATBA,PDMA Scatter-Gather Descriptor Table Base Address \nIn Scatter-Gather mode this is the base address for calculating the next link - list address"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "PDMA_REQSEL0_3,PDMA Source Module Select Register 0"
|
|
bitfld.long 0x00 24.--28. "REQSRC3,Channel 3 Selection \nThis filed defines which peripheral is connected to PDMA channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "REQSRC2,Channel 2 Selection \nThis filed defines which peripheral is connected to PDMA channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "REQSRC1,Channel 1 Selection \nThis filed defines which peripheral is connected to PDMA channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--4. "REQSRC0,Channel 0 Selection \nThis filed defines which peripheral is connected to PDMA channel 0" "0: Connect to SPI0_TX,1: Connect to SPI1_TX,2: Connect to SPI2_TX,3: Connect to SPI3_TX,4: Connect to UART0_TX,5: Connect to UART1_TX,6: Connect to UART2_TX,7: Connect to UART3_TX,8: Connect to UART4_TX,9: Connect to UART5_TX,10: Reserved,11: Connect to I2S_TX,12: Connect to I2S1_TX,13: Connect to SPI0_RX,14: Connect to SPI1_RX,15: Connect to SPI2_RX,16: Connect to SPI3_RX,17: Connect to UART0_RX,18: Connect to UART1_RX,19: Connect to UART2_RX,20: Connect to UART3_RX,21: Connect to UART4_RX,22: Connect to UART5_RX,23: Reserved,24: Connect to ADC,25: Connect to I2S_RX,26: Connect to I2S1_RX,?..."
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|
group.long 0x484++0x03
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|
line.long 0x00 "PDMA_REQSEL4_7,PDMA Source Module Select Register 1"
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|
bitfld.long 0x00 24.--28. "REQSRC7,Channel 7 Selection \nThis filed defines which peripheral is connected to PDMA channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. "REQSRC6,Channel 6 Selection \nThis filed defines which peripheral is connected to PDMA channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
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|
bitfld.long 0x00 8.--12. "REQSRC5,Channel 1 Selection \nThis filed defines which peripheral is connected to PDMA channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "REQSRC4,Channel 0 Selection \nThis filed defines which peripheral is connected to PDMA channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0x488++0x03
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|
line.long 0x00 "PDMA_REQSEL8_11,PDMA Source Module Select Register 2"
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bitfld.long 0x00 24.--28. "REQSRC11,Channel 11 Selection \nThis filed defines which peripheral is connected to PDMA channel 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. "REQSRC10,Channel 10 Selection \nThis filed defines which peripheral is connected to PDMA channel 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
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|
bitfld.long 0x00 8.--12. "REQSRC9,Channel 9 Selection \nThis filed defines which peripheral is connected to PDMA channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "REQSRC8,Channel 8 Selection \nThis filed defines which peripheral is connected to PDMA channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0x48C++0x03
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|
line.long 0x00 "PDMA_REQSEL12_15,PDMA Source Module Select Register 3"
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bitfld.long 0x00 24.--28. "REQSRC15,Channel 15 Selection \nThis filed defines which peripheral is connected to PDMA channel 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. "REQSRC14,Channel 14 Selection \nThis filed defines which peripheral is connected to PDMA channel 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
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bitfld.long 0x00 8.--12. "REQSRC13,Channel 13 Selection \nThis filed defines which peripheral is connected to PDMA channel 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "REQSRC12,Channel 12 Selection \nThis filed defines which peripheral is connected to PDMA channel 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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tree.end
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tree "PS2"
|
|
base ad:0x400E0000
|
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group.long 0x00++0x03
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line.long 0x00 "PS2_CTL,PS/2 Control Register"
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bitfld.long 0x00 11. "FPS2DAT,Force DATSTAT Line\nIt forces DATSTAT high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n" "0: Force DATSTAT low,1: Force DATSTAT high"
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bitfld.long 0x00 10. "FPS2CLK,Force CLKSTAT Line\nIt forces CLKSTAT line high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n" "0: Force CLKSTAT line low,1: Force CLKSTAT line high"
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newline
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bitfld.long 0x00 9. "OVERRIDE,Software Override PS/2 CLK/DATA Pin State\n" "0: CLKSTAT and DATSTAT pins are controlled by..,1: CLKSTAT and DATSTAT pins are controlled by.."
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bitfld.long 0x00 8. "CLRFIFO,Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission" "0: Not active,1: Clear FIFO"
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newline
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bitfld.long 0x00 7. "ACK,Acknowledge Enable Bit\n" "0: Always sends acknowledge to host at 12th..,1: If parity error or stop bit is not received.."
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bitfld.long 0x00 3.--6. "TXFDEPTH,Transmit Data FIFO Depth\nThere is 16-byte buffer for data transmit" "0: 1 byte,1: 2 bytes,?,?,?,?,?,?,?,?,?,?,?,?,14: 15 bytes,15: 16 bytes"
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|
newline
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bitfld.long 0x00 2. "RXIEN,Receive Interrupt Enable Bit\n" "0: Data receive complete interrupt Disabled,1: Data receive complete interrupt Enabled"
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|
bitfld.long 0x00 1. "TXIEN,Transmit Interrupt Enable Bit\n" "0: Data transmit complete interrupt Disabled,1: Data transmit complete interrupt Enabled"
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|
newline
|
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bitfld.long 0x00 0. "PS2EN,PS/2 Device Enable Bit\nEnable PS/2 device controller.\n" "0: Disabled,1: Enabled"
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|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "PS2_TXDAT$1,PS/2 Transmit DATA Register $1"
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hexmask.long 0x00 0.--31. 1. "DAT,Transmit Data\nWrite data to this register starts device to host communication if bus is in IDLE state"
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repeat.end
|
|
rgroup.long 0x14++0x03
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line.long 0x00 "PS2_RXDAT,PS/2 Receive DATA Register"
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|
hexmask.long.byte 0x00 0.--7. 1. "DAT,Received Data\nFor host to device communication after acknowledge bit is sent the received data is copied from receive shift register to PS2_RXDAT register"
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|
group.long 0x18++0x03
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|
line.long 0x00 "PS2_STATUS,PS/2 Status Register"
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|
bitfld.long 0x00 8.--11. "BYTEIDX,Byte Index\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "TXEMPTY,TX FIFO Empty\nWhen software writes any data to PS2_TXDAT0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled" "0: There is data to be transmitted,1: FIFO is empty"
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|
newline
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bitfld.long 0x00 6. "RXOV,RX Buffer Overwrite\nNote: Write 1 to clear this bit" "0: No over,1: Data in PS2_RXDAT register is overwritten by.."
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bitfld.long 0x00 5. "TXBUSY,Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nNote: This bit is read only" "0: Idle,1: Currently sending data"
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|
newline
|
|
bitfld.long 0x00 4. "RXBUSY,Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nNote: This bit is read only" "0: Idle,1: Currently receiving data"
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|
bitfld.long 0x00 3. "RXPARITY,Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nNote: This bit is read only" "0,1"
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|
newline
|
|
bitfld.long 0x00 2. "FRAMEERR,Frame Error\nFor host to device communication if STOP bit (logic 1) is not received it is a frame error" "0: No frame error,1: Frame error occurred"
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|
bitfld.long 0x00 1. "DATSTAT,DATA Pin State\nThis bit reflects the status of the DATSTAT line after synchronizing and sampling" "0,1"
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|
newline
|
|
bitfld.long 0x00 0. "CLKSTAT,CLK Pin State\nThis bit reflects the status of the CLKSTAT line after synchronizing" "0,1"
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|
group.long 0x1C++0x03
|
|
line.long 0x00 "PS2_INTSTS,PS/2 Interrupt Status Register"
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|
bitfld.long 0x00 1. "TXIF,Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted" "0: No interrupt,1: Transmit interrupt occurred"
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|
bitfld.long 0x00 0. "RXIF,Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication" "0: No interrupt,1: Receive interrupt occurred"
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tree.end
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|
tree "PWM"
|
|
repeat 2. (list 0. 1.) (list ad:0x40058000 ad:0x40059000)
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|
tree "PWM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWM_CLKPSC,PWM Clock Prescale Register"
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|
hexmask.long.byte 0x00 16.--23. 1. "CLKPSC45,PWM Counter Base-Clock Prescale For PWM Pair Of Channel 4 And Channel 5\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider"
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hexmask.long.byte 0x00 8.--15. 1. "CLKPSC23,PWM Counter Base-Clock Prescale For PWM Pair Of Channel 2 And Channel 3\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CLKPSC01,PWM Counter Base-Clock Prescale For PWM Pair Of Channel 0 And Channel 1\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider"
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group.long 0x04++0x03
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line.long 0x00 "PWM_CLKDIV,PWM Clock Divide Register"
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bitfld.long 0x00 20.--22. "CLKDIV5,PWM Counter Base-Clock Divide For PWMx_CH5\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider" "0: 0,1: 1,2: 2,3: 16,4: 4,?..."
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bitfld.long 0x00 16.--18. "CLKDIV4,PWM Counter Base-Clock Divide For PWMx_CH4\n (Table is the same as CLKDIV5)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 12.--14. "CLKDIV3,PWM Counter Base-Clock Divide For PWMx_CH3\n (Table is the same as CLKDIV5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. "CLKDIV2,PWM Counter Base-Clock Divide For PWMx_CH2\n (Table is the same as CLKDIV5)" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x00 4.--6. "CLKDIV1,PWM Counter Base-Clock Divide For PWMx_CH1\n (Table is the same as CLKDIV5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "CLKDIV0,PWM Counter Base-Clock Divide For PWMx_CH0\n (Table is the same as CLKDIV5)" "0,1,2,3,4,5,6,7"
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group.long 0x08++0x03
|
|
line.long 0x00 "PWM_CTL,PWM Control Register"
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|
bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nNote: The PWM pin will keep output no matter ICE debug mode acknowledged or not" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 24.--29. "CNTTYPE,PWM Counter Operation Aligned Type\nNote: Each bit control corresponding PWM channel" "0: PWM counter operating as Edge-aligned type,1: PWM counter operating as Center-aligned type,?..."
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newline
|
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bitfld.long 0x00 16.--21. "CNTMODE,PWM Counter Operation Mode\nNote: Each bit control corresponding PWM channel\nNote: If there is a transition at this bit it will cause PWM_PERIODn and PWM_CMPDATn be cleared" "0: PWM counter working as One-shot mode,1: PWM counter working as Auto-reload mode,?..."
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bitfld.long 0x00 15. "SYNCEN,Synchronous Mode Enable Bit\nNote: If Group and Synchronous mode are enabled simultaneously the Synchronous mode will be inactive" "0: The signals timing of each PWM channel are..,1: Unify the signals timing of PWM_CH0 and.."
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newline
|
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bitfld.long 0x00 8.--13. "PINV,PWM Output Polar Inverse Enable Bit\nThe register controls polarity state of PWM output\nNote: Each bit controls the corresponding PWM channel" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled,?..."
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bitfld.long 0x00 7. "GROUPEN,Group Mode Enable Bit\n" "0: The signals timing of each PWM channel are..,1: Unify the signals timing of PWM_CH0 PWM_CH2.."
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newline
|
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bitfld.long 0x00 6. "OUTMODE,PWM Output Mode\nThe register controls the output mode of PWM\n" "0: PWM output at independent mode,1: PWM output at complementary mode"
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bitfld.long 0x00 0.--5. "CMPINV,PWM Comparator Output Inverter Enable Bit\nWhen CMPINV is set to high the PWM comparator output signals will be inversed \nNote: Each bit control corresponding PWM channel" "0: Comparator output inverter Disabled,1: Comparator output inverter Enabled,?..."
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|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWM_CNTEN,PWM Counter Enable Control Register"
|
|
bitfld.long 0x00 0.--5. "CNTEN,PWM Counter Enable Bit\nNote: Each bit controls the corresponding PWM channel" "0: PWM Counter Stop Running,1: PWM Counter Start Running,?..."
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|
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "PWM_PERIOD$1,PWM Period Register $1"
|
|
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nPERIOD determines the PWM period.\nNote1: Any write to PERIOD will take effect in next PWM cycle.\nNote2: When PWM operating at center-aligned type PERIOD value should be set between 0x0000 to 0xFFFE"
|
|
repeat.end
|
|
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
|
|
group.long ($2+0x28)++0x03
|
|
line.long 0x00 "PWM_CMPDAT$1,PWM Comparator Register $1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Compare Register\nCMP determines the PWM duty.\nNote: Any write to CMP will take effect in next PWM cycle"
|
|
repeat.end
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "PWM_CNT0,PWM Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register\nUser can monitor CNT to know the current value in 16-bit down counter.\nNote: It is recommended that read this register when PWM engine clock is source from system clock otherwise a transition value of PWM counter may be"
|
|
repeat 5. (strings "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 )
|
|
group.long ($2+0x44)++0x03
|
|
line.long 0x00 "PWM_CNT$1,PWM Data Register $1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register\nUser can monitor CNT to know the current value in 16-bit down counter.\nNote: It is recommended that read this register when PWM engine clock is source from system clock otherwise a transition value of PWM counter may be"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PWM_MSKEN,PWM Mask Control Register"
|
|
bitfld.long 0x00 0.--5. "MSKEN,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output with..,?..."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PWM_MSK,PWM Mask Data Register"
|
|
bitfld.long 0x00 0.--5. "MSKDAT,PWM Mask Data Bit:\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled.\nNote: Each bit controls the corresponding PWM channel" "0: Output logic low to PWMn,1: Output logic high to PWMn,?..."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PWM_DTCTL,PWM Dead-zone Control Register"
|
|
bitfld.long 0x00 30. "DTEN45,Dead-Zone Enable Control for PWM Pair Of Channel 4 and Channel 5\nDead-zone insertion is only active when this pair of complementary PWM is enabled" "0: Dead-zone insertion Disabled,1: Dead-zone insertion Enabled"
|
|
bitfld.long 0x00 29. "DTEN23,Dead-Zone Enable Control for PWM Pair Of Channel 2 and Channel 3\nDead-zone insertion is only active when this pair of complementary PWM is enabled" "0: Dead-zone insertion Disabled,1: Dead-zone insertion Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. "DTEN01,Dead-Zone Enable Control for PWM Pair Of Channel 0 and Channel 1\nDead-zone insertion is only active when this pair of complementary PWM is enabled" "0: Dead-zone insertion Disabled,1: Dead-zone insertion Enabled"
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bitfld.long 0x00 24.--25. "DTDIV,Dead-Zone Generator Divider\n" "0: Dead-zone clock equal to PWM base clock..,1: Dead-zone clock equal to PWM base clock..,2: Dead-zone clock equal to PWM base clock..,3: Dead-zone clock equal to PWM base clock.."
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|
newline
|
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hexmask.long.byte 0x00 16.--23. 1. "DTCNT45,Dead-Zone Interval For PWM Pair Of Channel 4 And Channel 5\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV"
|
|
hexmask.long.byte 0x00 8.--15. 1. "DTCNT23,Dead-Zone Interval For PWM Pair Of Channel 2 And Channel 3\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DTCNT01,Dead-Zone Interval For PWM Pair Of Channel 0 And Channel 1\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PWM_TRGADCTL,PWM Trigger Control Register"
|
|
bitfld.long 0x00 24.--29. "RTRGEN,PWM Rising Edge Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM output pin rising edge is detected if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel" "0: PWM rising edge point trigger ADC function..,1: PWM rising edge point trigger ADC function..,?..."
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|
bitfld.long 0x00 16.--21. "FTRGEN,PWM Falling Edge Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM output pin falling edge is detected if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel" "0: PWM falling edge point trigger ADC function..,1: PWM falling edge point trigger ADC function..,?..."
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|
newline
|
|
bitfld.long 0x00 8.--13. "CTRGEN,PWM Center Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM counter up count to (PERIODn+1) if this bit is set to1.\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit.." "0: PWM center point trigger ADC function Disabled,1: PWM center point trigger ADC function Enabled,?..."
|
|
bitfld.long 0x00 0.--5. "PTRGEN,PWM Period Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM counter down count to zero if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel" "0: PWM period point trigger ADC function Disabled,1: PWM period point trigger ADC function Enabled,?..."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PWM_TRGADCSTS,PWM Trigger ADC Status Register"
|
|
bitfld.long 0x00 24.--29. "RTRGF,PWM Rising Edge Point Trigger Indicator\nThis bit is set to 1 by hardware when PWM output pin rising edge is detected if corresponding RETRGEN bit is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "FTRGF,PWM Falling Edge Point Trigger Indicator\nThis bit is set to 1 by hardware when PWM output pin falling edge is detected if corresponding FETRGEN bit is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CTRGF,PWM Center Point Trigger Flag\nThis bit is set to 1 by hardware when PWM counter up counts to (PERIODn+1) if the corresponding CTRGEN bit is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "PTRGF,PWM Period Point Trigger Flag\nThis bit is set to 1 by hardware when PWM counter down count to zero if corresponding PTRGEN bit is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PWM_BRKCTL,PWM Brake Control Register"
|
|
bitfld.long 0x00 24.--29. "BKOD,PWM Brake Output Data Register\nNote: Each bit controls the corresponding PWM channel" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions..,?..."
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bitfld.long 0x00 19. "LVDBKEN,Low-Level Detection Trigger PWM Brake Function 1 Enable Bit\n" "0: Brake Function 1 triggered by Low-level..,1: Brake Function 1 triggered by Low-level.."
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bitfld.long 0x00 18. "CPO2BKEN,CPO2 Digital Output As Brake 0 Source Enable Bit\n" "0: CPO2 as one brake source in Brake 0 Disabled,1: CPO2 as one brake source in Brake 0 Enabled"
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bitfld.long 0x00 17. "CPO1BKEN,CPO1 Digital Output As Brake 0 Source Enable Bit\n" "0: CPO1 as one brake source in Brake 0 Disabled,1: CPO1 as one brake source in Brake 0 Enabled"
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bitfld.long 0x00 16. "CPO0BKEN,CPO0 Digital Output As Brake0 Source Enable Bit\n" "0: CPO0 as one brake source in Brake 0 Disabled,1: CPO0 as one brake source in Brake 0 Enabled"
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bitfld.long 0x00 14.--15. "BRK1NFSEL,Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/16"
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bitfld.long 0x00 12.--13. "BK1SEL,Brake Function 1 Source Selection\n" "0: From external pin BKP1,1: From analog comparator 0 output (CPO0),2: From analog comparator 1 output (CPO1),3: Reserved"
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bitfld.long 0x00 10. "BRK1INV,Inverse BKP1 State\n" "0: The state of pin BKPx1 is passed to the..,1: The inversed state of pin BKPx1 is passed to.."
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bitfld.long 0x00 9. "BRK1NFDIS,PWM Brake 1 Noise Filter Disable Bit\n" "0: Noise filter of PWM Brake 1 Enabled,1: Noise filter of PWM Brake 1 Disabled"
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bitfld.long 0x00 8. "BRKP1EN,Brake1 Function Enable Bit\n" "0: Brake1 function Disabled,1: Brake1 function Enabled"
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bitfld.long 0x00 6.--7. "BRK0NFSEL,Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/16"
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bitfld.long 0x00 2. "BRK0INV,Inverse BKP0 State\n" "0: The state of pin BKPx0 is passed to the..,1: The inversed state of pin BKPx0 is passed to.."
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bitfld.long 0x00 1. "BRK0NFDIS,PWM Brake 0 Noise Filter Disable Bit\n" "0: Noise filter of PWM Brake 0 Enabled,1: Noise filter of PWM Brake 0 Disabled"
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bitfld.long 0x00 0. "BRKP0EN,Brake0 Function Enable Bit\n" "0: Brake0 detect function Disabled,1: Brake0 detect function Enabled"
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group.long 0x70++0x03
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line.long 0x00 "PWM_INTCTL,PWM Interrupt Control Register"
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bitfld.long 0x00 8.--13. "DINTTYPE,PWM Duty Interrupt Type Selection\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit controls the corresponding PWM channel" "0: DIF[n] will be set if PWM counter matches..,1: DIF[n] will be set if PWM counter matches..,?..."
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bitfld.long 0x00 0.--5. "PINTTYPE,PWM Period Interrupt Type Selection\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit controls the corresponding PWM channel" "0: PIF[n] will be set if PWM counter underflow,1: PIF[n] will be set if PWM counter matches..,?..."
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group.long 0x74++0x03
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line.long 0x00 "PWM_INTEN,PWM Interrupt Enable Control Register"
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bitfld.long 0x00 24.--29. "FLIEN,Falling Latch Interrupt Enable Bit\nNote: Each bit controls the corresponding PWM channel" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled,?..."
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bitfld.long 0x00 16.--21. "RLIEN,Rising Latch Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled,?..."
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bitfld.long 0x00 8.--13. "DIEN,PWM Duty Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel" "0: Duty interrupt Disabled,1: Duty interrupt Enabled,?..."
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bitfld.long 0x00 6. "BRKIEN,Brake0 and Brak1 Interrupt Enable Bit\n" "0: Disabling flags BFK0 and BFK1 to trigger PWM..,1: Enabling flags BRKIF0 and BRKIF1 can trigger.."
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bitfld.long 0x00 0.--5. "PIEN,PWM Period Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel" "0: Period interrupt Disabled,1: Period interrupt Enabled,?..."
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group.long 0x78++0x03
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line.long 0x00 "PWM_INTSTS,PWM Interrupt Flag Register"
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bitfld.long 0x00 24.--29. "CFLIF,Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this..,?..."
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rbitfld.long 0x00 23. "BRKSTS1,Brake 1 Status (Read Only)\n" "0: PWM had been out of Brake 1 state,1: PWM is in Brake 1 state"
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rbitfld.long 0x00 22. "BRKSTS0,Brake 0 Status (Read Only)\n" "0: PWM had been out of Brake 0 state,1: PWM is in Brake 0 state"
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bitfld.long 0x00 16.--21. "CRLIF,Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this..,?..."
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bitfld.long 0x00 14. "BRKLK0,PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to it" "0: Brake 0 state is released,1: When PWM Brake detects a falling signal at.."
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bitfld.long 0x00 8.--13. "DIF,PWM Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMP0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. "BRKIF1,PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to it" "0: PWM Brake 1 is able to poll falling signal at..,1: When PWM Brake 1 detects a falling signal at.."
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bitfld.long 0x00 6. "BRKIF0,PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to it" "0: PWM Brake 0 is able to poll falling signal at..,1: When PWM Brake 0 detects a falling signal at.."
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bitfld.long 0x00 0.--5. "PIF,PWM Period Interrupt Flag\nThis bit is set by hardware when PWM counter reaches the requirement condition of interrupt (depending on PINTTYPE (PWM_INTCTL[n]) )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x7C++0x03
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line.long 0x00 "PWM_POEN,PWM Output Enable Control Register"
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bitfld.long 0x00 0.--5. "POEN,PWM Pin Output Enable Bit\nNote: Each bit controls the corresponding PWM channel" "0: PWM pin at tri-state,1: PWM pin in output mode,?..."
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group.long 0x80++0x03
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line.long 0x00 "PWM_CAPCTL,PWM Capture Control Register"
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bitfld.long 0x00 24.--29. "FCRLDEN,Falling Latch Reload Enable Bits\n" "0: Falling latch reload counter Disabled,1: Falling latch reload counter Enabled,?..."
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bitfld.long 0x00 16.--21. "RCRLDEN,Rising Latch Reload Enable Bits\n" "0: Rising latch reload counter Enabled,1: Rising latch reload counter Enabled,?..."
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bitfld.long 0x00 8.--13. "CAPINV,Capture Inverter Enable Bits\nNote: Each bit controls the corresponding PWM channel" "0: Capture source inverter Disabled,1: Capture source inverter Enabled,?..."
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bitfld.long 0x00 0.--5. "CAPEN,Capture Function Enable Bits\nNote: Each bit controls the corresponding PWM channel" "0: Capture function Disabled,1: Capture function Enabled,?..."
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group.long 0x84++0x03
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line.long 0x00 "PWM_CAPINEN,PWM Capture Input Enable Control Register"
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bitfld.long 0x00 0.--5. "CAPINEN,Capture Input Enable Bits\nNote: Each bit controls the corresponding PWM channel" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled,?..."
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rgroup.long 0x88++0x03
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line.long 0x00 "PWM_CAPSTS,PWM Capture Status Register"
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bitfld.long 0x00 8.--13. "FLIFOV,Falling Latch Interrupt Flag Overrun Status\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "CRIFOV,Rising Latch Interrupt Flag Overrun Status\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rgroup.long 0x90++0x03
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line.long 0x00 "PWM_RCAPDAT0,PWM Capture Rising Latch Register 0"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has rising transition"
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rgroup.long 0x94++0x03
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line.long 0x00 "PWM_FCAPDAT0,PWM Capture Falling Latch Register 0"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition"
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group.long 0x98++0x03
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line.long 0x00 "PWM_RCAPDAT1,PWM Capture Rising Latch Register 1"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has rising transition"
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group.long 0x9C++0x03
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line.long 0x00 "PWM_FCAPDAT1,PWM Capture Falling Latch Register 1"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition"
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group.long 0xA0++0x03
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line.long 0x00 "PWM_RCAPDAT2,PWM Capture Rising Latch Register 2"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has rising transition"
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group.long 0xA4++0x03
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line.long 0x00 "PWM_FCAPDAT2,PWM Capture Falling Latch Register 2"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition"
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group.long 0xA8++0x03
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line.long 0x00 "PWM_RCAPDAT3,PWM Capture Rising Latch Register 3"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has rising transition"
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group.long 0xAC++0x03
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line.long 0x00 "PWM_FCAPDAT3,PWM Capture Falling Latch Register 3"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition"
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group.long 0xB0++0x03
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line.long 0x00 "PWM_RCAPDAT4,PWM Capture Rising Latch Register 4"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has rising transition"
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group.long 0xB4++0x03
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line.long 0x00 "PWM_FCAPDAT4,PWM Capture Falling Latch Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition"
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group.long 0xB8++0x03
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line.long 0x00 "PWM_RCAPDAT5,PWM Capture Rising Latch Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has rising transition"
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group.long 0xBC++0x03
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line.long 0x00 "PWM_FCAPDAT5,PWM Capture Falling Latch Register 5"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition"
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rgroup.long 0xE0++0x03
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line.long 0x00 "PWM_SBS0,PWM0 Synchronous Busy Status Register"
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bitfld.long 0x00 0. "SYNCBUSY,PWM Synchronous Busy\nWhen software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 counter operation mode CNTMOD (PWM_CTL[16]) PWM will have a busy time to update these values completely because PWM clock may be different from system.." "0,1"
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rgroup.long 0xE4++0x03
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line.long 0x00 "PWM_SBS1,PWM1 Synchronous Busy Status Register"
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bitfld.long 0x00 0. "SYNCBUSY,PWM Synchronous Busy\nWhen software writes PWM_PERIOD1/PWM_CMPDAT1/PWM_CLKPSC or switch PWM1 counter operation mode CNTMOD (PWM_CTL [17]) PWM will have a busy time to update these values completely because PWM clock may be different from system.." "0,1"
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rgroup.long 0xE8++0x03
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line.long 0x00 "PWM_SBS2,PWM2 Synchronous Busy Status Register"
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bitfld.long 0x00 0. "SYNCBUSY,PWM Synchronous Busy\nWhen software writes PWM_PERIOD2/PWM_CMPDAT2/PWM_CLKPSC or switch PWM2 counter operation mode CNTMOD (PWM_CTL [18]) PWM will have a busy time to update these values completely because PWM clock may be different from system.." "0,1"
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rgroup.long 0xEC++0x03
|
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line.long 0x00 "PWM_SBS3,PWM3 Synchronous Busy Status Register"
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bitfld.long 0x00 0. "SYNCBUSY,PWM Synchronous Busy\nWhen software writes PWM_PERIOD3/PWM_CMPDAT3/PWM_CLKPSC or switch PWM3 counter operation mode CNTMOD (PWM_CTL [19]) PWM will have a busy time to update these values completely because PWM clock may be different from system.." "0,1"
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rgroup.long 0xF0++0x03
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line.long 0x00 "PWM_SBS4,PWM4 Synchronous Busy Status Register"
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bitfld.long 0x00 0. "SYNCBUSY,PWM Synchronous Busy\nWhen software writes PWM_PERIOD4/PWM_CMPDAT4/PWM_CLKPSC or switch PWM4 counter operation mode CNTMOD (PWM_CTL [20]) PWM will have a busy time to update these values completely because PWM clock may be different from system.." "0,1"
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rgroup.long 0xF4++0x03
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line.long 0x00 "PWM_SBS5,PWM5 Synchronous Busy Status Register"
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bitfld.long 0x00 0. "SYNCBUSY,PWM Synchronous Busy\nWhen software writes PWM_PERIOD5/PWM_CMPDAT5/PWM_CLKPSC or switch PWM5 counter operation mode CNTMOD (PWM_CTL [21]) PWM will have a busy time to update these values completely because PWM clock may be different from system.." "0,1"
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tree.end
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repeat.end
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tree.end
|
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tree "QEI"
|
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repeat 2. (list 0. 1.) (list ad:0x400B0000 ad:0x400B1000)
|
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tree "QEI$1"
|
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base $2
|
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group.long 0x00++0x03
|
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line.long 0x00 "QEI_CNT,QEI Pulse Counter"
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hexmask.long 0x00 0.--31. 1. "VAL,Quadrature Encoder Pulse Counter\nA 32-bit up/down counter"
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group.long 0x04++0x03
|
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line.long 0x00 "QEI_CNTHOLD,QEI Pulse Counter Hold Register"
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hexmask.long 0x00 0.--31. 1. "VAL,Quadrature Encoder Pulse Counter Hold Register\nWhen bit HOLDCNT (QEIx_CTL[24]) goes from low to high the QEI_CNT value is copied into QEI_CNTHOLD register"
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group.long 0x08++0x03
|
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line.long 0x00 "QEI_CNTLATCH,QEI Pulse Counter Index Latch Register"
|
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hexmask.long 0x00 0.--31. 1. "VAL,Quadrature Encoder Pulse Counter Index Latch\nWhen the IDXF (QEI_STATUS[0]) bit is set the QEI_CNT value is copied into QEI_CNTLATCH register"
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group.long 0x0C++0x03
|
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line.long 0x00 "QEI_CNTCMP,QEI Pulse Counter Compare Register"
|
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hexmask.long 0x00 0.--31. 1. "VAL,Quadrature Encoder Pulse Counter Compare\n"
|
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group.long 0x14++0x03
|
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line.long 0x00 "QEI_CNTMAX,QEI Pre-set Maximum Count Register"
|
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hexmask.long 0x00 0.--31. 1. "VAL,Quadrature Encoder Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the quadrature encoder pulses in a revolution for the QEI controller compare-counting mode"
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group.long 0x18++0x03
|
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line.long 0x00 "QEI_CTL,QEI Controller Control Register"
|
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bitfld.long 0x00 29. "QEIEN,Quadrature Encoder Interface Controller Enable Bit\n" "0: QEI controller function Disabled,1: QEI controller function Enabled"
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bitfld.long 0x00 28. "CMPEN,The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register QEI_CNTCMP if QEI_CNT value reaches QEI_CNTCMP the flag CMPF will be set" "0: Compare function Disabled,1: Compare function Enabled"
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newline
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bitfld.long 0x00 27. "IDXRLDEN,Index Trigger QEI_CNT Reload Enable Bit\n" "0: Reload function Disabled,1: QEI_CNT re-initialized by Index signal Enabled"
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bitfld.long 0x00 25. "IDXLATEN,Index Latch QEI_CNT Enable Bit\nIf this bit is set to high the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.\n" "0: The index signal latch QEI counter function..,1: The index signal latch QEI counter function.."
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newline
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bitfld.long 0x00 24. "HOLDCNT,Hold QEI_CNT Control\nWhen this bit is set from low to high the QEI_CNT value is copied into QEI_CNTHOLD" "0: No operation,1: QEI_CNT content is captured and stored in.."
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bitfld.long 0x00 23. "HOLDTMR3,Hold QEI_CNT By Timer 3 \n" "0: TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER3_INTSTS[0]) in.."
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newline
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bitfld.long 0x00 22. "HOLDTMR2,Hold QEI_CNT By Timer 2\n" "0: TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER2_INTSTS[0]) in.."
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bitfld.long 0x00 21. "HOLDTMR1,Hold QEI_CNT By Timer 1 \n" "0: TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF (TIMER1_INTSTS[0]).."
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newline
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bitfld.long 0x00 20. "HOLDTMR0,Hold QEI_CNT By Timer 0 \n" "0: TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER0_INTSTS[0]) in.."
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bitfld.long 0x00 19. "IDXIEN,IDXF Trigger QEI Interrupt Enable Bit\n" "0: The IDXF can trigger QEI interrupt Disabled,1: The IDXF can trigger QEI interrupt Enabled"
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newline
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bitfld.long 0x00 18. "CMPIEN,CMPF Trigger QEI Interrupt Enable Bit\n" "0: CMPF can trigger QEI controller interrupt..,1: CMPF can trigger QEI controller interrupt.."
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bitfld.long 0x00 17. "DIRIEN,DIRCHGF Trigger QEI Interrupt Enable Bit\n" "0: DIRCHGF can trigger QEI controller interrupt..,1: DIRCHGF can trigger QEI controller interrupt.."
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newline
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bitfld.long 0x00 16. "OVUNIEN,OVUNF Trigger QEI Interrupt Enable Bit\n" "0: OVUNF can trigger QEI controller interrupt..,1: OVUNF can trigger QEI controller interrupt.."
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bitfld.long 0x00 14. "IDXINV,Inverse IDX Input Polarity\n" "0: Not inverse IDX input polarity,1: IDX input polarity is inversed to QEI.."
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newline
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bitfld.long 0x00 13. "CHBINV,Inverse QEB Input Polarity\n" "0: Not inverse QEB input polarity,1: QEB input polarity is inversed to QEI.."
|
|
bitfld.long 0x00 12. "CHAINV,Inverse QEA Input Polarity\n" "0: Not inverse QEA input polarity,1: QEA input polarity is inversed to QEI.."
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|
newline
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bitfld.long 0x00 8.--9. "MODE,QEI Counting Mode Selection\nThere are four quadrature encoder pulse counter operation modes.\n" "0: X4 Free-counting Mode,1: X2 Free-counting Mode,2: X4 Compare-counting Mode,3: X2 Compare-counting Mode"
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bitfld.long 0x00 6. "IDXEN,IDX Input To QEI Controller Enable Bit\n" "0: IDX input to QEI Controller Disabled,1: IDX input to QEI Controller Enabled"
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newline
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bitfld.long 0x00 5. "CHBEN,QEB Input To QEI Controller Enable Bit\n" "0: QEB input to QEI Controller Disabled,1: QEB input to QEI Controller Enabled"
|
|
bitfld.long 0x00 4. "CHAEN,QEA Input To QEI Controller Enable Bit\n" "0: QEA input to QEI Controller Disabled,1: QEA input to QEI Controller Enabled"
|
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newline
|
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bitfld.long 0x00 3. "NFDIS,QEI Controller Input Noise Filter Disable Bit\n" "0: The noise filter of QEI controller Enabled,1: The noise filter of QEI controller Disabled"
|
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bitfld.long 0x00 0.--1. "NFCLKSEL,Noise Filter Clock Pre-Divide Selection\nTo determine the sampling frequency of the Noise Filter clock .\n" "0: QEI_CLK,1: QEI_CLK/2,2: QEI_CLK/4,3: QEI_CLK/16"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "QEI_STATUS,QEI Controller Status Register"
|
|
bitfld.long 0x00 8. "DIRF,QEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB" "0: QEI Counter is in down-counting,1: QEI Counter is in up-counting"
|
|
bitfld.long 0x00 3. "DIRCHGF,Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed" "0: No change in QEI counter counting direction,1: QEI counter counting direction is changed"
|
|
newline
|
|
bitfld.long 0x00 2. "OVUNF,QEI Counter Overflow Or Underflow Flag\nFlag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the QEI_CNTMAX value to zero in compare-counting mode" "0: No overflow or underflow occurs in QEI counter,1: QEI counter occurs counting overflow or.."
|
|
bitfld.long 0x00 1. "CMPF,Compare-Match Flag\nIf the QEI compare function is enabled the flag is set by hardware while QEI counter up or down counts and reach to the QEI_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it" "0: QEI counter does not match with QEI_CNTCMP..,1: QEI counter counts to the same as QEI_CNTCMP.."
|
|
newline
|
|
bitfld.long 0x00 0. "IDXF,IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it" "0: No rising edge detected on signal CHX,1: A rising edge occurs on signal CHX"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "RTC"
|
|
base ad:0x40041000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_INIT,RTC Initiation Register"
|
|
hexmask.long 0x00 1.--31. 1. "INIT,RTC Initiation\nWhen RTC block is powered on RTC is at reset state"
|
|
rbitfld.long 0x00 0. "INIT_Active,RTC Active Status (Read Only)\n" "0: RTC is at reset state,1: RTC is at normal active state"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_RWEN,RTC Access Enable Register"
|
|
rbitfld.long 0x00 16. "RWENF,RTC Register Access Enable Flag (Read Only)\n" "0: RTC register read/write Disabled,1: RTC register read/write Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. "RWEN,RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clock"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_FREQADJ,RTC Frequency Compensation Register"
|
|
bitfld.long 0x00 8.--11. "INTEGER,Integer Part\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--5. "FRACTION,Fraction Part\nNote: Digit in RTC_FREQADJ must be expressed as hexadecimal number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RTC_TIME,Time Loading Register"
|
|
bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit (0~2)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_CAL,Calendar Loading Register"
|
|
bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
|
|
bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_CLKFMT,Time Scale Selection Register"
|
|
bitfld.long 0x00 0. "_24HEN,24-Hour / 12-Hour Time Scale Selection\n" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RTC_WEEKDAY,Day of the Week Register"
|
|
bitfld.long 0x00 0.--2. "WEEKDAY,Day Of The Week Bits\n" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_TALM,Time Alarm Register"
|
|
bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit of Alarm Setting (0~2)" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_CALM,Calendar Alarm Register"
|
|
bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
|
|
bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RTC_LEAPYEAR,Leap Year Indication Register"
|
|
bitfld.long 0x00 0. "LEAPYEAR,Leap Year Indicator (Read Only)\n" "0: This year is not a leap year,1: This year is leap year"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "RTC_INTEN,RTC Interrupt Enable Register"
|
|
bitfld.long 0x00 1. "TICKIEN,Time Tick Interrupt Enable Bit\n" "0: RTC Time Tick Interrupt Disabled,1: RTC Time Tick Interrupt Enabled"
|
|
bitfld.long 0x00 0. "ALMIEN,Alarm Interrupt Enable Bit\n" "0: RTC Alarm Interrupt Disabled,1: RTC Alarm Interrupt Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RTC_INTSTS,RTC Interrupt Indicator Register"
|
|
bitfld.long 0x00 1. "TICKIF,RTC Time Tick Interrupt Flag\nWhen RTC Time Tick happened this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled (TICKIEN (RTC_INTEN[1])) is set to 1" "0,1"
|
|
bitfld.long 0x00 0. "ALMIF,RTC Alarm Interrupt Flag\nWhen RTC real time counters RTC_TIME and RTC_CAL reach the alarm setting time registers RTC_TALM and RTC_CALM this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled (ALMIEN.." "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RTC_TICK,RTC Time Tick Register"
|
|
bitfld.long 0x00 0.--2. "TICKSEL,Time Tick Bits\n" "0,1,2,3,4,5,6,7"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RTC_SPRCTL,RTC Spare Functional Control Register"
|
|
bitfld.long 0x00 7. "SPRRWRDY,SPR Register Ready\nThis bit indicates if the registers RTC_SPRCTL RTC_SPR0 ~ RTC_SPR23 are ready to be accessed.\nAfter CPU writing registers RTC_SPRCTL RTC_SPR0 ~ RTC_SPR23 polling this bit to check if these registers are updated done is.." "0: RTC_SPRCTL RTC_SPR0 ~ RTC_SPR23 updating is..,1: RTC_SPRCTL RTC_SPR0 ~ RTC_SPR23 are updated.."
|
|
bitfld.long 0x00 2. "SPRRWEN,SPR Register Enable Bit\nThis bit controls the spare register to be enabled or not.\n" "0: Spare register Disabled and RTC_SPR0 ~..,1: Spare register Enabled and RTC_SPR0 ~.."
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|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "RTC_SPR$1,RTC Spare Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SPARE,SPARE Bits\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to SPARE register software should.."
|
|
repeat.end
|
|
repeat 8. (strings "16" "17" "18" "19" "20" "21" "22" "23" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "RTC_SPR$1,RTC Spare Register $1"
|
|
hexmask.long 0x00 0.--31. 1. "SPARE,SPARE Bits\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to SPARE register software should.."
|
|
repeat.end
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "RTC_TAMPCTL,Tamper Control Register"
|
|
bitfld.long 0x00 7. "TAMPLV1,Tamper1 Level \n" "0: Low,1: High"
|
|
bitfld.long 0x00 6. "TAMPLV0,Tamper0 Level \n" "0: Low,1: High"
|
|
newline
|
|
bitfld.long 0x00 5. "TAMPDBEN1,Tamper1 De-Bounce Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 4. "TAMPDBEN0,Tamper0 De-Bounce Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TAMPEN1,Tamper1 Detect Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 2. "TAMPEN0,Tamper0 Detect Enable Bit\n" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "DESTROYEN,Destroy Spare Register Enable Bit\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 0. "TIEN,Tamper Interrupt Enable Bit\n" "0: Tamper interrupt Disabled,1: Tamper interrupt Enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "RTC_TAMPSTS,Tamper Status Register"
|
|
bitfld.long 0x00 1. "TAMPSTS1,Tamper1 Sense Flag \nNote: Write 1 to clear it" "0: No invasion,1: Tamper1 detect invasion"
|
|
bitfld.long 0x00 0. "TAMPSTS0,Tamper0 Sense Flag\nNote: Write 1 to clear it" "0: No invasion,1: Tamper0 detect invasion"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "RTC_TAMP0PCTL,TAMPER0 Pin I/O Mode Control"
|
|
bitfld.long 0x00 4. "DINOFF,Off Digital\n" "0: Off digital Disabled,1: Off digital Enabled"
|
|
bitfld.long 0x00 3. "TYPE,Type\n" "0: Input Schmitt Trigger function Disabled,1: Input Schmitt Trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TRIEN,Tri-State\n" "0: Tri-state Disabled,1: Tri-state Enabled"
|
|
bitfld.long 0x00 1. "OUTEN,Output Enable Bit\n" "0: Output Enabled,1: Output Disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "OUTLV,Output Level\n" "0: Low,1: High"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "RTC_TAMP1PCTL,TAMPER1 Pin I/O Mode Control"
|
|
bitfld.long 0x00 4. "DINOFF,Off Digital\n" "0: Off digital Disabled,1: Off digital Enabled"
|
|
bitfld.long 0x00 3. "TYPE,Type\n" "0: Input Schmitt Trigger function Disabled,1: Input Schmitt Trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TRIEN,Tri-State\n" "0: Tri-state Disabled,1: Tri-state Enabled"
|
|
bitfld.long 0x00 1. "OUTEN,Output Enable Bit\n" "0: Output Enabled,1: Output Disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "OUTLV,Output Level\n" "0: Low,1: High"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "RTC_LXTIPCTL,32K Input Pin I/O Mode Control"
|
|
bitfld.long 0x00 4. "DINOFF,Off Digital\n" "0: Off digital Disabled,1: Off digital Enabled"
|
|
bitfld.long 0x00 3. "TYPE,Type\n" "0: Input Schmitt Trigger function Disabled,1: Input Schmitt Trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TRIEN,Tri-State\n" "0: Tri-state Disabled,1: Tri-state Enabled"
|
|
bitfld.long 0x00 1. "OUTEN,Output Enable Bit\n" "0: Output Enabled,1: Output Disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "OUTLV,Output Level\n" "0: Low,1: High"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "RTC_LXTOPCTL,32K Output Pin I/O Mode Control"
|
|
bitfld.long 0x00 4. "DINOFF,Off Digital\n" "0: Off digital Disabled,1: Off digital Enabled"
|
|
bitfld.long 0x00 3. "TYPE,Type\n" "0: Input Schmitt Trigger function Disabled,1: Input Schmitt Trigger function Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TRIEN,Tri-State\n" "0: Tri-state Disabled,1: Tri-state Enabled"
|
|
bitfld.long 0x00 1. "OUTEN,Output Enable Bit\n" "0: Output Enabled,1: Output Disabled"
|
|
newline
|
|
bitfld.long 0x00 0. "OUTLV,Output Level\n" "0: Low,1: High"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RTC_TAMSK,Time Alarm MASK Register"
|
|
bitfld.long 0x00 5. "MTENHR,Mask 10-Hour Time Digit of Alarm Setting (0~2)" "0,1"
|
|
bitfld.long 0x00 4. "MHR,Mask 1-Hour Time Digit of Alarm Setting (0~9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MTENMIN,Mask 10-Min Time Digit of Alarm Setting (0~5)" "0,1"
|
|
bitfld.long 0x00 2. "MMIN,Mask 1-Min Time Digit of Alarm Setting (0~9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "MTENSEC,Mask 10-Sec Time Digit of Alarm Setting (0~5)" "0,1"
|
|
bitfld.long 0x00 0. "MSEC,Mask 1-Sec Time Digit of Alarm Setting (0~9)" "0,1"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "RTC_CAMSK,Calendar Alarm MASK Register"
|
|
bitfld.long 0x00 5. "MTENYEAR,Mask 10-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
|
|
bitfld.long 0x00 4. "MYEAR,Mask 1-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "MTENMON,Mask 10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
|
|
bitfld.long 0x00 2. "MMON,Mask 1-Month Calendar Digit of Alarm Setting (0~9)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "MTENDAY,Mask 10-Day Calendar Digit of Alarm Setting (0~3)" "0,1"
|
|
bitfld.long 0x00 0. "MDAY,Mask 1-Day Calendar Digit of Alarm Setting (0~9)" "0,1"
|
|
tree.end
|
|
tree "SC"
|
|
repeat 6. (list 0. 1. 2. 3. 4. 5.) (list ad:0x40090000 ad:0x40091000 ad:0x40092000 ad:0x40093000 ad:0x40094000 ad:0x40095000)
|
|
tree "SC$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC_DAT,SC Receive and Transmit Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAT,Receiving/ Transmit Buffer \nWrite Operation:\nBy writing data to DAT the SC will send out an 8-bit data.\nNote: If SCEN(SC_CTL[0]) is not enabled DAT cannot be programmed.\nRead Operation:\nBy reading DAT the SC will return an 8-bit received data"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC_CTL,SC Control Register"
|
|
bitfld.long 0x00 30. "SYNC,SYNC Flag Indicator\nDue to synchronization software should check this bit before writing a new value to RXRTY and TXRTY.\nNote: This bit is read only" "0: synchronizing is completion user can write..,1: Last value is synchronizing"
|
|
bitfld.long 0x00 26. "CDLV,Card Detect Level \n\nNote: Software must select card detect level before Smart Card engine enabled" "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "CDDBSEL,Card Detect De-Bounce Selection\nThis field indicates the card detect de-bounce selection.\n" "0: De-bounce sample card insert once per 384..,1: De-bounce sample card insert once per 192 (64..,2: De-bounce sample card insert once per 96 (32..,3: De-bounce sample card insert once per 48 (16.."
|
|
bitfld.long 0x00 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.\n" "0: TX error retry function Disabled,1: TX error retry function Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19. "RXRTYEN,\n" "0: RX error retry function Disabled,1: RX error retry function Enabled"
|
|
newline
|
|
bitfld.long 0x00 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote: The default stop bit length is 2" "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
|
|
newline
|
|
bitfld.long 0x00 13.--14. "TMRSEL,Timer Selection \n" "0: All internal timer function Disabled,1: Internal 24 bit timer Enabled,2: internal 24 bit timer and 8 bit internal..,3: Internal 24 bit timer and two 8 bit timers.."
|
|
bitfld.long 0x00 8.--12. "BGT,Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV the RDA_IF will be set (if IER [RDAIENN] is enabled an interrupt will be generated).\n" "0: INTR_RDA Trigger Level with 01 Bytes,1: INTR_RDA Trigger Level with 02 Bytes,2: INTR_RDA Trigger Level with 03 Bytes,3: Reserved"
|
|
bitfld.long 0x00 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN(SC_CTL[3]) enabled this fields are ignored" "0: Direct convention,1: Reserved,2: Reserved,3: Inverse convention"
|
|
newline
|
|
bitfld.long 0x00 3. "AUTOCEN,Auto Convention Enable Bit\n" "0: Auto-convention Disabled,1: Auto-convention Enabled"
|
|
bitfld.long 0x00 2. "TXOFF,TX Transition Disable Bit\n" "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x00 1. "RXOFF,RX Transition Disable Bit\nNote: If AUTOCEN is enabled this field must be ignored" "0: The receiver Enabled,1: The receiver Disabled"
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bitfld.long 0x00 0. "SCEN,SC Engine Enable Bit\nSet this bit to 1 to enable SC operation" "0,1"
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group.long 0x08++0x03
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line.long 0x00 "SC_ALTCTL,SC Alternate Control Register"
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rbitfld.long 0x00 15. "ACTSTS2,Internal Timer2 Active State (Read Only)\nThis bit indicates the timer counter status of timer2.\n" "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x00 14. "ACTSTS1,Internal Timer1 Active State (Read Only)\nThis bit indicates the timer counter status of timer1.\n" "0: Timer1 is not active,1: Timer1 is active"
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rbitfld.long 0x00 13. "ACTSTS0,Internal Timer0 Active State (Read Only)\nThis bit indicates the timer counter status of timer0.\n" "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x00 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit\n" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
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bitfld.long 0x00 11. "ADACEN,Auto Deactivation When Card Removal\nNote: When the card is removed hardware will stop any process and then do deactivation sequence (if this bit is set)" "0: Auto deactivation Disabled when hardware..,1: Auto deactivation Enabled when hardware.."
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bitfld.long 0x00 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).\nUnit: SC clock\nActivation: refer to SC Activation Sequence in Figure 5.19-4.\nWarm-reset: refer to Warm-Reset.." "0,1,2,3"
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bitfld.long 0x00 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set.." "0: No effect,1: Warm reset sequence generator Enabled"
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bitfld.long 0x00 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence\nNote1: When the activation sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to.." "0: No effect,1: Activation sequence generator Enabled"
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bitfld.long 0x00 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be.." "0: No effect,1: Deactivation sequence generator Enabled"
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bitfld.long 0x00 1. "RXRST,Rx Software Reset\nWhen RXRST is set all the bytes in the receiver buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the Rx internal state machine and.."
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bitfld.long 0x00 0. "TXRST,TX Software Reset\nWhen TXRST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the TX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "SC_EGT,SC Extend Guard Time Register"
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hexmask.long.byte 0x00 0.--7. 1. "EGT,Extended Guard Time\nThis field indicates the extended guard timer value.\n\nNote: The counter is ETU base and the real extended guard time is EGT"
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group.long 0x10++0x03
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line.long 0x00 "SC_RXTOUT,SC Receive Buffer Time-out Register"
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hexmask.long.word 0x00 0.--8. 1. "RFTM,SC Receiver Buffer Time-Out (ETU Base)\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5\nNote2: Fill all 0 to this field indicates to disable this function"
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group.long 0x14++0x03
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line.long 0x00 "SC_ETUCTL,SC ETU Control Register"
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bitfld.long 0x00 15. "CMPEN,Compensation Mode Enable Bit\nThis bit enables clock compensation function" "0: Compensation function Disabled,1: Compensation function Enabled"
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hexmask.long.word 0x00 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field indicates the clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: Software can configure this field but this field must be greater than 0x004"
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group.long 0x18++0x03
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line.long 0x00 "SC_INTEN,SC Interrupt Enable Control Register"
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bitfld.long 0x00 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit \nThis field is used for auto-convention error interrupt enable.\n" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x00 9. "RXTOIF,Receiver Buffer Time-Out Interrupt Enable Bit \nThis field is used for receiver buffer time-out interrupt enable.\n" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x00 8. "INITIEN,Initial End Interrupt Enable Bit\n" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x00 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used for card detect interrupt enable" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x00 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used for block guard time interrupt enable.\n" "0: Block guard time Disabled,1: Block guard time Enabled"
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bitfld.long 0x00 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used for TMR2 interrupt enable.\n" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x00 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the TMR1 interrupt.\n" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x00 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable TMR0 interrupt enable.\n" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x00 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used for transfer error interrupt enable" "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x00 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used for transmit buffer empty interrupt enable.\n" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.\n" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt.."
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group.long 0x1C++0x03
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line.long 0x00 "SC_INTSTS,SC Interrupt Status Register"
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rbitfld.long 0x00 10. "ACERRIF,Auto Convention Error Interrupt Status Flag (Read Only)\nThis field indicates auto convention sequence error" "0,1"
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rbitfld.long 0x00 9. "RBTOIF,Receiver Buffer Time-Out Interrupt Status Flag (Read Only)\nThis field is used for receiver buffer time-out interrupt status flag.\nNote: This field is the status flag of receiver buffer time-out state" "0,1"
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rbitfld.long 0x00 8. "INITIF,Initial End Interrupt Status Flag (Read Only)\nThis field is used for activation (ACTEN(SC_ALTCTL[3])) deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit is read only but.." "0,1"
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rbitfld.long 0x00 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag" "0,1"
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rbitfld.long 0x00 6. "BGTIF,\n" "0,1"
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rbitfld.long 0x00 5. "TMR2IF,Timer2 Interrupt Status Flag (Read Only)\nThis field is used for TMR2 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 4. "TMR1IF,Timer1 Interrupt Status Flag (Read Only)\nThis field is used for TMR1 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 3. "TMR0IF,Timer0 Interrupt Status Flag (Read Only)\nThis field is used for TMR0 interrupt status flag.\nNote: This bit is read only but it can be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 2. "TERRIF,Transfer Error Interrupt Status Flag (Read Only)\nThis field is used for transfer error interrupt status flag" "0,1"
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rbitfld.long 0x00 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This field is the status flag of transmit buffer empty state" "0,1"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6])" "0,1"
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group.long 0x20++0x03
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line.long 0x00 "SC_STATUS,SC Status Register"
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rbitfld.long 0x00 31. "TXACT,Transmit In Active Status Flag (Read Only)\n" "0: This bit is cleared automatically when TX..,1: This bit is set by hardware when TX transfer.."
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rbitfld.long 0x00 30. "TXOVERR,Transmitter Over Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits over retry number limitation.\nNote: This bit is read only but it can be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 29. "TXRERR,Transmitter Retry Error (Read Only)\nThis bit is set by hardware when transmitter re-transmits.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU" "0,1"
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rbitfld.long 0x00 24.--25. "TXPOINT,Transmit Buffer Pointer Status Flag (Read Only)\nThis field indicates the TX buffer pointer status flag" "0,1,2,3"
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rbitfld.long 0x00 23. "RXACT,Receiver In Active Status Flag (Read Only)\nThis bit is set by hardware when RX transfer is in active.\nThis bit is cleared automatically when RX transfer is finished" "0,1"
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rbitfld.long 0x00 22. "RXOVERR,Receiver Over Retry Error (Read Only)\nThis bit is set by hardware when RX transfer error retry over retry number limit.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by.." "0,1"
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rbitfld.long 0x00 21. "RXRERR,Receiver Retry Error (Read Only)\nThis bit is set by hardware when RX has any error and retries transfer.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to.." "0,1"
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rbitfld.long 0x00 16.--17. "RXPOINT,Receiver Buffer Pointer Status Flag (Read Only)\nThis field indicates the RX buffer pointer status flag" "0,1,2,3"
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rbitfld.long 0x00 13. "CDPINSTS,Card Detect Status Of SC_CD Pin Status (Read Only)\nThis bit is the pin status flag of SC_CD\n" "0: The SC_CD pin state at low,1: The SC_CD pin state at high"
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rbitfld.long 0x00 12. "CINSERT,Card Detect Insert Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been inserted.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: The card detect engine will start after SCEN (SC_CTL[0]) set" "0: No effect.1 = Card insert,?..."
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rbitfld.long 0x00 11. "CREMOVE,Card Detect Removal Status Of SC_CD Pin (Read Only)\nThis bit is set whenever card has been removal.\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: Card detect engine will start after SCEN (SC_CTL[0])set" "0: No effect,1: Card removed"
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rbitfld.long 0x00 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates TX buffer full or not" "0,1"
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rbitfld.long 0x00 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nWhen the last byte of TX buffer has been transferred to Transmitter Shift Register hardware sets this bit high" "0,1"
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rbitfld.long 0x00 8. "TXOV,TX Overflow Error Interrupt Status Flag (Read Only)\nIf TX buffer is full an additional write to SC_DAT will cause this bit be set to 1 by hardware" "0,1"
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rbitfld.long 0x00 6. "BEF,Receiver Break Error Status Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input (RX) held in the spacing state (logic 0) is longer than a full word transmission time (that is the total time of start bit + data bits +.." "0,1"
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rbitfld.long 0x00 5. "FEF,Receiver Frame Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as a logic 0)" "0,1"
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rbitfld.long 0x00 4. "PEF,Receiver Parity Error Status Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote1: This bit is read only but it can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries.." "0,1"
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rbitfld.long 0x00 2. "RXFULL,Receiver Buffer Full Status Flag (Read Only)\nThis bit indicates RX buffer full or not.\nThis bit is set when RX pointer is equal to 4 otherwise it is cleared by hardware" "0,1"
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rbitfld.long 0x00 1. "RXEMPTY,Receiver Buffer Empty Status Flag(Read Only)\nThis bit indicates RX buffer empty or not.\nWhen the last byte of Rx buffer has been read by CPU hardware sets this bit high" "0,1"
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rbitfld.long 0x00 0. "RXOV,RX Overflow Error Status Flag (Read Only) \nThis bit is set when RX buffer overflow.\nIf the number of received bytes is greater than Rx Buffer size (4 bytes) this bit will be set.\nNote: This bit is read only but it can be cleared by writing 1 to it" "0,1"
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group.long 0x24++0x03
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line.long 0x00 "SC_PINCTL,SC Pin Control State Register"
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bitfld.long 0x00 30. "SYNC,SYNC Flag Indicator\nDue to synchronization software should check this bit when writing a new value to SC_PINCTL register.\nNote: This bit is read only" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 18. "RSTSTS,SC_RST Pin Signals\nThis bit is the pin status of SC_RST\nNote: When SC is operated at activation warm reset or deactivation mode this bit will be changed automatically" "0: SC_RST pin is low,1: SC_RST pin is high"
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bitfld.long 0x00 17. "PWRSTS,\n" "0: SC_PWR pin to low,1: SC_PWR pin to high"
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bitfld.long 0x00 16. "DATSTS,\n" "0: The SC_DAT pin is low,1: The SC_DAT pin is high"
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bitfld.long 0x00 11. "PWRINV,SC_POW Pin Inverse\nThis bit is used for inverse the SC_POW pin.\nThere are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0])" "0,1"
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bitfld.long 0x00 9. "SCDOOUT,SC Data Output Pin \nThis bit is the pin status of SCDOSTS but user can drive SCDOSTS pin to high or low by setting this bit.\nNote: When SC is at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCDOSTS pin to low,1: Drive SCDOSTS pin to high"
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bitfld.long 0x00 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically" "0: SC clock generation Disabled,1: SC clock always keeps free running"
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bitfld.long 0x00 1. "SCRST,SCRST Pin Signal\nThis bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit.\nWrite this field to drive SCRST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be.." "0: Drive SCRST pin to low.\nSCRST pin status is..,1: Drive SCRST pin to high.\nSCRST pin status is.."
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bitfld.long 0x00 0. "PWREN,SC_PWREN Pin Signal\nSoftware can set PWREN and PWRINV to decide SC_PWR pin is in high or low level.\nWrite this field to drive SC_PWR pin\nRefer PWRINV description for programming SC_PWR pin voltage level" "0: SC_PWR pin status is low,1: SC_PWR pin status is high"
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group.long 0x28++0x03
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line.long 0x00 "SC_TMRCTL0,SC Internal Timer Control Register 0"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer 0 Counter Value (ETU Base)\nThis field indicates the internal timer operation values"
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group.long 0x2C++0x03
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line.long 0x00 "SC_TMRCTL1,SC Internal Timer Control Register 1"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection.\nRefer to 6.17.4.4 for programming Timer1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 1 Counter Value (ETU Base)\nThis field indicates the internal timer operation values"
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group.long 0x30++0x03
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line.long 0x00 "SC_TMRCTL2,SC Internal Timer Control Register 2"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit timer operation selection\nRefer to 6.17.4.4 for programming Timer2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 2 Counter Value (ETU Base)\nThis field indicates the internal timer operation values"
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group.long 0x34++0x03
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line.long 0x00 "SC_UARTCTL,SC UART Mode Control Register"
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bitfld.long 0x00 7. "OPE,Odd Parity Enable Bit\nNote: This bit has effect only when PBOFF bit is '0'" "0: Even number of logic 1's are transmitted or..,1: Odd number of logic 1's are transmitted or.."
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bitfld.long 0x00 6. "PBOFF,Parity Bit Disable Bit\nNote: In smart card mode this field must be '0' (default setting is with parity bit)" "0: Parity bit is generated or checked between..,1: Parity bit is not generated (transmitting.."
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bitfld.long 0x00 4.--5. "WLS,Data Length\nNote: In smart card mode this WLS must be '00'" "0: Character Data Length is 8 bits,1: Character Data Length is 7 bits,2: Character Data length is 6 bits,3: Character Data Length is 5 bits"
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bitfld.long 0x00 0. "UARTEN,UART Mode Enable Bit\nNote3: When UART is enabled hardware will generate a reset to reset FIFO and internal state machine" "0: Smart Card mode,1: UART mode"
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rgroup.long 0x38++0x03
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line.long 0x00 "SC_TMRDAT0,SC Timer 0 Current Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT0,Timer0 Current Counter Value (Read Only)\nThis field indicates the current count values of timer0"
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rgroup.long 0x3C++0x03
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line.long 0x00 "SC_TMRDAT1_2,SC Timer 1 and 2 Current Data Register"
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hexmask.long.byte 0x00 8.--15. 1. "CNT2,Timer2 Current Counter Value (Read Only)\nThis field indicates the current count values of timer2"
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hexmask.long.byte 0x00 0.--7. 1. "CNT1,Timer1 Current Counter Value (Read Only)\nThis field indicates the current count values of timer1"
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tree.end
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repeat.end
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tree.end
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tree "SCS"
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base ad:0xE000E000
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1"
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bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection\n" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
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bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled\n" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
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bitfld.long 0x00 0. "ENABLE,System Tick Counter Enabled\n" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
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group.long 0x14++0x03
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0"
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group.long 0x18++0x03
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line.long 0x00 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value"
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group.long 0xD04++0x03
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x00 31. "NMIPENDSET,NMI Set-Pending Bit\nWrite:\nNote: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: No effect.\nNMI exception is not pending,1: Changes NMI exception state to pending.\nNMI.."
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bitfld.long 0x00 28. "PENDSVSET,PendSV Set-Pending Bit\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
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bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-Pending Bit\nWrite:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the PendSV.."
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bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-Pending Bit\nWrite:\n" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
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bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-Pending Bit\nWrite:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the SysTick.."
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rbitfld.long 0x00 23. "ISRPREEMPT,Interrupt Preempt Bit (Read only)\nIf set a pending exception will be serviced on exit from the debug halt state" "0,1"
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rbitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read only)\n" "0: Interrupt not pending,1: Interrupt pending"
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bitfld.long 0x00 12.--17. "VECTPENDING,Number of the Highest Pended Exception\nIndicate the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers but not any effect of the.." "0: no pending exceptions,?..."
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bitfld.long 0x00 11. "RETTOBASE,Preempted Active Exceptions indicator\nIndicate whether There are Preempted Active Exceptions\n" "0: there are preempted active exceptions to..,1: there are no active exceptions or the.."
|
|
bitfld.long 0x00 0.--5. "VECTACTIVE,Contains The Active Exception Number\n" "0: Thread mode,?..."
|
|
group.long 0xD0C++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register this field should be 0x05FA otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of.."
|
|
bitfld.long 0x00 15. "ENDIANNESS,Data Endianness\n" "0: Little-endian,1: Big-endian"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "PRIGROUP,Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's.." "0,1"
|
|
bitfld.long 0x00 0. "VECTRESET,Reserved for Debug Use \nThis bit is read as 0" "0,1"
|
|
group.long 0xD10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. "SEVONPEND,Send Event On Pending\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
|
|
bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode.\n" "0: Sleep,1: Deep sleep"
|
|
newline
|
|
bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enters sleep or deep sleep on return from an.."
|
|
group.long 0xD18++0x03
|
|
line.long 0x00 "SHPR1,System Handler Priority Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault"
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage"
|
|
group.long 0xD1C++0x03
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. "PRI_11,Priority Of System Handler" "0,1,2,3"
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x00 30.--31. "PRI_15,Priority Of System Handler" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_14,Priority Of System Handler" "0,1,2,3"
|
|
tree.end
|
|
tree "SDH"
|
|
base ad:0x4000D000
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "SDH_FB_$1,Shared Buffer (FIFO)"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "SDH_FB_$1,Shared Buffer (FIFO)"
|
|
repeat.end
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "SDH_DMACTL,DMA Control and Status Register"
|
|
bitfld.long 0x00 9. "DMABUSY,DMA Transfer Is In Progress\nThis bit indicates if SD Host is granted and doing DMA transfer or not.\n" "0: DMA transfer is not in progress,1: DMA transfer is in progress"
|
|
bitfld.long 0x00 3. "SGEN,Scatter-Gather Function Enable Bit\n" "0: Scatter-gather function Disabled (DMA will..,1: Scatter-gather function Enabled (DMA will.."
|
|
newline
|
|
bitfld.long 0x00 1. "DMARST,Software Engine Reset\nNote: The software reset DMA related registers" "0: No effect,1: Reset internal state machine and pointers"
|
|
bitfld.long 0x00 0. "DMAEN,DMA Engine Enable Bit\nIf this bit is cleared DMA will ignore all requests from SD host and force bus master into IDLE state.\nNote: If target abort is occurred DMAEN will be cleared" "0: DMA Disabled,1: DMA Enabled"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "SDH_DMASA,DMA Transfer Starting Address Register"
|
|
hexmask.long 0x00 1.--31. 1. "DMASA,DMA Transfer Starting Address\nThis field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.\nIf DMA is not in normal mode this field will be interpreted as a starting.."
|
|
bitfld.long 0x00 0. "ORDER,Determined To The PAD Table Fetching Is In Order Or Out Of Order\n" "0: PAD table is fetched in order,1: PAD table is fetched out of order"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "SDH_DMABCNT,DMA Transfer Byte Count Register"
|
|
hexmask.long 0x00 0.--25. 1. "BCNT,DMA Transfer Byte Count (Read Only)\nThis field indicates the remained byte count of DMA transfer"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "SDH_DMAINTEN,DMA Interrupt Enable Control Register"
|
|
bitfld.long 0x00 1. "WEOTIEN,Wrong EOT Encountered Interrupt Enable Bit\n" "0: Interrupt generation Disabled when wrong EOT..,1: Interrupt generation Enabled when wrong EOT.."
|
|
bitfld.long 0x00 0. "ABORTIEN,DMA Read/Write Target Abort Interrupt Enable Bit\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled.."
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "SDH_DMAINTSTS,DMA Interrupt Status Register"
|
|
bitfld.long 0x00 1. "WEOTIF,Wrong EOT Encountered Interrupt Flag\nWhen DMA Scatter-Gather function is enabled and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host) this.." "0: No EOT encountered before DMA transfer finished,1: EOT encountered before DMA transfer finished"
|
|
bitfld.long 0x00 0. "ABORTIF,DMA Read/Write Target Abort Interrupt Flag\nNote: This bit is read only but can be cleared by writing '1' to it" "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SDH_GCTL,Global Control and Status Register"
|
|
bitfld.long 0x00 1. "SDEN,Secure Digital Functionality Enable Bit\n" "0: SD functionality disabled,1: SD functionality enabled"
|
|
bitfld.long 0x00 0. "GCTLRST,Software Engine Reset\n" "0: No effect,1: Reset SD host"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "SDH_GINTEN,Global Interrupt Control Register"
|
|
bitfld.long 0x00 0. "DTAIEN,DMA READ/WRITE Target Abort Interrupt Enable Bit\n" "0: DMA READ/WRITE target abort interrupt..,1: DMA READ/WRITE target abort interrupt.."
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "SDH_GINTSTS,Global Interrupt Status Register"
|
|
rbitfld.long 0x00 0. "DTAIF,DMA READ/WRITE Target Abort Interrupt Flag (Read Only)\nThis bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation" "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SDH_CTL,SD Control and Status Register"
|
|
bitfld.long 0x00 31. "CLKKEEP1,SD Clock Enable Control for Port 1\n" "0: SD host decided when to output clock and when..,1: SD clock always keeps free running"
|
|
bitfld.long 0x00 29.--30. "SDPORT,SD Port Selection\n" "0: Port 0 selected,1: Port 1 selected,?..."
|
|
newline
|
|
bitfld.long 0x00 24.--27. "SDNWR,NWR Parameter For Block Write Operation\nThis value indicates the NWR parameter for data block write operation in SD clock counts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BLKCNT,Block Counts To Be Transferred Or Received\nThis field contains the block counts for data-in and data-out transfer"
|
|
newline
|
|
bitfld.long 0x00 15. "DBW,SD Data Bus Width (For 1-Bit / 4-Bit Selection)\n" "0: Data bus width is 1-bit,1: Data bus width is 4-bit"
|
|
bitfld.long 0x00 14. "CTLRST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine and counters"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CMDCODE,SD Command Code\nThis register contains the SD command code (0x00 - 0x3F)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 7. "CLKKEEP0,SD Clock Enable Control for Port 0\n" "0: SD host decided when to output clock and when..,1: SD clock always keeps free running"
|
|
newline
|
|
bitfld.long 0x00 6. "CLK8OEN,Generating 8 Clock Cycles Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled SD host will output 8 clock cycles"
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|
bitfld.long 0x00 5. "CLK74OEN,Initial 74 Clock Cycles Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled SD host will output 74 clock cycles.."
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|
newline
|
|
bitfld.long 0x00 4. "R2EN,Response R2 Input Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled SD host will wait to receive a.."
|
|
bitfld.long 0x00 3. "DOEN,Data Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled SD host will transfer block data and.."
|
|
newline
|
|
bitfld.long 0x00 2. "DIEN,Data Input Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled SD host will wait to receive block.."
|
|
bitfld.long 0x00 1. "RIEN,Response Input Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled SD host will wait to receive a.."
|
|
newline
|
|
bitfld.long 0x00 0. "COEN,Command Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled SD host will output a command to SD.."
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "SDH_CMDARG,SD Command Argument Register"
|
|
hexmask.long 0x00 0.--31. 1. "ARGUMENT,SD Command Argument\nThis register contains a 32-bit value specifies the argument of SD command from host controller to SD card"
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SDH_INTEN,SD Interrupt Control Register"
|
|
bitfld.long 0x00 31. "CDSRC1,SD1 Card Detect Source Selection\n" "0: From SD1 card's DAT3 pin,1: From GPIO pin"
|
|
bitfld.long 0x00 30. "CDSRC0,SD0 Card Detect Source Selection\n" "0: From SD0 card's DAT3 pin,1: From GPIO pin"
|
|
newline
|
|
bitfld.long 0x00 14. "WKIEN,Wake-Up Signal Generating Enable Bit\nEnable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.\n" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 13. "DITOIEN,Data Input Time-Out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when data input time-out" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "RTOIEN,Response Time-Out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when receiving response or R2 time-out" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 9. "CDIEN1,SD1 Card Detection Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when card 1 is inserted or removed.\n" "0: Disable,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "CDIEN0,SD0 Card Detection Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when card 0 is inserted or removed.\n" "0: Disable,1: Enabled"
|
|
bitfld.long 0x00 1. "CRCIEN,CRC7 CRC16 And CRC Status Error Interrupt Enable Bit\n" "0: SD host will not generate interrupt when CRC7..,1: SD host will generate interrupt when CRC7.."
|
|
newline
|
|
bitfld.long 0x00 0. "BLKDIEN,Block Transfer Done Interrupt Enable Bit\n" "0: SD host will not generate interrupt when..,1: SD host will generate interrupt when data-in.."
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "SDH_INTSTS,SD Interrupt Status Register"
|
|
rbitfld.long 0x00 18. "DAT1STS,DAT1 Pin Status Of SD Port (Read Only)\nThis bit indicates the DAT1 pin status of SD port" "0,1"
|
|
rbitfld.long 0x00 17. "CDSTS1,Card Detect Status Of SD1 (Read Only)\nThis bit indicates the card detect pin status of SD1 and is used for card detection" "0: Card removed.\nCard inserted,1: Card inserted.\nCard removed"
|
|
newline
|
|
rbitfld.long 0x00 16. "CDSTS0,Card Detect Status Of SD0 (Read Only)\nThis bit indicates the card detect pin status of SD0 and is used for card detection" "0: Card removed.\nCard inserted,1: Card inserted.\nCard removed"
|
|
rbitfld.long 0x00 13. "DITOIF,Data Input Time-Out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\nNote: This bit is read only but can be cleared by writing '1' to it" "0: Not time-out,1: Data input time-out"
|
|
newline
|
|
rbitfld.long 0x00 12. "RTOIF,Response Time-Out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\nNote: This bit is read only but can be cleared by writing '1' to it" "0: Not time-out,1: Response time-out"
|
|
rbitfld.long 0x00 9. "CDIF1,SD1 Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card 1 is inserted or removed" "0: No card is inserted or removed,1: There is a card inserted in or removed from SD1"
|
|
newline
|
|
rbitfld.long 0x00 8. "CDIF0,SD0 Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card 0 is inserted or removed" "0: No card is inserted or removed,1: There is a card inserted in or removed from SD0"
|
|
rbitfld.long 0x00 7. "DAT0STS,DAT0 Pin Status Of Current Selected SD Port (Read Only)\nThis bit is the DAT0 pin status of current selected SD port" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "CRCSTS,CRC Status Value Of Data-Out Transfer (Read Only)\nSD host will record CRC status of data-out transfer" "?,?,2: Positive CRC status,?,?,5: Negative CRC status,?,7: SD card programming error occurs"
|
|
rbitfld.long 0x00 3. "CRC16,CRC16 Check Status Of Data-In Transfer (Read Only)\nSD host will check CRC16 correctness after data-in transfer.\n" "0: Fault,1: OK"
|
|
newline
|
|
rbitfld.long 0x00 2. "CRC7,CRC7 Check Status (Read Only)\nSD host will check CRC7 correctness during each response in" "0: Fault,1: OK"
|
|
rbitfld.long 0x00 1. "CRCIF,CRC7 CRC16 And CRC Status Error Interrupt Flag (Read Only)\nThis bit indicates that SD host has occurred CRC error during response in data-in or data-out (CRC status error) transfer" "0: No CRC error is occurred,1: CRC error is occurred"
|
|
newline
|
|
rbitfld.long 0x00 0. "BLKDIF,Block Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that SD host has finished all data-in or data-out block transfer" "0: Not finished yet,1: Done"
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SDH_RESP0,SD Receiving Response Token Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "RESPTK0,SD Receiving Response Token 0\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set"
|
|
rgroup.long 0x834++0x03
|
|
line.long 0x00 "SDH_RESP1,SD Receiving Response Token Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESPTK1,SD Receiving Response Token 1\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set"
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SDH_BLEN,SD Block Length Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "BLKLEN,SD BLOCK LENGTH In Byte Unit\nAn 11-bit value specifies the SD transfer byte count of a block"
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "SDH_TOUT,SD Response/Data-in Time-out Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TOUT,SD Response/Data-In Time-Out Value\nA 24-bit value specifies the time-out counts of response and data input"
|
|
tree.end
|
|
tree "SPI"
|
|
repeat 4. (list 0. 1. 2. 3.) (list ad:0x40060000 ad:0x40061000 ad:0x40062000 ad:0x40063000)
|
|
tree "SPI$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPI_CTL,SPI Control Register"
|
|
bitfld.long 0x00 22. "QUADIOEN,Quad I/O Mode Enable Bit\n" "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
|
|
bitfld.long 0x00 21. "DUALIOEN,Dual I/O Mode Enable Bit\n" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "QDIODIR,Quad Or Dual I/O Mode Direction Control\n" "0: Quad or Dual Input mode,1: Quad or Dual Output mode"
|
|
bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote:\nByte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits.\nByte Reorder function is not supported when the Quad or Dual I/O mode is enabled" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "SLAVE,Slave Mode Enable Bit\n" "0: Master mode,1: Slave mode"
|
|
bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit\n" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "TWOBIT,2-Bit Mode Enable Bit\nNote: When 2-bit mode is enabled the first serial transmitted bit data is from the first FIFO buffer data and the 2nd serial transmitted bit data is from the second FIFO buffer data" "0: 2-bit mode Disabled,1: 2-bit mode Enabled"
|
|
bitfld.long 0x00 13. "LSB,Send LSB First\n" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
|
|
newline
|
|
bitfld.long 0x00 8.--12. "DWIDTH,Data Transmit Bit Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 3. "CLKPOL,Clock Polarity\n" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
|
|
bitfld.long 0x00 2. "TXNEG,Transmit On Negative Edge\n" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
|
|
newline
|
|
bitfld.long 0x00 1. "RXNEG,Receive On Negative Edge\n" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
|
|
bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is a data in the FIFO buffer after this is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPI_CLKDIV,SPI Clock Divider Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIVIDER,Clock Divider Register \nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI master"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SPI_SSCTL,SPI Slave Select Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SLVTOCNT,Slave Mode Time-Out Period \nIn Slave mode these bits indicate the time-out period when there is bus clock input during slave select active"
|
|
bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit \n" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit \n" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
|
|
bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit\n" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\n" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
|
|
bitfld.long 0x00 6. "SLVTORST,Slave Mode Time-Out Reset Control\n" "0: When Slave mode time-out event occurs the TX..,1: When Slave mode time-out event occurs the TX.."
|
|
newline
|
|
bitfld.long 0x00 5. "SLVTOIEN,Slave Mode Time-Out Interrupt Enable Bit\n" "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
|
|
bitfld.long 0x00 4. "SLV3WIRE,Slave 3-Wire Mode Enable Bit\nIn Slave 3-wire mode the SPI controller can work with 3-wire interface including SPIn_CLK SPIn_MISO and SPIn_MOSI pins.\n" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
|
|
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)\n" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIn_SS).\n" "0: The slave selection signal SPIn_SS is active..,1: The slave selection signal SPIn_SS is active.."
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0 \n" "0: set the SPIn_SS line to inactive state.\nKeep..,1: set the SPIn_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPI_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset\n" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit\n" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "SPI_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nIn Slave mode when TX underflow event occurs this interrupt flag will be set to 1.\n" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\n" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit\n" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-Out Interrupt Enable Bit (Slave Only)\n" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit\n" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit\n" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If there is slave receive time-out event the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset\nNote: If there is slave receive time-out event the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "SPI_STATUS,SPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 23. "TXRXRST,TX Or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)\n" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: The SPI controller is disabled,1: The SPI controller is enabled"
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bitfld.long 0x00 12. "RXTOIF,Receive Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: Receive FIFO does not over run,1: Receive FIFO over run"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)\n" "0: The valid data count within the RX FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)\n" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurs"
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurs"
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bitfld.long 0x00 5. "SLVTOIF,Slave Time-Out Interrupt Flag\nWhen the slave select is active and the value of SLVTOCNT is not 0 as the bus clock is detected the slave time-out counter in SPI controller logic will be started" "0: Slave time-out is not active,1: Slave time-out is active"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt be cleared or..,1: Slave select inactive interrupt event occurrs"
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newline
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt be cleared or..,1: Slave select active interrupt event occurrs"
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
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newline
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)\n" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x03
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line.long 0x00 "SPI_TX,SPI Data Transmit Register"
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer"
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rgroup.long 0x30++0x03
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line.long 0x00 "SPI_RX,SPI Data Receive Register"
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThere are 8-level FIFO buffers in this controller"
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tree.end
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repeat.end
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tree.end
|
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tree "SYS"
|
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base ad:0x40000000
|
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rgroup.long 0x00++0x03
|
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line.long 0x00 "SYS_PDID,Part Device Identification Number Register"
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hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number\nThis register reflects device part number code"
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group.long 0x04++0x03
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line.long 0x00 "SYS_RSTSTS,System Reset Source Register"
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bitfld.long 0x00 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).\nNote: Write to clear this bit to 0" "0: No reset from CPU,1: The Cortex-M4 Core and FMC are reset by.."
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bitfld.long 0x00 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the Reset Signal from the Cortex-M4 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from Cortex-M4,1: The Cortex-M4 had issued the reset signal to.."
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bitfld.long 0x00 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from BOD,1: The BOD had issued the reset signal to reset.."
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bitfld.long 0x00 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
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bitfld.long 0x00 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the Reset Signal from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote1: Write 1 to clear this bit to 0.\nNote2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is.." "0: No reset from watchdog timer or window..,1: The watchdog timer or window watchdog timer.."
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bitfld.long 0x00 1. "PINRF,nRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to.."
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bitfld.long 0x00 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued.."
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group.long 0x08++0x03
|
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line.long 0x00 "SYS_IPRST0,Peripheral Controller Reset Control Register 1"
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bitfld.long 0x00 12. "CRPTRST,CRYPTO Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRYPTO controller" "0: CRYPTO controller normal operation,1: CRYPTO controller reset"
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bitfld.long 0x00 8. "CAPRST,Image Capture Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CAP controller" "0: CAP controller normal operation,1: CAP controller reset"
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newline
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bitfld.long 0x00 7. "CRCRST,CRC Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRC controller" "0: CRC controller normal operation,1: CRC controller reset"
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bitfld.long 0x00 6. "SDHRST,SD HOST Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the SD HOST controller" "0: SD HOST controller normal operation,1: SD HOST controller reset"
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bitfld.long 0x00 5. "EMACRST,EMAC Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the EMAC controller" "0: EMAC controller normal operation,1: EMAC controller reset"
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bitfld.long 0x00 4. "USBHRST,USBH Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the HSB HOST controller" "0: USBH controller normal operation,1: USBH controller reset"
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newline
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bitfld.long 0x00 3. "EBIRST,EBI Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the EBI" "0: EBI controller normal operation,1: EBI controller reset"
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bitfld.long 0x00 2. "PDMARST,PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA" "0: PDMA controller normal operation,1: PDMA controller reset"
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newline
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bitfld.long 0x00 1. "CPURST,Processor Core One-Shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles\nThis bit is a write protected bit It means.." "0: Processor core normal operation,1: Processor core one-shot reset"
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bitfld.long 0x00 0. "CHIPRST,Chip One-Shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the chip.." "0: Chip normal operation,1: Chip one shot reset"
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group.long 0x0C++0x03
|
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line.long 0x00 "SYS_IPRST1,Peripheral Controller Reset Control Register 2"
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bitfld.long 0x00 31. "PS2RST,PS/2 Controller Reset\n" "0: PS/2 controller normal operation,1: PS/2 controller reset"
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bitfld.long 0x00 30. "I2S1RST,I2S1 Controller Reset\n" "0: I2S1 controller normal operation,1: I2S1 controller reset"
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newline
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bitfld.long 0x00 29. "I2SRST,I2S Controller Reset\n" "0: I2S controller normal operation,1: I2S controller reset"
|
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bitfld.long 0x00 28. "EADCRST,ADC Controller Reset\n" "0: ADC controller normal operation,1: ADC controller reset"
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newline
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bitfld.long 0x00 27. "USBDRST,USB Device Controller Reset\n" "0: USB device controller normal operation,1: USB device controller reset"
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bitfld.long 0x00 25. "CAN1RST,CAN1 Controller Reset\n" "0: CAN1 controller normal operation,1: CAN1 controller reset"
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newline
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bitfld.long 0x00 24. "CAN0RST,CAN0 Controller Reset\n" "0: CAN0 controller normal operation,1: CAN0 controller reset"
|
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bitfld.long 0x00 21. "UART5RST,UART2 Controller Reset \n" "0: UART5 controller normal operation,1: UART5 controller reset"
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newline
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bitfld.long 0x00 20. "UART4RST,UART4 Controller Reset \n" "0: UART4 controller normal operation,1: UART4 controller reset"
|
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bitfld.long 0x00 19. "UART3RST,UART3 Controller Reset \n" "0: UART3 controller normal operation,1: UART3 controller reset"
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newline
|
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bitfld.long 0x00 18. "UART2RST,UART2 Controller Reset \n" "0: UART2 controller normal operation,1: UART2 controller reset"
|
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bitfld.long 0x00 17. "UART1RST,UART1 Controller Reset\n" "0: UART1 controller normal operation,1: UART1 controller reset"
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newline
|
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bitfld.long 0x00 16. "UART0RST,UART0 Controller Reset\n" "0: UART0 controller normal operation,1: UART0 controller reset"
|
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bitfld.long 0x00 15. "SPI3RST,SPI3 Controller Reset \n" "0: SPI3 controller normal operation,1: SPI3 controller reset"
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newline
|
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bitfld.long 0x00 14. "SPI2RST,SPI2 Controller Reset \n" "0: SPI2 controller normal operation,1: SPI2 controller reset"
|
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bitfld.long 0x00 13. "SPI1RST,SPI1 Controller Reset\n" "0: SPI1 controller normal operation,1: SPI1 controller reset"
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newline
|
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bitfld.long 0x00 12. "SPI0RST,SPI0 Controller Reset\n" "0: SPI0 controller normal operation,1: SPI0 controller reset"
|
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bitfld.long 0x00 9. "I2C1RST,I2C1 Controller Reset\n" "0: I2C1 controller normal operation,1: I2C1 controller reset"
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newline
|
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bitfld.long 0x00 8. "I2C0RST,I2C0 Controller Reset\n" "0: I2C0 controller normal operation,1: I2C0 controller reset"
|
|
bitfld.long 0x00 7. "ACMPRST,Analog Comparator Controller Reset\n" "0: Analog Comparator controller normal operation,1: Analog Comparator controller reset"
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newline
|
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bitfld.long 0x00 5. "TMR3RST,Timer3 Controller Reset\n" "0: Timer3 controller normal operation,1: Timer3 controller reset"
|
|
bitfld.long 0x00 4. "TMR2RST,Timer2 Controller Reset\n" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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newline
|
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bitfld.long 0x00 3. "TMR1RST,Timer1 Controller Reset\n" "0: Timer1 controller normal operation,1: Timer1 controller reset"
|
|
bitfld.long 0x00 2. "TMR0RST,Timer0 Controller Reset\n" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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newline
|
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bitfld.long 0x00 1. "GPIORST,GPIO Controller Reset\n" "0: GPIO controller normal operation,1: GPIO controller reset"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYS_IPRST2,Peripheral Controller Reset Control Register 3"
|
|
bitfld.long 0x00 23. "QEI1RST,QEI1 Controller Reset\n" "0: QEI1 controller normal operation,1: QEI1 controller reset"
|
|
bitfld.long 0x00 22. "QEI0RST,QEI0 Controller Reset\n" "0: QEI0 controller normal operation,1: QEI0 controller reset"
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newline
|
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bitfld.long 0x00 17. "PWM1RST,PWM1 Controller Reset\n" "0: PWM1 controller normal operation,1: PWM1 controller reset"
|
|
bitfld.long 0x00 16. "PWM0RST,PWM0 Controller Reset\n" "0: PWM0 controller normal operation,1: PWM0 controller reset"
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newline
|
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bitfld.long 0x00 8. "I2C4RST,I2C4 Controller Reset\n" "0: I2C4 controller normal operation,1: I2C4 controller reset"
|
|
bitfld.long 0x00 5. "SC5RST,SC5 Controller Reset\n" "0: SC5 controller normal operation,1: SC5 controller reset"
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newline
|
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bitfld.long 0x00 4. "SC4RST,SC4 Controller Reset\n" "0: SC4 controller normal operation,1: SC4 controller reset"
|
|
bitfld.long 0x00 3. "SC3RST,SC3 Controller Reset\n" "0: SC3 controller normal operation,1: SC3 controller reset"
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newline
|
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bitfld.long 0x00 2. "SC2RST,SC2 Controller Reset\n" "0: SC2 controller normal operation,1: SC2 controller reset"
|
|
bitfld.long 0x00 1. "SC1RST,SC1 Controller Reset\n" "0: SC1 controller normal operation,1: SC1 controller reset"
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newline
|
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bitfld.long 0x00 0. "SC0RST,SC0 Controller Reset\n" "0: SC0 controller normal operation,1: SC0 controller reset"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SYS_BODCTL,Brown-out Detector Control Register"
|
|
bitfld.long 0x00 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled - After.."
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|
bitfld.long 0x00 6. "BODOUT,Brown-Out Detector Output Status\n" "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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newline
|
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bitfld.long 0x00 5. "BODLPM,Brown-Out Detector Low Power Mode (Write Protect)\nThe BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response.\nThis bit is the protected bit which means programming this needs to.." "0: BOD operate in normal mode (default),1: BOD Low Power mode Enabled"
|
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bitfld.long 0x00 4. "BODINTF,Brown-Out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.."
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newline
|
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bitfld.long 0x00 3. "BODRSTEN,Brown-Out Reset Enable Bit (Write Protect)\nWhile the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high) BOD will assert a signal to reset chip when the detected voltage is lower than the.." "0: Brown-out INTERRUPT function Enabled,1: Brown-out RESET function Enabled"
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bitfld.long 0x00 1.--2. "BODVL,Brown-Out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register config0 bit[22:21]\nRelationship between BODVL and Brown-out voltage listed below:\nThis bit is the protected.." "0: 2.2V,1: 2.7V,2: 3.7V,3: 4.5V"
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newline
|
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bitfld.long 0x00 0. "BODEN,Brown-Out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register config0 bit[23]\nThis bit is the protected bit which means programming this needs to write 59h 16h 88h to address 0x4000_0100.." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SYS_TEMPCTL,Temperature Sensor Control Register"
|
|
bitfld.long 0x00 0. "VTEMPEN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nAfter this bit is set to 1 the value of temperature sensor output can be obtained from ADC conversion result" "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SYS_VCID,Hardware Version Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "VCID,Hardware Version Control (Ready Only)\nThese registers repress hardware version"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SYS_PORCTL,Power-On-reset Controller Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "POROFF,Power-On-Reset Enable Bit (Write Protect)\nWhen power on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SYS_VREFCTL,ADC VREF Control Register"
|
|
bitfld.long 0x00 9. "PWMSYNCMODE,PWM SYNC MODE (Write Protect)\n" "0: PWM SYNC MODE Disabled PWM engine clock can..,1: PWM SYNC MODE Enabled PWM engine clock is.."
|
|
bitfld.long 0x00 8. "ADCMODESEL,ADC IP Selection (Write Protect)\n" "0: ADC mode,1: E ADC mode"
|
|
newline
|
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bitfld.long 0x00 0.--4. "VREFCTL,VREF Control Bits (Write Protect)\n" "?,?,?,3: VREF is internal 2.65V,?,?,?,7: VREF is internal 2.048V,?,?,?,11: VREF is internal 3.072V,?,?,?,15: VREF is internal 4.096V,16: VREF is from AVDD,?..."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SYS_USBPHY,USB PHY Control Register"
|
|
bitfld.long 0x00 8. "LDO33EN,LDO33 Enable Bit (Write Protect) \n" "0: USB LDO33 Disabled,1: USB LDO33 Enabled"
|
|
bitfld.long 0x00 0.--1. "USBROLE,USB Role Configuration (Write Protect)\nUSB role configuration can be from ROMMAP or software setting if software setting option controlled by ROMMAP is enabled.\n" "0: Standard USB device,1: Standard USB host,2: ID dependent device,3: On-The-Go device"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SYS_GPA_MFPL,Port A Low Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PA7MFP,PA.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PA6MFP,PA.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PA5MFP,PA.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PA4MFP,PA.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PA3MFP,PA.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PA2MFP,PA.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PA1MFP,PA.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PA0MFP,PA.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SYS_GPA_MFPH,Port A High Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PA15MFP,PA.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PA14MFP,PA.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PA13MFP,PA.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PA12MFP,PA.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PA11MFP,PA.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PA10MFP,PA.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PA9MFP,PA.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PA8MFP,PA.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SYS_GPB_MFPL,Port B Low Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PB7MFP,PB.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PB6MFP,PB.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PB5MFP,PB.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PB4MFP,PB.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PB3MFP,PB.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PB2MFP,PB.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PB1MFP,PB.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PB0MFP,PB.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SYS_GPB_MFPH,Port B High Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PB15MFP,PB.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PB14MFP,PB.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PB13MFP,PB.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PB12MFP,PB.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PB11MFP,PB.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PB10MFP,PB.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PB9MFP,PB.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PB8MFP,PB.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SYS_GPC_MFPL,Port C Low Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PC7MFP,PC.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PC6MFP,PC.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PC5MFP,PC.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PC4MFP,PC.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PC3MFP,PC.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PC2MFP,PC.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PC1MFP,PC.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC0MFP,PC.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SYS_GPC_MFPH,Port C High Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PC15MFP,PC.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PC14MFP,PC.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PC13MFP,PC.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PC12MFP,PC.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PC11MFP,PC.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PC10MFP,PC.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PC9MFP,PC.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PC8MFP,PC.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SYS_GPD_MFPL,Port D Low Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PD7MFP,PD.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PD6MFP,PD.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PD5MFP,PD.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PD4MFP,PD.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PD3MFP,PD.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PD2MFP,PD.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PD1MFP,PD.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PD0MFP,PD.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SYS_GPD_MFPH,Port D High Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PD15MFP,PD.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PD14MFP,PD.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PD13MFP,PD.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PD12MFP,PD.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PD11MFP,PD.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PD10MFP,PD.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PD9MFP,PD.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PD8MFP,PD.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SYS_GPE_MFPL,Port E Low Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PE7MFP,PE.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PE6MFP,PE.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PE5MFP,PE.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PE4MFP,PE.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PE3MFP,PE.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PE2MFP,PE.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PE1MFP,PE.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PE0MFP,PE.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SYS_GPE_MFPH,Port E High Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PE15MFP,PE.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PE14MFP,PE.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PE13MFP,PE.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PE12MFP,PE.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PE11MFP,PE.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PE10MFP,PE.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PE9MFP,PE.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PE8MFP,PE.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYS_GPF_MFPL,Port F Low Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PF7MFP,PF.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PF6MFP,PF.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PF5MFP,PF.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PF4MFP,PF.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PF3MFP,PF.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PF2MFP,PF.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PF1MFP,PF.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PF0MFP,PF.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SYS_GPF_MFPH,Port F High Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PF15MFP,PF.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PF14MFP,PF.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PF13MFP,PF.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PF12MFP,PF.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PF11MFP,PF.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PF10MFP,PF.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PF9MFP,PF.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "PF8MFP,PF.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SYS_GPG_MFPL,Port G Low Byte Multi-function Control Register"
|
|
bitfld.long 0x00 28.--31. "PG7MFP,PG.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "PG6MFP,PG.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "PG5MFP,PG.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "PG4MFP,PG.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. "PG3MFP,PG.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PG2MFP,PG.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "PG1MFP,PG.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PG0MFP,PG.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x64++0x03
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line.long 0x00 "SYS_GPG_MFPH,Port G High Byte Multi-function Control Register"
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bitfld.long 0x00 28.--31. "PG15MFP,PG.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PG14MFP,PG.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PG13MFP,PG.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PG12MFP,PG.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PG11MFP,PG.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PG10MFP,PG.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PG9MFP,PG.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PG8MFP,PG.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x68++0x03
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line.long 0x00 "SYS_GPH_MFPL,Port H Low Byte Multi-function Control Register"
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bitfld.long 0x00 28.--31. "PH7MFP,PH.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PH6MFP,PH.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PH5MFP,PH.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PH4MFP,PH.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PH3MFP,PH.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PH2MFP,PH.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PH1MFP,PH.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PH0MFP,PH.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x6C++0x03
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line.long 0x00 "SYS_GPH_MFPH,Port H High Byte Multi-function Control Register"
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bitfld.long 0x00 28.--31. "PH15MFP,PH.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PH14MFP,PH.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PH13MFP,PH.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PH12MFP,PH.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PH11MFP,PH.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PH10MFP,PH.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PH9MFP,PH.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PH8MFP,PH.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x70++0x03
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line.long 0x00 "SYS_GPI_MFPL,Port I Low Byte Multi-function Control Register"
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bitfld.long 0x00 28.--31. "PI7MFP,PI.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PI6MFP,PI.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PI5MFP,PI.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PI4MFP,PI.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PI3MFP,PI.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PI2MFP,PI.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PI1MFP,PI.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PI0MFP,PI.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x74++0x03
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line.long 0x00 "SYS_GPI_MFPH,Port I High Byte Multi-function Control Register"
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bitfld.long 0x00 28.--31. "PI15MFP,PI.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PI14MFP,PI.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 20.--23. "PI13MFP,PI.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PI12MFP,PI.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PI11MFP,PI.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PI10MFP,PI.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PI9MFP,PI.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PI8MFP,PI.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xC0++0x03
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line.long 0x00 "SYS_SRAM_INTCTL,SRAM Failed Interrupt Enable Control Register"
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bitfld.long 0x00 0. "PERRIEN,SRAM Parity Check Fail Interrupt Enable Bit\n" "0: SRAMF INT Disabled,1: SRAMF INT Enabled when SRAM fail flag"
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group.long 0xC4++0x03
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line.long 0x00 "SYS_SRAM_STATUS,SRAM Parity Check Error Flag"
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bitfld.long 0x00 1. "PERRIF1,SRAM Parity Check Fail Flag\n" "0: 2nd SRAM fail,1: 2nd SRAM Fail"
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bitfld.long 0x00 0. "PERRIF0,SRAM Parity Check Fail Flag\n" "0: No first 1 SRAM fail,1: First SRAM Fail"
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rgroup.long 0xC8++0x03
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line.long 0x00 "SYS_SRAM0_ERRADDR,SRAM Parity Check Error First Address1"
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hexmask.long 0x00 0.--31. 1. "PERRADDR,First SRAM Parity Check Fail Address\nThis register shows the first system SRAM parity error byte address"
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rgroup.long 0xCC++0x03
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line.long 0x00 "SYS_SRAM1_ERRADDR,SRAM Parity Check Error First Address2"
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hexmask.long 0x00 0.--31. 1. "PERRADDR,Second SRAM Parity Check Fail Address\nThis register shows the second system SRAM parity error byte address"
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group.long 0xF0++0x03
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line.long 0x00 "SYS_IRCTCTL,IRC Trim Control Register"
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bitfld.long 0x00 8. "CESTOPEN,Clock Error Stop Enable Bit\n" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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bitfld.long 0x00 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64,1: Trim retry count limitation is 128,2: Trim retry count limitation is 256,3: Trim retry count limitation is 512"
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newline
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bitfld.long 0x00 4.--5. "LOOPSEL,Trim Calculation Loop\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nFor example if CALCLOOP is set as 00 auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.."
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bitfld.long 0x00 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of HIRC auto trim.\nIf no any target frequency is selected (FREQSEL is 00) the HIRC auto trim function is disabled.\nDuring auto trim operation if clock error detected with.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC..,2: Enable HIRC auto trim function and trim HIRC..,3: Reserved"
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group.long 0xF4++0x03
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line.long 0x00 "SYS_IRCTIEN,IRC Trim Interrupt Enable Control Register"
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bitfld.long 0x00 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF is set during auto trim operation an interrupt will be triggered to.." "0: Disable CLKERRIF status to trigger an..,1: Enable CLKERRIF status to trigger an.."
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bitfld.long 0x00 1. "TFAILIEN,Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL.\nIf this bit is high and TFAILIF is.." "0: Disable TFAILIF status to trigger an..,1: Enable TFAILIF status to trigger an interrupt.."
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group.long 0xF8++0x03
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line.long 0x00 "SYS_IRCTISTS,IRC Trim Interrupt Status Register"
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bitfld.long 0x00 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of external 32.768 kHz low-speed crystal or HIRC is shift larger to unreasonable value this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1 the.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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bitfld.long 0x00 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked" "0: Trim value update limitation count does not..,1: Trim value update limitation count reached.."
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newline
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bitfld.long 0x00 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt" "0,1"
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group.long 0x100++0x03
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line.long 0x00 "SYS_REGLCTL,Register Write-protection Control Register"
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hexmask.long.byte 0x00 0.--7. 1. "REGLCTL,Register Write-Protection Code (Write Only)\nSome registers have write-protection function"
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tree.end
|
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tree "TIMER"
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tree "TIMER01"
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base ad:0x40050000
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group.long 0x00++0x03
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line.long 0x00 "TIMER0_CTL,Timer0 Control and Status Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x00 29. "INTEN,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Operation Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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newline
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bitfld.long 0x00 26. "RSTCNT,Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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newline
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bitfld.long 0x00 24. "EXTCNTEN,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-Up Enable\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer.."
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newline
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bitfld.long 0x00 22. "TOGDIS2,Toggle Output 2 Disable\nSetting this bit will disable the Toggle output pins group 2.\nNote1: If both TOUT1 (group 1 pins) and TOUT2 (group 2 pins) function are enabled toggle output signal is generated only from TOUT1 pins.\nNote2: The group2.." "0: Toggle output pins group 2 Enabled,1: Toggle output pins group 2 Disabled"
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bitfld.long 0x00 21. "TOGDIS1,Toggle Output 1 Disable\nSetting this bit will disable the Toggle output pins group 1.\nNote: The group1 pins are PB4 PB1 PC6 and PC1" "0: Toggle output pins group 1 Enabled,1: Toggle output pins group 1 Disabled"
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newline
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bitfld.long 0x00 16. "CNTDATEN,Data Load Enable\nWhen this bit is set timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
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hexmask.long.byte 0x00 0.--7. 1. "PSC,PSC Counter\n"
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group.long 0x04++0x03
|
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line.long 0x00 "TIMER0_CMP,Timer0 Compare Register"
|
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x08++0x03
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line.long 0x00 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TIMERx_CNT value matches the CMPDAT value"
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rgroup.long 0x0C++0x03
|
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line.long 0x00 "TIMER0_CNT,Timer0 Data Register"
|
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nUser can read CNT for getting current 24- bit event counter value if TIMERx_CTL[24] is 1"
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rgroup.long 0x10++0x03
|
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line.long 0x00 "TIMER0_CAP,Timer0 Capture Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x14++0x03
|
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line.long 0x00 "TIMER0_EXTCTL,Timer0 External Control Register"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-Bounce Enable\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-Bounce Enable\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x00 5. "CAPIEN,Timer External Interrupt Enable\n" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
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bitfld.long 0x00 4. "CAPFUNCS,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT (x= 0~3) pin is using..,1: Transition on TMx_EXT (x= 0~3) pin is using.."
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newline
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bitfld.long 0x00 3. "CAPEN,Timer External Pin Enable \nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin" "0: CAPFUNCS function of TMx_EXT (x= 0~3) pin..,1: CAPFUNCS function of TMx_EXT (x= 0~3) pin is.."
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bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT (x= 0~3) pin..,1: A 0 to 1 transition on TMx_EXT (x= 0~3) pin..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
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newline
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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|
group.long 0x18++0x03
|
|
line.long 0x00 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
|
|
bitfld.long 0x00 0. "CAPIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x20++0x03
|
|
line.long 0x00 "TIMER1_CTL,Timer1 Control and Status Register"
|
|
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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|
bitfld.long 0x00 30. "CNTEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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newline
|
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bitfld.long 0x00 29. "INTEN,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Operation Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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newline
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bitfld.long 0x00 26. "RSTCNT,Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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newline
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bitfld.long 0x00 24. "EXTCNTEN,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-Up Enable\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer.."
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newline
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bitfld.long 0x00 22. "TOGDIS2,Toggle Output 2 Disable\nSetting this bit will disable the Toggle output pins group 2.\nNote1: If both TOUT1 (group 1 pins) and TOUT2 (group 2 pins) function are enabled toggle output signal is generated only from TOUT1 pins.\nNote2: The group2.." "0: Toggle output pins group 2 Enabled,1: Toggle output pins group 2 Disabled"
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bitfld.long 0x00 21. "TOGDIS1,Toggle Output 1 Disable\nSetting this bit will disable the Toggle output pins group 1.\nNote: The group1 pins are PB4 PB1 PC6 and PC1" "0: Toggle output pins group 1 Enabled,1: Toggle output pins group 1 Disabled"
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newline
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bitfld.long 0x00 16. "CNTDATEN,Data Load Enable\nWhen this bit is set timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
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hexmask.long.byte 0x00 0.--7. 1. "PSC,PSC Counter\n"
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group.long 0x24++0x03
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line.long 0x00 "TIMER1_CMP,Timer1 Compare Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x28++0x03
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line.long 0x00 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TIMERx_CNT value matches the CMPDAT value"
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group.long 0x2C++0x03
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line.long 0x00 "TIMER1_CNT,Timer1 Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nUser can read CNT for getting current 24- bit event counter value if TIMERx_CTL[24] is 1"
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group.long 0x30++0x03
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line.long 0x00 "TIMER1_CAP,Timer1 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x34++0x03
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line.long 0x00 "TIMER1_EXTCTL,Timer1 External Control Register"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-Bounce Enable\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-Bounce Enable\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x00 5. "CAPIEN,Timer External Interrupt Enable\n" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
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bitfld.long 0x00 4. "CAPFUNCS,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT (x= 0~3) pin is using..,1: Transition on TMx_EXT (x= 0~3) pin is using.."
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newline
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bitfld.long 0x00 3. "CAPEN,Timer External Pin Enable \nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin" "0: CAPFUNCS function of TMx_EXT (x= 0~3) pin..,1: CAPFUNCS function of TMx_EXT (x= 0~3) pin is.."
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bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT (x= 0~3) pin..,1: A 0 to 1 transition on TMx_EXT (x= 0~3) pin..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
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newline
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x38++0x03
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line.long 0x00 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
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tree.end
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tree "TIMER23"
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base ad:0x40051000
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group.long 0x00++0x03
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line.long 0x00 "TIMER2_CTL,Timer2 Control and Status Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x00 29. "INTEN,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Operation Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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newline
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bitfld.long 0x00 26. "RSTCNT,Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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newline
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bitfld.long 0x00 24. "EXTCNTEN,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-Up Enable\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer.."
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newline
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bitfld.long 0x00 22. "TOGDIS2,Toggle Output 2 Disable\nSetting this bit will disable the Toggle output pins group 2.\nNote1: If both TOUT1 (group 1 pins) and TOUT2 (group 2 pins) function are enabled toggle output signal is generated only from TOUT1 pins.\nNote2: The group2.." "0: Toggle output pins group 2 Enabled,1: Toggle output pins group 2 Disabled"
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bitfld.long 0x00 21. "TOGDIS1,Toggle Output 1 Disable\nSetting this bit will disable the Toggle output pins group 1.\nNote: The group1 pins are PB4 PB1 PC6 and PC1" "0: Toggle output pins group 1 Enabled,1: Toggle output pins group 1 Disabled"
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newline
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bitfld.long 0x00 16. "CNTDATEN,Data Load Enable\nWhen this bit is set timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
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hexmask.long.byte 0x00 0.--7. 1. "PSC,PSC Counter\n"
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group.long 0x04++0x03
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line.long 0x00 "TIMER2_CMP,Timer2 Compare Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x08++0x03
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line.long 0x00 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TIMERx_CNT value matches the CMPDAT value"
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rgroup.long 0x0C++0x03
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line.long 0x00 "TIMER2_CNT,Timer2 Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nUser can read CNT for getting current 24- bit event counter value if TIMERx_CTL[24] is 1"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER2_CAP,Timer2 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER2_EXTCTL,Timer2 External Control Register"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-Bounce Enable\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-Bounce Enable\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x00 5. "CAPIEN,Timer External Interrupt Enable\n" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
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bitfld.long 0x00 4. "CAPFUNCS,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT (x= 0~3) pin is using..,1: Transition on TMx_EXT (x= 0~3) pin is using.."
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newline
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bitfld.long 0x00 3. "CAPEN,Timer External Pin Enable \nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin" "0: CAPFUNCS function of TMx_EXT (x= 0~3) pin..,1: CAPFUNCS function of TMx_EXT (x= 0~3) pin is.."
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bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT (x= 0~3) pin..,1: A 0 to 1 transition on TMx_EXT (x= 0~3) pin..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
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newline
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x18++0x03
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line.long 0x00 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x20++0x03
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line.long 0x00 "TIMER3_CTL,Timer3 Control and Status Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x00 29. "INTEN,Interrupt Enable Bit\nIf this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Operation Mode\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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newline
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bitfld.long 0x00 26. "RSTCNT,Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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newline
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bitfld.long 0x00 24. "EXTCNTEN,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-Up Enable\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer.."
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newline
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bitfld.long 0x00 22. "TOGDIS2,Toggle Output 2 Disable\nSetting this bit will disable the Toggle output pins group 2.\nNote1: If both TOUT1 (group 1 pins) and TOUT2 (group 2 pins) function are enabled toggle output signal is generated only from TOUT1 pins.\nNote2: The group2.." "0: Toggle output pins group 2 Enabled,1: Toggle output pins group 2 Disabled"
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bitfld.long 0x00 21. "TOGDIS1,Toggle Output 1 Disable\nSetting this bit will disable the Toggle output pins group 1.\nNote: The group1 pins are PB4 PB1 PC6 and PC1" "0: Toggle output pins group 1 Enabled,1: Toggle output pins group 1 Disabled"
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newline
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bitfld.long 0x00 16. "CNTDATEN,Data Load Enable\nWhen this bit is set timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
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hexmask.long.byte 0x00 0.--7. 1. "PSC,PSC Counter\n"
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group.long 0x24++0x03
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line.long 0x00 "TIMER3_CMP,Timer3 Compare Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x28++0x03
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line.long 0x00 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TIMERx_CNT value matches the CMPDAT value"
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group.long 0x2C++0x03
|
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line.long 0x00 "TIMER3_CNT,Timer3 Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nUser can read CNT for getting current 24- bit event counter value if TIMERx_CTL[24] is 1"
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group.long 0x30++0x03
|
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line.long 0x00 "TIMER3_CAP,Timer3 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x34++0x03
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line.long 0x00 "TIMER3_EXTCTL,Timer3 External Control Register"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-Bounce Enable\nIf this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-Bounce Enable\nIf this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x00 5. "CAPIEN,Timer External Interrupt Enable\n" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
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bitfld.long 0x00 4. "CAPFUNCS,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT (x= 0~3) pin is using..,1: Transition on TMx_EXT (x= 0~3) pin is using.."
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newline
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bitfld.long 0x00 3. "CAPEN,Timer External Pin Enable \nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin" "0: CAPFUNCS function of TMx_EXT (x= 0~3) pin..,1: CAPFUNCS function of TMx_EXT (x= 0~3) pin is.."
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bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT (x= 0~3) pin..,1: A 0 to 1 transition on TMx_EXT (x= 0~3) pin..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
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newline
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x38++0x03
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line.long 0x00 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
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tree.end
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tree.end
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tree "UART"
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repeat 6. (list 0. 1. 2. 3. 4. 5.) (list ad:0x40070000 ad:0x40071000 ad:0x40072000 ad:0x40073000 ad:0x40074000 ad:0x40075000)
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tree "UART$1"
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base $2
|
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group.long 0x00++0x03
|
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line.long 0x00 "UART_DAT,UARTx Receive / Transmit Buffer Register"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UARTx Interrupt Enable Register"
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bitfld.long 0x00 15. "RXPDMAEN,RX DMA Enable Bit\nThis bit can enable or disable RX DMA service.\n" "0: RX DMA Disabled,1: RX DMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX DMA Enable Bit\nThis bit can enable or disable TX DMA service.\n" "0: TX DMA Disabled,1: TX DMA Enabled"
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newline
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bitfld.long 0x00 13. "ATOCTSEN,CTS Auto Flow Control Enable Bit\nWhen CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)" "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,RTS Auto Flow Control Enable Bit\nWhen RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert RTS signal" "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
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newline
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bitfld.long 0x00 11. "TOCNTEN,Time-Out Counter Enable Bit\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN RX Break Field Detected Interrupt Enable Bit\nNote: This field is used for LIN function mode" "0: Lin bus RX break filed interrupt Disabled,1: Lin bus RX break filed interrupt Enabled"
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newline
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bitfld.long 0x00 6. "WKCTSIEN,UART Wake-Up Function Enable Bit\n" "0: UART wake-up function Disabled,1: UART wake-up function Enabled when the chip.."
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit\n" "0: INT_BUF_ERR Disabled,1: INT_BUF_ERR Enabled"
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newline
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bitfld.long 0x00 4. "RXTOIEN,RX Time-Out Interrupt Enable Bit\n" "0: NT_TOUT Disabled,1: INT_TOUT Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit\n" "0: INT_MODEM Disabled,1: INT_MODEM Enabled"
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newline
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit \n" "0: INT_RLS Disabled,1: INT_RLS Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit\n" "0: INT_THRE Disabled,1: INT_THRE Enabled"
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newline
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit\n" "0: INT_RDA Disabled,1: INT_RDA Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UARTx FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,RTS Trigger Level For Auto-Flow Control Use\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8. "RXOFF,Receiver Disable\nThe receiver is disabled or not.\nNote: This field is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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newline
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles" "0: No effect,1: Reset the TX internal state machine and.."
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newline
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared for at least 3 UART engine clock cycles" "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UARTx Line Control Register"
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bitfld.long 0x00 6. "BCB,Break Control\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0,1"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\n" "0: Stick parity Disabled,1: If bit 3 and 4 are logic 1 the parity bit is.."
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newline
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nThis bit is effective only when bit 3 (parity bit enable) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\n" "0: No parity bit,1: Parity bit is generated on each outgoing.."
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bitfld.long 0x00 2. "NSB,Number Of STOP Bit \nTwo STOP bit is generated when 6- 7- and 8-bit word length is selected" "0: One STOP bit is generated in the transmitted..,1: One and a half STOP bit is generated in the.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\n" "0,1,2,3"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UARTx Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,RTS Pin State (Read Only) \nThis bit is the output pin status of RTS" "0,1"
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bitfld.long 0x00 9. "RTSACTLV,RTS Trigger Level \nThis bit can change the RTS trigger level.\n" "0: Low level triggered,1: High level triggered"
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bitfld.long 0x00 1. "RTS,RTS (Request-To-Send) Signal \n" "0: Drive RTS pin to logic 1 (If the RTSACTLV set..,1: Drive RTS pin to logic 0 (If the RTSACTLV set.."
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UARTx Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,CTS Trigger Level \nThis bit can change the CTS trigger level.\n" "0: Low level triggered,1: High level triggered"
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rbitfld.long 0x00 4. "CTSSTS,CTS Pin Status (Read Only) \nThis bit is the pin status of CTS" "0,1"
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rbitfld.long 0x00 0. "CTSDETF,Detect CTS State Change Flag (Read Only) \nThis bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nSoftware can write 1 to clear this bit to 0" "0,1"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UARTx FIFO Status Register"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not.." "0,1"
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rbitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1" "0,1"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TXPTR is equal to 64/16(UART0/UART1~5) otherwise is cleared by hardware" "0,1"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0,1"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RXPTR is equal to 64/16(UART0/UART1~5) otherwise is cleared by hardware" "0,1"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0,1"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is the total time of start bit + data bits + parity + stop.." "0,1"
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rbitfld.long 0x00 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as a logic 0) and is reset whenever the CPU writes.." "0,1"
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rbitfld.long 0x00 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only but it can be cleared by writing '1' to it" "0,1"
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rbitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is read only but it can be cleared by writing '1' to it" "0,1"
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bitfld.long 0x00 2. "SCERR,Smart Card Over Error Retry Flag\nIt is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0]))\nNote1: This field is used for SC.." "0: No any transmitter re-transmits over or..,1: one of the transmitter re-transmits over.."
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rbitfld.long 0x00 0. "RXOVIF,RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 64/16 bytes of UART0/UART1 this bit will be set.\nNote: This bit is read only but it can be.." "0,1"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UARTx Interrupt Status Register"
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rbitfld.long 0x00 29. "HWBUFEINT,In DMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and HWBFERIF are both set to 1.\n" "0: No buffer error interrupt is generated in DMA..,1: The buffer error interrupt is generated in.."
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rbitfld.long 0x00 28. "HWTOINT,In DMA Mode Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and HWTOIF are both set to 1.\n" "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode"
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rbitfld.long 0x00 27. "HWMODINT,In DMA Mode MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEMIEN and HWMODIF are both set to 1.\n" "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,In DMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN and HWRLSIF are both set to 1.\n" "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode"
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rbitfld.long 0x00 21. "HWBUFEIF,In DMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set)" "0,1"
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rbitfld.long 0x00 20. "HWTOIF,In DMA Mode Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC" "0,1"
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rbitfld.long 0x00 19. "HWMODIF,In DMA Mode MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF" "0,1"
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rbitfld.long 0x00 18. "HWRLSIF,In DMA Mode Receive Line Status Flag (Read Only) \nThis bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set)" "0,1"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN and LINIF are both set to 1.\n" "0: No LIN RX Break interrupt is generated,1: LIN RX Break interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BERRIF are both set to 1.\n" "0: No buffer error interrupt is generated,1: The buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOCNTEN and RXTOIF are both set to 1.\n" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEMIEN and MODENIF are both set to 1.\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN and RLSIF are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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rbitfld.long 0x00 7. "LINIF,LIN Bus Flag (Read Only)\nNote: This bit is cleared when both SLVHDETF and LIN_BRDER_F and BITEF and LINS_IDPENR_F and SLVHEF are cleared" "0,1"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set)" "0,1"
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rbitfld.long 0x00 4. "RXTOIF,Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC" "0,1"
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rbitfld.long 0x00 3. "MODENIF,MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF" "0,1"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set)" "0,1"
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rbitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0,1"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set" "0,1"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UARTx Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.\n\nNote: The counter clock is baud rate clock"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-Out Interrupt Comparator\n"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UARTx Baud Rate Divisor Register"
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bitfld.long 0x00 29. "BAUDM1,Divider X Enable Bit\nRefer to the table below for more information.\nNote: In IrDA mode this bit must disable" "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1.."
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bitfld.long 0x00 28. "BAUDM0,Divider X Equal To 1\nRefer to the table below for more information" "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
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bitfld.long 0x00 24.--27. "EDIVM1,Divider X\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicated the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UARTx IrDA Control Register"
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bitfld.long 0x00 7. "FIXPULSE,Pulse width of TX is fixed 1.6us" "0,1"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal\n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal\n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit\n" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UARTx Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit \nThis bit is use to enable RS-485 address detection mode" "0: address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation (AUO) mode..,1: RS-485 Auto Direction Operation (AUO) mode.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection (AAD) Operation..,1: RS-485 Auto Address Detection (AAD) Operation.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation Mode (NMM)..,1: RS-485 Normal Multi-drop Operation Mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nThe LIN TX header can be break field or break and sync field or break sync and frame ID field depending on the setting HSEL register.\nNote: When transmitter header field (it may be break or break + sync or break +.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "LIN_BKFL,LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UARTx Function Select Register"
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bitfld.long 0x00 0.--2. "FUNCSEL,Function Select Enable Bit\n" "0: UART function,1: LIN function Enabled,2: IrDA function Enabled,3: RS-485 function Enabled,4: Smart-Card function Enabled,?..."
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group.long 0x34++0x03
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line.long 0x00 "UART_LINCTL,UARTx LIN Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "PID,This Field Contains The LIN Frame ID Value In LIN Function Mode The Frame ID Parity Can Be Generated By Software Or Hardware Depending On UART_LINCTL [IDPEN] \n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB.."
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bitfld.long 0x00 22.--23. "HSEL,LIN Header Selection\n" "0: LIN header includes break field,1: LIN header includes break field and sync field,2: LIN header includes break field sync field..,3: LIN header includes break field sync field.."
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bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to send header field" "0: LIN break/sync delimiter length is 1 bit time,?,2: The LIN break/sync delimiter length is 2 bit..,3: The LIN break/sync delimiter length is 4 bit.."
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bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UART_ALTCTL[3:0]) User can read/write it by setting LIN_BKFL (UART_ALTCTL[3:0]) or LIN_BKFL.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit\nNote: In LIN function mode when occur bit error hardware will generate an interrupt to CPU (INT_LIN) and the BITEF (UART_LINSTS[9]) flag will be asserted" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
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bitfld.long 0x00 11. "RXOFF," "0: Bit error detection function Disabled,1: Bit error detection Enabled"
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bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit\n" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit\n" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit \nThe LIN TX header can be break field or break and sync field or break sync and frame ID field depending on the setting HSEL register.\nNote: When transmitter header field (it may be break or break + sync or break +.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The wake-up condition from mute mode and each control and interactions of this field are explained in 6.16.5.3" "0: LIN mute mode,1: LIN mute mode Enabled"
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bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN slave automatic resynchronization mode (for non-automatic resynchronization mode this bit should be kept cleared).\nNote3: The control and interactions of this field are.." "0: UART_BAUD is updated as soon as UART_BAUD is..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operating in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit\nNote2: In LIN function mode when header field (break + sync + frame ID) is detected hardware will generate an interrupt to CPU (INT_LIN) and the SLVHDETF flag (UART_LINSTS[0]) will be asserted" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit\n" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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group.long 0x38++0x03
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line.long 0x00 "UART_LINSTS,UARTx LIN Status Register"
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rbitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag (Read Only)\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BITEF will be set.\nWhen occur bit error hardware will generate an.." "0,1"
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rbitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\nNote1: This bit is read only but can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN.." "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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rbitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n" "0: no active,1: Receipted frame ID parity is not correct"
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rbitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
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rbitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n" "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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group.long 0x3C++0x03
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line.long 0x00 "UART_LINDEBUG,UARTx LIN Debug Register"
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rbitfld.long 0x00 3. "SYNCERRF,LIN Header Sync Data Error (Read Only)\nThis bit indicates the header error cause by the LIN received sync data is not 0x55" "0,1"
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rbitfld.long 0x00 2. "FRAMEERRF,LIN Header Frame Error Flag (Read Only)\nThis bit indicates the header error cause by break delimiter is too short or frame error in sync field or Identifier field" "0,1"
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rbitfld.long 0x00 1. "TOF,LIN Header Time-Out (Read Only)\nThis bit indicates the header error cause by the LIN header reception time-out" "0,1"
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rbitfld.long 0x00 0. "DEVERRF,LIN Header Deviation Error (Read Only)\nThis bit indicates the header error cause by the sync field deviation error or sync field measure time-out with automatic resynchronization mode" "0,1"
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group.long 0x40++0x03
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line.long 0x00 "UART_SCCTL,UARTx SC Control Register"
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group.long 0x44++0x03
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line.long 0x00 "UART_SCSTATUS,UARTx SC Flag Status Register"
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tree.end
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repeat.end
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tree.end
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tree "USBD"
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base ad:0x40019000
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rgroup.long 0x00++0x03
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line.long 0x00 "USBD_GINTSTS,Interrupt Status Low Register"
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bitfld.long 0x00 13. "EPLIEN,Interrupt Enable Control for Endpoint L \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 12. "EPKIEN,Interrupt Enable Control for Endpoint K \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 11. "EPJIEN,Interrupt Enable Control for Endpoint J \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 10. "EPIIEN,Interrupt Enable Control for Endpoint I \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 9. "EPHIEN,Interrupt Enable Control for Endpoint H \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 8. "EPGIEN,Interrupt Enable Control for Endpoint G\nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 7. "EPFIEN,Interrupt Enable Control for Endpoint F \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 6. "EPEIEN,Interrupt Enable Control for Endpoint E \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 5. "EPDIEN,Interrupt Enable Control for Endpoint D \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 4. "EPCIEN,Interrupt Enable Control for Endpoint C \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 3. "EPBIEN,Interrupt Enable Control for Endpoint B \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B \n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 2. "EPAIEN,Interrupt Enable Control for Endpoint A \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 1. "CEPIEN,Control Endpoint Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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bitfld.long 0x00 0. "USBIEN,USB Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be generated when a USB event occurs on the bus.\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "USBD_GINTEN,Interrupt Enable Low Register"
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group.long 0x10++0x03
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line.long 0x00 "USBD_BUSINTSTS,USB Bus Interrupt Status Register"
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bitfld.long 0x00 8. "VBUSDETIF,VBUS Detection Interrupt Status \nNote: Write 1 to clear this bit to 0" "0: No VBUS is plug-in,1: VBUS is plug-in"
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bitfld.long 0x00 6. "PHYCLKVLDIF,Usable Clock Interrupt \nNote: Write 1 to clear this bit to 0" "0: Usable clock is not available,1: Usable clock is available from the transceiver"
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bitfld.long 0x00 5. "DMADONEIF,DMA Completion Interrupt \nNote: Write 1 to clear this bit to 0" "0: No DMA transfer over,1: DMA transfer is over"
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bitfld.long 0x00 4. "HISPDIF,High-Speed Settle \nNote: Write 1 to clear this bit to 0" "0: No valid high-speed reset protocol is detected,1: Valid high-speed reset protocol is over and.."
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bitfld.long 0x00 3. "SUSPENDIF,Suspend Request \nThis bit is set as default and it has to be cleared by writing '1' before the USB reset" "0: No USB Suspend request is detected from the..,1: USB Suspend request is detected from the host"
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bitfld.long 0x00 2. "RESUMEIF,Resume \nWhen set this bit indicates that a device resume has occurred.\nNote: Write 1 to clear this bit to 0" "0: No device resume has occurred,1: Device resume has occurred"
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bitfld.long 0x00 1. "RSTIF,Reset Status \nWhen set this bit indicates that either the USB root port reset is end.\nNote: Write 1 to clear this bit to 0" "0: No USB root port reset is end,1: USB root port reset is end"
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bitfld.long 0x00 0. "SOFIF,SOF Receive Control\nThis bit indicates when a start-of-frame packet has been received" "0: No start-of-frame packet has been received,1: Start-of-frame packet has been received"
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group.long 0x14++0x03
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line.long 0x00 "USBD_BUSINTEN,USB Bus Interrupt Enable Register"
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bitfld.long 0x00 8. "VBUSDETIEN,VBUS Detection Interrupt Enable Bit\nThis bit enables the VBUS floating detection interrupt.\n" "0: VBUS floating detection interrupt Disabled,1: VBUS floating detection interrupt Enabled"
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bitfld.long 0x00 6. "PHYCLKVLDIEN,Usable Clock Interrupt\nThis bit enables the usable clock interrupt.\n" "0: Usable clock interrupt Disabled,1: Usable clock interrupt Enabled"
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bitfld.long 0x00 5. "DMADONEIEN,DMA Completion Interrupt \nThis bit enables the DMA completion interrupt\n" "0: DMA completion interrupt Disabled,1: DMA completion interrupt Enabled"
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bitfld.long 0x00 4. "HISPDIEN,High-Speed Settle \nThis bit enables the high-speed settle interrupt.\n" "0: High-speed settle interrupt Disabled,1: High-speed settle interrupt Enabled"
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bitfld.long 0x00 3. "SUSPENDIEN,Suspend Request \nThis bit enables the Suspend interrupt.\n" "0: Suspend interrupt Disabled,1: Suspend interrupt Enabled"
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bitfld.long 0x00 2. "RESUMEIEN,Resume \nThis bit enables the Resume interrupt.\n" "0: Resume interrupt Disabled,1: Resume interrupt Enabled"
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bitfld.long 0x00 1. "RSTIEN,Reset Status \nThis bit enables the USB-Reset interrupt.\n" "0: USB-Reset interrupt Disabled,1: USB-Reset interrupt Enabled"
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bitfld.long 0x00 0. "SOFIEN,SOF Interrupt\nThis bit enables the SOF interrupt.\n" "0: SOF interrupt Disabled,1: SOF interrupt Enabled"
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group.long 0x18++0x03
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line.long 0x00 "USBD_OPER,USB Operational Register"
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bitfld.long 0x00 2. "CURSPD,USB Current Speed\n" "0: The device has settled in Full Speed,1: The USB device controller has settled in.."
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bitfld.long 0x00 1. "HISPDEN,USB High-Speed\n" "0: The USB device controller to suppress the..,1: The USB device controller to initiate a.."
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bitfld.long 0x00 0. "RESUMEEN,Generate Resume\n" "0: No Resume sequence to be initiated to the host,1: A Resume sequence to be initiated to the host.."
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rgroup.long 0x1C++0x03
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line.long 0x00 "USBD_FRAMECNT,USB Frame Count Register"
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hexmask.long.word 0x00 3.--13. 1. "FRAMECNT,Frame Counter\nThis field contains the frame count from the most recent start-of-frame packet"
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bitfld.long 0x00 0.--2. "MFRAMECNT,Micro-Frame Counter\nThis field contains the micro-frame number for the frame number in the frame counter field" "0,1,2,3,4,5,6,7"
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group.long 0x20++0x03
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line.long 0x00 "USBD_FADDR,USB Function Address Register"
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hexmask.long.byte 0x00 0.--6. 1. "FADDR,USB Function Address\nThis field contains the current USB address of the device"
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group.long 0x24++0x03
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line.long 0x00 "USBD_TEST,USB Test Mode Register"
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bitfld.long 0x00 0.--2. "TESTMODE,Test Mode Selection\nNote: This field is cleared when root port reset is detected" "0: Normal Operation,1: Test_J,2: Test_K,3: Test_SE0_NAK,4: Test_Packet,5: Test_Force_Enable,6: Reserved,7: Reserved"
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group.long 0x28++0x03
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line.long 0x00 "USBD_CEPDAT,Control-endpoint Data Buffer"
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hexmask.long 0x00 0.--31. 1. "DAT,Control-Endpoint Data Buffer \nControl endpoint data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0x2C++0x03
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line.long 0x00 "USBD_CEPCTL,Control-endpoint Control and Status"
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bitfld.long 0x00 3. "FLUSH,CEP-FLUSH Bit \n" "0: No the packet buffer and its corresponding..,1: The packet buffer and its corresponding.."
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bitfld.long 0x00 2. "ZEROLEN,Zero Packet Length\nThis bit is valid for Auto Validation mode only" "0: No zero length packet to the host during Data..,1: USB device controller can send a zero length.."
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bitfld.long 0x00 1. "STALLEN,Stall Enable Bit\nWhen this stall bit is set the control endpoint sends a stall handshake in response to any in or out token thereafter" "0: No sends a stall handshake in response to any..,1: The control endpoint sends a stall handshake.."
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bitfld.long 0x00 0. "NAKCLR,No Acknowledge Control\nThis bit plays a crucial role in any control transfer" "0: The bit is being cleared by the local CPU by..,1: This bit is set to one by the USB device.."
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group.long 0x30++0x03
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line.long 0x00 "USBD_CEPINTEN,Control-endpoint Interrupt Enable"
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bitfld.long 0x00 12. "BUFEMPTYIEN,Buffer Empty Interrupt \n" "0: The buffer empty interrupt in Control..,1: The buffer empty interrupt in Control.."
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bitfld.long 0x00 11. "BUFFULLIEN,Buffer Full Interrupt \n" "0: The buffer full interrupt in Control Endpoint..,1: The buffer full interrupt in Control Endpoint.."
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bitfld.long 0x00 10. "STSDONEIEN,Status Completion Interrupt \n" "0: The Status Completion interrupt in Control..,1: The Status Completion interrupt in Control.."
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bitfld.long 0x00 9. "ERRIEN,USB Error Interrupt \n" "0: The USB Error interrupt in Control Endpoint..,1: The USB Error interrupt in Control Endpoint.."
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bitfld.long 0x00 8. "STALLIEN,STALL Sent Interrupt \n" "0: The STALL sent interrupt in Control Endpoint..,1: The STALL sent interrupt in Control Endpoint.."
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bitfld.long 0x00 7. "NAKIEN,NAK Sent Interrupt \n" "0: The NAK sent interrupt in Control Endpoint..,1: The NAK sent interrupt in Control Endpoint.."
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bitfld.long 0x00 6. "RXPKIEN,Data Packet Received Interrupt \n" "0: The data received interrupt in Control..,1: The data received interrupt in Control.."
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bitfld.long 0x00 5. "TXPKIEN,Data Packet Transmitted Interrupt \n" "0: The data packet transmitted interrupt in..,1: The data packet transmitted interrupt in.."
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bitfld.long 0x00 4. "PINGIEN,Ping Token Interrupt \n" "0: The ping token interrupt in Control Endpoint..,1: The ping token interrupt Control Endpoint.."
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bitfld.long 0x00 3. "INTKIEN,In Token Interrupt \n" "0: The IN token interrupt in Control Endpoint..,1: The IN token interrupt in Control Endpoint.."
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bitfld.long 0x00 2. "OUTTKIEN,Out Token Interrupt \n" "0: The OUT token interrupt in Control Endpoint..,1: The OUT token interrupt in Control Endpoint.."
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bitfld.long 0x00 1. "SETUPPKIEN,Setup Packet Interrupt \n" "0: The SETUP packet interrupt in Control..,1: The SETUP packet interrupt in Control.."
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bitfld.long 0x00 0. "SETUPTKIEN,Setup Token Interrupt Enable Bit \n" "0: The SETUP token interrupt in Control Endpoint..,1: The SETUP token interrupt in Control Endpoint.."
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group.long 0x34++0x03
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line.long 0x00 "USBD_CEPINTSTS,Control-endpoint Interrupt Status"
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bitfld.long 0x00 12. "BUFEMPTYIF,Buffer Empty Interrupt \nNote: Write 1 to clear this bit to 0" "0: The control-endpoint buffer is not empty,1: The control-endpoint buffer is empty"
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bitfld.long 0x00 11. "BUFFULLIF,Buffer Full Interrupt \nNote: Write 1 to clear this bit to 0" "0: The control-endpoint buffer is not full,1: The control-endpoint buffer is full"
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bitfld.long 0x00 10. "STSDONEIF,Status Completion Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a USB transaction has completed..,1: The status stage of a USB transaction has.."
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bitfld.long 0x00 9. "ERRIF,USB Error Interrupt\nNote: Write 1 to clear this bit to 0" "0: No error had occurred during the transaction,1: An error had occurred during the transaction"
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bitfld.long 0x00 8. "STALLIF,STALL Sent Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a stall-token is sent in response to an..,1: A stall-token is sent in response to an.."
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bitfld.long 0x00 7. "NAKIF,NAK Sent Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a NAK-token is sent in response to an..,1: A NAK-token is sent in response to an IN/OUT.."
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bitfld.long 0x00 6. "RXPKIF,Data Packet Received Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is successfully received..,1: A data packet is successfully received from.."
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bitfld.long 0x00 5. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is successfully transmitted..,1: A data packet is successfully transmitted to.."
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bitfld.long 0x00 4. "PINGIF,Ping Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: The control-endpoint does not received a ping..,1: The control-endpoint receives a ping token.."
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bitfld.long 0x00 3. "INTKIF,In Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: The control-endpoint does not received an IN..,1: The control-endpoint receives an IN token.."
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bitfld.long 0x00 2. "OUTTKIF,Out Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: The control-endpoint does not received an OUT..,1: The control-endpoint receives an OUT token.."
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bitfld.long 0x00 1. "SETUPPKIF,Setup Packet Interrupt \nThis bit must be cleared (by writing 1) before the next setup packet can be received" "0: Not a Setup packet has been received from the..,1: A Setup packet has been received from the host"
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bitfld.long 0x00 0. "SETUPTKIF,Setup Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a Setup token is received,1: A Setup token is received"
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group.long 0x38++0x03
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line.long 0x00 "USBD_CEPTXCNT,Control-endpoint In-transfer Data Count"
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hexmask.long.byte 0x00 0.--7. 1. "TXCNT,In-Transfer Data Count\nThere is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this.."
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rgroup.long 0x3C++0x03
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line.long 0x00 "USBD_CEPRXCNT,Control-endpoint Out-transfer Data Count"
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hexmask.long.byte 0x00 0.--7. 1. "RXCNT,Out-Transfer Data Count \nThe USB device controller maintains the count of the data received in case of an out transfer during the control transfer"
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rgroup.long 0x40++0x03
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line.long 0x00 "USBD_CEPDATCNT,Control-endpoint Data Count"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Control-Endpoint Data Count \nThe USB device controller maintains the count of the data of control-endpoint"
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rgroup.long 0x44++0x03
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line.long 0x00 "USBD_SETUP1_0,Setup1 Setup0 Bytes"
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hexmask.long.byte 0x00 8.--15. 1. "SETUP1,Setup Byte 1[15:8]\nThis register provides byte 1 of the last setup packet received"
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abitfld.long 0x00 0.--7. "SETUP0,Setup Byte 0[7:0]\nThis register provides byte 0 of the last setup packet received" "0x00=0: Device\n,0x01=1: Interface\n,0x0A=10: Endpoint\n,0x0B=11: Other\n Others: Reserved"
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rgroup.long 0x48++0x03
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line.long 0x00 "USBD_SETUP3_2,Setup3 Setup2 Bytes"
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hexmask.long.byte 0x00 8.--15. 1. "SETUP3,Setup Byte 3 [15:8]\nThis register provides byte 3 of the last setup packet received"
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hexmask.long.byte 0x00 0.--7. 1. "SETUP2,Setup Byte 2 [7:0]\nThis register provides byte 2 of the last setup packet received"
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rgroup.long 0x4C++0x03
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line.long 0x00 "USBD_SETUP5_4,Setup5 Setup4 Bytes"
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hexmask.long.byte 0x00 8.--15. 1. "SETUP5,Setup Byte 5[15:8] \nThis register provides byte 5 of the last setup packet received"
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hexmask.long.byte 0x00 0.--7. 1. "SETUP4,Setup Byte 4[7:0] \nThis register provides byte 4 of the last setup packet received"
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rgroup.long 0x50++0x03
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line.long 0x00 "USBD_SETUP7_6,Setup7 Setup6 Bytes"
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hexmask.long.byte 0x00 8.--15. 1. "SETUP7,Setup Byte 7[15:8] \nThis register provides byte 7 of the last setup packet received"
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hexmask.long.byte 0x00 0.--7. 1. "SETUP6,Setup Byte 6[7:0] \nThis register provides byte 6 of the last setup packet received"
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group.long 0x54++0x03
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line.long 0x00 "USBD_CEPBUFSTART,Control Endpoint RAM Start Address Register"
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Control-Endpoint Start Address\nThis is the start-address of the RAM space allocated for the control-endpoint"
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group.long 0x58++0x03
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line.long 0x00 "USBD_CEPBUFEND,Control Endpoint RAM End Address Register"
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hexmask.long.word 0x00 0.--11. 1. "EADDR,Control-Endpoint End Address\nThis is the end-address of the RAM space allocated for the control-endpoint"
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group.long 0x5C++0x03
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line.long 0x00 "USBD_DMACTL,DMA Control Status Register"
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bitfld.long 0x00 7. "DMARST,Reset DMA State Machine\n" "0: No reset the DMA state machine,1: Reset the DMA state machine"
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bitfld.long 0x00 6. "SGEN,Scatter Gather Function Enable Bit\n" "0: Scatter gather function Disabled,1: Scatter gather function Enabled"
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bitfld.long 0x00 5. "DMAEN,DMA Enable Bit\n" "0: DMA function Disabled,1: DMA function Enabled"
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bitfld.long 0x00 4. "DMARD,DMA Operation\n" "0: The operation is a DMA write (read from USB..,1: The operation is a DMA read (write to USB.."
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bitfld.long 0x00 0.--3. "EPNUM,DMA Endpoint Address Bits\nUsed to define the Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x60++0x03
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line.long 0x00 "USBD_DMACNT,DMA Count Register"
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hexmask.long.tbyte 0x00 0.--19. 1. "DMACNT,DMA Transfer Count\nThe transfer count of the DMA operation to be performed is written to this register"
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group.long 0x64++0x03
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line.long 0x00 "USBD_EPADAT,Endpoint A Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0x68++0x03
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line.long 0x00 "USBD_EPAINTSTS,Endpoint A Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0x6C++0x03
|
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line.long 0x00 "USBD_EPAINTEN,Endpoint A Interrupt Enable Register"
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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rgroup.long 0x70++0x03
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line.long 0x00 "USBD_EPADATCNT,Endpoint A Data Available Count Register"
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0x74++0x03
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line.long 0x00 "USBD_EPARSPCTL,Endpoint A Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
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group.long 0x78++0x03
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line.long 0x00 "USBD_EPAMPS,Endpoint A Maximum Packet Size Register"
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hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
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group.long 0x7C++0x03
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line.long 0x00 "USBD_EPATXCNT,Endpoint A Transfer Count Register"
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hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
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group.long 0x80++0x03
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line.long 0x00 "USBD_EPACFG,Endpoint A Configuration Register"
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bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
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bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
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group.long 0x84++0x03
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line.long 0x00 "USBD_EPABUFSTART,Endpoint A RAM Start Address Register"
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
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group.long 0x88++0x03
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line.long 0x00 "USBD_EPABUFEND,Endpoint A RAM End Address Register"
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hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
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group.long 0x8C++0x03
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line.long 0x00 "USBD_EPBDAT,Endpoint B Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0x90++0x03
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line.long 0x00 "USBD_EPBINTSTS,Endpoint B Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0x94++0x03
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line.long 0x00 "USBD_EPBINTEN,Endpoint B Interrupt Enable Register"
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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group.long 0x98++0x03
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line.long 0x00 "USBD_EPBDATCNT,Endpoint B Data Available Count Register"
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0x9C++0x03
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line.long 0x00 "USBD_EPBRSPCTL,Endpoint B Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
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group.long 0xA0++0x03
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line.long 0x00 "USBD_EPBMPS,Endpoint B Maximum Packet Size Register"
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hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
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group.long 0xA4++0x03
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line.long 0x00 "USBD_EPBTXCNT,Endpoint B Transfer Count Register"
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hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
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group.long 0xA8++0x03
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line.long 0x00 "USBD_EPBCFG,Endpoint B Configuration Register"
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bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
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bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
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group.long 0xAC++0x03
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line.long 0x00 "USBD_EPBBUFSTART,Endpoint B RAM Start Address Register"
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
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group.long 0xB0++0x03
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line.long 0x00 "USBD_EPBBUFEND,Endpoint B RAM End Address Register"
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hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
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group.long 0xB4++0x03
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line.long 0x00 "USBD_EPCDAT,Endpoint C Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0xB8++0x03
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line.long 0x00 "USBD_EPCINTSTS,Endpoint C Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0xBC++0x03
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line.long 0x00 "USBD_EPCINTEN,Endpoint C Interrupt Enable Register"
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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group.long 0xC0++0x03
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line.long 0x00 "USBD_EPCDATCNT,Endpoint C Data Available Count Register"
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0xC4++0x03
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line.long 0x00 "USBD_EPCRSPCTL,Endpoint C Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
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group.long 0xC8++0x03
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line.long 0x00 "USBD_EPCMPS,Endpoint C Maximum Packet Size Register"
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hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
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group.long 0xCC++0x03
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line.long 0x00 "USBD_EPCTXCNT,Endpoint C Transfer Count Register"
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hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
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group.long 0xD0++0x03
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line.long 0x00 "USBD_EPCCFG,Endpoint C Configuration Register"
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bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
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bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
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group.long 0xD4++0x03
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line.long 0x00 "USBD_EPCBUFSTART,Endpoint C RAM Start Address Register"
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
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group.long 0xD8++0x03
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line.long 0x00 "USBD_EPCBUFEND,Endpoint C RAM End Address Register"
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hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
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group.long 0xDC++0x03
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line.long 0x00 "USBD_EPDDAT,Endpoint D Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0xE0++0x03
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line.long 0x00 "USBD_EPDINTSTS,Endpoint D Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0xE4++0x03
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line.long 0x00 "USBD_EPDINTEN,Endpoint D Interrupt Enable Register"
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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group.long 0xE8++0x03
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line.long 0x00 "USBD_EPDDATCNT,Endpoint D Data Available Count Register"
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0xEC++0x03
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line.long 0x00 "USBD_EPDRSPCTL,Endpoint D Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
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group.long 0xF0++0x03
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line.long 0x00 "USBD_EPDMPS,Endpoint D Maximum Packet Size Register"
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hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
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group.long 0xF4++0x03
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line.long 0x00 "USBD_EPDTXCNT,Endpoint D Transfer Count Register"
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hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
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group.long 0xF8++0x03
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line.long 0x00 "USBD_EPDCFG,Endpoint D Configuration Register"
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bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
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bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
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group.long 0xFC++0x03
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line.long 0x00 "USBD_EPDBUFSTART,Endpoint D RAM Start Address Register"
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
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group.long 0x100++0x03
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line.long 0x00 "USBD_EPDBUFEND,Endpoint D RAM End Address Register"
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hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
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group.long 0x104++0x03
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line.long 0x00 "USBD_EPEDAT,Endpoint E Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0x108++0x03
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line.long 0x00 "USBD_EPEINTSTS,Endpoint E Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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newline
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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newline
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0x10C++0x03
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line.long 0x00 "USBD_EPEINTEN,Endpoint E Interrupt Enable Register"
|
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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newline
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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group.long 0x110++0x03
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line.long 0x00 "USBD_EPEDATCNT,Endpoint E Data Available Count Register"
|
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0x114++0x03
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line.long 0x00 "USBD_EPERSPCTL,Endpoint E Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
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group.long 0x118++0x03
|
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line.long 0x00 "USBD_EPEMPS,Endpoint E Maximum Packet Size Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
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group.long 0x11C++0x03
|
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line.long 0x00 "USBD_EPETXCNT,Endpoint E Transfer Count Register"
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hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
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group.long 0x120++0x03
|
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line.long 0x00 "USBD_EPECFG,Endpoint E Configuration Register"
|
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bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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newline
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
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bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
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group.long 0x124++0x03
|
|
line.long 0x00 "USBD_EPEBUFSTART,Endpoint E RAM Start Address Register"
|
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
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|
group.long 0x128++0x03
|
|
line.long 0x00 "USBD_EPEBUFEND,Endpoint E RAM End Address Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
|
|
group.long 0x12C++0x03
|
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line.long 0x00 "USBD_EPFDAT,Endpoint F Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0x130++0x03
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line.long 0x00 "USBD_EPFINTSTS,Endpoint F Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0x134++0x03
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line.long 0x00 "USBD_EPFINTEN,Endpoint F Interrupt Enable Register"
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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group.long 0x138++0x03
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line.long 0x00 "USBD_EPFDATCNT,Endpoint F Data Available Count Register"
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0x13C++0x03
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line.long 0x00 "USBD_EPFRSPCTL,Endpoint F Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
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group.long 0x140++0x03
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line.long 0x00 "USBD_EPFMPS,Endpoint F Maximum Packet Size Register"
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hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
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group.long 0x144++0x03
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line.long 0x00 "USBD_EPFTXCNT,Endpoint F Transfer Count Register"
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hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
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group.long 0x148++0x03
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line.long 0x00 "USBD_EPFCFG,Endpoint F Configuration Register"
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bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
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bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
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group.long 0x14C++0x03
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line.long 0x00 "USBD_EPFBUFSTART,Endpoint F RAM Start Address Register"
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
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group.long 0x150++0x03
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line.long 0x00 "USBD_EPFBUFEND,Endpoint F RAM End Address Register"
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hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
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group.long 0x154++0x03
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line.long 0x00 "USBD_EPGDAT,Endpoint G Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0x158++0x03
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line.long 0x00 "USBD_EPGINTSTS,Endpoint G Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0x15C++0x03
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line.long 0x00 "USBD_EPGINTEN,Endpoint G Interrupt Enable Register"
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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group.long 0x160++0x03
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line.long 0x00 "USBD_EPGDATCNT,Endpoint G Data Available Count Register"
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0x164++0x03
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line.long 0x00 "USBD_EPGRSPCTL,Endpoint G Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
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group.long 0x168++0x03
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line.long 0x00 "USBD_EPGMPS,Endpoint G Maximum Packet Size Register"
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hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
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group.long 0x16C++0x03
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line.long 0x00 "USBD_EPGTXCNT,Endpoint G Transfer Count Register"
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hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
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group.long 0x170++0x03
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line.long 0x00 "USBD_EPGCFG,Endpoint G Configuration Register"
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bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
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bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
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group.long 0x174++0x03
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line.long 0x00 "USBD_EPGBUFSTART,Endpoint G RAM Start Address Register"
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
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group.long 0x178++0x03
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line.long 0x00 "USBD_EPGBUFEND,Endpoint G RAM End Address Register"
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hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
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group.long 0x17C++0x03
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line.long 0x00 "USBD_EPHDAT,Endpoint H Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0x180++0x03
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line.long 0x00 "USBD_EPHINTSTS,Endpoint H Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0x184++0x03
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line.long 0x00 "USBD_EPHINTEN,Endpoint H Interrupt Enable Register"
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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group.long 0x188++0x03
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line.long 0x00 "USBD_EPHDATCNT,Endpoint H Data Available Count Register"
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0x18C++0x03
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line.long 0x00 "USBD_EPHRSPCTL,Endpoint H Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
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group.long 0x190++0x03
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line.long 0x00 "USBD_EPHMPS,Endpoint H Maximum Packet Size Register"
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hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
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group.long 0x194++0x03
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line.long 0x00 "USBD_EPHTXCNT,Endpoint H Transfer Count Register"
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hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
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group.long 0x198++0x03
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line.long 0x00 "USBD_EPHCFG,Endpoint H Configuration Register"
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bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
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bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
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group.long 0x19C++0x03
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line.long 0x00 "USBD_EPHBUFSTART,Endpoint H RAM Start Address Register"
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
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group.long 0x1A0++0x03
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line.long 0x00 "USBD_EPHBUFEND,Endpoint H RAM End Address Register"
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hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
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group.long 0x1A4++0x03
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line.long 0x00 "USBD_EPIDAT,Endpoint I Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0x1A8++0x03
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line.long 0x00 "USBD_EPIINTSTS,Endpoint I Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0x1AC++0x03
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line.long 0x00 "USBD_EPIINTEN,Endpoint I Interrupt Enable Register"
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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group.long 0x1B0++0x03
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line.long 0x00 "USBD_EPIDATCNT,Endpoint I Data Available Count Register"
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0x1B4++0x03
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line.long 0x00 "USBD_EPIRSPCTL,Endpoint I Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
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group.long 0x1B8++0x03
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line.long 0x00 "USBD_EPIMPS,Endpoint I Maximum Packet Size Register"
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hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
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group.long 0x1BC++0x03
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line.long 0x00 "USBD_EPITXCNT,Endpoint I Transfer Count Register"
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hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
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group.long 0x1C0++0x03
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line.long 0x00 "USBD_EPICFG,Endpoint I Configuration Register"
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bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
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bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
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group.long 0x1C4++0x03
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line.long 0x00 "USBD_EPIBUFSTART,Endpoint I RAM Start Address Register"
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
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group.long 0x1C8++0x03
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line.long 0x00 "USBD_EPIBUFEND,Endpoint I RAM End Address Register"
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hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
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group.long 0x1CC++0x03
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line.long 0x00 "USBD_EPJDAT,Endpoint J Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0x1D0++0x03
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line.long 0x00 "USBD_EPJINTSTS,Endpoint J Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0x1D4++0x03
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line.long 0x00 "USBD_EPJINTEN,Endpoint J Interrupt Enable Register"
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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group.long 0x1D8++0x03
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line.long 0x00 "USBD_EPJDATCNT,Endpoint J Data Available Count Register"
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0x1DC++0x03
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line.long 0x00 "USBD_EPJRSPCTL,Endpoint J Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
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group.long 0x1E0++0x03
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line.long 0x00 "USBD_EPJMPS,Endpoint J Maximum Packet Size Register"
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hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
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group.long 0x1E4++0x03
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line.long 0x00 "USBD_EPJTXCNT,Endpoint J Transfer Count Register"
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hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
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group.long 0x1E8++0x03
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line.long 0x00 "USBD_EPJCFG,Endpoint J Configuration Register"
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bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
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bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
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group.long 0x1EC++0x03
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line.long 0x00 "USBD_EPJBUFSTART,Endpoint J RAM Start Address Register"
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
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group.long 0x1F0++0x03
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line.long 0x00 "USBD_EPJBUFEND,Endpoint J RAM End Address Register"
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hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
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group.long 0x1F4++0x03
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line.long 0x00 "USBD_EPKDAT,Endpoint K Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0x1F8++0x03
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line.long 0x00 "USBD_EPKINTSTS,Endpoint K Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0x1FC++0x03
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line.long 0x00 "USBD_EPKINTEN,Endpoint K Interrupt Enable Register"
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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group.long 0x200++0x03
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line.long 0x00 "USBD_EPKDATCNT,Endpoint K Data Available Count Register"
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0x204++0x03
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line.long 0x00 "USBD_EPKRSPCTL,Endpoint K Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
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group.long 0x208++0x03
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line.long 0x00 "USBD_EPKMPS,Endpoint K Maximum Packet Size Register"
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hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
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group.long 0x20C++0x03
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line.long 0x00 "USBD_EPKTXCNT,Endpoint K Transfer Count Register"
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hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
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group.long 0x210++0x03
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line.long 0x00 "USBD_EPKCFG,Endpoint K Configuration Register"
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bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
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bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
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group.long 0x214++0x03
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line.long 0x00 "USBD_EPKBUFSTART,Endpoint K RAM Start Address Register"
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hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
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group.long 0x218++0x03
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line.long 0x00 "USBD_EPKBUFEND,Endpoint K RAM End Address Register"
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hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
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group.long 0x21C++0x03
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line.long 0x00 "USBD_EPLDAT,Endpoint L Data Register"
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hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported"
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group.long 0x220++0x03
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line.long 0x00 "USBD_EPLINTSTS,Endpoint L Interrupt Status Register"
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bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
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bitfld.long 0x00 11. "ERRIF,ERR Sent \nNote: Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
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bitfld.long 0x00 10. "NYETIF,NYET Sent \nNote: Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
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bitfld.long 0x00 9. "STALLIF,USB STALL Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
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bitfld.long 0x00 8. "NAKIF,USB NAK Sent\nNote: Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
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bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
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bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not Data IN token has been received from the..,1: A Data IN token has been received from the host"
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bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
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bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
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bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: Not a data packet is transmitted from the..,1: A data packet is transmitted from the.."
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bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
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bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
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bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
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group.long 0x224++0x03
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line.long 0x00 "USBD_EPLINTEN,Endpoint L Interrupt Enable Register"
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bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
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bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
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bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
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bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
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bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
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bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
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bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
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bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
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bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
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bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
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bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
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bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
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group.long 0x228++0x03
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line.long 0x00 "USBD_EPLDATCNT,Endpoint L Data Available Count Register"
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hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
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hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
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group.long 0x22C++0x03
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line.long 0x00 "USBD_EPLRSPCTL,Endpoint L Response Control Register"
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bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
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bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
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bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
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bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Not send a STALL handshake as response to the..,1: Send a STALL handshake as response to the.."
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bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
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bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits decide the operation mode of the in-endpoint" "0,1,2,3"
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bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "USBD_EPLMPS,Endpoint L Maximum Packet Size Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "USBD_EPLTXCNT,Endpoint L Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "USBD_EPLCFG,Endpoint L Configuration Register"
|
|
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
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|
newline
|
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bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
|
|
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "USBD_EPLBUFSTART,Endpoint L RAM Start Address Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "USBD_EPLBUFEND,Endpoint L RAM End Address Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "USBD_DMAADDR,AHB DMA Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMAADDR\nThe register specifies the address from which the DMA has to read /"
|
|
group.long 0x704++0x03
|
|
line.long 0x00 "USBD_PHYCTL,USB PHY Control Register"
|
|
bitfld.long 0x00 31. "VBUSDET,VBUS Status\n" "0: The VBUS is not detected yet,1: The VBUS is detected"
|
|
bitfld.long 0x00 24. "WKEN,Wake-Up Enable Bit\n" "0: The wake-up function Disabled,1: The wake-up function Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "PHYEN,PHY Suspend Enable Bit\n" "0: The USB PHY is suspend,1: The USB PHY is not suspend"
|
|
bitfld.long 0x00 8. "DPPUEN,DP Pull-Up\n" "0: Pull-up resistor on D+ Disabled,1: Pull-up resistor on D+ Enabled"
|
|
tree.end
|
|
tree "USBH"
|
|
base ad:0x40009000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "HcRevision,Host Controller Revision Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REV,Revision\nIndicates the Open HCI Specification revision number implemented by the Hardware"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HcControl,Host Controller Control Register"
|
|
bitfld.long 0x00 6.--7. "HCFS,Host Controller Functional State\nThis field sets the Host Controller state" "0: USBSUSPEND,1: USBOPERATIONAL,2: USBRESUME,3: USBRESET"
|
|
bitfld.long 0x00 5. "BLE,Bulk List Enable Bit\n" "0: Processing of the Bulk list after next SOF..,1: Processing of the Bulk list in the next frame.."
|
|
newline
|
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bitfld.long 0x00 4. "CLE,Control List Enable Bit\n" "0: Processing of the Control list after next SOF..,1: Processing of the Control list in the next.."
|
|
bitfld.long 0x00 3. "IE,Isochronous Enable Bit\nBoth ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list" "0: Processing of the Isochronous list after next..,1: Processing of the Isochronous list in the.."
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|
newline
|
|
bitfld.long 0x00 2. "PLE,Periodic List Enable Bit\nWhen set this bit enables processing of the Periodic (interrupt and isochronous) list" "0: Processing of the Periodic (Interrupt and..,1: Processing of the Periodic (Interrupt and.."
|
|
bitfld.long 0x00 0.--1. "CBSR,Control Bulk Service Ratio\nThis specifies the service ratio between Control and Bulk EDs" "0: Number of Control EDs over Bulk EDs served is..,1: Number of Control EDs over Bulk EDs served is..,2: Number of Control EDs over Bulk EDs served is..,3: Number of Control EDs over Bulk EDs served is.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "HcCommandStatus,Host Controller Command Status Register"
|
|
bitfld.long 0x00 16.--17. "SOC,Scheduling Overrun Count\nThese bits are incremented on each scheduling overrun error" "0,1,2,3"
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|
bitfld.long 0x00 2. "BLF,Bulk List Filled\nSet high to indicate there is an active TD on the Bulk list" "0: No active TD found or Host Controller begins..,1: An active TD added or found on the Bulk list"
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|
newline
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bitfld.long 0x00 1. "CLF,Control List Filled\nSet high to indicate there is an active TD on the Control List" "0: No active TD found or Host Controller begins..,1: An active TD added or found on the Control list"
|
|
bitfld.long 0x00 0. "HCR,Host Controller Reset\nThis bit is set to initiate the software reset of Host Controller" "0: Host Controller is not in software reset state,1: Host Controller is in software reset state"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "HcInterruptStatus,Host Controller Interrupt Status Register"
|
|
bitfld.long 0x00 6. "RHSC,Root Hub Status Change\nThis bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed.\n" "0: The content of HcRhStatus and the content of..,1: The content of HcRhStatus or the content of.."
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|
bitfld.long 0x00 5. "FNO,Frame Number Overflow\nThis bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.\n" "0: The bit 15 of Frame Number didn't change,1: The bit 15 of Frame Number changes from 1 to.."
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|
newline
|
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bitfld.long 0x00 3. "RD,Resume Detected\nSet when Host Controller detects resume signaling on a downstream port.\n" "0: No resume signaling detected on a downstream..,1: Resume signaling detected on a downstream port"
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|
bitfld.long 0x00 2. "SF,Start Of Frame\nSet when the Frame Management functional block signals a 'Start of Frame' event" "0: .Not the start of a frame,1: .Indicate the start of a frame and Host.."
|
|
newline
|
|
bitfld.long 0x00 1. "WDH,Write Back Done Head\nSet after the Host Controller has written HcDoneHead to HccaDoneHead" "0: .Host Controller didn't update HccaDoneHead,1: .Host Controller has written HcDoneHead to.."
|
|
bitfld.long 0x00 0. "SO,Scheduling Overrun\nSet when the List Processor determines a Schedule Overrun has occurred.\n" "0: Schedule Overrun didn't occur,1: Schedule Overrun has occurred"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "HcInterruptEnable,Host Controller Interrupt Enable Control Register"
|
|
bitfld.long 0x00 31. "MIE,Master Interrupt Enable Bit\nThis bit is a global interrupt enable" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
|
|
bitfld.long 0x00 6. "RHSC,Root Hub Status Change Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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|
newline
|
|
bitfld.long 0x00 5. "FNO,Frame Number Overflow Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
|
|
bitfld.long 0x00 3. "RD,Resume Detected Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
|
|
newline
|
|
bitfld.long 0x00 2. "SF,Start Of Frame Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
|
|
bitfld.long 0x00 1. "WDH,Write Back Done Head Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
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|
newline
|
|
bitfld.long 0x00 0. "SO,Scheduling Overrun Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "HcInterruptDisable,Host Controller Interrupt Disable Control Register"
|
|
bitfld.long 0x00 31. "MIE,Master Interrupt Disable Bit\nGlobal interrupt disable" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
|
|
bitfld.long 0x00 6. "RHSC,Root Hub Status Change Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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|
newline
|
|
bitfld.long 0x00 5. "FNO,Frame Number Overflow Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
|
|
bitfld.long 0x00 3. "RD,Resume Detected Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
|
|
newline
|
|
bitfld.long 0x00 2. "SF,Start Of Frame Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
|
|
bitfld.long 0x00 1. "WDH,Write Back Done Head Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
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|
newline
|
|
bitfld.long 0x00 0. "SO,Scheduling Overrun Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "HcHCCA,Host Controller Communication Area Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "HCCA,Host Controller Communication Area\nPointer to indicate base address of the Host Controller Communication Area (HCCA)"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HcPeriodCurrentED,Host Controller Period Current ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "PCED,Periodic Current ED\nPointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "HcControlHeadED,Host Controller Control Head ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "CHED,Control Head ED\nPointer to indicate physical address of the first Endpoint Descriptor of the Control list"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "HcControlCurrentED,Host Controller Control Current ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "CCED,Control Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Control list"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HcBulkHeadED,Host Controller Bulk Head ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "BHED,Bulk Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "HcBulkCurrentED,Host Controller Bulk Current ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "BCED,Bulk Current Head ED\nPointer to indicate the physical address of the current endpoint of the Bulk list"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "HcDoneHead,Host Controller Done Head Register"
|
|
hexmask.long 0x00 4.--31. 1. "DH,Done Head\nPointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "HcFmInterval,Host Controller Frame Interval Register"
|
|
bitfld.long 0x00 31. "FIT,Frame Interval Toggle\nThis bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).\n" "0: Host Controller Driver didn't load new value..,1: Host Controller Driver loads a new value into.."
|
|
hexmask.long.word 0x00 16.--30. 1. "FSMPS,FS Largest Data Packet\nThis field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame"
|
|
newline
|
|
hexmask.long.word 0x00 0.--13. 1. "FI,Frame Interval\nThis field specifies the length of a frame as (bit times - 1)"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "HcFmRemaining,Host Controller Frame Remaining Register"
|
|
bitfld.long 0x00 31. "FRT,Frame Remaining Toggle\nThis bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0" "0,1"
|
|
hexmask.long.word 0x00 0.--13. 1. "FR,Frame Remaining\nWhen the Host Controller is in the USBOPERATIONAL state this 14-bit field decrements each 12 MHz clock period"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "HcFmNumber,Host Controller Frame Number Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "FN,Frame Number\nThis 16-bit incrementing counter field is incremented coincident with the loading of FR (HcFmRemaining[13:0])"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "HcPeriodicStart,Host Controller Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. "PS,Periodic Start\nThis field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "HcLSThreshold,Host Controller Low-speed Threshold Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "LST,Low-Speed Threshold\n"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "HcRhDescriptorA,Host Controller Root Hub Descriptor A Register"
|
|
bitfld.long 0x00 12. "NOCP,No Overcurrent Protection\nThis bit describes how the over current status for the Root Hub ports reported.\n" "0: Over current status is reported,1: Over current status is not reported"
|
|
bitfld.long 0x00 11. "OCPM,Overcurrent Protection Mode\nThis bit describes how the over current status for the Root Hub ports reported" "0: Global Over current,1: Individual Over current"
|
|
newline
|
|
bitfld.long 0x00 8. "PSM,Power Switching Mode\nThis bit is used to specify how the power switching of the Root Hub ports is controlled.\n" "0: Global Switching,1: Individual Switching"
|
|
hexmask.long.byte 0x00 0.--7. 1. "NDP,Number Downstream Ports\nRoot Hub supports two downstream ports"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "HcRhDescriptorB,Host Controller Root Hub Descriptor B Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PPCM,Port Power Control Mask\nGlobal power switching"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "HcRhStatus,Host Controller Root Hub Status Register"
|
|
bitfld.long 0x00 31. "CRWE,Clear Remote Wake-Up Enable Bit\nThis bit is use to clear DRWE (HcRhStatus[15]).\nThis bit always read as zero.\nWrite Operation:\n" "0: No effect,1: Clear DRWE (HcRhStatus[15])"
|
|
bitfld.long 0x00 17. "OCIC,Over Current Indicator Change\nThis bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\nWrite 1 to clear this bit to zero.\n" "0: OCI (HcRhStatus[1]) didn't change,1: OCI (HcRhStatus[1]) change"
|
|
newline
|
|
bitfld.long 0x00 16. "LPSC,SetGlobalPower\n" "0: No effect,1: Set global power"
|
|
bitfld.long 0x00 15. "DRWE,Device Remote Wakeup Enable Bit\nThis bit controls if port's Connect Status Change as a remote wake-up event.\nWrite Operation:\n" "0: No effect.\nConnect Status Change as a remote..,1: Connect Status Change as a remote wake-up.."
|
|
newline
|
|
bitfld.long 0x00 1. "OCI,Overcurrent Indicator\nThis bit reflects the state of the over current status pin" "0: No over current condition,1: Over current condition"
|
|
bitfld.long 0x00 0. "LPS,Clear Global Power\n" "0: No effect,1: Clear global power"
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "HcRhPortStatus$1,Host Controller Root Hub Port Status [1]"
|
|
bitfld.long 0x00 20. "PRSC,Port Reset Status Change\nThis bit indicates that the port reset signal has completed.\nWrite 1 to clear this bit to zero.\n" "0: Port reset is not complete,1: Port reset is complete"
|
|
bitfld.long 0x00 19. "OCIC,Port Over Current Indicator Change\nThis bit is set when POCI (HcRhPortStatus1[3]) changes.\nWrite 1 to clear this bit to zero.\n" "0: POCI (HcRhPortStatus1[3]) didn't change,1: POCI (HcRhPortStatus1[3]) changes"
|
|
newline
|
|
bitfld.long 0x00 18. "PSSC,Port Suspend Status Change\nThis bit indicates the completion of the selective resume sequence for the port.\nWrite 1 to clear this bit to zero.\n" "0: Port resume is not completed,1: Port resume completed"
|
|
bitfld.long 0x00 17. "PESC,Port Enable Status Change\nThis bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.\nWrite 1 to clear this bit to zero.\n" "0: PES (HcRhPortStatus1[1]) didn't change,1: PES (HcRhPortStatus1[1]) changed"
|
|
newline
|
|
bitfld.long 0x00 16. "CSC,Connect Status Change\nThis bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).\nWrite 1 to clear this bit to zero.\n" "0: No connect/disconnect event (CCS..,1: Hardware detection of connect/disconnect.."
|
|
bitfld.long 0x00 9. "LSDA,Low Speed Device Attached (Read) Or Clear Port Power (Write)\nThis bit defines the speed (and bud idle) of the attached device" "0: No effect.\nFull Speed device,1: Clear PPS (HcRhPortStatus1[8]).\nLow-speed.."
|
|
newline
|
|
bitfld.long 0x00 8. "PPS,Port Power Status\nThis bit reflects the power state of the port regardless of the power switching mode.\nWrite Operation:\n" "0: No effect.\nPort power is Diabled,1: Port Power Enabled.\nPort power is Enabled"
|
|
bitfld.long 0x00 4. "PRS,Port Reset Status\nThis bit reflects the reset state of the port.\nWrite Operation:\n" "0: No effect.\nPort reset signal is not active,1: Set port reset.\nPort reset signal is active"
|
|
newline
|
|
bitfld.long 0x00 3. "POCI,Port Over Current Indicator (Read) Or Clear Port Suspend (Write)\nThis bit reflects the state of the over current status pin dedicated to this port" "0: No effect.\nNo over current condition,1: Clear port suspend.\nOver current condition"
|
|
bitfld.long 0x00 2. "PSS,Port Suspend Status\nThis bit indicates the port is suspended\nWrite Operation:\n" "0: No effect.\nPort is not suspended,1: Set port suspend.\nPort is selectively.."
|
|
newline
|
|
bitfld.long 0x00 1. "PES,Port Enable Status\nWrite Operation:\n" "0: No effect.\nPort Disabled,1: Set port enable.\nPort Enabled"
|
|
bitfld.long 0x00 0. "CCS,CurrentConnectStatus (Read) Or ClearPortEnable Bit (Write)\nWrite Operation:\n" "0: No effect.\nNo device connected,1: Clear port enable.\nDevice connected"
|
|
repeat.end
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "HcPhyControl,Host Controller PHY Control Register"
|
|
bitfld.long 0x00 27. "STBYEN,USB Transceiver Standby Enable Bit\nThis bit controls if USB transceiver could enter the standby mode to reduce power consumption.\n" "0: The USB transceiver would never enter the..,1: The USB transceiver will enter standby mode.."
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "HcMiscControl,Host Controller Miscellaneous Control Register"
|
|
bitfld.long 0x00 17. "DPRT2,Port 2 Disable Bit\nThis bit controls if the connection between USB host controller and transceiver of port 2 is disabled" "0: The connection between USB host controller..,1: The connection between USB host controller.."
|
|
bitfld.long 0x00 16. "DPRT1,Port 1 Disable Bit\nThis bit controls if the connection between USB host controller and transceiver of port 1 is disabled" "0: The connection between USB host controller..,1: The connection between USB host controller.."
|
|
newline
|
|
bitfld.long 0x00 8. "SIEPD,SIE Pipeline Disable Bit\nWhen set waits for all USB bus activity to complete prior to returning completion status to the List Processor" "0,1"
|
|
bitfld.long 0x00 4. "PCAL,Port Power Control Active Low\nThis bit controls the polarity of port power control to external power IC.\n" "0: Port power control is high active,1: Port power control is low active"
|
|
newline
|
|
bitfld.long 0x00 3. "OCAL,Overcurrent Active Low\nThis bit controls the polarity of overcurrent flag from external power IC.\n" "0: Overcurrent flag is high active,1: Overcurrent flag is low active"
|
|
bitfld.long 0x00 1. "ABORT,AHB Bus ERROR Response\nThis bit indicates there is an ERROR response received in AHB bus.\n" "0: No ERROR response received,1: ERROR response received"
|
|
newline
|
|
bitfld.long 0x00 0. "DBR16,Data Buffer Region 16\nWhen set the size of the data buffer region is 16 bytes" "0,1"
|
|
tree.end
|
|
tree "WDT"
|
|
base ad:0x40040000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "WDT_CTL,Watchdog Timer Control Register"
|
|
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nNote: Watchdog Timer counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement affects..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x00 8.--10. "TOUTSEL,Watchdog Timer Time-Out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the Watchdog Timer.\n" "0: 24 *TWDT,1: 26 *TWDT,2: 28 *TWDT,3: 210 *TWDT,4: 212 *TWDT,5: 214 *TWDT,6: 216 *TWDT,7: 218 *TWDT"
|
|
newline
|
|
bitfld.long 0x00 7. "WDTEN,Watchdog Timer Enable Bit (Write Protect)\nNote: If CWDTEN (Config0[31] watchdog enable) bit is set to 0 this bit is forced as 1 and software cannot change this bit to 0" "0: Watchdog Timer Disabled (This action will..,1: Watchdog Timer Enabled"
|
|
bitfld.long 0x00 6. "INTEN,Watchdog Timer Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU" "0: Watchdog Timer interrupt Disabled,1: Watchdog Timer interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "WKF,Watchdog Timer Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of WDT\nNote: This bit is cleared by writing 1 to it" "0: Watchdog Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
|
|
bitfld.long 0x00 4. "WKEN,Watchdog Timer Wake-Up Function Enable Bit (Write Protect)\nIf this bit is set to 1 while WDT interrupt flag IF(WDT_CTL[3]) is generated to 1 and INTEN (WDT_CTL[6] WDT interrupt enable) is enabled the WDT time-out interrupt signal will generate a.." "0: Wake-up trigger event Disabled if WDT..,1: Wake-up trigger event Enabled if WDT time-out.."
|
|
newline
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bitfld.long 0x00 3. "IF,Watchdog Timer Interrupt Flag\nThis bit will set to 1 while WDT counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it" "0: Watchdog Timer time-out interrupt did not occur,1: Watchdog Timer time-out interrupt occurred"
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bitfld.long 0x00 2. "RSTF,Watchdog Timer Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: Watchdog Timer time-out reset did not occur,1: Watchdog Timer time-out reset occurred"
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bitfld.long 0x00 1. "RSTEN,Watchdog Timer Reset Enable Bit (Write Protect)\nSetting this bit will enable the Watchdog Timer time-out reset function If the WDT counter value has not been cleared after the specific WDT reset delay period expires.\n" "0: Watchdog Timer time-out reset function Disabled,1: Watchdog Timer time-out reset function Enabled"
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bitfld.long 0x00 0. "RSTCNT,Clear Watchdog Timer (Write Protect)\nNote: This bit will be automatically cleared by hardware" "0: No effect,1: Reset the internal 18-bit WDT counter"
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group.long 0x04++0x03
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line.long 0x00 "WDT_ALTCTL,Watchdog Timer Alternative Control Register"
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bitfld.long 0x00 0.--1. "RSTDSEL,Watchdog Timer Reset Delay Selection (Write Protect)\nWhen WDT time-out happened software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened" "0: Watchdog Timer reset delay period is (1024+2)..,1: Watchdog Timer reset delay period is (128+2)..,2: Watchdog Timer reset delay period is (16+2) *..,3: Watchdog Timer reset delay period is (1+2) *.."
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tree.end
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tree "WWDT"
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base ad:0x40040100
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wgroup.long 0x00++0x03
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line.long 0x00 "WWDT_RLDCNT,Window Watchdog Timer Reload Counter Register"
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hexmask.long 0x00 0.--31. 1. "RLDCNT,WWDT Reload Counter Bit\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F"
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group.long 0x04++0x03
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line.long 0x00 "WWDT_CTL,Window Watchdog Timer Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nWWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 16.--21. "CMPDAT,WWDT Window Compare Bits\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--11. "PSCSEL,WWDT Counter Prescale Period Selection\n" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.."
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bitfld.long 0x00 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU.\n" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
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bitfld.long 0x00 0. "WWDTEN,WWDT Enable Bit\nSet this bit to enable Window Watchdog Timer counter counting.\n" "0: Window Watchdog Timer counter is stopped,1: Window Watchdog Timer counter is starting.."
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group.long 0x08++0x03
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line.long 0x00 "WWDT_STATUS,Window Watchdog Timer Status Register"
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bitfld.long 0x00 1. "WWDTRF,WWDT Timer-Out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
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bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT counter value matches CMPDAT value"
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rgroup.long 0x0C++0x03
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line.long 0x00 "WWDT_CNT,Window Watchdog Timer Counter Value Register"
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bitfld.long 0x00 0.--5. "CNTDAT,WWDT Counter Value\nThis register reflects the current WWDT counter value and is read only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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tree.end
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autoindent.off
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newline
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