29897 lines
2.2 MiB
29897 lines
2.2 MiB
; --------------------------------------------------------------------------------
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; @Title: IMX50 On-Chip Peripherals
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; @Props: Released
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; @Author: TPP, ZAK
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; @Changelog: 2013-03-23
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; @Manufacturer:
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; FREESCALE - Freescale Semiconductor, Inc.
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; @Doc: IMX50RM.pdf (Rev. 1, 2011-10)
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; @Core: Cortex-A8
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: permcimx50.per 15961 2023-04-12 15:09:02Z bschroefel $
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config 16. 8.
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width 0xB
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tree "Core Registers (Cortex-A8)"
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup c15:0x0--0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x100--0x100
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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textline " "
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup c15:0x200--0x200
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line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "ARMv6,ARMv6,ARMv6,ARMv6,ARMv7,ARMv6,ARMv6,ARMv6"
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bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x300--0x300
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line.long 0x0 "TLBTR,TLB Type Register"
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hexmask.long.byte 0x0 16.--23. 0x1 " ITLBLOCK ,Specifies the number of instruction TLB lockable entries"
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hexmask.long.byte 0x0 8.--15. 0x1 " DTLBLOCK ,Specifies the number of unified or data TLB lockable entries"
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bitfld.long 0x0 0. " S ,Unified or Separate TLBs" "Unified,Separate"
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rgroup c15:0x400--0x400
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line.long 0x0 "MPUTR,MPU type register"
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rgroup c15:0x500--0x500
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitniy Level 2"
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hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitniy Level 1"
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hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitniy Level 0"
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textline " "
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rgroup c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
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rgroup c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
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rgroup c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup c15:0x0010++0x00
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line.long 0x00 "PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup c15:0x0110++0x00
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line.long 0x00 "PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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textline " "
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rgroup c15:0x0210++0x00
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line.long 0x00 "DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
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rgroup c15:0x0310++0x00
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line.long 0x00 "AFR0,Auxiliary Feature Register 0"
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hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group c15:0x1--0x1
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
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bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
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textline " "
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group c15:0x101--0x101
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 31. " L2RD ,L2 hardware reset disable" "Enable,Disable"
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bitfld.long 0x00 30. " L1RD ,L1 hardware reset disable" "Enable,Disable"
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textline " "
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bitfld.long 0x00 18. " CPISEL ,CP14/CP15 instruction serialization" "No,Yes"
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bitfld.long 0x00 17. " CPWAI ,CP14/CP15 wait on idle" "No,Yes"
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bitfld.long 0x00 16. " CPFL ,CP14/CP15 pipeline flush" "No,Yes"
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textline " "
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bitfld.long 0x00 15. " FETMCLK ,Force ETM clock" "No,Yes"
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bitfld.long 0x00 14. " FNCLK ,Force NEON clock" "No,Yes"
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bitfld.long 0x00 13. " FMCLK ,Force main clock" "No,Yes"
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textline " "
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bitfld.long 0x00 12. " FNSI ,Force NEON single issue" "No,Yes"
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bitfld.long 0x00 11. " FLSSI ,Force load/store single issue" "No,Yes"
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bitfld.long 0x00 10. " FSI ,Force single issue" "No,Yes"
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textline " "
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bitfld.long 0x00 9. " PLDNOP ,PLD executes as NOP" "Execute,NOP"
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bitfld.long 0x00 8. " WFINOP ,WFI executes as NOP" "Execute,NOP"
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textline " "
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bitfld.long 0x00 7. " DBSM ,Disable branch size mispredicts" "Enable,Disable"
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bitfld.long 0x00 6. " IBE ,Invalidate BTB Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 5. " L1NEON ,NEON Data Caching Within the L1 Data Cache Enable" "Disable,Enable"
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bitfld.long 0x00 4. " ASA ,Speculative Accesses on AXI Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 3. " L1PE ,L1 Cache Parity Detection Enable" "Disable,Enable"
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bitfld.long 0x00 1. " L2EN ,L2 Cache Enable" "Disable,Enable"
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bitfld.long 0x00 0. " L1ALIAS ,L1 Data Cache Hardware Alias Checks Enable" "Enable,Disable"
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group c15:0x201--0x201
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line.long 0x0 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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group c15:0x11--0x11
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line.long 0x0 "SCR,Secure Configuration Register"
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bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
|
|
bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
|
|
bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
|
|
group c15:0x111--0x111
|
|
line.long 0x0 "SDER,Secure Debug Enable Register"
|
|
bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
group c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " PLE ,PLE Registers Access in Nonsecure World" "Denied,Permitted"
|
|
bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CL ,Lockdown Entries Allocation Within the L2 Cache in Nonsecure World" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CP13 ,Coprocessor 13 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 12. " CP12 ,Coprocessor 12 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CP9 ,Coprocessor 9 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 8. " CP8 ,Coprocessor 8 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CP7 ,Coprocessor 7 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 6. " CP6 ,Coprocessor 6 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CP5 ,Coprocessor 5 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 4. " CP4 ,Coprocessor 4 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CP3 ,Coprocessor 3 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 2. " CP2 ,Coprocessor 2 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CP1 ,Coprocessor 1 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " CP0 ,Coprocessor 0 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
group c15:0x000c++0x00
|
|
line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
|
|
group c15:0x10c--0x10c
|
|
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address"
|
|
textline " "
|
|
rgroup c15:0x1C--0x1C
|
|
line.long 0x0 "ISR,Interrupt status Register"
|
|
bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending"
|
|
bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending"
|
|
bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending"
|
|
tree.end
|
|
width 0x0d
|
|
tree "Memory Management Unit"
|
|
width 8.
|
|
group c15:0x1--0x1
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable"
|
|
bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable"
|
|
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
|
|
textline " "
|
|
group c15:0x3--0x3
|
|
line.long 0x0 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
group c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/decode,Reserved,Imprecise/parity/ECC,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/slave,?..."
|
|
group c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
group c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/parity,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,?..."
|
|
group c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
group c15:0x0015++0x00
|
|
line.long 0x00 "DAFSR,Data Auxiliary Fault Status Register"
|
|
group c15:0x0115++0x00
|
|
line.long 0x00 "IAFSR,Instruction Auxiliary Fault Status Register"
|
|
textline " "
|
|
group c15:0x002A--0x002A
|
|
line.long 0x00 "PMRRR,Primary Memory Region Remap Register"
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
group c15:0x012A--0x012A
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
group c15:0x000d++0x00
|
|
line.long 0x00 "FCSEPID,FCSE PID Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " FCSEPID ,Process for Fast Context Switch Identification and Specification"
|
|
group c15:0x10d--0x10d
|
|
line.long 0x0 "CONTEXT,Context ID Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID"
|
|
hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID"
|
|
group c15:0x020d++0x00
|
|
line.long 0x00 "URWTPID,User Read/Write Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " URWTPID ,User Read/Write Thread and Process ID"
|
|
group c15:0x030d++0x00
|
|
line.long 0x00 "UROTPID,User Read-Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " UROTPID ,User Read-Only Thread and Process ID"
|
|
group c15:0x040d++0x00
|
|
line.long 0x00 "POTPID,Privileged Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " POTPID ,Privileged Only Thread and Process ID"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup c15:0x1100--0x1100
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CTYPE8 ,Cache type for levels 8" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
rgroup c15:0x1000--0x1000
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words"
|
|
group c15:0x2000--0x2000
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/unified,Instruction"
|
|
tree.end
|
|
width 0x8
|
|
tree "L2 Cache Control and Configuration"
|
|
group c15:0x1009++0x00
|
|
line.long 0x00 "L2CLR,L2 Cache Lockdown Register"
|
|
bitfld.long 0x00 7. " LOCK_way_7 ,Way 7 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LOCK_way_6 ,Way 6 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LOCK_way_5 ,Way 5 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOCK_way_4 ,Way 4 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LOCK_way_3 ,Way 3 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LOCK_way_2 ,Way 2 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCK_way_1 ,Way 1 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LOCK_way_0 ,Way 0 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
group c15:0x1209++0x00
|
|
line.long 0x00 "L2CACR,L2 Cache Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " ECCP ,ECC/Parity Selection" "Parity,ECC"
|
|
bitfld.long 0x00 27. " PLDFD ,PLD Forwarding to LS Request Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " PLDD ,PLD Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCD ,Write Combining Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " WADD ,External Linefill When Storing an Entire Line With Write Allocate Permission Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 23. " WACD ,Combining of Data in the L2 Write Combining Buffers Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAD ,Allocate on Write Miss in L2 Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " PECCE ,Parity/ECC Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " L2I ,L2 Inner" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " TRAML ,Program Tag RAM Latency" "2 cycles,2 cycles,3 cycles,4 cycles,4 cycles,4 cycles,4 cycles,4 cycles"
|
|
bitfld.long 0x00 0.--3. " DRAML ,Program Data RAM Latency" "3 cycles,3 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,13 cycles,13 cycles,13 cycles"
|
|
textline " "
|
|
rgroup c15:0x000b++0x00
|
|
line.long 0x00 "PLEISR0,PLE Identification and Status Register 0"
|
|
bitfld.long 0x00 1. " CH1P ,Channel 1 Present" "Not present,Present"
|
|
bitfld.long 0x00 0. " CH0P ,Channel 0 Present" "Not present,Present"
|
|
rgroup c15:0x010b++0x00
|
|
line.long 0x00 "PLEISR1,PLE Identification and Status Register 1"
|
|
bitfld.long 0x00 1. " CH1Q ,Channel 1 Queue" "Not queued,Queued"
|
|
bitfld.long 0x00 0. " CH0Q ,Channel 0 Queue" "Not queued,Queued"
|
|
rgroup c15:0x020b++0x00
|
|
line.long 0x00 "PLEISR2,PLE Identification and Status Register 2"
|
|
bitfld.long 0x00 1. " CH1R ,Channel 1 Run" "Not running,Running"
|
|
bitfld.long 0x00 0. " CH0R ,Channel 0 Run" "Not running,Running"
|
|
rgroup c15:0x030b++0x00
|
|
line.long 0x00 "PLEISR3,PLE Identification and Status Register 3"
|
|
bitfld.long 0x00 1. " CH1I ,Channel 1 Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " CH0I ,Channel 0 Interrupt" "No interrupt,Interrupt"
|
|
group c15:0x001b++0x00
|
|
line.long 0x00 "PLEUAR,PLE User Accessibility Register"
|
|
bitfld.long 0x00 1. " U1 ,User Mode Process Access Registers for Channel 1 Permission" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " U0 ,User Mode Process Access Registers for Channel 0 Permission" "Not permitted,Permitted"
|
|
group c15:0x002b++0x00
|
|
line.long 0x00 "PLECNR,PLE Channel Number Register"
|
|
bitfld.long 0x00 0. " CN ,PLE Channel Selection" "Channel 0,Channel 1"
|
|
wgroup c15:0x003b++0x00
|
|
line.long 0x00 "PLEER0,PLE Enable Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PLEE_STOP ,PLE Enable Stop"
|
|
wgroup c15:0x013b++0x00
|
|
line.long 0x00 "PLEER1,PLE Enable Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PLEE_START ,PLE Enable Start"
|
|
wgroup c15:0x023b++0x00
|
|
line.long 0x00 "PLEER2,PLE Enable Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PLEES_CLEAR ,PLE Enable Clear"
|
|
group c15:0x004b++0x00
|
|
line.long 0x00 "PLECR,PLE Control Register"
|
|
bitfld.long 0x00 30. " DT ,Transfer Direction" "Memory->cache,Cache->memory"
|
|
bitfld.long 0x00 29. " IC ,Interrupt on Completion of the PLE Transfer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IE ,Interrupt on an Error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " UM ,Permission Checks Type" "Privileged,User"
|
|
bitfld.long 0x00 0.--2. " Wy ,L2 Cache Way for Filling Data" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7"
|
|
textline " "
|
|
group c15:0x005b++0x00
|
|
line.long 0x00 "PLEISAR,PLE Internal Start Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " PLEISA ,PLE Internal Start Address"
|
|
group c15:0x007b++0x00
|
|
line.long 0x00 "PLEIEAR,PLE Internal End Address Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " Lines ,Number of Cache Lines Transferred"
|
|
rgroup c15:0x008b++0x00
|
|
line.long 0x00 "PLECSR,PLE Channel Status Register"
|
|
hexmask.long.byte 0x00 2.--8. 1. " EC ,External Address Error Status"
|
|
bitfld.long 0x00 0.--1. " Status ,PLE Channel Status" "Idle,Queued,Running,Complete/error"
|
|
group c15:0x00fb++0x00
|
|
line.long 0x00 "PLECIDR,PLE Context ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,ASID Extension to Form the Process ID and Current Process Identification"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,ASID of the Current Process and the Current ASID Identification"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group c15:0xC9--0xC9
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group c15:0x1C9--0x1C9
|
|
line.long 0x0 "CNTENS,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x2C9--0x2C9
|
|
line.long 0x0 "CNTENC,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x3C9--0x3C9
|
|
line.long 0x0 "FLAG,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group c15:0x4C9--0x4C9
|
|
line.long 0x0 "SWINCR,Software Increment Register"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group c15:0x5C9--0x5C9
|
|
line.long 0x0 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,..."
|
|
group c15:0xD9--0xD9
|
|
line.long 0x0 "PMCCNTR,Cycle Count Register"
|
|
group c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
line.long 0x00 "PMCNT,Performance Monitor Count Register"
|
|
group c15:0xE9--0xE9
|
|
line.long 0x0 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group c15:0x1E9--0x1E9
|
|
line.long 0x0 "INTENS,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group c15:0x2E9--0x2E9
|
|
line.long 0x0 "INTENC,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree.end
|
|
width 8.
|
|
tree "Debug Registers"
|
|
width 10.
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CONTEXT ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 10.
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DBGDSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " nSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
textline " "
|
|
width 10.
|
|
if (((data.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
width 10.
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DBGDTRRX,Debug Receive Register (External View)"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DBGDTRTX,Debug Transmit Register (External View)"
|
|
group c14:0x09++0x00
|
|
line.long 0x00 "DBGECR,Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group c14:0x0a++0x00
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
|
|
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
wgroup c14:0xc0++0x00
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup c14:0xc1++0x00
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
|
|
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
|
|
group c14:0xc2++0x00
|
|
line.long 0x00 "DBGOSSRR,Operating System Save and Restore Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
|
|
group c14:0xc4++0x00
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held"
|
|
bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
|
|
hgroup c14:0xc5++0x00
|
|
hide.long 0x00 "DBGPRSR,Device Power-Down and Reset Status Register"
|
|
in
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "CPUID,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup c14:0x34b--0x34b
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
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|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x355--0x355
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
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width 0xC
|
|
tree "Coresight Management Registers"
|
|
width 17.
|
|
group c14:0x03bd++0x00
|
|
line.long 0x00 "DBGITCTRL_IOC,Integration Internal Output Control Register"
|
|
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
|
|
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I_nPMUIRQ ,Internal nPMUIRQ" "0,1"
|
|
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
|
|
group c14:0x03be++0x00
|
|
line.long 0x00 "DBGITCTRL_EOC,Integration External Output Control Register"
|
|
bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
|
|
bitfld.long 0x00 6. " nDMASIRQ ,External nDMASIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1"
|
|
bitfld.long 0x00 4. " nPMUIRQ ,External nPMUIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
|
|
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
|
|
rgroup c14:0x03bf++0x00
|
|
line.long 0x00 "DBGITCTRL_IS,Integration Input Status Register"
|
|
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
|
|
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
|
|
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " nFIQ ,nFIQ Input" "0,1"
|
|
bitfld.long 0x00 1. " nIRQ ,nIRQ Input" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "DBGLAR,Lock Access Register"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
|
|
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
|
|
width 17.
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
|
|
width 17.
|
|
hgroup c14:0x3f2--0x3f2
|
|
hide.long 0x0 "DBGDEVID,Device Identifier (RESERVED)"
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DBGDEVTYPE,Device Type"
|
|
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x00 "DBGCID0,Debug Component ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x00 "DBGCID1,Debug Component ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x00 "DBGCID2,Debug Component ID 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x00 "DBGCID3,Debug Component ID 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
|
|
tree.end
|
|
tree.end
|
|
width 7.
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x43++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
group c14:0x53++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x44++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
group c14:0x54++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x45++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
group c14:0x55++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 6.
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
tree.end
|
|
tree "CCM (Clock Controller Module)"
|
|
base ad:0x53FD4000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CCR,CCM Control Register"
|
|
bitfld.long 0x00 12. " COSC_EN ,On chip oscillator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CAMP1_EN ,CAMP1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OSCNT ,Oscillator ready counter value"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x04 "CCDR,CCM Control Divider Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CSR,CCM Status Register"
|
|
bitfld.long 0x00 5. " COSC_READY ,Status indication of on board oscillator" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " LVS_VALUE ,Status of the value of pll_lvs output of ccm" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CAMP1_READY ,Status indication of camp1" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " TEMP_MON_ALARM ,Status of input temp_mon_alarm of the Temperature Monitor logic" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REF_EN_B ,Status of the value of ref_en_b output of ccm" "0,1"
|
|
group.long 0x0c++0x13
|
|
line.long 0x00 "CCSR,CCM Clock Switcher Register"
|
|
bitfld.long 0x00 13. " PLL3_PFD_EN ,PFD enable for pll3_sw_clk" "Pll3_main_clk or pll3 bypass,PFD source"
|
|
bitfld.long 0x00 12. " PLL2_PFD_EN ,PFD enable for pll2_sw_clk" "Pll2_main_clk or pll2 bypass,PFD source"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLL1_PFD_EN ,PFD enable for pll1_sw_clk" "Pll1_main_clk or pll1 step,PFD source"
|
|
bitfld.long 0x00 10. " LP_APM ,Low Power Audio Playback source clock" "Oscillator,Fixed 480MHz PLL"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " STEP_SEL ,Step frequency when shifting ARM frequency" "Source 4,Pll bypass,Divided pll2,Divided pll3"
|
|
bitfld.long 0x00 5.--6. " PLL2_DIV_PODF ,Divider for pll2 clock" "/1,/2,/3,/4"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " PLL3_DIV_PODF ,Divider for pll3 clock" "/1,/2,/3,/4"
|
|
bitfld.long 0x00 2. " PLL1_SW_CLK_SEL ,Selects source to generate pll1_sw_clk" "Pll1_main_clk,Step_clk"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLL2_SW_CLK_SEL ,Selects source to generate pll2_sw_clk" "Pll2_main_clk,Pll2 bypass"
|
|
bitfld.long 0x00 0. " PLL3_SW_CLK_SEL ,Selects source to generate pll3_sw_clk" "Pll3_main_clk,Pll3 bypass"
|
|
line.long 0x04 "CACRR,CCM Arm Clock Root Register"
|
|
bitfld.long 0x04 0.--2. " ARM_PODF ,Divider for ARM clock root" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x08 "CBCDR,CCM Bus Clock Divider Register"
|
|
bitfld.long 0x08 27. " WEIM_CLK_SEL ,Selector for weim clock group" "Ahb clock root,Dvfs divider"
|
|
bitfld.long 0x08 25.--26. " PERIPH_CLK_SEL ,Selector for peripheral main clock" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm"
|
|
textline " "
|
|
bitfld.long 0x08 22.--24. " WEIM_PODF ,Divider for weim podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x08 19.--21. " AXI_B_PODF ,Divider for axi b podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " AXI_A_PODF ,Divider for axi a podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
|
|
bitfld.long 0x08 10.--12. " AHB_PODF ,Divider for ahb podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x08 8.--9. " IPG_PODF ,Divider for ipg podf" "/1,/2,/3,/4"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " PERCLK_PRED1 ,Divider for perclk pred1" "/1,/2,/3,/4"
|
|
bitfld.long 0x08 3.--5. " PERCLK_PRED2 ,Divider for perclk pred2" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " PERCLK_PODF ,Divider for perclk podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
width 9.
|
|
line.long 0x0c "CBCMR,CCM Bus Clock Multiplexer Register"
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bitfld.long 0x0c 16.--17. " GPU2D_CLK_SEL ,Selector for gpu2d clock multiplexer" "Axi a,Axi b,Weim_clk_root,Ahb clock root"
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bitfld.long 0x0C 2.--3. " DEBUG_APB_CLK_SEL ,Selector for debug apb clock multiplexer" "Axi a,Axi b,Weim_clk_root,Ahb clock root"
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textline " "
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bitfld.long 0x0C 1. " PERCLK_LP_APM_SEL ,Peripherals main clock/lp_apm selection" "Peripherals main clock,Lp_apm"
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bitfld.long 0x0C 0. " PERCLK_IPG_SEL ,Selector for perclk multiplexer" "Division of pll frequency,Ipg_clk"
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line.long 0x10 "CSCMR1,CCM Serial Clock Multiplexer Register 1"
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bitfld.long 0x10 30.--31. " SSI_EXT2_CLK_SEL ,Selector for ssi_ext2 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Ssi_lp_apm_clk"
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bitfld.long 0x10 28.--29. " SSI_EXT1_CLK_SEL ,Selector for ssi_ext1 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Ssi_lp_apm_clk"
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textline " "
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bitfld.long 0x10 24.--25. " UART_CLK_SEL ,Selector for uart clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock"
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bitfld.long 0x10 21.--22. " ESDHC1_CLK_SEL ,Selector for esdhc1 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock"
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textline " "
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bitfld.long 0x10 20. " ESDHC2_CLK_SEL ,Selector for esdhc2 clock multiplexer" "Esdhc1_clk_sel,Esdhc3_clk_sel"
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bitfld.long 0x10 19. " ESDHC4_CLK_SEL ,Selector for esdhc4 clock multiplexer" "Esdhc1_clk_sel,Esdhc3_clk_sel"
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textline " "
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bitfld.long 0x10 16.--18. " ESDHC3_CLK_SEL ,Selector for esdhc3 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock,PFD0,PFD1,PFD4,Osc_clk"
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bitfld.long 0x10 14.--15. " SSI1_CLK_SEL ,Selector for ssi1 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Ssi_lp_apm_clk"
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textline " "
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bitfld.long 0x10 12.--13. " SSI2_CLK_SEL ,Selector for ssi2 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Ssi_lp_apm_clk"
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bitfld.long 0x10 8. " SSI_APM_CLK_SEL ,Controlls the multiplexer for the ssi_lp_apm_clk clock generation" "CAMP1 of CKIH,LP-APM clk. sel. out"
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textline " "
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bitfld.long 0x10 4.--5. " ECSPI_CLK_SEL ,Selector for ecspi clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock"
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bitfld.long 0x10 1. " SSI_EXT2_COM ,Controlls the multiplexer to communize ssi_ext2 clock generation based on ssi2 clock root" "Dividers,Ssi2_clk_root"
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textline " "
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bitfld.long 0x10 0. " SSI_EXT1_COM ,Controlls the multiplexer to communize ssi_ext1 clock generation based on ssi1 clock root" "Dividers,Ssi1_clk_root"
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hgroup.long 0x20++0x03
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hide.long 0x00 "CSCMR2,CCM Serial Clock Multiplexer Register 2"
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group.long 0x24++0x0B
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line.long 0x00 "CSCDR1,CCM Serial Clock Divider Register 1"
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bitfld.long 0x00 22.--24. " ESDHC2_CLK_PRED ,Divider for esdhc2 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x00 19.--21. " ESDHC3_CLK_PODF ,Divider for esdhc3 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8"
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textline " "
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bitfld.long 0x00 16.--18. " ESDHC1_CLK_PRED ,Divider for esdhc1 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x00 14.--15. " PGC_CLK_PODF ,Divider for pgc (power gating controler) clock podf" "/1,/2,/4,/8"
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textline " "
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bitfld.long 0x00 11.--13. " ESDHC1_CLK_PODF ,Divider for esdhc1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x00 3.--5. " UART_CLK_PRED ,Divider for uart clock pred" "/1,/2,/3,/4,/5,/6,/7,/8"
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textline " "
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bitfld.long 0x00 0.--2. " UART_CLK_PODF ,Divider for uart clock podf" "/1,/2,/3,/4,/5,/6,/7,/8"
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line.long 0x04 "CS1CDR,CCM SSI1 Clock Divider Register"
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bitfld.long 0x04 22.--24. " SSI_EXT1_CLK_PRED ,Divider for ssi_ext1 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x04 16.--21. " SSI_EXT1_CLK_PODF ,Divider for ssi_ext1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
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textline " "
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bitfld.long 0x04 6.--8. " SSI1_CLK_PRED ,Divider for ssi1 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x04 0.--5. " SSI1_CLK_PODF ,Divider for ssi1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
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line.long 0x08 "CS2CDR,CCM SSI2 Clock Divider Register"
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bitfld.long 0x08 22.--24. " SSI_EXT2_CLK_PRED ,Divider for ssi_ext2 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x08 16.--21. " SSI_EXT2_CLK_PODF ,Divider for ssi_ext2 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
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textline " "
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bitfld.long 0x08 6.--8. " SSI2_CLK_PRED ,Divider for ssi2 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x08 0.--5. " SSI2_CLK_PODF ,Divider for ssi2 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
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hgroup.long 0x30++0x07
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hide.long 0x00 "CDCDR,CCM DI Clock Divider Register"
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hide.long 0x04 "CHSCCDR,CCM HSC Clock Divider Register"
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group.long 0x38++0x03
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line.long 0x00 "CSCDR2,CCM Serial Clock Divider Register 2"
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bitfld.long 0x00 25.--27. " ECSPI_CLK_PRED ,Divider for ecspi clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x00 19.--24. " ECSPI_CLK_PODF ,Divider for ecspi clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
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hgroup.long 0x3C++0x0B
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hide.long 0x00 "CSCDR3,CCM Serial Clock Divider Register 3"
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hide.long 0x04 "CSCDR4,CCM Serial Clock Divider Register 4"
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hide.long 0x08 "CWDR,CCM Wakeup Detector Register"
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rgroup.long 0x48++0x03
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line.long 0x00 "CDHIPR,CCM Divider Handshake In-Process Register"
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bitfld.long 0x00 16. " ARM_PODF_BUSY ,Busy indicator for arm_podf" "Not busy,Busy"
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bitfld.long 0x00 6. " WEIM_CLK_SEL_BUSY ,Busy indicator for gcm weim_clk_sel" "Not busy,Busy"
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textline " "
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bitfld.long 0x00 5. " PERIPH_CLK_SEL_BUSY ,Busy indicator for periph_clk_sel mux control" "Not busy,Busy"
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bitfld.long 0x00 3. " AHB_PODF_BUSY ,Busy indicator for ahb_podf" "Not busy,Busy"
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textline " "
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bitfld.long 0x00 2. " WEIM_PODF_BUSY ,Busy indicator for weim_podf" "Not busy,Busy"
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bitfld.long 0x00 1. " AXI_B_PODF_BUSY ,Busy indicator for axi_b_podf" "Not busy,Busy"
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textline " "
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bitfld.long 0x00 0. " AXI_A_PODF_BUSY ,Busy indicator for axi_a_podf" "Not busy,Busy"
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width 9.
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group.long 0x4c++0x17
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line.long 0x00 "CDCR,CCM DVFS Control Register"
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eventfld.long 0x00 7. " SW_PERIPH_CLK_DIV_REQ_STATUS ,Status bit to define the operation of DVFS driver in case of software control of DVFS divider" "Not finished,Finished"
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textline " "
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bitfld.long 0x00 6. " SW_PERIPH_CLK_DIV_REQ ,Start DVFS frequency division operation" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 5. " SOFTWARE_DVFS_EN ,Software DVFS Enabled" "Periph_clk_div_req,Sw_periph_clk_div_req"
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textline " "
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bitfld.long 0x00 2. " ARM_FREQ_SHIFT_DIVIDER ,ARM domain done through" "Pll relock,Arm_podf change"
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textline " "
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bitfld.long 0x00 0.--1. " PERIPH_CLK_DVFS_PODF ,Divider value for next operation of peripheral dvfs" "Reserved,/2,/3,/4"
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line.long 0x04 "CTOR,CCM Testing Observability Register"
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bitfld.long 0x04 13. " OBS_EN ,Observability enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 8.--12. " OBS_SPARE_OUTPUT_0_SEL ,Signal to be generated on CCM_OUT_0 (output of CCM) for observability on the pads" "Ccm_system_in_stop_mode,Lpm_current_state[0],Hndsk_current_state[0],Shd_current_state[0],Ccm_ipg_stop,Ccm_pdn_4arm_req,Reserved,Reserved,Reserved,Reserved,Pll_lrf_sticky1,Reserved,Clk_src_on,Reserved,Src_warm_dvfs_req,Periph_clk_div_req,Arm_clk_switch_req,Ccm_clk_switch_ack,Reserved,Weim_lpmd,Reserved,Reserved,Reserved,Reserved,Reserved,Obs_input_6,Obs_input_0,Obs_input_1,Obs_input_2,Obs_input_3,Obs_input_4,Obs_input_5"
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textline " "
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bitfld.long 0x04 4.--7. " OBS_SPARE_OUTPUT_1_SEL ,Selection of the signal to be generated on obs_output_1 for observability on the pads" "Ccm_system_in_wait_mode,Lpm_current_state[1],Hndsk_current_state[1],Reserved,Ccm_ipg_wait,Ccm_camp_dis,Dpll_en_dpllip,Ccm_pdn_4all_req,Reserved,Reserved,Reserved,Reserved,Arm_dsm_request,Reserved,Gpc_pup_ack,Pll_lrf_sticky2"
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textline " "
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bitfld.long 0x04 0.--3. " OBS_SPARE_OUTPUT_2_SEL ,Selection of the signal to be generated on obs_output_2 for observability on the pads" "Reserved,Lpm_current_state[2],Hndsk_current_state[2],Shd_current_state[1],Pll_lvs,Src_clock_ready,Ref_clk_en_dpllip,Ccm_pup_req,Weim_lpack,Reserved,Reserved,Reserved,Src_power_gating_reset_done,Tzic_dsm_wakeup,Gpc_pdn_ack,Pll_lrf_sticky3"
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line.long 0x08 "CLPCR,CCM Low Power Control Register"
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bitfld.long 0x08 25. " BYPASS_MAX_LPM_HS ,Bypass handshake with max on next entrance to low power mode" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 24. " BYPASS_SDMA_LPM_HS ,Bypass handshake with sdma on next entrance to low power mode" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 23. " BYPASS_RNGB_LPM_HS ,Bypass handshake with rngb on next entrance to low power mode" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 19. " BYPASS_WEIM_LPM_HS ,Bypass handshake with weimon next entrance to low power mode" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 11. " COSC_PWRDOWN ,Control powering down of on chip oscillator" "Not powered down,Powered down"
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textline " "
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bitfld.long 0x08 9.--10. " STBY_COUNT ,Standby counter definition" "2 ckil clocks,4 ckil clocks,8 ckil clocks,16 ckil clocks"
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textline " "
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bitfld.long 0x08 8. " VSTBY ,Voltage standby request" "Not requested,Requested"
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textline " "
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bitfld.long 0x08 7. " DIS_REF_OSC ,External reference oscillator clock disable" "No,Yes"
|
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textline " "
|
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bitfld.long 0x08 6. " SBYOS ,Standby clock oscillator" "Enabled/Not powered down,Disabled/Powered down"
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textline " "
|
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bitfld.long 0x08 5. " ARM_CLK_DIS_ON_LPM ,ARM clocks disabled on wait mode" "No,Yes"
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textline " "
|
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bitfld.long 0x08 2. " BYPASS_PMIC_VFUNCTIONAL_READY ,Bypass pmic vfunctional" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 0.--1. " LPM ,Low power mode" "Remain in run mode,Transfer to wait mode,Transfer to stop mode,Transfer to LPSR mode"
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line.long 0x0c "CISR,CCM Interrupt Status Register"
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eventfld.long 0x0C 26. " ARM_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of arm_podf" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 25. " TEMP_MON_ALARM ,Interrupt ipi_int_1 generated due to alarm event by the temperature monitor" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 23. " EMI_CLK_SEL_LOADED ,Interrupt ipi_int_1 generated due to update of emi_clk_sel" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 22. " PERIPH_CLK_SEL_LOADED ,Interrupt ipi_int_1 generated due to update of periph_clk_sel" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 20. " AHB_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of ahb_podf" "No interrupt,Interrupt"
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textline " "
|
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eventfld.long 0x0C 19. " WEIM_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of weim_podf" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 18. " AXI_B_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of axi_b_podf" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 17. " AXI_A_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of axi_a_podf" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 16. " DIVIDERS_LOADED ,Interrupt ipi_int_1 generated due to updated of axi_a_podf/axi_b_podf/emi_slow_podf/ahb_podf/nfc_podf/periph_clk_sel/emi_clk_sel" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 6. " COSC_READY ,Interrupt ipi_int_2 generated due to on board oscillator ready" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 4. " CAMP1_READY ,Interrupt ipi_int_2 generated due to camp1 ready" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 2. " LRF_PLL3 ,Interrupt ipi_int_2 generated due to lock of pll3" "No interrupt,Interrupt"
|
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textline " "
|
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eventfld.long 0x0C 1. " LRF_PLL2 ,Interrupt ipi_int_2 generated due to lock of pll2" "No interrupt,Interrupt"
|
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textline " "
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eventfld.long 0x0C 0. " LRF_PLL1 ,Interrupt ipi_int_2 generated due to lock of pll1" "No interrupt,Interrupt"
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line.long 0x10 "CIMR,CCM Interrupt Mask Register"
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bitfld.long 0x10 26. " ARM_PODF_LOADED ,Mask interrupt generation due to frequency change of arm_podf" "Not masked,Masked"
|
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textline " "
|
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bitfld.long 0x10 25. " TEMP_MON_ALARM ,Mask interrupt generation due to temperature monitor alarm event" "Not masked,Masked"
|
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textline " "
|
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bitfld.long 0x10 23. " MASK_WEIM_CLK_SEL_LOADED ,Mask interrupt generation due to update of weim_clk_sel" "Not masked,Masked"
|
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textline " "
|
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bitfld.long 0x10 22. " MASK_PERIPH_CLK_SEL_LOADED ,Mask interrupt generation due to update of periph_clk_sel" "Not masked,Masked"
|
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textline " "
|
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bitfld.long 0x10 20. " MASK_AHB_PODF_LOADED ,Mask interrupt generation due to frequency change of ahb_podf" "Not masked,Masked"
|
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textline " "
|
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bitfld.long 0x10 19. " MASK_WEIM_PODF_LOADED ,Mask interrupt generation due to frequency change of weim_podf" "Not masked,Masked"
|
|
textline " "
|
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bitfld.long 0x10 18. " MASK_AXI_B_PODF_LOADED ,Mask interrupt generation due to frequency change of axi_b_podf" "Not masked,Masked"
|
|
textline " "
|
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bitfld.long 0x10 17. " MASK_AXI_A_PODF_LOADED ,Mask interrupt generation due to frequency change of axi_a_podf" "Not masked,Masked"
|
|
textline " "
|
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bitfld.long 0x10 16. " MASK_DIVIDERS_LOADED ,Mask interrupt generation due to updated of axi_a_podf, axi_b_podf, emi_slow_podf, ahb_podf, nfc_podf, periph_clk_sel, emi_clk_sel" "Not masked,Masked"
|
|
textline " "
|
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bitfld.long 0x10 7. " MASK_KPP_WAKEUP_DET ,Mask interrupt generation due to key press detection" "Not masked,Masked"
|
|
textline " "
|
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bitfld.long 0x10 6. " MASK_COSC_READY ,Mask interrupt generation due to on board oscillator ready" "Not masked,Masked"
|
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textline " "
|
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bitfld.long 0x10 4. " MASK_CAMP1_READY ,Mask interrupt generation due to camp1 ready" "Not masked,Masked"
|
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textline " "
|
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bitfld.long 0x10 2. " MASK_LRF_PLL3 ,Mask interrupt generation due to lrf of pll3" "Not masked,Masked"
|
|
textline " "
|
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bitfld.long 0x10 1. " MASK_LRF_PLL2 ,Mask interrupt generation due to lrf of pll2" "Not masked,Masked"
|
|
textline " "
|
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bitfld.long 0x10 0. " MASK_LRF_PLL1 ,Mask interrupt generation due to lrf of pll1" "Not masked,Masked"
|
|
width 9.
|
|
line.long 0x14 "CCOSR,CCM Clock Output Source Register"
|
|
bitfld.long 0x14 24. " CKO2_EN ,Enable of CKO2 clock" "Disabled,Enabled"
|
|
bitfld.long 0x14 21.--23. " CKO2_DIV ,Setting the divider of CKO2" "/1,/2,/3,/4,/5,/6,/7,/8"
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textline " "
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bitfld.long 0x14 16.--20. " CKO2_SEL ,Selection of the clock to be generated on cko2" "Reserved,Reserved,Display_axi_clk_root,Esdhc1_clk_root,Reserved,Wrck_clk_root,Ecspi_clk_root,Pll1_ref_clk,Esdhc3_clk_root,Ddr_clk_root,Reserved,Usbphy_pll_out_480,Gpu2d_clk_root,Debug_apb_clk_root,Osc_clk,Ckih_camp1_clk,Esdhc4_clk_root,Esdhc2_clk_root,Ssi1_clk_root,Ssi2_clk_root,Gpmi_clk_root,Epdc_axi_clk_root,Reserved,Pgc_clk_root,Bch_clk_root,Usb_phy_clk_root,Reserved,Lp_apm clock,Uart_clk_root,Sys_clk,Mshc_xmscki_clk_root,Async_ref_clock_obs div 8"
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bitfld.long 0x14 8. " CKO1_SLOW_SEL ,Select of CKO1 slow clocks" "Fast,Slow"
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textline " "
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bitfld.long 0x14 7. " CKO1_EN ,Enable of CKO1 clock" "Disabled,Enabled"
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bitfld.long 0x14 4.--6. " CKO1_DIV ,Setting the divider of CKO1" "/1,/2,/3,/4,/5,/6,/7,/8"
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textline " "
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bitfld.long 0x14 0.--3. " CKO1_SEL ,Selection of the clock to be generated on cko1 fast clocks" "Ref_480pll_clk,Ref_pfd0_clk,Ref_pfd1_clk,Ref_pfd2_clk,Ref_pfd3_clk,Ref_pfd4_clk,Ref_pfd5_clk,Ref_pfd6_clk,Epdc_pix_clk_root,Elcdif_pix_clk_root,Weim_clk_root,Ahb_clk_root,Ipg_clk_root,Perclk_root,Ckil_sync_clk_root,Ref_pfd7_clk"
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hgroup.long 0x64++0x03
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hide.long 0x18 "CGPR,CCM General Purpose Register"
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width 7.
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group.long 0x68++0x1F
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line.long 0x00 "CCGR0,CCM Clock Gating Register 0"
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bitfld.long 0x00 28.--29. " CG14 ,Clock gating for power reduction of AHBMAX-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x00 26.--27. " CG13 ,Clock gating for power reduction of AIPSTZ2-ahb_clk_root clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x00 24.--25. " CG12 ,Clock gating for power reduction of AIPSTZ1-ahb_clk_root clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x00 22.--23. " CG11 ,Clock gating for power reduction of ROM-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x00 20.--21. " CG10 ,Clock gating for power reduction of ROMCP-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x00 16.--17. " CG08 ,Clock gating for power reduction of AHBMUX1-ahb_clk_root(Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x00 14.--15. " CG07 ,Clock gating for power reduction of CTI3-debug_apb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x00 12.--13. " CG06 ,Clock gating for power reduction of CTI2-debug_apb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x00 10.--11. " CG05 ,Clock gating for power reduction of TPIU-tpiu clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x00 8.--9. " CG04 ,Clock gating for power reduction of CoreSight Debug AccessPort (DAP) - ahb_clk_root clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x00 6.--7. " CG03 ,Clock gating for power reduction of TZIC-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x00 4.--5. " CG02 ,Clock gating for power reduction of ARM Cortex A8-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x00 0.--1. " CG00 ,Clock gating for power reduction of ARM Cortex A8-ipg_clk_root(Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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line.long 0x04 "CCGR1,CCM Clock Gating Register 1"
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bitfld.long 0x04 22.--23. " CG11 ,Clock gating for power reduction of I2C3-perclk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x04 20.--21. " CG10 ,Clock gating for power reduction of I2C2-perclk_root clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x04 18.--19. " CG09 ,Clock gating for power reduction of I2C1-perclk_root clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x04 16.--17. " CG08 ,Clock gating for power reduction of UART3-uart_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x04 14.--15. " CG07 ,Clock gating for power reduction of UART3-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x04 12.--13. " CG06 ,Clock gating for power reduction of UART2-uart_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x04 10.--11. " CG05 ,Clock gating for power reduction of UART2-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x04 8.--9. " CG04 ,Clock gating for power reduction of UART1-uart_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x04 6.--7. " CG03 ,Clock gating for power reduction of UART1-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x04 2.--3. " CG01 ,Clock gating for power reduction of TMAX2-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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line.long 0x08 "CCGR2,CCM Clock Gating Register 2"
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bitfld.long 0x08 26.--27. " CG13 ,Clock gating for power reduction of USBOH1-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x08 24.--25. " CG12 ,Clock gating for power reduction of FEC-ipg_clk_root clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x08 22.--23. " CG11 ,Clock gating for power reduction of OWIRE-perclk_root clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x08 20.--21. " CG10 ,Clock gating for power reduction of GPT-perclk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x08 18.--19. " CG09 ,Clock gating for power reduction of GPT-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x08 16.--17. " CG08 ,Clock gating for power reduction of PWM2-perclk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x08 14.--15. " CG07 ,Clock gating for power reduction of PWM2-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x08 12.--13. " CG06 ,Clock gating for power reduction of PWM1-perclk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x08 10.--11. " CG05 ,Clock gating for power reduction of PWM1-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x08 4.--5. " CG02 ,Clock gating for power reduction of EPIT1-perclk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x08 2.--3. " CG01 ,Clock gating for power reduction of EPIT1-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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line.long 0x0C "CCGR3,CCM Clock Gating Register 3"
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bitfld.long 0x0C 30.--31. " CG15 ,Clock gating for power reduction of EPIT0 PAD - ssi2e_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x0C 28.--29. " CG14 ,Clock gating for power reduction of OWIRE PAD - ssi1e_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x0C 22.--23. " CG11 ,Clock gating for power reduction of SSI2-ssi1_clk_root(Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x0C 20.--21. " CG10 ,Clock gating for power reduction of SSI2-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x0C 18.--19. " CG09 ,Clock gating for power reduction of SSI1-ssi_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x0C 16.--17. " CG08 ,Clock gating for power reduction of SSI1-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x0C 14.--15. " CG07 ,Clock gating for power reduction of eSDHCv2_4-esdhc4_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x0C 12.--13. " CG06 ,Clock gating for power reduction of eSDHCv2_4-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x0C 10.--11. " CG05 ,Clock gating for power reduction of eSDHCv3_3-esdhc3_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x0C 8.--9. " CG04 ,Clock gating for power reduction of eSDHCv3_3-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x0C 6.--7. " CG03 ,Clock gating for power reduction of eSDHCv2_2-esdhc2_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x0C 4.--5. " CG02 ,Clock gating for power reduction of eSDHCv2_2-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x0C 2.--3. " CG01 ,Clock gating for power reduction of eSDHCv2_1-esdhc1_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x0C 0.--1. " CG00 ,Clock gating for power reduction of eSDHCv2_1-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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line.long 0x10 "CCGR4,CCM Clock Gating Register 4"
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bitfld.long 0x10 30.--31. " CG15 ,Clock gating for power reduction of SDMA-ahb_clk_root clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x10 28.--29. " CG14 ,Clock gating for power reduction of SRTC- clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x10 26.--27. " CG13 ,Clock gating for power reduction of CSPI-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x10 24.--25. " CG12 ,Clock gating for power reduction of ECSPI2 - ecspi_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x10 22.--23. " CG11 ,Clock gating for power reduction of ECSPI2 - ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x10 20.--21. " CG10 ,Clock gating for power reduction of ECSPI1 - ecspi_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x10 18.--19. " CG09 ,Clock gating for power reduction of ECSPI1 - ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x10 12.--13. " CG6 ,Clock gating for power reduction of USBPHY2 - usb_phy_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x10 10.--11. " CG5 ,Clock gating for power reduction of USBPHY1-usb_phy_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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line.long 0x14 "CCGR5,CCM Clock Gating Register 5"
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bitfld.long 0x14 24.--25. " CG12 ,Clock gating for power reduction of GPC-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x14 18.--19. " CG09 ,Clock gating for power reduction of EMI-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x14 16.--17. " CG08 ,Clock gating for power reduction of EMI-weim_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x14 12.--13. " CG06 ,Clock gating for power reduction of IPMUX1-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x14 0.--1. " CG00 ,Clock gating for power reduction of SPBA-ipg_clk_root clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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line.long 0x18 "CCGR6,CCM Clock Gating Register 6"
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bitfld.long 0x18 30.--31. " CG15 ,Clock gating for power reduction of DRAM MC - ahb_clk_root clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x18 28.--29. " CG14 ,Clock gating for power reduction of CCM Analog - ahb_clk_root clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x18 20.--21. " CG10 ,Clock gating for power reduction of LCDIF-ahb_clk_root clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x18 18.--19. " CG09 ,Clock gating for power reduction of PXP-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x18 18.--19. " CG08 ,Clock gating for power reduction of EPDC-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x18 14.--15. " CG07 ,Clock gating for power reduction of gpu2d-gpu2d_clk_root clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x18 12.--13. " CG06 ,Clock gating for power reduction of LCDIF-elcdif_pix_clk_root clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x18 10.--11. " CG05 ,Clock gating for power reduction of EPDC-epdc_pix_clk_root clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x18 8.--9. " CG04 ,Clock gating for power reduction of MSHC-mshc_xmscki_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x18 2.--3. " CG01 ,Clock gating for power reduction of OCRAM-sys_clk_root (CTRL) clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x18 0.--1. " CG00 ,Clock gating for power reduction of IPMUX2-ahb_clk_root clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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line.long 0x1C "CCGR7,CCM Clock Gating Register 7"
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bitfld.long 0x1C 30.--31. " CG15 ,Clock gating for power reduction of DIGCTRL-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x1C 28.--29. " CG14 ,Clock gating for power reduction of MSHC-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x1C 26.--27. " CG12 ,Clock gating for power reduction of OCOTP-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x1C 24.--25. " CG12 ,Clock gating for power reduction of BCH-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x1C 22.--23. " CG11 ,Clock gating for power reduction of DCP-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x1C 20.--21. " CG10 ,Clock gating for power reduction of APBH-BRIDGE-DMA-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x1C 18.--19. " CG09 ,Clock gating for power reduction of GPMI-gpmi_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x1C 16.--17. " CG08 ,Clock gating for power reduction of GPMI-ahb_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x1C 14.--15. " CG07 ,Clock gating for power reduction of UART5-uart_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x1C 12.--13. " CG06 ,Clock gating for power reduction of UART5-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x1C 10.--11. " CG05 ,Clock gating for power reduction of UART4-uart_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x1C 8.--9. " CG04 ,Clock gating for power reduction of UART4-ipg_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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textline " "
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bitfld.long 0x1C 2.--3. " CG01 ,Clock gating for power reduction of RNGB-ipg_clk_root (CTRL)-sys_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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bitfld.long 0x1C 0.--1. " CG00 ,Clock gating for power reduction of BCH-bch_clk_root (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,On/On/On,On/On/Off"
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width 15.
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group.long 0x88++0x2F
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line.long 0x00 "CMEOR,CCM Module Enable Override Register"
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bitfld.long 0x00 10. " MOD_EN_OV_GPU2D ,Overide clock enable signal from gpu2d" "Not overridden,Overridden"
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bitfld.long 0x00 8. " MOD_EN_OV_DAP ,Overide clock enable signal from dap" "Not overridden,Overridden"
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textline " "
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bitfld.long 0x00 6. " MOD_EN_OV_EPIT ,Overide clock enable signal from epit" "Not overridden,Overridden"
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bitfld.long 0x00 5. " MOD_EN_OV_GPT ,Overide clock enable signal from gpt" "Not overridden,Overridden"
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|
textline " "
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bitfld.long 0x00 4. " MOD_EN_OV_ESDHC ,Overide clock enable signal from esdhc" "Not overridden,Overridden"
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bitfld.long 0x00 2. " MOD_EN_OV_OWIRE ,Overide clock enable signal from owire" "Not overridden,Overridden"
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line.long 0x04 "CSR2,CCM Control Status Register 2"
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bitfld.long 0x04 13. " EPDC_ASM_ACTIVE ,Auto Slow Mode is actively slowing down the epdc_axi_clk" "Not active,Active"
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bitfld.long 0x04 12. " EPXP_ASM_ACTIVE ,Auto Slow Mode is actively slowing down the epxp_axi_clk" "Not active,Active"
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textline " "
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bitfld.long 0x04 11. " ELCDIF_ASM_ACTIVE ,Auto Slow Mode is actively slowing down the elcdif_axi_clk" "Not active,Active"
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bitfld.long 0x04 10. " SYS_CLK_XTAL_ACTIVE ,24MHz xtal is active clock from the glitchless clock mux between xtal and pll sources" "Xtal Active,PLL/PFD"
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textline " "
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bitfld.long 0x04 9. " ELCDIF_PIX_BUSY ,Divider change in progress for elcdif_pix_div" "Completed,In progress"
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bitfld.long 0x04 8. " EPDC_PIX_BUSY ,Divider change in progress for epdc_pix_div" "Completed,In progress"
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|
textline " "
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bitfld.long 0x04 7. " MSHC_XMSCKI_BUSY ,Divider change in progress for mshc_xmscki_div" "Completed,In progress"
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|
bitfld.long 0x04 6. " BCH_BUSY ,Divider change in progress for bch_div" "Completed,In progress"
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|
textline " "
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bitfld.long 0x04 5. " GPMI_BUSY ,Divider change in progress for gpmi_div" "Completed,In progress"
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|
bitfld.long 0x04 4. " EPDC_AXI_BUSY ,Divider change in progress for epdc_axi_div" "Completed,In progress"
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|
textline " "
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bitfld.long 0x04 3. " DISPLAY_AXI_BUSY ,Divider change in progress for display_axi_div" "Completed,In progress"
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|
bitfld.long 0x04 2. " DDR_CLK_REF_PLL_BUSY ,Divider change in progress for ddr_div_pll" "Completed,In progress"
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textline " "
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bitfld.long 0x04 1. " SYS_CLK_REF_PLL_BUSY ,Divider change in progress for sys_div_pll" "Completed,In progress"
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|
bitfld.long 0x04 0. " SYS_CLK_REF_XTAL_BUSY ,Divider change in progress for sys_div_xtal" "Completed,In progress"
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|
line.long 0x08 "CLKSEQ_BYPASS,CCM Clock Sequence Bypass"
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bitfld.long 0x08 14.--15. " BYPASS_ELCDIF_PIX_CLK ,Mux select between 24 MHz xtal and PLL/PFD clock sources for elcdif_pix_clk" "24MHz xtal,PFD6,PLL1,Camp1"
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bitfld.long 0x08 12.--13. " BYPASS_EPDC_PIX_CLK ,Mux select between 24 MHz xtal and PLL/PFD clock sources for epdc_pix_clk" "24MHz xtal,PFD5,PLL1,Camp1"
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textline " "
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bitfld.long 0x08 10.--11. " BYPASS_MSHC_XMSCKI_CLK ,Mux select between 24 MHz xtal and PLL/PFD clock sources for mshc_xmscki" "24 MHz xtal,PFD7,PLL1,?..."
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bitfld.long 0x08 8.--9. " BYPASS_BCH_CLK ,Mux select between 24 MHz xtal and PLL/PFD clock sources for bch_clk" "24 MHz xtal,PFD4,PLL1,?..."
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|
textline " "
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bitfld.long 0x08 6.--7. " BYPASS_GPMI_CLK ,Mux select between 24 MHz xtal and PLL/PFD clock sources for gpmi_clk" "24 MHz xtal,PFD4,PLL1,?..."
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bitfld.long 0x08 4.--5. " BYPASS_EPDC_AXI_CLK ,Mux select between 24 MHz xtal and PLL/PFD clock sources for epdc_axi_clk" "24 MHz xtal,PFD3,PLL1,?..."
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|
textline " "
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bitfld.long 0x08 2.--3. " BYPASS_DISPLAY_AXI_CLK ,Mux select between 24 MHz xtal and PLL/PFD clock sources for display_axi_clk" "24 MHz xtal,PFD2,PLL1,?..."
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bitfld.long 0x08 1. " BYPASS_SYS_CLK ,Mux select between PFD1 and PLL clock sources for sys_clk" "PFD1,PLL1"
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textline " "
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bitfld.long 0x08 0. " BYPASS_SYS_CLK ,Mux select between 24 MHz xtal and PLL/PFD clock sources for sys_clk" "24 MHz xtal,PFD1/PLL"
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line.long 0x0C "CLK_SYS,CCM System Clock Register"
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bitfld.long 0x0C 30.--31. " SYS_XTAL_CLKGATE ,Enable/Disable sys_clk xtal source clock divider" "Gated off,ON in run / OFF wait & stop,Always on,All modes - except stop"
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bitfld.long 0x0C 28.--29. " SYS_PLL_CLKGATE ,Enable/Disable sys_clk PLL/PFD source clock divider" "Gated off,ON in run / OFF wait & stop,Always on,All modes - except stop"
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textline " "
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bitfld.long 0x0C 6.--9. " SYS_DIV_XTAL ,Divide field for sys_clk 24MHz xtal clock divider" "Off,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15"
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bitfld.long 0x0C 0.--5. " SYS_DIV_PLL ,Divide field for sys_clk PLL/PFD clock divider" "Off,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
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line.long 0x10 "CLK_DDR,CCM DDR Clock Register"
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bitfld.long 0x10 30.--31. " DDR_CLKGATE ,Enable/Disable asynchronous ddr_clk PLL/PFD source clock divider" "Gated off,ON in run / OFF wait & stop,Always on,All modes - except stop"
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bitfld.long 0x10 6. " DDR_PFD_SEL ,Selects between PLL and PFD reference clocks for the asynchronous ddr clock divider" "Select PLL,Select PFD0"
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|
textline " "
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bitfld.long 0x10 0.--5. " DDR_DIV_PLL ,Divide field for ddr_clk PLL/PFD clock divider" "Off,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
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line.long 0x14 "ELCDIFPIX,CCM ELCDIF PIX Clock Serial Divide Register"
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bitfld.long 0x14 30.--31. " ELCDIF_PIX_CLKGATE ,Enable/Disable asynchronous elcdif_pix_clk source clock divider" "Gated off,ON in run / OFF wait & stop,Always on,All modes - except stop"
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bitfld.long 0x14 12.--13. " ELCDIF_CLK_PRED ,Divider for elcdif pix clock pred" "Off,/1,/2,/3"
|
|
textline " "
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hexmask.long.word 0x14 0.--11. 1. " ELCDIF_PIX_CLK_PODF ,Divider for elcdif clock podf"
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line.long 0x18 "EPDCPIX,CCM EPDC PIX Clock Serial Divide Register"
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bitfld.long 0x18 30.--31. " EPDC_PIX_CLKGATE ,Enable/Disable asynchronous elcdif_pix_clk source clock divider" "Gated off,ON in run / OFF wait & stop,Always on,All modes - except stop"
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bitfld.long 0x18 12.--13. " ELCDIF_CLK_PRED ,Divider for elcdif pix clock pred" "Off,/1,/2,/3"
|
|
textline " "
|
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hexmask.long.word 0x18 0.--11. 1. " ELCDIF_PIX_CLK_PODF ,Divider for elcdif clock podf"
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line.long 0x1C "DISPLAY_AXI,CCM DISPLAY_AXI Clock Divide Register"
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bitfld.long 0x1C 30.--31. " DISPLAY_AXI_CLKGATE ,Enable/Disable asynchronous epdc_axi_clk source clock divider" "Gated off,ON in run / OFF wait & stop,Always on,All modes - except stop"
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bitfld.long 0x1C 13. " EPXP_ASM_EN ,Enable Auto slow Mode for epxp_axi clock" "Enabled,Disabled"
|
|
textline " "
|
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bitfld.long 0x1C 10.--12. " EPXP_ASM_SLOW_DIV ,EPXP auto slow mode divide" "Not auto slowed,/2,/4,/8,/16,/32,?..."
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bitfld.long 0x1C 9. " ELCDIF_ASM_EN ,Enable Auto slow Mode for elcdif_axi clock" "Enabled,Disbaled"
|
|
textline " "
|
|
bitfld.long 0x1C 6.--8. " ELCDIF_ASM_SLOW_DIV ,Elcdif auto slow mode divide" "Not auto slowed,/2,/4,/8,/16,/32,?..."
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|
bitfld.long 0x1C 0.--5. " DISPLAY_AXI_DIV ,Divider for display_axi clock" "Off,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
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line.long 0x20 "EPDC_AXI,CCM EPDC_AXI Clock Divide Register"
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bitfld.long 0x20 30.--31. " EPDC_AXI_CLKGATE ,Enable/Disable asynchronous epdc_axi_clk source clock divider" "Gated off,ON in run / OFF wait & stop,Always on,All modes - except stop"
|
|
bitfld.long 0x20 9. " EPDC_ASM_EN ,Enable Auto slow Mode for epdc_axi clock" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x20 6.--8. " EPDC_ASM_SLOW_DIV ,Elcdif auto slow mode divide" "Not auto slowed,/2,/4,/8,/16,/32,?..."
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|
bitfld.long 0x20 0.--5. " EPDC_AXI_DIV ,Divider for epdc_axi clock" "Off,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
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line.long 0x24 "GPMI,CCM GPMI Clock Divide Register"
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bitfld.long 0x24 30.--31. " GPMI_CLKGATE ,Enable/Disable asynchronous gpmi_clk source clock divider" "Gated off,ON in run / OFF wait & stop,Always on,All modes - except stop"
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bitfld.long 0x24 0.--5. " GPMI_DIV ,Divider for gpmi clock" "Off,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
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line.long 0x28 "BCH,CCM BCH Clock Divide Register"
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bitfld.long 0x28 30.--31. " BCH_CLKGATE ,Enable/Disable asynchronous bch_clk source clock divider" "Gated off,ON in run / OFF wait & stop,Always on,All modes - except stop"
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bitfld.long 0x28 0.--5. " BCH_DIV ,Divider for bch clock" "Off,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
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line.long 0x2C "MSHC_XMSCKI,CCM MSHC_XMSCKI Clock Divide Register"
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bitfld.long 0x2C 30.--31. " MSHC_XMSCKI_CLKGATE ,Enable/Disable asynchronous mshc_xmscki_clk source clock divider" "Gated off,ON in run / OFF wait & stop,Always on,All modes - except stop"
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bitfld.long 0x2C 0.--5. " MSHC_XMSCKI_DIV ,Divider for mshc_xmscki clock" "Off,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63"
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width 0xb
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tree.end
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tree "CCM Analog"
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base ad:0x41018000
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width 20.
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group.long 0x10++0x0F
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line.long 0x00 "ANALOG_FRAC0,Fractional Clock Control Register 0"
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bitfld.long 0x00 31. " PFD3_CLKGATE ,IO Clock Gate" "On,Off"
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rbitfld.long 0x00 30. " PFD3_STABLE ,PFD3 STABLE" "Low,High"
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bitfld.long 0x00 24.--29. " PFD3_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD3_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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textline " "
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bitfld.long 0x00 23. " PFD2_CLKGATE ,IO Clock Gate" "On,Off"
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rbitfld.long 0x00 22. " PFD2_STABLE ,PFD2 STABLE" "Low,High"
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bitfld.long 0x00 16.--21. " PFD2_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD2_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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textline " "
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bitfld.long 0x00 15. " PFD1_CLKGATE ,IO Clock Gate" "On,Off"
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rbitfld.long 0x00 14. " PFD1_STABLE ,PFD1 STABLE" "Low,High"
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bitfld.long 0x00 8.--13. " PFD1_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD1_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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textline " "
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bitfld.long 0x00 7. " PFD0_CLKGATE ,IO Clock Gate" "On,Off"
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rbitfld.long 0x00 6. " PFD0_STABLE ,PFD0 STABLE" "Low,High"
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bitfld.long 0x00 0.--5. " PFD0_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD0_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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line.long 0x04 "ANALOG_FRAC0_SET,Fractional Clock SET Register 0"
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bitfld.long 0x04 31. " PFD3_CLKGATE ,IO Clock Gate" "On,Off"
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rbitfld.long 0x04 30. " PFD3_STABLE ,PFD3 STABLE" "Low,High"
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bitfld.long 0x04 24.--29. " PFD3_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD3_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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textline " "
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bitfld.long 0x04 23. " PFD2_CLKGATE ,IO Clock Gate" "On,Off"
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rbitfld.long 0x04 22. " PFD2_STABLE ,PFD2 STABLE" "Low,High"
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bitfld.long 0x04 16.--21. " PFD2_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD2_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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textline " "
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bitfld.long 0x04 15. " PFD1_CLKGATE ,IO Clock Gate" "On,Off"
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rbitfld.long 0x04 14. " PFD1_STABLE ,PFD1 STABLE" "Low,High"
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bitfld.long 0x04 8.--13. " PFD1_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD1_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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textline " "
|
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bitfld.long 0x04 7. " PFD0_CLKGATE ,IO Clock Gate" "On,Off"
|
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rbitfld.long 0x04 6. " PFD0_STABLE ,PFD0 STABLE" "Low,High"
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bitfld.long 0x04 0.--5. " PFD0_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD0_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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line.long 0x08 "ANALOG_FRAC0_CLR,Fractional Clock CLR Register 0"
|
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bitfld.long 0x08 31. " PFD3_CLKGATE ,IO Clock Gate" "On,Off"
|
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rbitfld.long 0x08 30. " PFD3_STABLE ,PFD3 STABLE" "Low,High"
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bitfld.long 0x08 24.--29. " PFD3_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD3_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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textline " "
|
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bitfld.long 0x08 23. " PFD2_CLKGATE ,IO Clock Gate" "On,Off"
|
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rbitfld.long 0x08 22. " PFD2_STABLE ,PFD2 STABLE" "Low,High"
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bitfld.long 0x08 16.--21. " PFD2_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD2_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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textline " "
|
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bitfld.long 0x08 15. " PFD1_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x08 14. " PFD1_STABLE ,PFD1 STABLE" "Low,High"
|
|
bitfld.long 0x08 8.--13. " PFD1_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD1_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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textline " "
|
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bitfld.long 0x08 7. " PFD0_CLKGATE ,IO Clock Gate" "On,Off"
|
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rbitfld.long 0x08 6. " PFD0_STABLE ,PFD0 STABLE" "Low,High"
|
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bitfld.long 0x08 0.--5. " PFD0_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD0_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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line.long 0x0C "ANALOG_FRAC0_TOG,Fractional Clock TOG Register 0"
|
|
bitfld.long 0x0C 31. " PFD3_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x0C 30. " PFD3_STABLE ,PFD3 STABLE" "Low,High"
|
|
bitfld.long 0x0C 24.--29. " PFD3_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD3_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 23. " PFD2_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x0C 22. " PFD2_STABLE ,PFD2 STABLE" "Low,High"
|
|
bitfld.long 0x0C 16.--21. " PFD2_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD2_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
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textline " "
|
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bitfld.long 0x0C 15. " PFD1_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x0C 14. " PFD1_STABLE ,PFD1 STABLE" "Low,High"
|
|
bitfld.long 0x0C 8.--13. " PFD1_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD1_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 7. " PFD0_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x0C 6. " PFD0_STABLE ,PFD0 STABLE" "Low,High"
|
|
bitfld.long 0x0C 0.--5. " PFD0_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD0_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "ANALOG_FRAC1,Fractional Clock Control Register 1"
|
|
bitfld.long 0x00 31. " PFD7_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x00 30. " PFD7_STABLE ,PFD7 STABLE" "Low,High"
|
|
bitfld.long 0x00 24.--29. " PFD7_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD7_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFD6_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x00 22. " PFD6_STABLE ,PFD6 STABLE" "Low,High"
|
|
bitfld.long 0x00 16.--21. " PFD6_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD6_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " PFD5_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x00 14. " PFD5_STABLE ,PFD5 STABLE" "Low,High"
|
|
bitfld.long 0x00 8.--13. " PFD5_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD5_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " PFD4_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x00 6. " PFD4_STABLE ,PFD4 STABLE" "Low,High"
|
|
bitfld.long 0x00 0.--5. " PFD4_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD4_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
line.long 0x04 "ANALOG_FRAC1_SET,Fractional Clock SET Register 1"
|
|
bitfld.long 0x04 31. " PFD7_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x04 30. " PFD7_STABLE ,PFD7 STABLE" "Low,High"
|
|
bitfld.long 0x04 24.--29. " PFD7_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD7_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x04 23. " PFD6_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x04 22. " PFD6_STABLE ,PFD6 STABLE" "Low,High"
|
|
bitfld.long 0x04 16.--21. " PFD6_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD6_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x04 15. " PFD5_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x04 14. " PFD5_STABLE ,PFD5 STABLE" "Low,High"
|
|
bitfld.long 0x04 8.--13. " PFD5_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD5_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " PFD4_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x04 6. " PFD4_STABLE ,PFD4 STABLE" "Low,High"
|
|
bitfld.long 0x04 0.--5. " PFD4_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD4_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
line.long 0x08 "ANALOG_FRAC1_CLR,Fractional Clock CLR Register 1"
|
|
bitfld.long 0x08 31. " PFD7_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x08 30. " PFD7_STABLE ,PFD7 STABLE" "Low,High"
|
|
bitfld.long 0x08 24.--29. " PFD7_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD7_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x08 23. " PFD6_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x08 22. " PFD6_STABLE ,PFD6 STABLE" "Low,High"
|
|
bitfld.long 0x08 16.--21. " PFD6_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD6_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x08 15. " PFD5_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x08 14. " PFD5_STABLE ,PFD5 STABLE" "Low,High"
|
|
bitfld.long 0x08 8.--13. " PFD5_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD5_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x08 7. " PFD4_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x08 6. " PFD4_STABLE ,PFD4 STABLE" "Low,High"
|
|
bitfld.long 0x08 0.--5. " PFD4_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD4_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
line.long 0x0C "ANALOG_FRAC1_TOG,Fractional Clock TOG Register 1"
|
|
bitfld.long 0x0C 31. " PFD7_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x0C 30. " PFD7_STABLE ,PFD7 STABLE" "Low,High"
|
|
bitfld.long 0x0C 24.--29. " PFD7_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD7_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 23. " PFD6_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x0C 22. " PFD6_STABLE ,PFD6 STABLE" "Low,High"
|
|
bitfld.long 0x0C 16.--21. " PFD6_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD6_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 15. " PFD5_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x0C 14. " PFD5_STABLE ,PFD5 STABLE" "Low,High"
|
|
bitfld.long 0x0C 8.--13. " PFD5_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD5_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 7. " PFD4_CLKGATE ,IO Clock Gate" "On,Off"
|
|
rbitfld.long 0x0C 6. " PFD4_STABLE ,PFD4 STABLE" "Low,High"
|
|
bitfld.long 0x0C 0.--5. " PFD4_FRAC ,Controls the IO clocks fractional divider 480 * (18/PFD4_FRAC)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,480,454.74,432,411.43,392.73,375.65,360,345.6,332.31,320,308.57,297.93,288,278.71,270,261.82,254.12,246.86,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,?..."
|
|
group.long 0x60++0xF
|
|
line.long 0x00 "ANALOG_MISC,Miscellaneous Register Description"
|
|
bitfld.long 0x00 20. " REF_SELFBIAS_OFF ,Controls the source of the reference bias currents" "Low,High"
|
|
bitfld.long 0x00 18. " REF_PWD ,Powers down the bandgap reference" "Low,High"
|
|
bitfld.long 0x00 16. " CHGR_DET_DISABLE ,Disables the charget detect function" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHGR_FORCE_DET ,Asserts the open drain CHGR_DET_B pin regardless of the detector output" "Low,High"
|
|
rbitfld.long 0x00 14. " CHGR_DETECTED ,Status bit reflecting the state CHGR_DET_B pin" "Not asserted,Asserted"
|
|
bitfld.long 0x00 7. " PLL_HOLD_RING_OFF ,Hold ring off bit is essential when starting the APLL" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PLL_POWERUP ,PLL Power On" "Off,On"
|
|
line.long 0x04 "ANALOG_MISC_SET,Miscellaneous Register Description"
|
|
bitfld.long 0x04 20. " REF_SELFBIAS_OFF ,Controls the source of the reference bias currents" "Low,High"
|
|
bitfld.long 0x04 18. " REF_PWD ,Powers down the bandgap reference" "Low,High"
|
|
bitfld.long 0x04 16. " CHGR_DET_DISABLE ,Disables the charget detect function" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 15. " CHGR_FORCE_DET ,Asserts the open drain CHGR_DET_B pin regardless of the detector output" "Low,High"
|
|
rbitfld.long 0x04 14. " CHGR_DETECTED ,Status bit reflecting the state CHGR_DET_B pin" "Not asserted,Asserted"
|
|
bitfld.long 0x04 7. " PLL_HOLD_RING_OFF ,Hold ring off bit is essential when starting the APLL" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PLL_POWERUP ,PLL Power On" "Off,On"
|
|
line.long 0x08 "ANALOG_MISC_CLR,Miscellaneous Register Description"
|
|
bitfld.long 0x08 20. " REF_SELFBIAS_OFF ,Controls the source of the reference bias currents" "Low,High"
|
|
bitfld.long 0x08 18. " REF_PWD ,Powers down the bandgap reference" "Low,High"
|
|
bitfld.long 0x08 16. " CHGR_DET_DISABLE ,Disables the charget detect function" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 15. " CHGR_FORCE_DET ,Asserts the open drain CHGR_DET_B pin regardless of the detector output" "Low,High"
|
|
rbitfld.long 0x08 14. " CHGR_DETECTED ,Status bit reflecting the state CHGR_DET_B pin" "Not asserted,Asserted"
|
|
bitfld.long 0x08 7. " PLL_HOLD_RING_OFF ,Hold ring off bit is essential when starting the APLL" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PLL_POWERUP ,PLL Power On" "Off,On"
|
|
line.long 0x0C "ANALOG_MISC_TOG,Miscellaneous Register Description"
|
|
bitfld.long 0x0C 20. " REF_SELFBIAS_OFF ,Controls the source of the reference bias currents" "Low,High"
|
|
bitfld.long 0x0C 18. " REF_PWD ,Powers down the bandgap reference" "Low,High"
|
|
bitfld.long 0x0C 16. " CHGR_DET_DISABLE ,Disables the charget detect function" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " CHGR_FORCE_DET ,Asserts the open drain CHGR_DET_B pin regardless of the detector output" "Low,High"
|
|
rbitfld.long 0x0C 14. " CHGR_DETECTED ,Status bit reflecting the state CHGR_DET_B pin" "Not asserted,Asserted"
|
|
bitfld.long 0x0C 7. " PLL_HOLD_RING_OFF ,Hold ring off bit is essential when starting the APLL" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " PLL_POWERUP ,PLL Power On" "Off,On"
|
|
group.long 0x70++0x0F
|
|
line.long 0x00 "ANALOG_PLLCTRL,PLL Control Register"
|
|
rbitfld.long 0x00 31. " LOCK ,PLL0 Lock" "Unlocked,Locked"
|
|
bitfld.long 0x00 30. " FORCE_LOCK ,Force the PLL0 Lock sequence to start" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PFD_DISABLE_MASK ,Determines which PFDs are disabled when the disable_pfds_n is asserted"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " LOCK_COUNT ,Status of the PLL0 lock count"
|
|
line.long 0x04 "ANALOG_PLLCTRL_SET,PLL Control Register"
|
|
rbitfld.long 0x04 31. " LOCK ,PLL0 Lock" "Unlocked,Locked"
|
|
bitfld.long 0x04 30. " FORCE_LOCK ,Force the PLL0 Lock sequence to start" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PFD_DISABLE_MASK ,Determines which PFDs are disabled when the disable_pfds_n is asserted"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " LOCK_COUNT ,Status of the PLL0 lock count"
|
|
line.long 0x08 "ANALOG_PLLCTRL_CLR,PLL Control Register"
|
|
rbitfld.long 0x08 31. " LOCK ,PLL0 Lock" "Unlocked,Locked"
|
|
bitfld.long 0x08 30. " FORCE_LOCK ,Force the PLL0 Lock sequence to start" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 16.--23. 1. " PFD_DISABLE_MASK ,Determines which PFDs are disabled when the disable_pfds_n is asserted"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--15. 1. " LOCK_COUNT ,Status of the PLL0 lock count"
|
|
line.long 0x0C "ANALOG_PLLCTRL_TOD,PLL Control Register"
|
|
rbitfld.long 0x0C 31. " LOCK ,PLL0 Lock" "Unlocked,Locked"
|
|
bitfld.long 0x0C 30. " FORCE_LOCK ,Force the PLL0 Lock sequence to start" "Disabled,Enabled"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PFD_DISABLE_MASK ,Determines which PFDs are disabled when the disable_pfds_n is asserted"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--15. 1. " LOCK_COUNT ,Status of the PLL0 lock count"
|
|
width 0x0b
|
|
tree.end
|
|
tree "ARM CORTEX Platform Control"
|
|
base ad:0x63FA0000
|
|
width 6.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PVID,Platform Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SPEC ,Major architectural or significant spec changes"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IMPL ,Implementation changes"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MINOR ,Minor changes"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ECO ,ECO changes"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GPC,General Purpose Control Register"
|
|
bitfld.long 0x00 31. " DBGACTIVE ,Status of debug" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " NOCLKSTP ,Control clock-gating within the CORTEX-A8n" "Within the CORTEX-A8n,Normal"
|
|
bitfld.long 0x00 17. " ATRDY ,Platform boundary ATB interface disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
hexmask.long.word 0x00 0.--15. 1. " GPC ,General Purpose Control"
|
|
endif
|
|
sif (cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&cpu()!="IMX508"&&cpu()!="IMX507"&&cpu()!="IMX503"&&cpu()!="IMX502"&&cpu()!="IMX50")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIC,Platform Internal Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PIC ,Platform Internal Control"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "LPC,Low Power Control Register"
|
|
bitfld.long 0x00 1. " DBGDSM ,Debug Deep Sleep Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSM ,Deep Sleep Mode Enable" "Disabled,Enabled"
|
|
line.long 0x04 "NLPC,NEON Low Power Control Register"
|
|
bitfld.long 0x04 0. " NEONRST ,Neon Reset State" "From reset,Into reset"
|
|
line.long 0x08 "ICGC,Internal Clock Generation Control Register"
|
|
bitfld.long 0x08 11. " DT_PRLD ,Debug AMBA Trace Bus Clock Down Counter Preload" "No effect,Forced"
|
|
bitfld.long 0x08 8.--10. " DT_CLK_DIVR ,Debug AMBA Trace Bus Clock Divide Ratio" "1:1,2:1,3:1,4:1,5:1,6:1,7:1,8:1"
|
|
bitfld.long 0x08 7. " ACLK_PRLD ,AXI Master Port Clock Down Counter Preload" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " ACLK_DIVR ,AXI Master Port Clock Divide Ratio" "1:1,2:1,3:1,4:1,5:1,6:1,7:1,8:1"
|
|
bitfld.long 0x08 3. " IPG_PRLD ,Platform IP-Bus Port Clock Down Counter Preload" "No effect,Forced"
|
|
bitfld.long 0x08 0.--2. " IPG_CLK_DIVR ,Platform IP-Bus Port Clock Divide Ratio" "1:1,2:1,3:1,4:1,5:1,6:1,7:1,8:1"
|
|
line.long 0x0C "AMC,ARM Memory Configuration Register"
|
|
bitfld.long 0x0C 3. " ALPEN ,ALP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--2. " ALP ,Memory leakage configuration" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "NMC,NEON Monitor Control Register"
|
|
bitfld.long 0x00 31. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " NME ,NEON Monitor Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--19. 1. " PL ,Preload value for the upper 8 bits of the 16 bit NEON activity counter"
|
|
line.long 0x04 "NMS,NEON Monitor Status Register"
|
|
eventfld.long 0x04 31. " NI ,NEON Idle Status" "Not expired,Expired"
|
|
width 0xb
|
|
tree.end
|
|
tree.open "ARM Platform Debug"
|
|
tree "DAP ROM"
|
|
base ad:0x40000000
|
|
width 9.
|
|
rgroup.long 0xfd0++0x03
|
|
line.long 0x00 "PERID4,Peripheral ID4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID3 Register"
|
|
line.long 0x10 "COMPID0,Component ID0 Register"
|
|
line.long 0x14 "COMPID1,Component ID1 Register"
|
|
line.long 0x18 "COMPID2,Component ID2 Register"
|
|
line.long 0x1c "COMPID3,Component ID3 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "ETB"
|
|
base ad:0x40001000
|
|
width 13.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "RDP,RAM Depth Register"
|
|
rgroup.long 0x0c++0x0b
|
|
line.long 0x00 "STS,Status Register"
|
|
bitfld.long 0x00 3. " FTEMPTY ,Ft Empty" "Low,High"
|
|
bitfld.long 0x00 2. " ACQCOMP ,Acq Comp" "Low,High"
|
|
bitfld.long 0x00 1. " TRG ,Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " FULL ,Full" "Not full,Full"
|
|
line.long 0x04 "RRD,RAM Read Register"
|
|
line.long 0x08 "RRP,RAM Read Pointer Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " RRP ,RAM Read Pointer"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "RWP,RAM Write Pointer Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " RWP ,RAM Write Pointer"
|
|
group.long 0x1c++0x0b
|
|
line.long 0x00 "TRG,Trigger Counter Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " TRG ,Trigger Counter"
|
|
line.long 0x04 "CTL,Control Register"
|
|
bitfld.long 0x04 0. " TRACECAPTEN ,Trace Capt Enable" "Disabled,Enabled"
|
|
line.long 0x08 "RWD,RAM Write Data Register"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "FFS,Formatter Flush Status Register"
|
|
bitfld.long 0x00 1. " FTSTOPPED ,Formatter Stopped" "Not stopped,Stopped"
|
|
bitfld.long 0x00 0. " FLINPROG ,Flush Interrupt Prog" "No interrupt,Interrupt"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "FFCR,Formatter and Flush Ctl Register"
|
|
bitfld.long 0x00 13. " STOPTRIG ,Stop Trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 12. " STOPFL ,Stop Flush" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TRIGFL ,Trigger Flush" "Not triggered,Triggered"
|
|
bitfld.long 0x00 9. " TRIGEVT ,Trigger Event" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRIGIN ,Trigger Interrupt" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " FONMAN ,FOn Man" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FONTRIG ,FOn Trigger" "Low,High"
|
|
bitfld.long 0x00 4. " FONFLIN ,FOn Fl In" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENFCONT ,Enable F Cont" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENWFTC ,Enable W FTC" "Disabled,Enabled"
|
|
wgroup.long 0xee0++0x0B
|
|
line.long 0x00 "ITMISCOP0,Int Test Misc Output Register"
|
|
bitfld.long 0x00 1. " FULL ,FULL" "Not full,Full"
|
|
bitfld.long 0x00 0. " ACQCOMP ,ACQ COMP" "Low,High"
|
|
line.long 0x04 "ITTRFLINACK,Int Test Trig In and Flush In Ack Register"
|
|
bitfld.long 0x04 1. " FLUSHINACK ,Flush Interrupt ACK" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " TRIGINACK ,Trigger Interrupt ACK" "No interrupt,Interrupt"
|
|
line.long 0x08 "ITTRFLIN,Int Test Trig In and Flush In Register"
|
|
bitfld.long 0x08 1. " FLUSHIN ,Flush Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " TRIGIN ,Trigger Interrupt" "No interrupt,Interrupt"
|
|
rgroup.long 0xeec++0x03
|
|
line.long 0x00 "ITATBDATA0,Interrupt Test ATB Data Register 0"
|
|
bitfld.long 0x00 4. " ATDATA[31] ,AT Data [31]" "Low,High"
|
|
bitfld.long 0x00 3. " ATDATA[23] ,AT Data [23]" "Low,High"
|
|
bitfld.long 0x00 2. " ATDATA[15] ,AT Data [15]" "Low,High"
|
|
bitfld.long 0x00 1. " ATDATA[7] ,AT Data [7]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ATDATA[0] ,AT Data [0]" "Low,High"
|
|
wgroup.long 0xef0++0x07
|
|
line.long 0x00 "ITATBCTR2,Interrupt Test ATB Control Register 2"
|
|
bitfld.long 0x00 1. " AFVALID ,AF Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " AFREADY ,AF Ready" "Not ready,Ready"
|
|
line.long 0x04 "ITATBCTR1,Interrupt Test ATB Control Register 1"
|
|
hexmask.long.byte 0x04 0.--6. 1. " ATID ,ATID"
|
|
rgroup.long 0xef8++0x03
|
|
line.long 0x00 "ITATBCTR0,Interrupt Test ATB Control Register 0"
|
|
bitfld.long 0x00 8.--9. " ATBYTES ,AT Bytes" "0,1,2,3"
|
|
bitfld.long 0x00 1. " AFREADY ,AF Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ATVALID ,AT Valid" "Not valid,Valid"
|
|
rgroup.long 0xfb8++0x03
|
|
line.long 0x00 "AUTHSTS,Authentication Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AUTHSTS ,Authentication Status"
|
|
rgroup.long 0xfc8++0x07
|
|
line.long 0x00 "DEVID,Device ID Register"
|
|
line.long 0x04 "DEVTID,Device Type Identifier Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DEVTID ,Device Type Identifier"
|
|
rgroup.long 0xfe4++0x03
|
|
line.long 0x00 "PN[B:8],Part Number Register"
|
|
hexmask.long.byte 0x00 0.--4. 1. " PN ,Part Number [B:8]"
|
|
rgroup.long 0xfe0++0x03
|
|
line.long 0x00 "PN[7:0],Part Number [7:0]"
|
|
width 0xb
|
|
tree.end
|
|
tree "ETM"
|
|
base ad:0x40002000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ECR,ETM Control Register"
|
|
bitfld.long 0x00 25.--27. " CSEL ,Core Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24. " INRESACCCTR ,Instrumentation resources access control" "Privileged & User,Privileged"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DISSOFTWR ,Disable soft write" "No,Yes"
|
|
bitfld.long 0x00 22. " DISREGWR ,Disable register write" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DOMODE ,Data only mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " FLTR ,Filter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SUPPRRD ,Suppress data" "Low,High"
|
|
bitfld.long 0x00 14.--15. " CONTIDS ,Context ID size" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 13. 16.--17. " PMODE , Port mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12. " CACCTRACE ,Cyc accurate trace" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EPORTSEL ,ETM port selection" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " EPROG ,ETM prog" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DBGREQCNTL ,Debug request control" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " BRANCHOUTP ,Branch output" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STALLPROC ,Stall proc" "Low,High"
|
|
bitfld.long 0x00 4.--6. 21. " PSIZE ,Port size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DACCESS ,Data access" "0,1,2,3"
|
|
bitfld.long 0x00 1. " MONITORCPRT ,Monitor cprt" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EPWRDWN ,ETM power-down" "Power-up,Power-down"
|
|
rgroup.long 0x04++0x07
|
|
line.long 0x00 "CCR,Configuration Control Register"
|
|
bitfld.long 0x00 31. " ALL ,Indicates that the ETMIDR register 0x79 present" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CPMMSUP ,CP and MM supported" "Not supported,Supported"
|
|
bitfld.long 0x00 26. " TRCSTRTSTOPBP ,Trace start/ stop blk present" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " NUMCIDCOM ,Number of Context ID comparators" "0,1,2,3"
|
|
bitfld.long 0x00 23. " FIFOFULLLOGP ,Fifo full logic present" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " NUMEXTOUT ,Numb of external ouputs" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17.--19. " NUMEXTIN ,Numb of external inputs" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SEQP ,Seq present" "Low,High"
|
|
bitfld.long 0x00 13.--15. " NUMCNTRS ,Number of counters" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " NUMMEMMAODEC ,Number of memory map decoders" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " NUMDATCOMP ,Number of data comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " NUMADDRCOMPPA ,Number of address comparator pairs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TER,Trigger Event Register"
|
|
bitfld.long 0x04 16. " FNC[2] ,Function 2" "Low,High"
|
|
bitfld.long 0x04 15. " FNC[1] ,Function 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 14. " FNC[0] ,Function 0" "Low,High"
|
|
hexmask.long.byte 0x04 7.--13. 1. " RESB ,Resource B"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " RESA ,Resource A"
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "ASICCTRL,ASIC control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASICCTRL ,ASIC control"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ESR,ETM Status Register"
|
|
bitfld.long 0x00 3. " TRGFLG ,Trigger flag" "Low,High"
|
|
bitfld.long 0x00 2. " TRCSSRS ,Trace start/stop resource status" "Stopped,Started"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PROGBIT ,Prog bit" "Low,High"
|
|
rbitfld.long 0x00 0. " UNTROVRFLFLG ,Untraced overflow flag" "Low,High"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SCR,System Configuration Register"
|
|
bitfld.long 0x00 17. " NFC ,Nofetch comparison" "Low,High"
|
|
bitfld.long 0x00 12.--14. " NUMSC ,Number of supported cores minus 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PMS ,Port mode supported" "Not supported,Supported"
|
|
bitfld.long 0x00 10. " PSS ,Port size supported" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FIFIOFS ,Fifo full supported" "Not supported,Supported"
|
|
hexmask.long.byte 0x00 3.--7. 1. " SCR[7:3] ,System Configuration"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. 9. " MAXPS ,Max port size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((d.l(ad:0x40002000+0x1e8))&0x800)==0x800)
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "TSSRCR,Trace Start/Stop Res. Control Register"
|
|
line.long 0x04 "TECR2,Trace Enable Control 2 Register"
|
|
bitfld.long 0x04 15. " INEXCTRLCMP[16] ,Sets include/exclude control comparator 16" "Exclude,Include"
|
|
bitfld.long 0x04 14. " INEXCTRLCMP[15] ,Sets include/exclude control comparator 15" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INEXCTRLCMP[14] ,Sets include/exclude control comparator 14" "Exclude,Include"
|
|
bitfld.long 0x04 12. " INEXCTRLCMP[13] ,Sets include/exclude control comparator 13" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INEXCTRLCMP[12] ,Sets include/exclude control comparator 12" "Exclude,Include"
|
|
bitfld.long 0x04 10. " INEXCTRLCMP[11] ,Sets include/exclude control comparator 11" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INEXCTRLCMP[10] ,Sets include/exclude control comparator 10" "Exclude,Include"
|
|
bitfld.long 0x04 8. " INEXCTRLCMP[9] ,Sets include/exclude control comparator 9" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INEXCTRLCMP[8] ,Sets include/exclude control comparator 8" "Exclude,Include"
|
|
bitfld.long 0x04 6. " INEXCTRLCMP[7] ,Sets include/exclude control comparator 7" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INEXCTRLCMP[6] ,Sets include/exclude control comparator 6" "Exclude,Include"
|
|
bitfld.long 0x04 4. " INEXCTRLCMP[5] ,Sets include/exclude control comparator 5" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INEXCTRLCMP[4] ,Sets include/exclude control comparator 4" "Exclude,Include"
|
|
bitfld.long 0x04 2. " INEXCTRLCMP[3] ,Sets include/exclude control comparator 3" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INEXCTRLCMP[2] ,Sets include/exclude control comparator 2" "Exclude,Include"
|
|
bitfld.long 0x04 0. " INEXCTRLCMP[1] ,Sets include/exclude control comparator 1" "Exclude,Include"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TECR1,Trace Enable Control1 Register"
|
|
bitfld.long 0x00 25. " TRCCONTEN ,Trace Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INCLEXCLFLG ,Incl/Excl flag" "Low,High"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--23. 1. " MMDCONT ,MMD control"
|
|
bitfld.long 0x00 7. " ADDRCMP[8] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ADDRCMP[7] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 5. " ADDRCMP[6] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADDRCMP[5] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 3. " ADDRCMP[4] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADDRCMP[3] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 1. " ADDRCMP[2] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 0. " ADDRCMP[1] ,Address Comparator 8" "Low,High"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TRCENEV,Trace Enable Event Register"
|
|
bitfld.long 0x00 15. " TRCENEV[15] ,Trace Enable Event 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TRCENEV[14] ,Trace Enable Event 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TRCENEV[13] ,Trace Enable Event 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TRCENEV[12] ,Trace Enable Event 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TRCENEV[11] ,Trace Enable Event 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TRCENEV[10] ,Trace Enable Event 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TRCENEV[09] ,Trace Enable Event 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TRCENEV[08] ,Trace Enable Event 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TRCENEV[07] ,Trace Enable Event 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TRCENEV[06] ,Trace Enable Event 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TRCENEV[05] ,Trace Enable Event 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRCENEV[04] ,Trace Enable Event 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TRCENEV[03] ,Trace Enable Event 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TRCENEV[02] ,Trace Enable Event 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRCENEV[01] ,Trace Enable Event 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TRCENEV[00] ,Trace Enable Event 0" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFOFRR,FIFOFULL Region Register"
|
|
bitfld.long 0x00 24. " INCL/EXCLFLG ,Incl/ Excl flag" "Low,High"
|
|
bitfld.long 0x00 23. " MMDCONT[16] ,MMD control 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MMDCONT[15] ,MMD control 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MMDCONT[14] ,MMD control 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MMDCONT[13] ,MMD control 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MMDCONT[12] ,MMD control 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MMDCONT[11] ,MMD control 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MMDCONT[10] ,MMD control 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MMDCONT[09] ,MMD control 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MMDCONT[08] ,MMD control 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MMDCONT[07] ,MMD control 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MMDCONT[06] ,MMD control 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MMDCONT[05] ,MMD control 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MMDCONT[04] ,MMD control 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MMDCONT[03] ,MMD control 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MMDCONT[02] ,MMD control 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MMDCONT[01] ,MMD control 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ADDRCMP[8] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ADDRCMP[7] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 5. " ADDRCMP[6] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADDRCMP[5] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 3. " ADDRCMP[4] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADDRCMP[3] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 1. " ADDRCMP[2] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADDRCMP[1] ,Address Comparator 8" "Low,High"
|
|
else
|
|
wgroup.long 0x18++0x07
|
|
line.long 0x00 "TSSRCR,Trace Start/Stop Res. Control Register"
|
|
line.long 0x04 "TECR2,Trace Enable Control 2 Register"
|
|
bitfld.long 0x04 15. " INEXCTRLCMP[16] ,Sets include/exclude control comparator 16" "Exclude,Include"
|
|
bitfld.long 0x04 14. " INEXCTRLCMP[15] ,Sets include/exclude control comparator 15" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INEXCTRLCMP[14] ,Sets include/exclude control comparator 14" "Exclude,Include"
|
|
bitfld.long 0x04 12. " INEXCTRLCMP[13] ,Sets include/exclude control comparator 13" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INEXCTRLCMP[12] ,Sets include/exclude control comparator 12" "Exclude,Include"
|
|
bitfld.long 0x04 10. " INEXCTRLCMP[11] ,Sets include/exclude control comparator 11" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INEXCTRLCMP[10] ,Sets include/exclude control comparator 10" "Exclude,Include"
|
|
bitfld.long 0x04 8. " INEXCTRLCMP[9] ,Sets include/exclude control comparator 9" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INEXCTRLCMP[8] ,Sets include/exclude control comparator 8" "Exclude,Include"
|
|
bitfld.long 0x04 6. " INEXCTRLCMP[7] ,Sets include/exclude control comparator 7" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INEXCTRLCMP[6] ,Sets include/exclude control comparator 6" "Exclude,Include"
|
|
bitfld.long 0x04 4. " INEXCTRLCMP[5] ,Sets include/exclude control comparator 5" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INEXCTRLCMP[4] ,Sets include/exclude control comparator 4" "Exclude,Include"
|
|
bitfld.long 0x04 2. " INEXCTRLCMP[3] ,Sets include/exclude control comparator 3" "Exclude,Include"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INEXCTRLCMP[2] ,Sets include/exclude control comparator 2" "Exclude,Include"
|
|
bitfld.long 0x04 0. " INEXCTRLCMP[1] ,Sets include/exclude control comparator 1" "Exclude,Include"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "TECR1,Trace Enable Control1 Register"
|
|
bitfld.long 0x00 25. " TRCCONTEN ,Trace Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INCLEXCLFLG ,Incl/ Excl flag" "Low,High"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--23. 1. " MMDCONT ,MMD control"
|
|
bitfld.long 0x00 7. " ADDRCMP[8] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ADDRCMP[7] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 5. " ADDRCMP[6] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 4. " ADDRCMP[5] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRCMP[4] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 2. " ADDRCMP[3] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADDRCMP[2] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 0. " ADDRCMP[1] ,Address Comparator 8" "Low,High"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "TRCENEV,Trace Enable Event Register"
|
|
bitfld.long 0x00 15. " TRCENEV[15] ,Trace Enable Event 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TRCENEV[14] ,Trace Enable Event 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TRCENEV[13] ,Trace Enable Event 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TRCENEV[12] ,Trace Enable Event 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TRCENEV[11] ,Trace Enable Event 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TRCENEV[10] ,Trace Enable Event 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TRCENEV[09] ,Trace Enable Event 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TRCENEV[08] ,Trace Enable Event 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TRCENEV[07] ,Trace Enable Event 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TRCENEV[06] ,Trace Enable Event 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TRCENEV[05] ,Trace Enable Event 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRCENEV[04] ,Trace Enable Event 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TRCENEV[03] ,Trace Enable Event 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TRCENEV[02] ,Trace Enable Event 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRCENEV[01] ,Trace Enable Event 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TRCENEV[00] ,Trace Enable Event 0" "Disabled,Enabled"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "FIFOFRR,FIFOFULL Region Register"
|
|
bitfld.long 0x00 24. " INCL/EXCLFLG ,Incl/ Excl flag" "Low,High"
|
|
bitfld.long 0x00 23. " MMDCONT[16] ,MMD control 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MMDCONT[15] ,MMD control 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MMDCONT[14] ,MMD control 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MMDCONT[13] ,MMD control 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MMDCONT[12] ,MMD control 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MMDCONT[11] ,MMD control 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MMDCONT[10] ,MMD control 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MMDCONT[09] ,MMD control 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MMDCONT[08] ,MMD control 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MMDCONT[07] ,MMD control 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MMDCONT[06] ,MMD control 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MMDCONT[05] ,MMD control 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MMDCONT[04] ,MMD control 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MMDCONT[03] ,MMD control 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MMDCONT[02] ,MMD control 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MMDCONT[01] ,MMD control 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ADDRCMP[8] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ADDRCMP[7] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 5. " ADDRCMP[6] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADDRCMP[5] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 3. " ADDRCMP[4] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADDRCMP[3] ,Address Comparator 8" "Low,High"
|
|
bitfld.long 0x00 1. " ADDRCMP[2] ,Address Comparator 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADDRCMP[1] ,Address Comparator 8" "Low,High"
|
|
endif
|
|
group.long 0x2c++0x03
|
|
line.long 0x00 "FIFOFLR,FIFOFULL Level Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIFOFLR ,FIFOFULL Level"
|
|
if (((d.l(ad:0x40002000+0x1e8))&0x800)==0x800)
|
|
group.long 0x30++0x4f
|
|
line.long 0x00 "VDER,View Data Event Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FNCRESBRESA ,Function/ResourceB/ResourceA"
|
|
line.long 0x04 "VDCR1,View Data Control 1 Reg"
|
|
bitfld.long 0x04 31. " SACE[16] ,Single Address Comparators (Exclude) 16" "Low,High"
|
|
bitfld.long 0x04 30. " SACE[15] ,Single Address Comparators (Exclude) 15" "Low,High"
|
|
bitfld.long 0x04 29. " SACE[14] ,Single Address Comparators (Exclude) 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 28. " SACE[13] ,Single Address Comparators (Exclude) 13" "Low,High"
|
|
bitfld.long 0x04 27. " SACE[12] ,Single Address Comparators (Exclude) 12" "Low,High"
|
|
bitfld.long 0x04 26. " SACE[11] ,Single Address Comparators (Exclude) 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SACE[10] ,Single Address Comparators (Exclude) 10" "Low,High"
|
|
bitfld.long 0x04 24. " SACE[09] ,Single Address Comparators (Exclude) 9" "Low,High"
|
|
bitfld.long 0x04 23. " SACE[08] ,Single Address Comparators (Exclude) 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SACE[07] ,Single Address Comparators (Exclude) 7" "Low,High"
|
|
bitfld.long 0x04 21. " SACE[06] ,Single Address Comparators (Exclude) 6" "Low,High"
|
|
bitfld.long 0x04 20. " SACE[05] ,Single Address Comparators (Exclude) 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SACE[04] ,Single Address Comparators (Exclude) 4" "Low,High"
|
|
bitfld.long 0x04 18. " SACE[03] ,Single Address Comparators (Exclude) 3" "Low,High"
|
|
bitfld.long 0x04 17. " SACE[02] ,Single Address Comparators (Exclude) 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 16. " SACE[01] ,Single Address Comparators (Exclude) 1" "Low,High"
|
|
bitfld.long 0x04 15. " SACI[16] ,Single Address Comparator (Include) 16" "Low,High"
|
|
bitfld.long 0x04 14. " SACI[15] ,Single Address Comparator (Include) 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SACI[14] ,Single Address Comparator (Include) 14" "Low,High"
|
|
bitfld.long 0x04 12. " SACI[13] ,Single Address Comparator (Include) 13" "Low,High"
|
|
bitfld.long 0x04 11. " SACI[12] ,Single Address Comparator (Include) 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SACI[11] ,Single Address Comparator (Include) 11" "Low,High"
|
|
bitfld.long 0x04 9. " SACI[10] ,Single Address Comparator (Include) 10" "Low,High"
|
|
bitfld.long 0x04 8. " SACI[09] ,Single Address Comparator (Include) 9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SACI[08] ,Single Address Comparator (Include) 8" "Low,High"
|
|
bitfld.long 0x04 6. " SACI[07] ,Single Address Comparator (Include) 7" "Low,High"
|
|
bitfld.long 0x04 5. " SACI[06] ,Single Address Comparator (Include) 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SACI[05] ,Single Address Comparator (Include) 5" "Low,High"
|
|
bitfld.long 0x04 3. " SACI[04] ,Single Address Comparator (Include) 4" "Low,High"
|
|
bitfld.long 0x04 2. " SACI[03] ,Single Address Comparator (Include) 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SACI[02] ,Single Address Comparator (Include) 2" "Low,High"
|
|
bitfld.long 0x04 0. " SACI[01] ,Single Address Comparator (Include) 1" "Low,High"
|
|
line.long 0x08 "VDCR2,View Data Control 2 Register"
|
|
bitfld.long 0x08 31. " MMDE[16] ,MMD 16 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 30. " MMDE[15] ,MMD 15 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 29. " MMDE[14] ,MMD 14 (Exclude)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 28. " MMDE[13] ,MMD 13 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 27. " MMDE[12] ,MMD 12 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 26. " MMDE[11] ,MMD 11 (Exclude)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 25. " MMDE[10] ,MMD 10 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 24. " MMDE[09] ,MMD 9 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 23. " MMDE[08] ,MMD 8 (Exclude)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 22. " MMDE[07] ,MMD 7 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 21. " MMDE[06] ,MMD 6 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 20. " MMDE[05] ,MMD 5 (Exclude)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 19. " MMDE[04] ,MMD 4 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 18. " MMDE[03] ,MMD 3 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 17. " MMDE[02] ,MMD 2 (Exclude)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 16. " MMDE[01] ,MMD 1 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 15. " MMDI[16] ,MMD 16 (Include)" "Low,High"
|
|
bitfld.long 0x08 14. " MMDI[15] ,MMD 15 (Include)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MMDI[14] ,MMD 14 (Include)" "Low,High"
|
|
bitfld.long 0x08 12. " MMDI[13] ,MMD 13 (Include)" "Low,High"
|
|
bitfld.long 0x08 11. " MMDI[12] ,MMD 12 (Include)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 10. " MMDI[11] ,MMD 11 (Include)" "Low,High"
|
|
bitfld.long 0x08 9. " MMDI[10] ,MMD 10 (Include)" "Low,High"
|
|
bitfld.long 0x08 8. " MMDI[09] ,MMD 9 (Include)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MMDI[08] ,MMD 8 (Include)" "Low,High"
|
|
bitfld.long 0x08 6. " MMDI[07] ,MMD 7 (Include)" "Low,High"
|
|
bitfld.long 0x08 5. " MMDI[06] ,MMD 6 (Include)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 4. " MMDI[05] ,MMD 5 (Include)" "Low,High"
|
|
bitfld.long 0x08 3. " MMDI[04] ,MMD 4 (Include)" "Low,High"
|
|
bitfld.long 0x08 2. " MMDI[03] ,MMD 3 (Include)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MMDI[02] ,MMD 2 (Include)" "Low,High"
|
|
bitfld.long 0x08 0. " MMDI[01] ,MMD 1 (Include)" "Low,High"
|
|
line.long 0x0c "VDCR3,View Data Control 3 Register"
|
|
bitfld.long 0x0C 15. " CE[7] ,Comparator 7 Exclude" "Low,High"
|
|
bitfld.long 0x0C 14. " CE[6] ,Comparator 6 Exclude" "Low,High"
|
|
bitfld.long 0x0C 13. " CE[5] ,Comparator 5 Exclude" "Low,High"
|
|
bitfld.long 0x0C 12. " CE[4] ,Comparator 4 Exclude" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CE[3] ,Comparator 3 Exclude" "Low,High"
|
|
bitfld.long 0x0C 10. " CE[2] ,Comparator 2 Exclude" "Low,High"
|
|
bitfld.long 0x0C 9. " CE[1] ,Comparator 1 Exclude" "Low,High"
|
|
bitfld.long 0x0C 8. " CE[0] ,Comparator 0 Exclude" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CI[7] ,Comparators 7 Include" "Low,High"
|
|
bitfld.long 0x0C 6. " CI[6] ,Comparators 6 Include" "Low,High"
|
|
bitfld.long 0x0C 5. " CI[5] ,Comparators 5 Include" "Low,High"
|
|
bitfld.long 0x0C 4. " CI[4] ,Comparators 4 Include" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " CI[3] ,Comparators 3 Include" "Low,High"
|
|
bitfld.long 0x0C 2. " CI[2] ,Comparators 2 Include" "Low,High"
|
|
bitfld.long 0x0C 1. " CI[1] ,Comparators 1 Include" "Low,High"
|
|
bitfld.long 0x0C 0. " CI[0] ,Comparators 0 Include" "Low,High"
|
|
line.long 0x10 "ACVR1,Address Comparator 1 Value Register"
|
|
line.long 0x14 "ACVR2,Address Comparator 2 Value Register"
|
|
line.long 0x18 "ACVR3,Address Comparator 3 Value Register"
|
|
line.long 0x1C "ACVR4,Address Comparator 4 Value Register"
|
|
line.long 0x20 "ACVR5,Address Comparator 5 Value Register"
|
|
line.long 0x24 "ACVR6,Address Comparator 6 Value Register"
|
|
line.long 0x28 "ACVR7,Address Comparator 7 Value Register"
|
|
line.long 0x2C "ACVR8,Address Comparator 8 Value Register"
|
|
line.long 0x30 "ACVR9,Address Comparator 9 Value Register"
|
|
line.long 0x34 "ACVR10,Address Comparator 10 Value Register"
|
|
line.long 0x38 "ACVR11,Address Comparator 11 Value Register"
|
|
line.long 0x3C "ACVR12,Address Comparator 12 Value Register"
|
|
line.long 0x40 "ACVR13,Address Comparator 13 Value Register"
|
|
line.long 0x44 "ACVR14,Address Comparator 14 Value Register"
|
|
line.long 0x48 "ACVR15,Address Comparator 15 Value Register"
|
|
line.long 0x4C "ACVR16,Address Comparator 16 Value Register"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DCVR1,Data Comparator Value Register 1"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DCVR2,Data Comparator Value Register 2"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DCVR3,Data Comparator Value Register 3"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "DCVR4,Data Comparator Value Register 4"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DCVR5,Data Comparator Value Register 5"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "DCVR6,Data Comparator Value Register 6"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DCVR7,Data Comparator Value Register 7"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "DCVR8,Data Comparator Value Register 8"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "DCMR1,Data Comparator Mask Register 1"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "DCMR2,Data Comparator Mask Register 2"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "DCMR3,Data Comparator Mask Register 3"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "DCMR4,Data Comparator Mask Register 4"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "DCMR5,Data Comparator Mask Register 5"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "DCMR6,Data Comparator Mask Register 6"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
group.long 0x130++0x3
|
|
line.long 0x00 "DCMR7,Data Comparator Mask Register 7"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
group.long 0x138++0x3
|
|
line.long 0x00 "DCMR8,Data Comparator Mask Register 8"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
group.long 0x140++0x2f
|
|
line.long 0x0 "CRVR1,Counter 1 Reload Value Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " IC ,Initial Count"
|
|
line.long 0x4 "CRVR2,Counter 2 Reload Value Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " IC ,Initial Count"
|
|
line.long 0x8 "CRVR3,Counter 3 Reload Value Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " IC ,Initial Count"
|
|
line.long 0xC "CRVR4,Counter 4 Reload Value Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " IC ,Initial Count"
|
|
line.long 0x10 "CER1,Counter 1 Enable Register"
|
|
bitfld.long 0x10 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x10 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x10 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x14 "CER2,Counter 2 Enable Register"
|
|
bitfld.long 0x14 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x14 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x14 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x18 "CER3,Counter 3 Enable Register"
|
|
bitfld.long 0x18 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x18 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x18 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x1C "CER4,Counter 4 Enable Register"
|
|
bitfld.long 0x1C 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x1C 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x1C 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x20 "CRER1,Counter 3 Reload Event Register"
|
|
bitfld.long 0x20 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x20 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x24 "CRER2,Counter 3 Reload Event Register"
|
|
bitfld.long 0x24 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x24 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x24 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x28 "CRER3,Counter 3 Reload Event Register"
|
|
bitfld.long 0x28 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x28 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x28 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x2C "CRER4,Counter 3 Reload Event Register"
|
|
bitfld.long 0x2C 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x2C 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x2C 0.--6. 1. " RESA ,Resource A"
|
|
else
|
|
wgroup.long 0x30++0x4f
|
|
line.long 0x00 "VDER,View Data Event Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FNCRESBRESA ,Function/ResourceB/ResourceA"
|
|
line.long 0x04 "VDCR1,View Data Control 1 Reg"
|
|
bitfld.long 0x04 31. " SACE[16] ,Single Address Comparators (Exclude) 16" "Low,High"
|
|
bitfld.long 0x04 30. " SACE[15] ,Single Address Comparators (Exclude) 15" "Low,High"
|
|
bitfld.long 0x04 29. " SACE[14] ,Single Address Comparators (Exclude) 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 28. " SACE[13] ,Single Address Comparators (Exclude) 13" "Low,High"
|
|
bitfld.long 0x04 27. " SACE[12] ,Single Address Comparators (Exclude) 12" "Low,High"
|
|
bitfld.long 0x04 26. " SACE[11] ,Single Address Comparators (Exclude) 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SACE[10] ,Single Address Comparators (Exclude) 10" "Low,High"
|
|
bitfld.long 0x04 24. " SACE[09] ,Single Address Comparators (Exclude) 9" "Low,High"
|
|
bitfld.long 0x04 23. " SACE[08] ,Single Address Comparators (Exclude) 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SACE[07] ,Single Address Comparators (Exclude) 7" "Low,High"
|
|
bitfld.long 0x04 21. " SACE[06] ,Single Address Comparators (Exclude) 6" "Low,High"
|
|
bitfld.long 0x04 20. " SACE[05] ,Single Address Comparators (Exclude) 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SACE[04] ,Single Address Comparators (Exclude) 4" "Low,High"
|
|
bitfld.long 0x04 18. " SACE[03] ,Single Address Comparators (Exclude) 3" "Low,High"
|
|
bitfld.long 0x04 17. " SACE[02] ,Single Address Comparators (Exclude) 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 16. " SACE[01] ,Single Address Comparators (Exclude) 1" "Low,High"
|
|
bitfld.long 0x04 15. " SACI[16] ,Single Address Comparator (Include) 16" "Low,High"
|
|
bitfld.long 0x04 14. " SACI[15] ,Single Address Comparator (Include) 15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SACI[14] ,Single Address Comparator (Include) 14" "Low,High"
|
|
bitfld.long 0x04 12. " SACI[13] ,Single Address Comparator (Include) 13" "Low,High"
|
|
bitfld.long 0x04 11. " SACI[12] ,Single Address Comparator (Include) 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SACI[11] ,Single Address Comparator (Include) 11" "Low,High"
|
|
bitfld.long 0x04 9. " SACI[10] ,Single Address Comparator (Include) 10" "Low,High"
|
|
bitfld.long 0x04 8. " SACI[09] ,Single Address Comparator (Include) 9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SACI[08] ,Single Address Comparator (Include) 8" "Low,High"
|
|
bitfld.long 0x04 6. " SACI[07] ,Single Address Comparator (Include) 7" "Low,High"
|
|
bitfld.long 0x04 5. " SACI[06] ,Single Address Comparator (Include) 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SACI[05] ,Single Address Comparator (Include) 5" "Low,High"
|
|
bitfld.long 0x04 3. " SACI[04] ,Single Address Comparator (Include) 4" "Low,High"
|
|
bitfld.long 0x04 2. " SACI[03] ,Single Address Comparator (Include) 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SACI[02] ,Single Address Comparator (Include) 2" "Low,High"
|
|
bitfld.long 0x04 0. " SACI[01] ,Single Address Comparator (Include) 1" "Low,High"
|
|
line.long 0x08 "VDCR2,View Data Control 2 Register"
|
|
bitfld.long 0x08 31. " MMDE[16] ,MMD 16 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 30. " MMDE[15] ,MMD 15 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 29. " MMDE[14] ,MMD 14 (Exclude)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 28. " MMDE[13] ,MMD 13 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 27. " MMDE[12] ,MMD 12 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 26. " MMDE[11] ,MMD 11 (Exclude)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 25. " MMDE[10] ,MMD 10 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 24. " MMDE[09] ,MMD 9 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 23. " MMDE[08] ,MMD 8 (Exclude)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 22. " MMDE[07] ,MMD 7 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 21. " MMDE[06] ,MMD 6 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 20. " MMDE[05] ,MMD 5 (Exclude)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 19. " MMDE[04] ,MMD 4 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 18. " MMDE[03] ,MMD 3 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 17. " MMDE[02] ,MMD 2 (Exclude)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 16. " MMDE[01] ,MMD 1 (Exclude)" "Low,High"
|
|
bitfld.long 0x08 15. " MMDI[16] ,MMD 16 (Include)" "Low,High"
|
|
bitfld.long 0x08 14. " MMDI[15] ,MMD 15 (Include)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MMDI[14] ,MMD 14 (Include)" "Low,High"
|
|
bitfld.long 0x08 12. " MMDI[13] ,MMD 13 (Include)" "Low,High"
|
|
bitfld.long 0x08 11. " MMDI[12] ,MMD 12 (Include)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 10. " MMDI[11] ,MMD 11 (Include)" "Low,High"
|
|
bitfld.long 0x08 9. " MMDI[10] ,MMD 10 (Include)" "Low,High"
|
|
bitfld.long 0x08 8. " MMDI[09] ,MMD 9 (Include)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MMDI[08] ,MMD 8 (Include)" "Low,High"
|
|
bitfld.long 0x08 6. " MMDI[07] ,MMD 7 (Include)" "Low,High"
|
|
bitfld.long 0x08 5. " MMDI[06] ,MMD 6 (Include)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 4. " MMDI[05] ,MMD 5 (Include)" "Low,High"
|
|
bitfld.long 0x08 3. " MMDI[04] ,MMD 4 (Include)" "Low,High"
|
|
bitfld.long 0x08 2. " MMDI[03] ,MMD 3 (Include)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MMDI[02] ,MMD 2 (Include)" "Low,High"
|
|
bitfld.long 0x08 0. " MMDI[01] ,MMD 1 (Include)" "Low,High"
|
|
line.long 0x0c "VDCR3,View Data Control 3 Register"
|
|
bitfld.long 0x0C 15. " CE[7] ,Comparator 7 Exclude" "Low,High"
|
|
bitfld.long 0x0C 14. " CE[6] ,Comparator 6 Exclude" "Low,High"
|
|
bitfld.long 0x0C 13. " CE[5] ,Comparator 5 Exclude" "Low,High"
|
|
bitfld.long 0x0C 12. " CE[4] ,Comparator 4 Exclude" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CE[3] ,Comparator 3 Exclude" "Low,High"
|
|
bitfld.long 0x0C 10. " CE[2] ,Comparator 2 Exclude" "Low,High"
|
|
bitfld.long 0x0C 9. " CE[1] ,Comparator 1 Exclude" "Low,High"
|
|
bitfld.long 0x0C 8. " CE[0] ,Comparator 0 Exclude" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CI[7] ,Comparators 7 Include" "Low,High"
|
|
bitfld.long 0x0C 6. " CI[6] ,Comparators 6 Include" "Low,High"
|
|
bitfld.long 0x0C 5. " CI[5] ,Comparators 5 Include" "Low,High"
|
|
bitfld.long 0x0C 4. " CI[4] ,Comparators 4 Include" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " CI[3] ,Comparators 3 Include" "Low,High"
|
|
bitfld.long 0x0C 2. " CI[2] ,Comparators 2 Include" "Low,High"
|
|
bitfld.long 0x0C 1. " CI[1] ,Comparators 1 Include" "Low,High"
|
|
bitfld.long 0x0C 0. " CI[0] ,Comparators 0 Include" "Low,High"
|
|
line.long 0x10 "ACVR1,Address Comparator 1 Value Register"
|
|
line.long 0x14 "ACVR2,Address Comparator 2 Value Register"
|
|
line.long 0x18 "ACVR3,Address Comparator 3 Value Register"
|
|
line.long 0x1C "ACVR4,Address Comparator 4 Value Register"
|
|
line.long 0x20 "ACVR5,Address Comparator 5 Value Register"
|
|
line.long 0x24 "ACVR6,Address Comparator 6 Value Register"
|
|
line.long 0x28 "ACVR7,Address Comparator 7 Value Register"
|
|
line.long 0x2C "ACVR8,Address Comparator 8 Value Register"
|
|
line.long 0x30 "ACVR9,Address Comparator 9 Value Register"
|
|
line.long 0x34 "ACVR10,Address Comparator 10 Value Register"
|
|
line.long 0x38 "ACVR11,Address Comparator 11 Value Register"
|
|
line.long 0x3C "ACVR12,Address Comparator 12 Value Register"
|
|
line.long 0x40 "ACVR13,Address Comparator 13 Value Register"
|
|
line.long 0x44 "ACVR14,Address Comparator 14 Value Register"
|
|
line.long 0x48 "ACVR15,Address Comparator 15 Value Register"
|
|
line.long 0x4C "ACVR16,Address Comparator 16 Value Register"
|
|
wgroup.long 0xC0++0x03
|
|
line.long 0x00 "DCVR1,Data Comparator Value Register 1"
|
|
wgroup.long 0xC8++0x03
|
|
line.long 0x00 "DCVR2,Data Comparator Value Register 2"
|
|
wgroup.long 0xD0++0x03
|
|
line.long 0x00 "DCVR3,Data Comparator Value Register 3"
|
|
wgroup.long 0xD8++0x03
|
|
line.long 0x00 "DCVR4,Data Comparator Value Register 4"
|
|
wgroup.long 0xE0++0x03
|
|
line.long 0x00 "DCVR5,Data Comparator Value Register 5"
|
|
wgroup.long 0xE8++0x03
|
|
line.long 0x00 "DCVR6,Data Comparator Value Register 6"
|
|
wgroup.long 0xF0++0x03
|
|
line.long 0x00 "DCVR7,Data Comparator Value Register 7"
|
|
wgroup.long 0xF8++0x03
|
|
line.long 0x00 "DCVR8,Data Comparator Value Register 8"
|
|
wgroup.long 0x100++0x3
|
|
line.long 0x00 "DCMR1,Data Comparator Mask Register 1"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
wgroup.long 0x108++0x3
|
|
line.long 0x00 "DCMR2,Data Comparator Mask Register 2"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
wgroup.long 0x110++0x3
|
|
line.long 0x00 "DCMR3,Data Comparator Mask Register 3"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
wgroup.long 0x118++0x3
|
|
line.long 0x00 "DCMR4,Data Comparator Mask Register 4"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x00 "DCMR5,Data Comparator Mask Register 5"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
wgroup.long 0x128++0x3
|
|
line.long 0x00 "DCMR6,Data Comparator Mask Register 6"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
wgroup.long 0x130++0x3
|
|
line.long 0x00 "DCMR7,Data Comparator Mask Register 7"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
wgroup.long 0x138++0x3
|
|
line.long 0x00 "DCMR8,Data Comparator Mask Register 8"
|
|
bitfld.long 0x00 31. " DM[31] ,Data mask 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " DM[30] ,Data mask 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " DM[29] ,Data mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DM[28] ,Data mask 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " DM[27] ,Data mask 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " DM[26] ,Data mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DM[25] ,Data mask 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DM[24] ,Data mask 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " DM[23] ,Data mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DM[22] ,Data mask 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " DM[21] ,Data mask 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " DM[20] ,Data mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DM[19] ,Data mask 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DM[18] ,Data mask 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DM[17] ,Data mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DM[16] ,Data mask 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " DM[15] ,Data mask 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " DM[14] ,Data mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DM[13] ,Data mask 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " DM[12] ,Data mask 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " DM[11] ,Data mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DM[10] ,Data mask 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " DM[09] ,Data mask 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " DM[08] ,Data mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DM[07] ,Data mask 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " DM[06] ,Data mask 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " DM[05] ,Data mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DM[04] ,Data mask 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DM[03] ,Data mask 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DM[02] ,Data mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DM[01] ,Data mask 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DM[00] ,Data mask 0" "Not masked,Masked"
|
|
wgroup.long 0x140++0x2f
|
|
line.long 0x0 "CRVR1,Counter 1 Reload Value Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " IC ,Initial Count"
|
|
line.long 0x4 "CRVR2,Counter 2 Reload Value Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " IC ,Initial Count"
|
|
line.long 0x8 "CRVR3,Counter 3 Reload Value Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " IC ,Initial Count"
|
|
line.long 0xC "CRVR4,Counter 4 Reload Value Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " IC ,Initial Count"
|
|
line.long 0x10 "CER1,Counter 1 Enable Register"
|
|
bitfld.long 0x10 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x10 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x10 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x14 "CER2,Counter 2 Enable Register"
|
|
bitfld.long 0x14 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x14 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x14 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x18 "CER3,Counter 3 Enable Register"
|
|
bitfld.long 0x18 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x18 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x18 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x1C "CER4,Counter 4 Enable Register"
|
|
bitfld.long 0x1C 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x1C 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x1C 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x20 "CRER1,Counter 3 Reload Event Register"
|
|
bitfld.long 0x20 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x20 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x20 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x24 "CRER2,Counter 3 Reload Event Register"
|
|
bitfld.long 0x24 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x24 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x24 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x28 "CRER3,Counter 3 Reload Event Register"
|
|
bitfld.long 0x28 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x28 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x28 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x2C "CRER4,Counter 3 Reload Event Register"
|
|
bitfld.long 0x2C 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x2C 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x2C 0.--6. 1. " RESA ,Resource A"
|
|
endif
|
|
group.long 0x170++0x0f
|
|
line.long 0x0 "CVR1,Counter 1 Value Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " CV ,Counter Value"
|
|
line.long 0x4 "CVR2,Counter 2 Value Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " CV ,Counter Value"
|
|
line.long 0x8 "CVR3,Counter 3 Value Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " CV ,Counter Value"
|
|
line.long 0xC "CVR4,Counter 4 Value Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " CV ,Counter Value"
|
|
if (((d.l(ad:0x40002000+0x1e8))&0x800)==0x800)
|
|
group.long 0x180++0x17
|
|
line.long 0x0 "SS1TO2ER,Seq State 1TO2 Evebt Register"
|
|
bitfld.long 0x0 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x0 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x4 "SS2TO1ER,Seq State 2TO1 Evebt Register"
|
|
bitfld.long 0x4 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x4 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x8 "SS2TO3ER,Seq State 2TO3 Evebt Register"
|
|
bitfld.long 0x8 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x8 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0xC "SS3TO1ER,Seq State 3TO1 Evebt Register"
|
|
bitfld.long 0xC 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0xC 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x10 "SS3TO2ER,Seq State 3TO2 Evebt Register"
|
|
bitfld.long 0x10 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x10 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x10 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x14 "SS3TO1ER,Seq State 3TO1 Evebt Register"
|
|
bitfld.long 0x14 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x14 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x14 0.--6. 1. " RESA ,Resource A"
|
|
else
|
|
wgroup.long 0x180++0x17
|
|
line.long 0x0 "SS1TO2ER,Seq State 1TO2 Evebt Register"
|
|
bitfld.long 0x0 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x0 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x4 "SS2TO1ER,Seq State 2TO1 Evebt Register"
|
|
bitfld.long 0x4 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x4 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x8 "SS2TO3ER,Seq State 2TO3 Evebt Register"
|
|
bitfld.long 0x8 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x8 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0xC "SS3TO1ER,Seq State 3TO1 Evebt Register"
|
|
bitfld.long 0xC 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0xC 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x10 "SS3TO2ER,Seq State 3TO2 Evebt Register"
|
|
bitfld.long 0x10 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x10 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x10 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x14 "SS3TO1ER,Seq State 3TO1 Evebt Register"
|
|
bitfld.long 0x14 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x14 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x14 0.--6. 1. " RESA ,Resource A"
|
|
endif
|
|
group.long 0x19c++0x03
|
|
line.long 0x00 "CSS,Current Sequencer State"
|
|
bitfld.long 0x00 0.--1. " CS ,Current State" "0,1,2,3"
|
|
if (((d.l(ad:0x40002000+0x1e8))&0x800)==0x800)
|
|
group.long 0x1a0++0x1f
|
|
line.long 0x0 "EOER1,External Output Event Register 1"
|
|
bitfld.long 0x0 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x0 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x4 "EOER2,External Output Event Register 2"
|
|
bitfld.long 0x4 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x4 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x8 "EOER3,External Output Event Register 3"
|
|
bitfld.long 0x8 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x8 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0xC "EOER4,External Output Event Register 4"
|
|
bitfld.long 0xC 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0xC 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x10 "CIDCV1,Context ID Comparator Value 1"
|
|
line.long 0x14 "CIDCV2,Context ID Comparator Value 2"
|
|
line.long 0x18 "CIDCV3,Context ID Comparator Value 3"
|
|
line.long 0x1c "CIDCM,Context ID Comparator Mask"
|
|
bitfld.long 0x1C 31. " CIDM[31] ,Context ID Mask 31" "Not masked,Masked"
|
|
bitfld.long 0x1C 30. " CIDM[30] ,Context ID Mask 30" "Not masked,Masked"
|
|
bitfld.long 0x1C 29. " CIDM[29] ,Context ID Mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 28. " CIDM[28] ,Context ID Mask 28" "Not masked,Masked"
|
|
bitfld.long 0x1C 27. " CIDM[27] ,Context ID Mask 27" "Not masked,Masked"
|
|
bitfld.long 0x1C 26. " CIDM[26] ,Context ID Mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " CIDM[25] ,Context ID Mask 25" "Not masked,Masked"
|
|
bitfld.long 0x1C 24. " CIDM[24] ,Context ID Mask 24" "Not masked,Masked"
|
|
bitfld.long 0x1C 23. " CIDM[23] ,Context ID Mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 22. " CIDM[22] ,Context ID Mask 22" "Not masked,Masked"
|
|
bitfld.long 0x1C 21. " CIDM[21] ,Context ID Mask 21" "Not masked,Masked"
|
|
bitfld.long 0x1C 20. " CIDM[20] ,Context ID Mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " CIDM[19] ,Context ID Mask 19" "Not masked,Masked"
|
|
bitfld.long 0x1C 18. " CIDM[18] ,Context ID Mask 18" "Not masked,Masked"
|
|
bitfld.long 0x1C 17. " CIDM[17] ,Context ID Mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " CIDM[16] ,Context ID Mask 16" "Not masked,Masked"
|
|
bitfld.long 0x1C 15. " CIDM[15] ,Context ID Mask 15" "Not masked,Masked"
|
|
bitfld.long 0x1C 14. " CIDM[14] ,Context ID Mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " CIDM[13] ,Context ID Mask 13" "Not masked,Masked"
|
|
bitfld.long 0x1C 12. " CIDM[12] ,Context ID Mask 12" "Not masked,Masked"
|
|
bitfld.long 0x1C 11. " CIDM[11] ,Context ID Mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " CIDM[10] ,Context ID Mask 10" "Not masked,Masked"
|
|
bitfld.long 0x1C 9. " CIDM[09] ,Context ID Mask 9" "Not masked,Masked"
|
|
bitfld.long 0x1C 8. " CIDM[08] ,Context ID Mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " CIDM[07] ,Context ID Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x1C 6. " CIDM[06] ,Context ID Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x1C 5. " CIDM[05] ,Context ID Mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " CIDM[04] ,Context ID Mask 4" "Not masked,Masked"
|
|
bitfld.long 0x1C 3. " CIDM[03] ,Context ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x1C 2. " CIDM[02] ,Context ID Mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " CIDM[01] ,Context ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x1C 0. " CIDM[00] ,Context ID Mask 0" "Not masked,Masked"
|
|
else
|
|
wgroup.long 0x1a0++0x1f
|
|
line.long 0x0 "EOER1,External Output Event Register 1"
|
|
bitfld.long 0x0 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x0 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x4 "EOER2,External Output Event Register 2"
|
|
bitfld.long 0x4 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x4 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x8 "EOER3,External Output Event Register 3"
|
|
bitfld.long 0x8 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0x8 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0xC "EOER4,External Output Event Register 4"
|
|
bitfld.long 0xC 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 7.--13. 1. " RESB ,Resource B"
|
|
hexmask.long.byte 0xC 0.--6. 1. " RESA ,Resource A"
|
|
line.long 0x10 "CIDCV1,Context ID Comparator Value 1"
|
|
line.long 0x14 "CIDCV2,Context ID Comparator Value 2"
|
|
line.long 0x18 "CIDCV3,Context ID Comparator Value 3"
|
|
line.long 0x1c "CIDCM,Context ID Comparator Mask"
|
|
bitfld.long 0x1C 31. " CIDM[31] ,Context ID Mask 31" "Not masked,Masked"
|
|
bitfld.long 0x1C 30. " CIDM[30] ,Context ID Mask 30" "Not masked,Masked"
|
|
bitfld.long 0x1C 29. " CIDM[29] ,Context ID Mask 29" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 28. " CIDM[28] ,Context ID Mask 28" "Not masked,Masked"
|
|
bitfld.long 0x1C 27. " CIDM[27] ,Context ID Mask 27" "Not masked,Masked"
|
|
bitfld.long 0x1C 26. " CIDM[26] ,Context ID Mask 26" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " CIDM[25] ,Context ID Mask 25" "Not masked,Masked"
|
|
bitfld.long 0x1C 24. " CIDM[24] ,Context ID Mask 24" "Not masked,Masked"
|
|
bitfld.long 0x1C 23. " CIDM[23] ,Context ID Mask 23" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 22. " CIDM[22] ,Context ID Mask 22" "Not masked,Masked"
|
|
bitfld.long 0x1C 21. " CIDM[21] ,Context ID Mask 21" "Not masked,Masked"
|
|
bitfld.long 0x1C 20. " CIDM[20] ,Context ID Mask 20" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " CIDM[19] ,Context ID Mask 19" "Not masked,Masked"
|
|
bitfld.long 0x1C 18. " CIDM[18] ,Context ID Mask 18" "Not masked,Masked"
|
|
bitfld.long 0x1C 17. " CIDM[17] ,Context ID Mask 17" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " CIDM[16] ,Context ID Mask 16" "Not masked,Masked"
|
|
bitfld.long 0x1C 15. " CIDM[15] ,Context ID Mask 15" "Not masked,Masked"
|
|
bitfld.long 0x1C 14. " CIDM[14] ,Context ID Mask 14" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " CIDM[13] ,Context ID Mask 13" "Not masked,Masked"
|
|
bitfld.long 0x1C 12. " CIDM[12] ,Context ID Mask 12" "Not masked,Masked"
|
|
bitfld.long 0x1C 11. " CIDM[11] ,Context ID Mask 11" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " CIDM[10] ,Context ID Mask 10" "Not masked,Masked"
|
|
bitfld.long 0x1C 9. " CIDM[09] ,Context ID Mask 9" "Not masked,Masked"
|
|
bitfld.long 0x1C 8. " CIDM[08] ,Context ID Mask 8" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " CIDM[07] ,Context ID Mask 7" "Not masked,Masked"
|
|
bitfld.long 0x1C 6. " CIDM[06] ,Context ID Mask 6" "Not masked,Masked"
|
|
bitfld.long 0x1C 5. " CIDM[05] ,Context ID Mask 5" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " CIDM[04] ,Context ID Mask 4" "Not masked,Masked"
|
|
bitfld.long 0x1C 3. " CIDM[03] ,Context ID Mask 3" "Not masked,Masked"
|
|
bitfld.long 0x1C 2. " CIDM[02] ,Context ID Mask 2" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " CIDM[01] ,Context ID Mask 1" "Not masked,Masked"
|
|
bitfld.long 0x1C 0. " CIDM[00] ,Context ID Mask 0" "Not masked,Masked"
|
|
endif
|
|
group.long 0x1c0++0x03
|
|
line.long 0x00 "ISR,Implementation Specific Register"
|
|
bitfld.long 0x00 4.--7. " EF ,Enable features" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1e0++0x03
|
|
line.long 0x00 "SFR,Synchronization Frequency Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " SF ,Synchronization Frequency"
|
|
rgroup.long 0x1e4++0x03
|
|
line.long 0x00 "EIR,ETM ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IC ,Implementor Code"
|
|
bitfld.long 0x00 19. " TZS ,TZ supported" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 18. " T2S ,Thumb-2 supported" "Not supported,Supported"
|
|
bitfld.long 0x00 16. " LPCF ,Load PC First" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CF ,Core Family" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 4.--11. 1. " EAVN ,ETM Architecture Version Number"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--3. 1. " IREV ,Implementation Revision"
|
|
group.long 0x1e8++0x07
|
|
line.long 0x00 "CCER,Configuration Code Extension"
|
|
bitfld.long 0x00 11. " CCE11 ,Set if all registers are readable" "Not readable,Readable"
|
|
hexmask.long.byte 0x00 3.--10. 1. " EEIBS ,Extended external input bus size"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " NEEIS ,Number of extended external input selectors" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "EEIS,Extended External Input Selection"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EEIS4 ,Fourth Extended External Input Selector"
|
|
hexmask.long.byte 0x04 16.--23. 1. " EEIS3 ,Third Extended External Input Selector"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " EEIS2 ,Second Extended External Input Selector"
|
|
hexmask.long.byte 0x04 0.--7. 1. " EEIS1 ,First Extended External Input Selector"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CTID,Coresight Trace ID"
|
|
hexmask.long.byte 0x00 0.--6. 1. " STB ,Signals to trace bus bit"
|
|
group.long 0xf00++0x03
|
|
line.long 0x00 "IMC,Integration Mode Control"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group.long 0xfa0++0x03
|
|
line.long 0x00 "CTSR,Claim Tag Set Register"
|
|
bitfld.long 0x00 7. " CTBV[7] ,Claim tag bit 7 values" "Not set,Set"
|
|
bitfld.long 0x00 6. " CTBV[6] ,Claim tag bit 6 values" "Not set,Set"
|
|
bitfld.long 0x00 5. " CTBV[5] ,Claim tag bit 5 values" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CTBV[4] ,Claim tag bit 4 values" "Not set,Set"
|
|
bitfld.long 0x00 3. " CTBV[3] ,Claim tag bit 3 values" "Not set,Set"
|
|
bitfld.long 0x00 2. " CTBV[2] ,Claim tag bit 2 values" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CTBV[1] ,Claim tag bit 1 values" "Not set,Set"
|
|
bitfld.long 0x00 0. " CTBV[0] ,Claim tag bit 0 values" "Not set,Set"
|
|
line.long 0x00 "CTCR,Claim Tag Clear Register"
|
|
eventfld.long 0x00 7. " CTV[7] ,Claim tag value 7" "Low,High"
|
|
eventfld.long 0x00 6. " CTV[6] ,Claim tag value 6" "Low,High"
|
|
eventfld.long 0x00 5. " CTV[5] ,Claim tag value 5" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CTV[4] ,Claim tag value 4" "Low,High"
|
|
eventfld.long 0x00 3. " CTV[3] ,Claim tag value 3" "Low,High"
|
|
eventfld.long 0x00 2. " CTV[2] ,Claim tag value 2" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CTV[1] ,Claim tag value 1" "Low,High"
|
|
eventfld.long 0x00 0. " CTV[0] ,Claim tag value 0" "Low,High"
|
|
wgroup.long 0xfb0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xfb4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
bitfld.long 0x00 0.--2. " STAT ,Status" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "ASR,Authentication Status Register"
|
|
bitfld.long 0x04 7. " AS[7] ,Authentication Status" "Low,High"
|
|
bitfld.long 0x04 6. " EN ,Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " AS[5:0] ,Authentication Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xfcc++0x03
|
|
line.long 0x00 "DTR,Device Type Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DT ,Device Type"
|
|
rgroup.long 0xfe0++0x0f
|
|
line.long 0x00 "PID0,Peripheral ID 0 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number"
|
|
line.long 0x04 "PID1,Peripheral ID 1 Register"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106C[3:0] ,JEP106 Code"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PN[11:8] ,Part Number"
|
|
line.long 0x08 "PID2,Peripheral ID 2 Register"
|
|
hexmask.long.byte 0x08 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x08 3. " PID2[3] ,Peripheral ID2 bit 3" "0,1"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106C[6:4] ,JEP106 Code"
|
|
line.long 0x0c "PID3,Peripheral ID 3 Register"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RA ,Revision And"
|
|
bitfld.long 0x0C 0.--3. " CM ,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xfd0++0x03
|
|
line.long 0x00 "PID4,Peripheral ID 4 Register"
|
|
bitfld.long 0x00 4.--7. " 4KBC ,4Kb Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106CC ,JEP106 Continuation Code"
|
|
rgroup.long 0xff0++0x0f
|
|
line.long 0x0 "CID0,Component ID 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CID0 ,Component ID 0"
|
|
line.long 0x4 "CID1,Component ID 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " CID1 ,Component ID 1"
|
|
line.long 0x8 "CID2,Component ID 2"
|
|
hexmask.long.byte 0x8 0.--7. 1. " CID2 ,Component ID 2"
|
|
line.long 0xC "CID3,Component ID 3"
|
|
hexmask.long.byte 0xC 0.--7. 1. " CID3 ,Component ID 3"
|
|
width 0xb
|
|
tree.end
|
|
tree "CSCTI"
|
|
tree "CTI 0"
|
|
base ad:0x40004000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTICONTROL,CTICONTROL Register"
|
|
bitfld.long 0x00 0. " GLBEN ,Enables or disables the ECT" "Disabled,Enabled"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CTIINTACK,CTIINTACK Register"
|
|
bitfld.long 0x00 7. " INTACK[7] ,Acknowledges the corresponding CTITRIGOUT output 7" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 6. " INTACK[6] ,Acknowledges the corresponding CTITRIGOUT output 6" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTACK[5] ,Acknowledges the corresponding CTITRIGOUT output 5" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 4. " INTACK[4] ,Acknowledges the corresponding CTITRIGOUT output 4" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTACK[3] ,Acknowledges the corresponding CTITRIGOUT output 3" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 2. " INTACK[2] ,Acknowledges the corresponding CTITRIGOUT output 2" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTACK[1] ,Acknowledges the corresponding CTITRIGOUT output 1" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 0. " INTACK[0] ,Acknowledges the corresponding CTITRIGOUT output 0" "No effect,CTITRIGOUT"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTIAPPSET_CLR,CTIAPPSET Register"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " APPSET3_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " APPSET2_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " APPSET1_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " APPSET0_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CTIAPPPULSE,CTIAPPPULSE Register"
|
|
bitfld.long 0x00 3. " APPULSE3 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
bitfld.long 0x00 2. " APPULSE2 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " APPULSE1 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
bitfld.long 0x00 0. " APPULSE0 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
group.long 0x20++0x1f
|
|
line.long 0x0 "CTIINEN0,CTIINEN Register 0"
|
|
bitfld.long 0x0 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x4 "CTIINEN1,CTIINEN Register 1"
|
|
bitfld.long 0x4 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x8 "CTIINEN2,CTIINEN Register 2"
|
|
bitfld.long 0x8 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0xC "CTIINEN3,CTIINEN Register 3"
|
|
bitfld.long 0xC 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0xC 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x10 "CTIINEN4,CTIINEN Register 4"
|
|
bitfld.long 0x10 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x14 "CTIINEN5,CTIINEN Register 5"
|
|
bitfld.long 0x14 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x18 "CTIINEN6,CTIINEN Register 6"
|
|
bitfld.long 0x18 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x1C "CTIINEN7,CTIINEN Register 7"
|
|
bitfld.long 0x1C 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
group.long 0xa0++0x1f
|
|
line.long 0x0 "CTIOUTEN0,CTIOUTEN Register 0"
|
|
bitfld.long 0x0 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x4 "CTIOUTEN1,CTIOUTEN Register 1"
|
|
bitfld.long 0x4 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x8 "CTIOUTEN2,CTIOUTEN Register 2"
|
|
bitfld.long 0x8 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0xC "CTIOUTEN3,CTIOUTEN Register 3"
|
|
bitfld.long 0xC 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0xC 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x10 "CTIOUTEN4,CTIOUTEN Register 4"
|
|
bitfld.long 0x10 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x14 "CTIOUTEN5,CTIOUTEN Register 5"
|
|
bitfld.long 0x14 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x18 "CTIOUTEN6,CTIOUTEN Register 6"
|
|
bitfld.long 0x18 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x1C "CTIOUTEN7,CTIOUTEN Register 7"
|
|
bitfld.long 0x1C 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
rgroup.long 0x130++0x0f
|
|
line.long 0x00 "CTITRIGINSTATUS,CTITRIGINSTATUS Register"
|
|
bitfld.long 0x000 7. " TRIGINSTATUS7 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 6. " TRIGINSTATUS6 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 5. " TRIGINSTATUS5 , Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 4. " TRIGINSTATUS4 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 3. " TRIGINSTATUS3 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 2. " TRIGINSTATUS2 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 1. " TRIGINSTATUS1 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 0. " TRIGINSTATUS0 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
line.long 0x04 "CTITRIGOUTSTATUS,CTITRIGOUTSTATUS Register"
|
|
bitfld.long 0x004 7. " TRIGOUTSTATUS7 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 6. " TRIGOUTSTATUS6 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 5. " TRIGOUTSTATUS5 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 4. " TRIGOUTSTATUS4 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 3. " TRIGOUTSTATUS3 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 2. " TRIGOUTSTATUS2 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 1. " TRIGOUTSTATUS1 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 0. " TRIGOUTSTATUS0 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
line.long 0x08 "CTICHINSTATUS,CTICHINSTATUS Register"
|
|
bitfld.long 0x08 7. " CTICHINSTATUS7 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 6. " CTICHINSTATUS6 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CTICHINSTATUS5 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 4. " CTICHINSTATUS4 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CTICHINSTATUS3 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 2. " CTICHINSTATUS2 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CTICHINSTATUS1 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 0. " CTICHINSTATUS0 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
line.long 0x0c "CTICHOUTSTATUS,CTI Channel Out Status Register"
|
|
bitfld.long 0x0C 3. " CTICHOUTSTATUS0 ,Shows the status of the CTICHOUT outputs 0" "Inactive,Active"
|
|
bitfld.long 0x0C 2. " CTICHOUTSTATUS ,Shows the status of the CTICHOUT outputs " "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CTICHOUTSTATUS0 ,Shows the status of the CTICHOUT outputs 0" "Inactive,Active"
|
|
bitfld.long 0x0C 0. " CTICHOUTSTATUS ,Shows the status of the CTICHOUT outputs " "Inactive,Active"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "CTIGATE,Channel gate"
|
|
bitfld.long 0x00 3. " CTIGATEEN3 ,Disable Channel Propagation (Gate CTICHOUT3)" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " CTIGATEEN2 ,Disable Channel Propagation (Gate CTICHOUT2)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CTIGATEEN1 ,Disable Channel Propagation (Gate CTICHOUT1)" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CTIGATEEN0 ,Disable Channel Propagation (Gate CTICHOUT0)" "Enabled,Disabled"
|
|
line.long 0x04 "ASICCTL,External Multiplexor Control"
|
|
hexmask.long.byte 0x004 0.--7. 1. " ASICCTL ,Implementation-defined ASIC Control, Value in Register Is Output On ASICCTL[7:0]"
|
|
wgroup.long 0xedc++0x0f
|
|
line.long 0x00 "ITCHINACK,ITCHINACK Register"
|
|
bitfld.long 0x000 0.--3. " CTCHINACK ,Value of the CTCHINACK Outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ITTRIGINACK,ITTRIGINACK Register"
|
|
hexmask.long.byte 0x004 0.--7. 1. " CTTRIGINACK ,Value of the CTTRIGINACK Outputs"
|
|
line.long 0x08 "ITCHOUT,ITCHOUT Register"
|
|
bitfld.long 0x008 0.--3. " CTCHOUT ,Value of the CTCHOUT Outputs" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF"
|
|
line.long 0x0c "ITTRIGOUT,ITTRIGOUT Register"
|
|
hexmask.long.byte 0x00C 0.--7. 1. " CTTRIGOUT ,Value of the CTTRIGOUT Outputs"
|
|
rgroup.long 0xeec++0x0f
|
|
line.long 0x00 "ITCHOUTACK,ITCHOUTACK Register"
|
|
hexmask.long.byte 0x000 0.--7. 1. " CTCHOUTACK ,Values of the CTCHOUTACK Inputs"
|
|
line.long 0x04 "ITTRIGOUTACK,ITTRIGOUTACK Register"
|
|
hexmask.long.byte 0x004 0.--7. 1. " CTTRIGOUTACK ,Values of the CTTRIGOUTACK Inputs"
|
|
line.long 0x08 "ITCHIN,ITCHIN Register"
|
|
bitfld.long 0x008 0.--3. " CTCHIN ,Value of the CTCHIN Inputs" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0x0c "ITTRIGIN,ITTRIGIN Register"
|
|
hexmask.long.byte 0x00C 0.--7. 1. " CTTRIGIN ,Values of the CTTRIGIN Inputs"
|
|
group.long 0xf00++0x03
|
|
line.long 0x00 "ITCTRL,ITCTRL Register"
|
|
group.long 0xfa0++0x07
|
|
line.long 0x00 "CTSR,Claim Tag Set Register"
|
|
bitfld.long 0x000 3. " SETCTV3 ,Set Claim Tag Value" "No effect,Set"
|
|
bitfld.long 0x000 2. " SETCTV2 ,Set Claim Tag Value" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x000 1. " SETCTV1 ,Set Claim Tag Value" "No effect,Set"
|
|
bitfld.long 0x000 0. " SETCTV0 ,Set Claim Tag Value" "No effect,Set"
|
|
line.long 0x04 "CTCR,Claim Tag Clear Register"
|
|
bitfld.long 0x004 3. " CLRCTV3 ,Clear Claim Tag Value" "No effect,Clear"
|
|
bitfld.long 0x004 2. " CLRCTV2 ,Clear Claim Tag Value" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x004 1. " CLRCTV1 ,Clear Claim Tag Value" "No effect,Clear"
|
|
bitfld.long 0x004 0. " CLRCTV0 ,Clear Claim Tag Value" "No effect,Clear"
|
|
wgroup.long 0xfb0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xfb4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
line.long 0x04 "ASR,Authentication Status Register"
|
|
rgroup.long 0xfc8++0x0b
|
|
line.long 0x00 "DEVID,Device ID Register"
|
|
line.long 0x04 "DTIR,Device Type Identifier Register"
|
|
line.long 0x08 "PERID4,Peripheral ID4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID3 Register"
|
|
line.long 0x10 "CID0,Component ID0 Register"
|
|
line.long 0x14 "CID1,Component ID1 Register"
|
|
line.long 0x18 "CID2,Component ID2 Register"
|
|
line.long 0x1c "CID3,Component ID3 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "CTI 1"
|
|
base ad:0x40005000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTICONTROL,CTICONTROL Register"
|
|
bitfld.long 0x00 0. " GLBEN ,Enables or disables the ECT" "Disabled,Enabled"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CTIINTACK,CTIINTACK Register"
|
|
bitfld.long 0x00 7. " INTACK[7] ,Acknowledges the corresponding CTITRIGOUT output 7" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 6. " INTACK[6] ,Acknowledges the corresponding CTITRIGOUT output 6" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTACK[5] ,Acknowledges the corresponding CTITRIGOUT output 5" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 4. " INTACK[4] ,Acknowledges the corresponding CTITRIGOUT output 4" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTACK[3] ,Acknowledges the corresponding CTITRIGOUT output 3" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 2. " INTACK[2] ,Acknowledges the corresponding CTITRIGOUT output 2" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTACK[1] ,Acknowledges the corresponding CTITRIGOUT output 1" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 0. " INTACK[0] ,Acknowledges the corresponding CTITRIGOUT output 0" "No effect,CTITRIGOUT"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTIAPPSET_CLR,CTIAPPSET Register"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " APPSET3_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " APPSET2_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " APPSET1_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " APPSET0_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CTIAPPPULSE,CTIAPPPULSE Register"
|
|
bitfld.long 0x00 3. " APPULSE3 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
bitfld.long 0x00 2. " APPULSE2 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " APPULSE1 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
bitfld.long 0x00 0. " APPULSE0 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
group.long 0x20++0x1f
|
|
line.long 0x0 "CTIINEN0,CTIINEN Register 0"
|
|
bitfld.long 0x0 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x4 "CTIINEN1,CTIINEN Register 1"
|
|
bitfld.long 0x4 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x8 "CTIINEN2,CTIINEN Register 2"
|
|
bitfld.long 0x8 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0xC "CTIINEN3,CTIINEN Register 3"
|
|
bitfld.long 0xC 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0xC 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x10 "CTIINEN4,CTIINEN Register 4"
|
|
bitfld.long 0x10 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x14 "CTIINEN5,CTIINEN Register 5"
|
|
bitfld.long 0x14 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x18 "CTIINEN6,CTIINEN Register 6"
|
|
bitfld.long 0x18 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x1C "CTIINEN7,CTIINEN Register 7"
|
|
bitfld.long 0x1C 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
group.long 0xa0++0x1f
|
|
line.long 0x0 "CTIOUTEN0,CTIOUTEN Register 0"
|
|
bitfld.long 0x0 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x4 "CTIOUTEN1,CTIOUTEN Register 1"
|
|
bitfld.long 0x4 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x8 "CTIOUTEN2,CTIOUTEN Register 2"
|
|
bitfld.long 0x8 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0xC "CTIOUTEN3,CTIOUTEN Register 3"
|
|
bitfld.long 0xC 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0xC 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x10 "CTIOUTEN4,CTIOUTEN Register 4"
|
|
bitfld.long 0x10 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x14 "CTIOUTEN5,CTIOUTEN Register 5"
|
|
bitfld.long 0x14 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x18 "CTIOUTEN6,CTIOUTEN Register 6"
|
|
bitfld.long 0x18 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x1C "CTIOUTEN7,CTIOUTEN Register 7"
|
|
bitfld.long 0x1C 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
rgroup.long 0x130++0x0f
|
|
line.long 0x00 "CTITRIGINSTATUS,CTITRIGINSTATUS Register"
|
|
bitfld.long 0x000 7. " TRIGINSTATUS7 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 6. " TRIGINSTATUS6 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 5. " TRIGINSTATUS5 , Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 4. " TRIGINSTATUS4 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 3. " TRIGINSTATUS3 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 2. " TRIGINSTATUS2 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 1. " TRIGINSTATUS1 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 0. " TRIGINSTATUS0 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
line.long 0x04 "CTITRIGOUTSTATUS,CTITRIGOUTSTATUS Register"
|
|
bitfld.long 0x004 7. " TRIGOUTSTATUS7 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 6. " TRIGOUTSTATUS6 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 5. " TRIGOUTSTATUS5 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 4. " TRIGOUTSTATUS4 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 3. " TRIGOUTSTATUS3 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 2. " TRIGOUTSTATUS2 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 1. " TRIGOUTSTATUS1 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 0. " TRIGOUTSTATUS0 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
line.long 0x08 "CTICHINSTATUS,CTICHINSTATUS Register"
|
|
bitfld.long 0x08 7. " CTICHINSTATUS7 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 6. " CTICHINSTATUS6 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CTICHINSTATUS5 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 4. " CTICHINSTATUS4 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CTICHINSTATUS3 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 2. " CTICHINSTATUS2 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CTICHINSTATUS1 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 0. " CTICHINSTATUS0 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
line.long 0x0c "CTICHOUTSTATUS,CTI Channel Out Status Register"
|
|
bitfld.long 0x0C 3. " CTICHOUTSTATUS0 ,Shows the status of the CTICHOUT outputs 0" "Inactive,Active"
|
|
bitfld.long 0x0C 2. " CTICHOUTSTATUS ,Shows the status of the CTICHOUT outputs " "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CTICHOUTSTATUS0 ,Shows the status of the CTICHOUT outputs 0" "Inactive,Active"
|
|
bitfld.long 0x0C 0. " CTICHOUTSTATUS ,Shows the status of the CTICHOUT outputs " "Inactive,Active"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "CTIGATE,Channel gate"
|
|
bitfld.long 0x00 3. " CTIGATEEN3 ,Disable Channel Propagation (Gate CTICHOUT3)" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " CTIGATEEN2 ,Disable Channel Propagation (Gate CTICHOUT2)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CTIGATEEN1 ,Disable Channel Propagation (Gate CTICHOUT1)" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CTIGATEEN0 ,Disable Channel Propagation (Gate CTICHOUT0)" "Enabled,Disabled"
|
|
line.long 0x04 "ASICCTL,External Multiplexor Control"
|
|
hexmask.long.byte 0x004 0.--7. 1. " ASICCTL ,Implementation-defined ASIC Control, Value in Register Is Output On ASICCTL[7:0]"
|
|
wgroup.long 0xedc++0x0f
|
|
line.long 0x00 "ITCHINACK,ITCHINACK Register"
|
|
bitfld.long 0x000 0.--3. " CTCHINACK ,Value of the CTCHINACK Outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ITTRIGINACK,ITTRIGINACK Register"
|
|
hexmask.long.byte 0x004 0.--7. 1. " CTTRIGINACK ,Value of the CTTRIGINACK Outputs"
|
|
line.long 0x08 "ITCHOUT,ITCHOUT Register"
|
|
bitfld.long 0x008 0.--3. " CTCHOUT ,Value of the CTCHOUT Outputs" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF"
|
|
line.long 0x0c "ITTRIGOUT,ITTRIGOUT Register"
|
|
hexmask.long.byte 0x00C 0.--7. 1. " CTTRIGOUT ,Value of the CTTRIGOUT Outputs"
|
|
rgroup.long 0xeec++0x0f
|
|
line.long 0x00 "ITCHOUTACK,ITCHOUTACK Register"
|
|
hexmask.long.byte 0x000 0.--7. 1. " CTCHOUTACK ,Values of the CTCHOUTACK Inputs"
|
|
line.long 0x04 "ITTRIGOUTACK,ITTRIGOUTACK Register"
|
|
hexmask.long.byte 0x004 0.--7. 1. " CTTRIGOUTACK ,Values of the CTTRIGOUTACK Inputs"
|
|
line.long 0x08 "ITCHIN,ITCHIN Register"
|
|
bitfld.long 0x008 0.--3. " CTCHIN ,Value of the CTCHIN Inputs" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0x0c "ITTRIGIN,ITTRIGIN Register"
|
|
hexmask.long.byte 0x00C 0.--7. 1. " CTTRIGIN ,Values of the CTTRIGIN Inputs"
|
|
group.long 0xf00++0x03
|
|
line.long 0x00 "ITCTRL,ITCTRL Register"
|
|
group.long 0xfa0++0x07
|
|
line.long 0x00 "CTSR,Claim Tag Set Register"
|
|
bitfld.long 0x000 3. " SETCTV3 ,Set Claim Tag Value" "No effect,Set"
|
|
bitfld.long 0x000 2. " SETCTV2 ,Set Claim Tag Value" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x000 1. " SETCTV1 ,Set Claim Tag Value" "No effect,Set"
|
|
bitfld.long 0x000 0. " SETCTV0 ,Set Claim Tag Value" "No effect,Set"
|
|
line.long 0x04 "CTCR,Claim Tag Clear Register"
|
|
bitfld.long 0x004 3. " CLRCTV3 ,Clear Claim Tag Value" "No effect,Clear"
|
|
bitfld.long 0x004 2. " CLRCTV2 ,Clear Claim Tag Value" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x004 1. " CLRCTV1 ,Clear Claim Tag Value" "No effect,Clear"
|
|
bitfld.long 0x004 0. " CLRCTV0 ,Clear Claim Tag Value" "No effect,Clear"
|
|
wgroup.long 0xfb0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xfb4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
line.long 0x04 "ASR,Authentication Status Register"
|
|
rgroup.long 0xfc8++0x0b
|
|
line.long 0x00 "DEVID,Device ID Register"
|
|
line.long 0x04 "DTIR,Device Type Identifier Register"
|
|
line.long 0x08 "PERID4,Peripheral ID4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID3 Register"
|
|
line.long 0x10 "CID0,Component ID0 Register"
|
|
line.long 0x14 "CID1,Component ID1 Register"
|
|
line.long 0x18 "CID2,Component ID2 Register"
|
|
line.long 0x1c "CID3,Component ID3 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "CTI 2"
|
|
base ad:0x40006000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTICONTROL,CTICONTROL Register"
|
|
bitfld.long 0x00 0. " GLBEN ,Enables or disables the ECT" "Disabled,Enabled"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CTIINTACK,CTIINTACK Register"
|
|
bitfld.long 0x00 7. " INTACK[7] ,Acknowledges the corresponding CTITRIGOUT output 7" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 6. " INTACK[6] ,Acknowledges the corresponding CTITRIGOUT output 6" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTACK[5] ,Acknowledges the corresponding CTITRIGOUT output 5" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 4. " INTACK[4] ,Acknowledges the corresponding CTITRIGOUT output 4" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTACK[3] ,Acknowledges the corresponding CTITRIGOUT output 3" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 2. " INTACK[2] ,Acknowledges the corresponding CTITRIGOUT output 2" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTACK[1] ,Acknowledges the corresponding CTITRIGOUT output 1" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 0. " INTACK[0] ,Acknowledges the corresponding CTITRIGOUT output 0" "No effect,CTITRIGOUT"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTIAPPSET_CLR,CTIAPPSET Register"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " APPSET3_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " APPSET2_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " APPSET1_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " APPSET0_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CTIAPPPULSE,CTIAPPPULSE Register"
|
|
bitfld.long 0x00 3. " APPULSE3 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
bitfld.long 0x00 2. " APPULSE2 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " APPULSE1 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
bitfld.long 0x00 0. " APPULSE0 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
group.long 0x20++0x1f
|
|
line.long 0x0 "CTIINEN0,CTIINEN Register 0"
|
|
bitfld.long 0x0 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x4 "CTIINEN1,CTIINEN Register 1"
|
|
bitfld.long 0x4 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x8 "CTIINEN2,CTIINEN Register 2"
|
|
bitfld.long 0x8 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0xC "CTIINEN3,CTIINEN Register 3"
|
|
bitfld.long 0xC 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0xC 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x10 "CTIINEN4,CTIINEN Register 4"
|
|
bitfld.long 0x10 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x14 "CTIINEN5,CTIINEN Register 5"
|
|
bitfld.long 0x14 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x18 "CTIINEN6,CTIINEN Register 6"
|
|
bitfld.long 0x18 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x1C "CTIINEN7,CTIINEN Register 7"
|
|
bitfld.long 0x1C 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
group.long 0xa0++0x1f
|
|
line.long 0x0 "CTIOUTEN0,CTIOUTEN Register 0"
|
|
bitfld.long 0x0 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x4 "CTIOUTEN1,CTIOUTEN Register 1"
|
|
bitfld.long 0x4 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x8 "CTIOUTEN2,CTIOUTEN Register 2"
|
|
bitfld.long 0x8 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0xC "CTIOUTEN3,CTIOUTEN Register 3"
|
|
bitfld.long 0xC 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0xC 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x10 "CTIOUTEN4,CTIOUTEN Register 4"
|
|
bitfld.long 0x10 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x14 "CTIOUTEN5,CTIOUTEN Register 5"
|
|
bitfld.long 0x14 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x18 "CTIOUTEN6,CTIOUTEN Register 6"
|
|
bitfld.long 0x18 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x1C "CTIOUTEN7,CTIOUTEN Register 7"
|
|
bitfld.long 0x1C 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
rgroup.long 0x130++0x0f
|
|
line.long 0x00 "CTITRIGINSTATUS,CTITRIGINSTATUS Register"
|
|
bitfld.long 0x000 7. " TRIGINSTATUS7 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 6. " TRIGINSTATUS6 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 5. " TRIGINSTATUS5 , Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 4. " TRIGINSTATUS4 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 3. " TRIGINSTATUS3 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 2. " TRIGINSTATUS2 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 1. " TRIGINSTATUS1 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 0. " TRIGINSTATUS0 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
line.long 0x04 "CTITRIGOUTSTATUS,CTITRIGOUTSTATUS Register"
|
|
bitfld.long 0x004 7. " TRIGOUTSTATUS7 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 6. " TRIGOUTSTATUS6 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 5. " TRIGOUTSTATUS5 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 4. " TRIGOUTSTATUS4 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 3. " TRIGOUTSTATUS3 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 2. " TRIGOUTSTATUS2 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 1. " TRIGOUTSTATUS1 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 0. " TRIGOUTSTATUS0 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
line.long 0x08 "CTICHINSTATUS,CTICHINSTATUS Register"
|
|
bitfld.long 0x08 7. " CTICHINSTATUS7 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 6. " CTICHINSTATUS6 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CTICHINSTATUS5 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 4. " CTICHINSTATUS4 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CTICHINSTATUS3 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 2. " CTICHINSTATUS2 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CTICHINSTATUS1 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 0. " CTICHINSTATUS0 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
line.long 0x0c "CTICHOUTSTATUS,CTI Channel Out Status Register"
|
|
bitfld.long 0x0C 3. " CTICHOUTSTATUS0 ,Shows the status of the CTICHOUT outputs 0" "Inactive,Active"
|
|
bitfld.long 0x0C 2. " CTICHOUTSTATUS ,Shows the status of the CTICHOUT outputs " "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CTICHOUTSTATUS0 ,Shows the status of the CTICHOUT outputs 0" "Inactive,Active"
|
|
bitfld.long 0x0C 0. " CTICHOUTSTATUS ,Shows the status of the CTICHOUT outputs " "Inactive,Active"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "CTIGATE,Channel gate"
|
|
bitfld.long 0x00 3. " CTIGATEEN3 ,Disable Channel Propagation (Gate CTICHOUT3)" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " CTIGATEEN2 ,Disable Channel Propagation (Gate CTICHOUT2)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CTIGATEEN1 ,Disable Channel Propagation (Gate CTICHOUT1)" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CTIGATEEN0 ,Disable Channel Propagation (Gate CTICHOUT0)" "Enabled,Disabled"
|
|
line.long 0x04 "ASICCTL,External Multiplexor Control"
|
|
hexmask.long.byte 0x004 0.--7. 1. " ASICCTL ,Implementation-defined ASIC Control, Value in Register Is Output On ASICCTL[7:0]"
|
|
wgroup.long 0xedc++0x0f
|
|
line.long 0x00 "ITCHINACK,ITCHINACK Register"
|
|
bitfld.long 0x000 0.--3. " CTCHINACK ,Value of the CTCHINACK Outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ITTRIGINACK,ITTRIGINACK Register"
|
|
hexmask.long.byte 0x004 0.--7. 1. " CTTRIGINACK ,Value of the CTTRIGINACK Outputs"
|
|
line.long 0x08 "ITCHOUT,ITCHOUT Register"
|
|
bitfld.long 0x008 0.--3. " CTCHOUT ,Value of the CTCHOUT Outputs" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF"
|
|
line.long 0x0c "ITTRIGOUT,ITTRIGOUT Register"
|
|
hexmask.long.byte 0x00C 0.--7. 1. " CTTRIGOUT ,Value of the CTTRIGOUT Outputs"
|
|
rgroup.long 0xeec++0x0f
|
|
line.long 0x00 "ITCHOUTACK,ITCHOUTACK Register"
|
|
hexmask.long.byte 0x000 0.--7. 1. " CTCHOUTACK ,Values of the CTCHOUTACK Inputs"
|
|
line.long 0x04 "ITTRIGOUTACK,ITTRIGOUTACK Register"
|
|
hexmask.long.byte 0x004 0.--7. 1. " CTTRIGOUTACK ,Values of the CTTRIGOUTACK Inputs"
|
|
line.long 0x08 "ITCHIN,ITCHIN Register"
|
|
bitfld.long 0x008 0.--3. " CTCHIN ,Value of the CTCHIN Inputs" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0x0c "ITTRIGIN,ITTRIGIN Register"
|
|
hexmask.long.byte 0x00C 0.--7. 1. " CTTRIGIN ,Values of the CTTRIGIN Inputs"
|
|
group.long 0xf00++0x03
|
|
line.long 0x00 "ITCTRL,ITCTRL Register"
|
|
group.long 0xfa0++0x07
|
|
line.long 0x00 "CTSR,Claim Tag Set Register"
|
|
bitfld.long 0x000 3. " SETCTV3 ,Set Claim Tag Value" "No effect,Set"
|
|
bitfld.long 0x000 2. " SETCTV2 ,Set Claim Tag Value" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x000 1. " SETCTV1 ,Set Claim Tag Value" "No effect,Set"
|
|
bitfld.long 0x000 0. " SETCTV0 ,Set Claim Tag Value" "No effect,Set"
|
|
line.long 0x04 "CTCR,Claim Tag Clear Register"
|
|
bitfld.long 0x004 3. " CLRCTV3 ,Clear Claim Tag Value" "No effect,Clear"
|
|
bitfld.long 0x004 2. " CLRCTV2 ,Clear Claim Tag Value" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x004 1. " CLRCTV1 ,Clear Claim Tag Value" "No effect,Clear"
|
|
bitfld.long 0x004 0. " CLRCTV0 ,Clear Claim Tag Value" "No effect,Clear"
|
|
wgroup.long 0xfb0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xfb4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
line.long 0x04 "ASR,Authentication Status Register"
|
|
rgroup.long 0xfc8++0x0b
|
|
line.long 0x00 "DEVID,Device ID Register"
|
|
line.long 0x04 "DTIR,Device Type Identifier Register"
|
|
line.long 0x08 "PERID4,Peripheral ID4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID3 Register"
|
|
line.long 0x10 "CID0,Component ID0 Register"
|
|
line.long 0x14 "CID1,Component ID1 Register"
|
|
line.long 0x18 "CID2,Component ID2 Register"
|
|
line.long 0x1c "CID3,Component ID3 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "CTI 3"
|
|
base ad:0x40007000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTICONTROL,CTICONTROL Register"
|
|
bitfld.long 0x00 0. " GLBEN ,Enables or disables the ECT" "Disabled,Enabled"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CTIINTACK,CTIINTACK Register"
|
|
bitfld.long 0x00 7. " INTACK[7] ,Acknowledges the corresponding CTITRIGOUT output 7" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 6. " INTACK[6] ,Acknowledges the corresponding CTITRIGOUT output 6" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTACK[5] ,Acknowledges the corresponding CTITRIGOUT output 5" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 4. " INTACK[4] ,Acknowledges the corresponding CTITRIGOUT output 4" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTACK[3] ,Acknowledges the corresponding CTITRIGOUT output 3" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 2. " INTACK[2] ,Acknowledges the corresponding CTITRIGOUT output 2" "No effect,CTITRIGOUT"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTACK[1] ,Acknowledges the corresponding CTITRIGOUT output 1" "No effect,CTITRIGOUT"
|
|
bitfld.long 0x00 0. " INTACK[0] ,Acknowledges the corresponding CTITRIGOUT output 0" "No effect,CTITRIGOUT"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTIAPPSET_CLR,CTIAPPSET Register"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " APPSET3_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " APPSET2_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " APPSET1_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " APPSET0_set/clr ,Application Trigger Active" "Inactive,Active"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CTIAPPPULSE,CTIAPPPULSE Register"
|
|
bitfld.long 0x00 3. " APPULSE3 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
bitfld.long 0x00 2. " APPULSE2 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " APPULSE1 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
bitfld.long 0x00 0. " APPULSE0 ,Generate Channel Event Pulse for the Selected Channel" "No effect,Generated"
|
|
group.long 0x20++0x1f
|
|
line.long 0x0 "CTIINEN0,CTIINEN Register 0"
|
|
bitfld.long 0x0 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x4 "CTIINEN1,CTIINEN Register 1"
|
|
bitfld.long 0x4 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x8 "CTIINEN2,CTIINEN Register 2"
|
|
bitfld.long 0x8 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0xC "CTIINEN3,CTIINEN Register 3"
|
|
bitfld.long 0xC 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0xC 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x10 "CTIINEN4,CTIINEN Register 4"
|
|
bitfld.long 0x10 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x14 "CTIINEN5,CTIINEN Register 5"
|
|
bitfld.long 0x14 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x18 "CTIINEN6,CTIINEN Register 6"
|
|
bitfld.long 0x18 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
line.long 0x1C "CTIINEN7,CTIINEN Register 7"
|
|
bitfld.long 0x1C 3. " TRIGINEN3 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " TRIGINEN2 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " TRIGINEN1 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TRIGINEN0 ,Enables CTITRIGIN Signal to Generate an Event on the Respective Channel of the CTM" "Disabled,Enabled"
|
|
group.long 0xa0++0x1f
|
|
line.long 0x0 "CTIOUTEN0,CTIOUTEN Register 0"
|
|
bitfld.long 0x0 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x4 "CTIOUTEN1,CTIOUTEN Register 1"
|
|
bitfld.long 0x4 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x8 "CTIOUTEN2,CTIOUTEN Register 2"
|
|
bitfld.long 0x8 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0xC "CTIOUTEN3,CTIOUTEN Register 3"
|
|
bitfld.long 0xC 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0xC 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x10 "CTIOUTEN4,CTIOUTEN Register 4"
|
|
bitfld.long 0x10 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x14 "CTIOUTEN5,CTIOUTEN Register 5"
|
|
bitfld.long 0x14 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x18 "CTIOUTEN6,CTIOUTEN Register 6"
|
|
bitfld.long 0x18 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
line.long 0x1C "CTIOUTEN7,CTIOUTEN Register 7"
|
|
bitfld.long 0x1C 3. " TRIGOUTEN3 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " TRIGOUTEN2 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " TRIGOUTEN1 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TRIGOUTEN0 ,Enables Channel Event for the Corresponding Channel to Generate an CTITRIGOUT Output" "Disabled,Enabled"
|
|
rgroup.long 0x130++0x0f
|
|
line.long 0x00 "CTITRIGINSTATUS,CTITRIGINSTATUS Register"
|
|
bitfld.long 0x000 7. " TRIGINSTATUS7 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 6. " TRIGINSTATUS6 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 5. " TRIGINSTATUS5 , Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 4. " TRIGINSTATUS4 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 3. " TRIGINSTATUS3 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 2. " TRIGINSTATUS2 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x000 1. " TRIGINSTATUS1 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x000 0. " TRIGINSTATUS0 ,Status of the CTITRIGIN Inputs" "Inactive,Active"
|
|
line.long 0x04 "CTITRIGOUTSTATUS,CTITRIGOUTSTATUS Register"
|
|
bitfld.long 0x004 7. " TRIGOUTSTATUS7 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 6. " TRIGOUTSTATUS6 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 5. " TRIGOUTSTATUS5 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 4. " TRIGOUTSTATUS4 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 3. " TRIGOUTSTATUS3 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 2. " TRIGOUTSTATUS2 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x004 1. " TRIGOUTSTATUS1 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
bitfld.long 0x004 0. " TRIGOUTSTATUS0 ,Status of the CTITRIGOUT Outputs" "Inactive,Active"
|
|
line.long 0x08 "CTICHINSTATUS,CTICHINSTATUS Register"
|
|
bitfld.long 0x08 7. " CTICHINSTATUS7 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 6. " CTICHINSTATUS6 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CTICHINSTATUS5 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 4. " CTICHINSTATUS4 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CTICHINSTATUS3 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 2. " CTICHINSTATUS2 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CTICHINSTATUS1 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
bitfld.long 0x08 0. " CTICHINSTATUS0 ,Status of the CTICHIN Inputs" "Inactive,Active"
|
|
line.long 0x0c "CTICHOUTSTATUS,CTI Channel Out Status Register"
|
|
bitfld.long 0x0C 3. " CTICHOUTSTATUS0 ,Shows the status of the CTICHOUT outputs 0" "Inactive,Active"
|
|
bitfld.long 0x0C 2. " CTICHOUTSTATUS ,Shows the status of the CTICHOUT outputs " "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CTICHOUTSTATUS0 ,Shows the status of the CTICHOUT outputs 0" "Inactive,Active"
|
|
bitfld.long 0x0C 0. " CTICHOUTSTATUS ,Shows the status of the CTICHOUT outputs " "Inactive,Active"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "CTIGATE,Channel gate"
|
|
bitfld.long 0x00 3. " CTIGATEEN3 ,Disable Channel Propagation (Gate CTICHOUT3)" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " CTIGATEEN2 ,Disable Channel Propagation (Gate CTICHOUT2)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CTIGATEEN1 ,Disable Channel Propagation (Gate CTICHOUT1)" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CTIGATEEN0 ,Disable Channel Propagation (Gate CTICHOUT0)" "Enabled,Disabled"
|
|
line.long 0x04 "ASICCTL,External Multiplexor Control"
|
|
hexmask.long.byte 0x004 0.--7. 1. " ASICCTL ,Implementation-defined ASIC Control, Value in Register Is Output On ASICCTL[7:0]"
|
|
wgroup.long 0xedc++0x0f
|
|
line.long 0x00 "ITCHINACK,ITCHINACK Register"
|
|
bitfld.long 0x000 0.--3. " CTCHINACK ,Value of the CTCHINACK Outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ITTRIGINACK,ITTRIGINACK Register"
|
|
hexmask.long.byte 0x004 0.--7. 1. " CTTRIGINACK ,Value of the CTTRIGINACK Outputs"
|
|
line.long 0x08 "ITCHOUT,ITCHOUT Register"
|
|
bitfld.long 0x008 0.--3. " CTCHOUT ,Value of the CTCHOUT Outputs" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF"
|
|
line.long 0x0c "ITTRIGOUT,ITTRIGOUT Register"
|
|
hexmask.long.byte 0x00C 0.--7. 1. " CTTRIGOUT ,Value of the CTTRIGOUT Outputs"
|
|
rgroup.long 0xeec++0x0f
|
|
line.long 0x00 "ITCHOUTACK,ITCHOUTACK Register"
|
|
hexmask.long.byte 0x000 0.--7. 1. " CTCHOUTACK ,Values of the CTCHOUTACK Inputs"
|
|
line.long 0x04 "ITTRIGOUTACK,ITTRIGOUTACK Register"
|
|
hexmask.long.byte 0x004 0.--7. 1. " CTTRIGOUTACK ,Values of the CTTRIGOUTACK Inputs"
|
|
line.long 0x08 "ITCHIN,ITCHIN Register"
|
|
bitfld.long 0x008 0.--3. " CTCHIN ,Value of the CTCHIN Inputs" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
line.long 0x0c "ITTRIGIN,ITTRIGIN Register"
|
|
hexmask.long.byte 0x00C 0.--7. 1. " CTTRIGIN ,Values of the CTTRIGIN Inputs"
|
|
group.long 0xf00++0x03
|
|
line.long 0x00 "ITCTRL,ITCTRL Register"
|
|
group.long 0xfa0++0x07
|
|
line.long 0x00 "CTSR,Claim Tag Set Register"
|
|
bitfld.long 0x000 3. " SETCTV3 ,Set Claim Tag Value" "No effect,Set"
|
|
bitfld.long 0x000 2. " SETCTV2 ,Set Claim Tag Value" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x000 1. " SETCTV1 ,Set Claim Tag Value" "No effect,Set"
|
|
bitfld.long 0x000 0. " SETCTV0 ,Set Claim Tag Value" "No effect,Set"
|
|
line.long 0x04 "CTCR,Claim Tag Clear Register"
|
|
bitfld.long 0x004 3. " CLRCTV3 ,Clear Claim Tag Value" "No effect,Clear"
|
|
bitfld.long 0x004 2. " CLRCTV2 ,Clear Claim Tag Value" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x004 1. " CLRCTV1 ,Clear Claim Tag Value" "No effect,Clear"
|
|
bitfld.long 0x004 0. " CLRCTV0 ,Clear Claim Tag Value" "No effect,Clear"
|
|
wgroup.long 0xfb0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xfb4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
line.long 0x04 "ASR,Authentication Status Register"
|
|
rgroup.long 0xfc8++0x0b
|
|
line.long 0x00 "DEVID,Device ID Register"
|
|
line.long 0x04 "DTIR,Device Type Identifier Register"
|
|
line.long 0x08 "PERID4,Peripheral ID4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID3 Register"
|
|
line.long 0x10 "CID0,Component ID0 Register"
|
|
line.long 0x14 "CID1,Component ID1 Register"
|
|
line.long 0x18 "CID2,Component ID2 Register"
|
|
line.long 0x1c "CID3,Component ID3 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "TPIU"
|
|
base ad:0x40003000
|
|
width 0xb
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SPSR,Supported port sizes Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CPCR,Current port size Register"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "STMR,Supported trigger modes Register"
|
|
group.long 0x104++0x07
|
|
line.long 0x00 "TCVR,Trigger counter value Register"
|
|
line.long 0x04 "TMR,Trigger multiplier Register"
|
|
rgroup.long 0x200++0x07
|
|
line.long 0x00 "STPMR,Supported test pattern/modes Register"
|
|
line.long 0x04 "CTPMR,Current test pattern/mode Register"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "TPRCR,Test pattern repeat counter Register"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "FFSR,Formatter flush and status Register"
|
|
group.long 0x304++0x07
|
|
line.long 0x00 "FFCR,Fomatter flush and control Register"
|
|
line.long 0x04 "FSCR,Formatter synchronization counter Register"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "EIPR,EXTCTL In Port Register"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "EOPR,EXTCTL Out Port Register"
|
|
wgroup.long 0xee4++0x0f
|
|
line.long 0x00 "ITTRFLINACK,Integration Register"
|
|
line.long 0x04 "ITTRFLIN,Integration Register"
|
|
line.long 0x08 "ITATBDATA0,Integration Register"
|
|
line.long 0x0c "ITATBCTR2,Integration Register"
|
|
rgroup.long 0xef4++0x07
|
|
line.long 0x00 "ITATBCTR1,Integration Register"
|
|
line.long 0x04 "ITATBCTR0,Integration Register"
|
|
group.long 0xf00++0x03
|
|
line.long 0x00 "ITATBCTR0,Integration Register"
|
|
group.long 0xfa0++0x07
|
|
line.long 0x00 "CTSR,Claim Tag Set Register"
|
|
line.long 0x04 "CTCR,Claim Tag Clear Register"
|
|
wgroup.long 0xfb0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xfb4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
line.long 0x04 "ASR,Authentication Status Register"
|
|
rgroup.long 0xfc8++0x0b
|
|
line.long 0x00 "DEVID,Device ID Register"
|
|
line.long 0x04 "DTIR,Device Type Identifier Register"
|
|
line.long 0x08 "PERID4,Peripheral ID 4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID 0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID 1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID 2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID 3 Register"
|
|
line.long 0x10 "COMPID0,Component ID0 Register"
|
|
line.long 0x14 "COMPID1,Component ID1 Register"
|
|
line.long 0x18 "COMPID2,Component ID2 Register"
|
|
line.long 0x1C "COMPID3,Component ID3 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "MAX (Multi-Layer AHB Crossbar Switch)"
|
|
base ad:0x63f94000
|
|
width 8.
|
|
if (((per.long(ad:0x63f94000+0x10))&0x80000000)==0x00)
|
|
group.long 0x00++0x3 "Slave Port 0"
|
|
line.long 0x00 "MPR0,Master Priority Register 0"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SGPCR0,General Purpose Control Register 0"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
else
|
|
rgroup.long 0x00++0x3 "Slave Port 0"
|
|
line.long 0x00 "MPR0,Master Priority Register 0"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "SGPCR0,General Purpose Control Register 0"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
endif
|
|
if (((per.long(ad:0x63f94000+0x110))&0x80000000)==0x00)
|
|
group.long 0x100++0x3 "Slave Port 1"
|
|
line.long 0x00 "MPR1,Master Priority Register 1"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "SGPCR1,General Purpose Control Register 1"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
else
|
|
rgroup.long 0x100++0x3 "Slave Port 1"
|
|
line.long 0x00 "MPR1,Master Priority Register 1"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
rgroup.long 0x110++0x3
|
|
line.long 0x00 "SGPCR1,General Purpose Control Register 1"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
endif
|
|
if (((per.long(ad:0x63f94000+0x210))&0x80000000)==0x00)
|
|
group.long 0x200++0x3 "Slave Port 2"
|
|
line.long 0x00 "MPR2,Master Priority Register 2"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
group.long 0x210++0x3
|
|
line.long 0x00 "SGPCR2,General Purpose Control Register 2"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
else
|
|
rgroup.long 0x200++0x3 "Slave Port 2"
|
|
line.long 0x00 "MPR2,Master Priority Register 2"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x00 "SGPCR2,General Purpose Control Register 2"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
endif
|
|
if (((per.long(ad:0x63f94000+0x310))&0x80000000)==0x00)
|
|
group.long 0x300++0x3 "Slave Port 3"
|
|
line.long 0x00 "MPR3,Master Priority Register 3"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
group.long 0x310++0x3
|
|
line.long 0x00 "SGPCR3,General Purpose Control Register 3"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
else
|
|
rgroup.long 0x300++0x3 "Slave Port 3"
|
|
line.long 0x00 "MPR3,Master Priority Register 3"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
rgroup.long 0x310++0x3
|
|
line.long 0x00 "SGPCR3,General Purpose Control Register 3"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
endif
|
|
group.long 0x800++0x3 "Master Port 0"
|
|
line.long 0x00 "MGPCR0,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0x900++0x3 "Master Port 1"
|
|
line.long 0x00 "MGPCR1,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0xa00++0x3 "Master Port 2"
|
|
line.long 0x00 "MGPCR2,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0xb00++0x3 "Master Port 3"
|
|
line.long 0x00 "MGPCR3,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0xc00++0x3 "Master Port 4"
|
|
line.long 0x00 "MGPCR4,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0xd00++0x3 "Master Port 5"
|
|
line.long 0x00 "MGPCR5,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0xe00++0x3 "Master Port 6"
|
|
line.long 0x00 "MGPCR6,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "APBH-Bridge-DMA (AHB-to-APBH Bridge with DMA)"
|
|
base ad:0x41000000
|
|
width 15.
|
|
group.long 0x00++0x3F
|
|
line.long 0x00 "APBH_CTRL0,AHB to APBH Bridge Control and Status Register 0"
|
|
bitfld.long 0x00 31. " SFTRST ,APBH DMA clocking disable" "No,Yes"
|
|
bitfld.long 0x00 30. " CLKGATE ,Clock gate" "Not gated,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 29. " AHB_BURST8_EN ,AHB 8-bit burst enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " APB_BURST_EN ,APB burst enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " CLKGATE_CHANNEL ,Clock gate channel"
|
|
line.long 0x04 "APBH_CTRL0_SET,AHB to APBH Bridge Control and Status Register 0"
|
|
bitfld.long 0x04 31. " SFTRST ,APBH DMA clocking disable set" "No effect,Set"
|
|
bitfld.long 0x04 30. " CLKGATE ,Clock gate set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 29. " AHB_BURST8_EN ,AHB 8-bit burst set" "No effect,Set"
|
|
bitfld.long 0x04 28. " APB_BURST_EN ,APB burst set" "No effect,Set"
|
|
line.long 0x08 "APBH_CTRL0_CLR,AHB to APBH Bridge Control and Status Register 0"
|
|
bitfld.long 0x08 31. " SFTRST ,APBH DMA clocking disable clear" "No effect,Clear"
|
|
bitfld.long 0x08 30. " CLKGATE ,Clock gate clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 29. " AHB_BURST8_EN ,AHB 8-bit burst clear" "No effect,Clear"
|
|
bitfld.long 0x08 28. " APB_BURST_EN ,APB burst clear" "No effect,Clear"
|
|
line.long 0x0C "APBH_CTRL0_TOG,AHB to APBH Bridge Control and Status Register 0"
|
|
bitfld.long 0x0C 31. " SFTRST ,APBH DMA clocking disable toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 30. " CLKGATE ,Clock gate toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " AHB_BURST8_EN ,AHB 8-bit burst toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 28. " APB_BURST_EN ,APB burst toggle" "Not toggled,Toggled"
|
|
width 19.
|
|
line.long 0x10 "HW_APBH_CTRL1,AHB to APBH Bridge Control and Status Register 1"
|
|
bitfld.long 0x10 31. " CH15_CMDCMPLT_IRQ_EN ,APBH DMA channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " CH14_CMDCMPLT_IRQ_EN ,APBH DMA channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " CH15_CMDCMPLT_IRQ ,Interrupt 15 request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 14. " CH14_CMDCMPLT_IRQ ,Interrupt 14 request status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 13. " CH13_CMDCMPLT_IRQ ,Interrupt 13 request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 12. " CH12_CMDCMPLT_IRQ ,Interrupt 12 request status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 11. " CH11_CMDCMPLT_IRQ ,Interrupt 11 request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 10. " CH10_CMDCMPLT_IRQ ,Interrupt 10 request status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 9. " CH9_CMDCMPLT_IRQ ,Interrupt 9 request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " CH8_CMDCMPLT_IRQ ,Interrupt 8 request status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 7. " CH7_CMDCMPLT_IRQ ,Interrupt 7 request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 6. " CH6_CMDCMPLT_IRQ ,Interrupt 6 request status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 5. " CH5_CMDCMPLT_IRQ ,Interrupt 5 request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " CH4_CMDCMPLT_IRQ ,Interrupt 4 request status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 3. " CH3_CMDCMPLT_IRQ ,Interrupt 3 request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " CH2_CMDCMPLT_IRQ ,Interrupt 2 request status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 1. " CH1_CMDCMPLT_IRQ ,Interrupt 1 request status" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " CH0_CMDCMPLT_IRQ ,Interrupt 0 request status" "No interrupt,Interrupt"
|
|
line.long 0x14 "APBH_CTRL1_SET,AHB to APBH Bridge Control and Status Register 1 Set"
|
|
bitfld.long 0x14 31. " CH15_CMDCMPLT_IRQ_EN ,APBH DMA channel 15 set" "No effect,Set"
|
|
bitfld.long 0x14 30. " CH14_CMDCMPLT_IRQ_EN ,APBH DMA channel 14 set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 set" "No effect,Set"
|
|
bitfld.long 0x14 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 set" "No effect,Set"
|
|
bitfld.long 0x14 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 set" "No effect,Set"
|
|
bitfld.long 0x14 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 set" "No effect,Set"
|
|
bitfld.long 0x14 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 set" "No effect,Set"
|
|
bitfld.long 0x14 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 set" "No effect,Set"
|
|
bitfld.long 0x14 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 set" "No effect,Set"
|
|
bitfld.long 0x14 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 15. " CH15_CMDCMPLT_IRQ ,Interrupt 15 request status" "No effect,Set"
|
|
bitfld.long 0x14 14. " CH14_CMDCMPLT_IRQ ,Interrupt 14 request status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 13. " CH13_CMDCMPLT_IRQ ,Interrupt 13 request status" "No effect,Set"
|
|
bitfld.long 0x14 12. " CH12_CMDCMPLT_IRQ ,Interrupt 12 request status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 11. " CH11_CMDCMPLT_IRQ ,Interrupt 11 request status" "No effect,Set"
|
|
bitfld.long 0x14 10. " CH10_CMDCMPLT_IRQ ,Interrupt 10 request status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 9. " CH9_CMDCMPLT_IRQ ,Interrupt 9 request status" "No effect,Set"
|
|
bitfld.long 0x14 8. " CH8_CMDCMPLT_IRQ ,Interrupt 8 request status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 7. " CH7_CMDCMPLT_IRQ ,Interrupt 7 request status" "No effect,Set"
|
|
bitfld.long 0x14 6. " CH6_CMDCMPLT_IRQ ,Interrupt 6 request status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 5. " CH5_CMDCMPLT_IRQ ,Interrupt 5 request status" "No effect,Set"
|
|
bitfld.long 0x14 4. " CH4_CMDCMPLT_IRQ ,Interrupt 4 request status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 3. " CH3_CMDCMPLT_IRQ ,Interrupt 3 request status" "No effect,Set"
|
|
bitfld.long 0x14 2. " CH2_CMDCMPLT_IRQ ,Interrupt 2 request status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 1. " CH1_CMDCMPLT_IRQ ,Interrupt 1 request status" "No effect,Set"
|
|
bitfld.long 0x14 0. " CH0_CMDCMPLT_IRQ ,Interrupt 0 request status" "No effect,Set"
|
|
line.long 0x18 "APBH_CTRL1_CLR,AHB to APBH Bridge Control and Status Register 1 Clear"
|
|
bitfld.long 0x18 31. " CH15_CMDCMPLT_IRQ_EN ,APBH DMA channel 15 clear" "No effect,Clear"
|
|
bitfld.long 0x18 30. " CH14_CMDCMPLT_IRQ_EN ,APBH DMA channel 14 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 clear" "No effect,Clear"
|
|
bitfld.long 0x18 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 clear" "No effect,Clear"
|
|
bitfld.long 0x18 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 clear" "No effect,Clear"
|
|
bitfld.long 0x18 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 clear" "No effect,Clear"
|
|
bitfld.long 0x18 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 clear" "No effect,Clear"
|
|
bitfld.long 0x18 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 clear" "No effect,Clear"
|
|
bitfld.long 0x18 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 clear" "No effect,Clear"
|
|
bitfld.long 0x18 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 15. " CH15_CMDCMPLT_IRQ ,Interrupt 15 request status" "No effect,Clear"
|
|
bitfld.long 0x18 14. " CH14_CMDCMPLT_IRQ ,Interrupt 14 request status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 13. " CH13_CMDCMPLT_IRQ ,Interrupt 13 request status" "No effect,Clear"
|
|
bitfld.long 0x18 12. " CH12_CMDCMPLT_IRQ ,Interrupt 12 request status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 11. " CH11_CMDCMPLT_IRQ ,Interrupt 11 request status" "No effect,Clear"
|
|
bitfld.long 0x18 10. " CH10_CMDCMPLT_IRQ ,Interrupt 10 request status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 9. " CH9_CMDCMPLT_IRQ ,Interrupt 9 request status" "No effect,Clear"
|
|
bitfld.long 0x18 8. " CH8_CMDCMPLT_IRQ ,Interrupt 8 request status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 7. " CH7_CMDCMPLT_IRQ ,Interrupt 7 request status" "No effect,Clear"
|
|
bitfld.long 0x18 6. " CH6_CMDCMPLT_IRQ ,Interrupt 6 request status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 5. " CH5_CMDCMPLT_IRQ ,Interrupt 5 request status" "No effect,Clear"
|
|
bitfld.long 0x18 4. " CH4_CMDCMPLT_IRQ ,Interrupt 4 request status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 3. " CH3_CMDCMPLT_IRQ ,Interrupt 3 request status" "No effect,Clear"
|
|
bitfld.long 0x18 2. " CH2_CMDCMPLT_IRQ ,Interrupt 2 request status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x18 1. " CH1_CMDCMPLT_IRQ ,Interrupt 1 request status" "No effect,Clear"
|
|
bitfld.long 0x18 0. " CH0_CMDCMPLT_IRQ ,Interrupt 0 request status" "No effect,Clear"
|
|
line.long 0x1C "APBH_CTRL1_TOG,AHB to APBH Bridge Control and Status Register 1 Toggle"
|
|
bitfld.long 0x1C 31. " CH15_CMDCMPLT_IRQ_EN ,APBH DMA channel 15 toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 30. " CH14_CMDCMPLT_IRQ_EN ,APBH DMA channel 14 toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " CH15_CMDCMPLT_IRQ ,Interrupt 15 request status" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 14. " CH14_CMDCMPLT_IRQ ,Interrupt 14 request status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " CH13_CMDCMPLT_IRQ ,Interrupt 13 request status" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 12. " CH12_CMDCMPLT_IRQ ,Interrupt 12 request status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " CH11_CMDCMPLT_IRQ ,Interrupt 11 request status" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 10. " CH10_CMDCMPLT_IRQ ,Interrupt 10 request status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " CH9_CMDCMPLT_IRQ ,Interrupt 9 request status" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 8. " CH8_CMDCMPLT_IRQ ,Interrupt 8 request status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " CH7_CMDCMPLT_IRQ ,Interrupt 7 request status" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 6. " CH6_CMDCMPLT_IRQ ,Interrupt 6 request status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " CH5_CMDCMPLT_IRQ ,Interrupt 5 request status" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 4. " CH4_CMDCMPLT_IRQ ,Interrupt 4 request status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " CH3_CMDCMPLT_IRQ ,Interrupt 3 request status" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 2. " CH2_CMDCMPLT_IRQ ,Interrupt 2 request status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " CH1_CMDCMPLT_IRQ ,Interrupt 1 request status" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 0. " CH0_CMDCMPLT_IRQ ,Interrupt 0 request status" "Not toggled,Toggled"
|
|
line.long 0x20 "HW_APBH_CTRL2,AHB to APBH Bridge Control and Status Register 2"
|
|
rbitfld.long 0x20 31. " CH15_ERROR_STATUS ,APBH DMA Channel 15 error status" "Early termination,AHB bus error"
|
|
rbitfld.long 0x20 30. " CH14_ERROR_STATUS ,APBH DMA Channel 14 error status" "Early termination,AHB bus error"
|
|
textline " "
|
|
rbitfld.long 0x20 29. " CH13_ERROR_STATUS ,APBH DMA Channel 13 error status" "Early termination,AHB bus error"
|
|
rbitfld.long 0x20 28. " CH12_ERROR_STATUS ,APBH DMA Channel 12 error status" "Early termination,AHB bus error"
|
|
textline " "
|
|
rbitfld.long 0x20 27. " CH11_ERROR_STATUS ,APBH DMA Channel 11 error status" "Early termination,AHB bus error"
|
|
rbitfld.long 0x20 26. " CH10_ERROR_STATUS ,APBH DMA Channel 10 error status" "Early termination,AHB bus error"
|
|
textline " "
|
|
rbitfld.long 0x20 25. " CH9_ERROR_STATUS ,APBH DMA Channel 9 error status" "Early termination,AHB bus error"
|
|
rbitfld.long 0x20 24. " CH8_ERROR_STATUS ,APBH DMA Channel 8 error status" "Early termination,AHB bus error"
|
|
textline " "
|
|
rbitfld.long 0x20 23. " CH7_ERROR_STATUS ,APBH DMA Channel 7 error status" "Early termination,AHB bus error"
|
|
rbitfld.long 0x20 22. " CH6_ERROR_STATUS ,APBH DMA Channel 6 error status" "Early termination,AHB bus error"
|
|
textline " "
|
|
rbitfld.long 0x20 21. " CH5_ERROR_STATUS ,APBH DMA Channel 5 error status" "Early termination,AHB bus error"
|
|
rbitfld.long 0x20 20. " CH4_ERROR_STATUS ,APBH DMA Channel 4 error status" "Early termination,AHB bus error"
|
|
textline " "
|
|
rbitfld.long 0x20 19. " CH3_ERROR_STATUS ,APBH DMA Channel 3 error status" "Early termination,AHB bus error"
|
|
rbitfld.long 0x20 18. " CH2_ERROR_STATUS ,APBH DMA Channel 2 error status" "Early termination,AHB bus error"
|
|
textline " "
|
|
rbitfld.long 0x20 17. " CH1_ERROR_STATUS ,APBH DMA Channel 1 error status" "Early termination,AHB bus error"
|
|
rbitfld.long 0x20 16. " CH0_ERROR_STATUS ,APBH DMA Channel 0 error status" "Early termination,AHB bus error"
|
|
textline " "
|
|
bitfld.long 0x20 15. " CH15_ERROR_IRQ ,Error interrupt 15 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 14. " CH14_ERROR_IRQ ,Error interrupt 14 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x20 13. " CH13_ERROR_IRQ ,Error interrupt 13 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 12. " CH12_ERROR_IRQ ,Error interrupt 12 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x20 11. " CH11_ERROR_IRQ ,Error interrupt 11 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 10. " CH10_ERROR_IRQ ,Error interrupt 10 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x20 9. " CH9_ERROR_IRQ ,Error interrupt 9 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 8. " CH8_ERROR_IRQ ,Error interrupt 8 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x20 7. " CH7_ERROR_IRQ ,Error interrupt 7 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 6. " CH6_ERROR_IRQ ,Error interrupt 6 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x20 5. " CH5_ERROR_IRQ ,Error interrupt 5 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 4. " CH4_ERROR_IRQ ,Error interrupt 4 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x20 3. " CH3_ERROR_IRQ ,Error interrupt 3 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 2. " CH2_ERROR_IRQ ,Error interrupt 2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x20 1. " CH1_ERROR_IRQ ,Error interrupt 1 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 0. " CH0_ERROR_IRQ ,Error interrupt 0 status" "No interrupt,Interrupt"
|
|
line.long 0x24 "HW_APBH_CTRL2_SET,AHB to APBH Bridge Control and Status Register 2 Set"
|
|
rbitfld.long 0x24 31. " CH15_ERROR_STATUS ,APBH DMA Channel 15 error status" "No effect,Set"
|
|
rbitfld.long 0x24 30. " CH14_ERROR_STATUS ,APBH DMA Channel 14 error status" "No effect,Set"
|
|
textline " "
|
|
rbitfld.long 0x24 29. " CH13_ERROR_STATUS ,APBH DMA Channel 13 error status" "No effect,Set"
|
|
rbitfld.long 0x24 28. " CH12_ERROR_STATUS ,APBH DMA Channel 12 error status" "No effect,Set"
|
|
textline " "
|
|
rbitfld.long 0x24 27. " CH11_ERROR_STATUS ,APBH DMA Channel 11 error status" "No effect,Set"
|
|
rbitfld.long 0x24 26. " CH10_ERROR_STATUS ,APBH DMA Channel 10 error status" "No effect,Set"
|
|
textline " "
|
|
rbitfld.long 0x24 25. " CH9_ERROR_STATUS ,APBH DMA Channel 9 error status" "No effect,Set"
|
|
rbitfld.long 0x24 24. " CH8_ERROR_STATUS ,APBH DMA Channel 8 error status" "No effect,Set"
|
|
textline " "
|
|
rbitfld.long 0x24 23. " CH7_ERROR_STATUS ,APBH DMA Channel 7 error status" "No effect,Set"
|
|
rbitfld.long 0x24 22. " CH6_ERROR_STATUS ,APBH DMA Channel 6 error status" "No effect,Set"
|
|
textline " "
|
|
rbitfld.long 0x24 21. " CH5_ERROR_STATUS ,APBH DMA Channel 5 error status" "No effect,Set"
|
|
rbitfld.long 0x24 20. " CH4_ERROR_STATUS ,APBH DMA Channel 4 error status" "No effect,Set"
|
|
textline " "
|
|
rbitfld.long 0x24 19. " CH3_ERROR_STATUS ,APBH DMA Channel 3 error status" "No effect,Set"
|
|
rbitfld.long 0x24 18. " CH2_ERROR_STATUS ,APBH DMA Channel 2 error status" "No effect,Set"
|
|
textline " "
|
|
rbitfld.long 0x24 17. " CH1_ERROR_STATUS ,APBH DMA Channel 1 error status" "No effect,Set"
|
|
rbitfld.long 0x24 16. " CH0_ERROR_STATUS ,APBH DMA Channel 0 error status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 15. " CH15_ERROR_IRQ ,Error interrupt 15 status" "No effect,Set"
|
|
bitfld.long 0x24 14. " CH14_ERROR_IRQ ,Error interrupt 14 status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 13. " CH13_ERROR_IRQ ,Error interrupt 13 status" "No effect,Set"
|
|
bitfld.long 0x24 12. " CH12_ERROR_IRQ ,Error interrupt 12 status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 11. " CH11_ERROR_IRQ ,Error interrupt 11 status" "No effect,Set"
|
|
bitfld.long 0x24 10. " CH10_ERROR_IRQ ,Error interrupt 10 status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 9. " CH9_ERROR_IRQ ,Error interrupt 9 status" "No effect,Set"
|
|
bitfld.long 0x24 8. " CH8_ERROR_IRQ ,Error interrupt 8 status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 7. " CH7_ERROR_IRQ ,Error interrupt 7 status" "No effect,Set"
|
|
bitfld.long 0x24 6. " CH6_ERROR_IRQ ,Error interrupt 6 status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 5. " CH5_ERROR_IRQ ,Error interrupt 5 status" "No effect,Set"
|
|
bitfld.long 0x24 4. " CH4_ERROR_IRQ ,Error interrupt 4 status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 3. " CH3_ERROR_IRQ ,Error interrupt 3 status" "No effect,Set"
|
|
bitfld.long 0x24 2. " CH2_ERROR_IRQ ,Error interrupt 2 status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 1. " CH1_ERROR_IRQ ,Error interrupt 1 status" "No effect,Set"
|
|
bitfld.long 0x24 0. " CH0_ERROR_IRQ ,Error interrupt 0 status" "No effect,Set"
|
|
line.long 0x28 "HW_APBH_CTRL2_CLR,AHB to APBH Bridge Control and Status Register 2 Clear"
|
|
rbitfld.long 0x28 31. " CH15_ERROR_STATUS ,APBH DMA Channel 15 error status" "No effect,Clear"
|
|
rbitfld.long 0x28 30. " CH14_ERROR_STATUS ,APBH DMA Channel 14 error status" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.long 0x28 29. " CH13_ERROR_STATUS ,APBH DMA Channel 13 error status" "No effect,Clear"
|
|
rbitfld.long 0x28 28. " CH12_ERROR_STATUS ,APBH DMA Channel 12 error status" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.long 0x28 27. " CH11_ERROR_STATUS ,APBH DMA Channel 11 error status" "No effect,Clear"
|
|
rbitfld.long 0x28 26. " CH10_ERROR_STATUS ,APBH DMA Channel 10 error status" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.long 0x28 25. " CH9_ERROR_STATUS ,APBH DMA Channel 9 error status" "No effect,Clear"
|
|
rbitfld.long 0x28 24. " CH8_ERROR_STATUS ,APBH DMA Channel 8 error status" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.long 0x28 23. " CH7_ERROR_STATUS ,APBH DMA Channel 7 error status" "No effect,Clear"
|
|
rbitfld.long 0x28 22. " CH6_ERROR_STATUS ,APBH DMA Channel 6 error status" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.long 0x28 21. " CH5_ERROR_STATUS ,APBH DMA Channel 5 error status" "No effect,Clear"
|
|
rbitfld.long 0x28 20. " CH4_ERROR_STATUS ,APBH DMA Channel 4 error status" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.long 0x28 19. " CH3_ERROR_STATUS ,APBH DMA Channel 3 error status" "No effect,Clear"
|
|
rbitfld.long 0x28 18. " CH2_ERROR_STATUS ,APBH DMA Channel 2 error status" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.long 0x28 17. " CH1_ERROR_STATUS ,APBH DMA Channel 1 error status" "No effect,Clear"
|
|
rbitfld.long 0x28 16. " CH0_ERROR_STATUS ,APBH DMA Channel 0 error status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x28 15. " CH15_ERROR_IRQ ,Error interrupt 15 status" "No effect,Clear"
|
|
bitfld.long 0x28 14. " CH14_ERROR_IRQ ,Error interrupt 14 status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x28 13. " CH13_ERROR_IRQ ,Error interrupt 13 status" "No effect,Clear"
|
|
bitfld.long 0x28 12. " CH12_ERROR_IRQ ,Error interrupt 12 status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x28 11. " CH11_ERROR_IRQ ,Error interrupt 11 status" "No effect,Clear"
|
|
bitfld.long 0x28 10. " CH10_ERROR_IRQ ,Error interrupt 10 status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x28 9. " CH9_ERROR_IRQ ,Error interrupt 9 status" "No effect,Clear"
|
|
bitfld.long 0x28 8. " CH8_ERROR_IRQ ,Error interrupt 8 status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x28 7. " CH7_ERROR_IRQ ,Error interrupt 7 status" "No effect,Clear"
|
|
bitfld.long 0x28 6. " CH6_ERROR_IRQ ,Error interrupt 6 status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x28 5. " CH5_ERROR_IRQ ,Error interrupt 5 status" "No effect,Clear"
|
|
bitfld.long 0x28 4. " CH4_ERROR_IRQ ,Error interrupt 4 status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x28 3. " CH3_ERROR_IRQ ,Error interrupt 3 status" "No effect,Clear"
|
|
bitfld.long 0x28 2. " CH2_ERROR_IRQ ,Error interrupt 2 status" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x28 1. " CH1_ERROR_IRQ ,Error interrupt 1 status" "No effect,Clear"
|
|
bitfld.long 0x28 0. " CH0_ERROR_IRQ ,Error interrupt 0 status" "No effect,Clear"
|
|
line.long 0x2C "HW_APBH_CTRL2_TOG,AHB to APBH Bridge Control and Status Register 2 Toggle"
|
|
rbitfld.long 0x2C 31. " CH15_ERROR_STATUS ,APBH DMA Channel 15 error status" "Not toggled,Toggled"
|
|
rbitfld.long 0x2C 30. " CH14_ERROR_STATUS ,APBH DMA Channel 14 error status" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x2C 29. " CH13_ERROR_STATUS ,APBH DMA Channel 13 error status" "Not toggled,Toggled"
|
|
rbitfld.long 0x2C 28. " CH12_ERROR_STATUS ,APBH DMA Channel 12 error status" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x2C 27. " CH11_ERROR_STATUS ,APBH DMA Channel 11 error status" "Not toggled,Toggled"
|
|
rbitfld.long 0x2C 26. " CH10_ERROR_STATUS ,APBH DMA Channel 10 error status" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x2C 25. " CH9_ERROR_STATUS ,APBH DMA Channel 9 error status" "Not toggled,Toggled"
|
|
rbitfld.long 0x2C 24. " CH8_ERROR_STATUS ,APBH DMA Channel 8 error status" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x2C 23. " CH7_ERROR_STATUS ,APBH DMA Channel 7 error status" "Not toggled,Toggled"
|
|
rbitfld.long 0x2C 22. " CH6_ERROR_STATUS ,APBH DMA Channel 6 error status" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x2C 21. " CH5_ERROR_STATUS ,APBH DMA Channel 5 error status" "Not toggled,Toggled"
|
|
rbitfld.long 0x2C 20. " CH4_ERROR_STATUS ,APBH DMA Channel 4 error status" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x2C 19. " CH3_ERROR_STATUS ,APBH DMA Channel 3 error status" "Not toggled,Toggled"
|
|
rbitfld.long 0x2C 18. " CH2_ERROR_STATUS ,APBH DMA Channel 2 error status" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x2C 17. " CH1_ERROR_STATUS ,APBH DMA Channel 1 error status" "Not toggled,Toggled"
|
|
rbitfld.long 0x2C 16. " CH0_ERROR_STATUS ,APBH DMA Channel 0 error status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x2C 15. " CH15_ERROR_IRQ ,Error interrupt 15 status" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 14. " CH14_ERROR_IRQ ,Error interrupt 14 status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x2C 13. " CH13_ERROR_IRQ ,Error interrupt 13 status" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 12. " CH12_ERROR_IRQ ,Error interrupt 12 status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x2C 11. " CH11_ERROR_IRQ ,Error interrupt 11 status" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 10. " CH10_ERROR_IRQ ,Error interrupt 10 status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " CH9_ERROR_IRQ ,Error interrupt 9 status" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 8. " CH8_ERROR_IRQ ,Error interrupt 8 status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x2C 7. " CH7_ERROR_IRQ ,Error interrupt 7 status" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 6. " CH6_ERROR_IRQ ,Error interrupt 6 status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " CH5_ERROR_IRQ ,Error interrupt 5 status" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 4. " CH4_ERROR_IRQ ,Error interrupt 4 status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " CH3_ERROR_IRQ ,Error interrupt 3 status" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 2. " CH2_ERROR_IRQ ,Error interrupt 2 status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " CH1_ERROR_IRQ ,Error interrupt 1 status" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 0. " CH0_ERROR_IRQ ,Error interrupt 0 status" "Not toggled,Toggled"
|
|
line.long 0x30 "APBH_CHANNEL_CTRL,AHB to APBH Bridge Channel Register"
|
|
bitfld.long 0x30 24. " RESET_CHANNEL8 ,SSP reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x30 23. " RESET_CHANNEL7 ,Channel 7 reset" "No reset,Reset"
|
|
bitfld.long 0x30 22. " RESET_CHANNEL6 ,Channel 6 reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x30 21. " RESET_CHANNEL5 ,Channel 5 reset" "No reset,Reset"
|
|
bitfld.long 0x30 20. " RESET_CHANNEL4 ,Channel 4 reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x30 19. " RESET_CHANNEL3 ,Channel 3 reset" "No reset,Reset"
|
|
bitfld.long 0x30 18. " RESET_CHANNEL2 ,Channel 2 reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x30 17. " RESET_CHANNEL1 ,Channel 1 reset" "No reset,Reset"
|
|
bitfld.long 0x30 16. " RESET_CHANNEL0 ,Channel 0 reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x30 8. " FREEZE_CHANNEL8 ,SSP freeze" "No frozen,Frozen"
|
|
textline " "
|
|
bitfld.long 0x30 7. " FREEZE_CHANNEL7 ,Channel 7 freeze" "No frozen,Frozen"
|
|
bitfld.long 0x30 6. " FREEZE_CHANNEL6 ,Channel 6 freeze" "No frozen,Frozen"
|
|
textline " "
|
|
bitfld.long 0x30 5. " FREEZE_CHANNEL5 ,Channel 5 freeze" "No frozen,Frozen"
|
|
bitfld.long 0x30 4. " FREEZE_CHANNEL4 ,Channel 4 freeze" "No frozen,Frozen"
|
|
textline " "
|
|
bitfld.long 0x30 3. " FREEZE_CHANNEL3 ,Channel 3 freeze" "No frozen,Frozen"
|
|
bitfld.long 0x30 2. " FREEZE_CHANNEL2 ,Channel 2 freeze" "No frozen,Frozen"
|
|
textline " "
|
|
bitfld.long 0x30 1. " FREEZE_CHANNEL1 ,Channel 1 freeze" "No frozen,Frozen"
|
|
bitfld.long 0x30 0. " FREEZE_CHANNEL0 ,Channel 0 freeze" "No frozen,Frozen"
|
|
line.long 0x34 "APBH_CHANNEL_SET,AHB to APBH Bridge Channel Register"
|
|
bitfld.long 0x34 24. " RESET_CHANNEL8 ,SSP reset set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x34 23. " RESET_CHANNEL7 ,Channel 7 reset set" "No effect,Set"
|
|
bitfld.long 0x34 22. " RESET_CHANNEL6 ,Channel 6 reset set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x34 21. " RESET_CHANNEL5 ,Channel 5 reset set" "No effect,Set"
|
|
bitfld.long 0x34 20. " RESET_CHANNEL4 ,Channel 4 reset set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x34 19. " RESET_CHANNEL3 ,Channel 3 reset set" "No effect,Set"
|
|
bitfld.long 0x34 18. " RESET_CHANNEL2 ,Channel 2 reset set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x34 17. " RESET_CHANNEL1 ,Channel 1 reset set" "No effect,Set"
|
|
bitfld.long 0x34 16. " RESET_CHANNEL0 ,Channel 0 reset set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x34 8. " FREEZE_CHANNEL8 ,SSP freeze set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x34 7. " FREEZE_CHANNEL7 ,Channel 7 freeze set" "No effect,Set"
|
|
bitfld.long 0x34 6. " FREEZE_CHANNEL6 ,Channel 6 freeze set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x34 5. " FREEZE_CHANNEL5 ,Channel 5 freeze set" "No effect,Set"
|
|
bitfld.long 0x34 4. " FREEZE_CHANNEL4 ,Channel 4 freeze set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x34 3. " FREEZE_CHANNEL3 ,Channel 3 freeze set" "No effect,Set"
|
|
bitfld.long 0x34 2. " FREEZE_CHANNEL2 ,Channel 2 freeze set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x34 1. " FREEZE_CHANNEL1 ,Channel 1 freeze set" "No effect,Set"
|
|
bitfld.long 0x34 0. " FREEZE_CHANNEL0 ,Channel 0 freeze set" "No effect,Set"
|
|
line.long 0x38 "APBH_CHANNEL_CLR,AHB to APBH Bridge Channel Register"
|
|
bitfld.long 0x38 24. " RESET_CHANNEL8 ,SSP reset clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x38 23. " RESET_CHANNEL7 ,Channel 7 reset clear" "No effect,Clear"
|
|
bitfld.long 0x38 22. " RESET_CHANNEL6 ,Channel 6 reset clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x38 21. " RESET_CHANNEL5 ,Channel 5 reset clear" "No effect,Clear"
|
|
bitfld.long 0x38 20. " RESET_CHANNEL4 ,Channel 4 reset clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x38 19. " RESET_CHANNEL3 ,Channel 3 reset clear" "No effect,Clear"
|
|
bitfld.long 0x38 18. " RESET_CHANNEL2 ,Channel 2 reset clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x38 17. " RESET_CHANNEL1 ,Channel 1 reset clear" "No effect,Clear"
|
|
bitfld.long 0x38 16. " RESET_CHANNEL0 ,Channel 0 reset clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x38 8. " FREEZE_CHANNEL8 ,SSP freeze clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x38 7. " FREEZE_CHANNEL7 ,Channel 7 freeze clear" "No effect,Clear"
|
|
bitfld.long 0x38 6. " FREEZE_CHANNEL6 ,Channel 6 freeze clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x38 5. " FREEZE_CHANNEL5 ,Channel 5 freeze clear" "No effect,Clear"
|
|
bitfld.long 0x38 4. " FREEZE_CHANNEL4 ,Channel 4 freeze clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x38 3. " FREEZE_CHANNEL3 ,Channel 3 freeze clear" "No effect,Clear"
|
|
bitfld.long 0x38 2. " FREEZE_CHANNEL2 ,Channel 2 freeze clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x38 1. " FREEZE_CHANNEL1 ,Channel 1 freeze clear" "No effect,Clear"
|
|
bitfld.long 0x38 0. " FREEZE_CHANNEL0 ,Channel 0 freeze clear" "No effect,Clear"
|
|
line.long 0x3C "APBH_CHANNEL_TOG,AHB to APBH Bridge Channel Register"
|
|
bitfld.long 0x3C 24. " RESET_CHANNEL8 ,SSP reset toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x3C 23. " RESET_CHANNEL7 ,Channel 7 reset toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x3C 22. " RESET_CHANNEL6 ,Channel 6 reset toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x3C 21. " RESET_CHANNEL5 ,Channel 5 reset toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x3C 20. " RESET_CHANNEL4 ,Channel 4 reset toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x3C 19. " RESET_CHANNEL3 ,Channel 3 reset toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x3C 18. " RESET_CHANNEL2 ,Channel 2 reset toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x3C 17. " RESET_CHANNEL1 ,Channel 1 reset toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x3C 16. " RESET_CHANNEL0 ,Channel 0 reset toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x3C 8. " FREEZE_CHANNEL8 ,SSP freeze toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x3C 7. " FREEZE_CHANNEL7 ,Channel 7 freeze toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x3C 6. " FREEZE_CHANNEL6 ,Channel 6 freeze toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x3C 5. " FREEZE_CHANNEL5 ,Channel 5 freeze toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x3C 4. " FREEZE_CHANNEL4 ,Channel 4 freeze toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x3C 3. " FREEZE_CHANNEL3 ,Channel 3 freeze toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x3C 2. " FREEZE_CHANNEL2 ,Channel 2 freeze toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x3C 1. " FREEZE_CHANNEL1 ,Channel 1 freeze toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x3C 0. " FREEZE_CHANNEL0 ,Channel 0 freeze toggle" "Not toggled,Toggled"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "APBH_DEVSEL,AHB to APBH DMA Device Assignment Register"
|
|
width 24.
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "APBH_DMA_BURST_SIZE,AHB to APBH DMA burst size register"
|
|
bitfld.long 0x00 16.--17. " CH8 ,DMA burst size for SSP" "BURST0,BURST4,BURST8,?..."
|
|
bitfld.long 0x00 14.--15. " CH7 ,DMA burst size for GPMI channel 7" "Reserved,BURST4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CH6 ,DMA burst size for GPMI channel 6" "Reserved,BURST4,?..."
|
|
bitfld.long 0x00 10.--11. " CH5 ,DMA burst size for GPMI channel 5" "Reserved,BURST4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CH4 ,DMA burst size for GPMI channel 4" "Reserved,BURST4,?..."
|
|
bitfld.long 0x00 6.--7. " CH3 ,DMA burst size for GPMI channel 3" "Reserved,BURST4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CH2 ,DMA burst size for GPMI channel 2" "Reserved,BURST4,?..."
|
|
bitfld.long 0x00 2.--3. " CH1 ,DMA burst size for GPMI channel 1" "Reserved,BURST4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CH0 ,DMA burst size for GPMI channel 0" "Reserved,BURST4,?..."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "HW_APBH_DEBUG,AHB to APBH DMA Debug Register"
|
|
bitfld.long 0x00 0. " GPMI_ONE_FIFO ,8 GMPI channels share DMA FIFO" "Not shared,Shared"
|
|
tree "APBH DMA Channel 0"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "APBH_CH0_CURCMDAR,APBH DMA Channel 0 Current Command Address Register"
|
|
group.long (0x100+0x10)++0x03
|
|
line.long 0x00 "APBH_CH0_NXTCMDAR,APBH DMA Channel 0 Next Command Address Register"
|
|
rgroup.long (0x100+0x20)++0x03
|
|
line.long 0x00 "APBH_CH0_CMD,APBH DMA Channel 0 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x100+0x30)++0x03
|
|
line.long 0x00 "APBH_CH0_BAR,APBH DMA Channel 0 Buffer Address Register"
|
|
group.long (0x100+0x40)++0x03
|
|
line.long 0x00 "APBH_CH0_SEMA,APBH DMA Channel 0 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x100+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH0_DEBUG1,AHB to APBH DMA Channel 0 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x100+0x60)++0x03
|
|
line.long 0x00 "APBH_CH0_DEBUG2,AHB to APBH DMA Channel 0 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 1"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "APBH_CH1_CURCMDAR,APBH DMA Channel 1 Current Command Address Register"
|
|
group.long (0x170+0x10)++0x03
|
|
line.long 0x00 "APBH_CH1_NXTCMDAR,APBH DMA Channel 1 Next Command Address Register"
|
|
rgroup.long (0x170+0x20)++0x03
|
|
line.long 0x00 "APBH_CH1_CMD,APBH DMA Channel 1 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x170+0x30)++0x03
|
|
line.long 0x00 "APBH_CH1_BAR,APBH DMA Channel 1 Buffer Address Register"
|
|
group.long (0x170+0x40)++0x03
|
|
line.long 0x00 "APBH_CH1_SEMA,APBH DMA Channel 1 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x170+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH1_DEBUG1,AHB to APBH DMA Channel 1 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 1 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x170+0x60)++0x03
|
|
line.long 0x00 "APBH_CH1_DEBUG2,AHB to APBH DMA Channel 1 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 2"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "APBH_CH2_CURCMDAR,APBH DMA Channel 2 Current Command Address Register"
|
|
group.long (0x1E0+0x10)++0x03
|
|
line.long 0x00 "APBH_CH2_NXTCMDAR,APBH DMA Channel 2 Next Command Address Register"
|
|
rgroup.long (0x1E0+0x20)++0x03
|
|
line.long 0x00 "APBH_CH2_CMD,APBH DMA Channel 2 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x1E0+0x30)++0x03
|
|
line.long 0x00 "APBH_CH2_BAR,APBH DMA Channel 2 Buffer Address Register"
|
|
group.long (0x1E0+0x40)++0x03
|
|
line.long 0x00 "APBH_CH2_SEMA,APBH DMA Channel 2 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x1E0+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH2_DEBUG1,AHB to APBH DMA Channel 2 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 2 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x1E0+0x60)++0x03
|
|
line.long 0x00 "APBH_CH2_DEBUG2,AHB to APBH DMA Channel 2 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 3"
|
|
rgroup.long 0x250++0x03
|
|
line.long 0x00 "APBH_CH3_CURCMDAR,APBH DMA Channel 3 Current Command Address Register"
|
|
group.long (0x250+0x10)++0x03
|
|
line.long 0x00 "APBH_CH3_NXTCMDAR,APBH DMA Channel 3 Next Command Address Register"
|
|
rgroup.long (0x250+0x20)++0x03
|
|
line.long 0x00 "APBH_CH3_CMD,APBH DMA Channel 3 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x250+0x30)++0x03
|
|
line.long 0x00 "APBH_CH3_BAR,APBH DMA Channel 3 Buffer Address Register"
|
|
group.long (0x250+0x40)++0x03
|
|
line.long 0x00 "APBH_CH3_SEMA,APBH DMA Channel 3 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x250+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH3_DEBUG1,AHB to APBH DMA Channel 3 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 3 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x250+0x60)++0x03
|
|
line.long 0x00 "APBH_CH3_DEBUG2,AHB to APBH DMA Channel 3 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 4"
|
|
rgroup.long 0x2C0++0x03
|
|
line.long 0x00 "APBH_CH4_CURCMDAR,APBH DMA Channel 4 Current Command Address Register"
|
|
group.long (0x2C0+0x10)++0x03
|
|
line.long 0x00 "APBH_CH4_NXTCMDAR,APBH DMA Channel 4 Next Command Address Register"
|
|
rgroup.long (0x2C0+0x20)++0x03
|
|
line.long 0x00 "APBH_CH4_CMD,APBH DMA Channel 4 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x2C0+0x30)++0x03
|
|
line.long 0x00 "APBH_CH4_BAR,APBH DMA Channel 4 Buffer Address Register"
|
|
group.long (0x2C0+0x40)++0x03
|
|
line.long 0x00 "APBH_CH4_SEMA,APBH DMA Channel 4 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x2C0+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH4_DEBUG1,AHB to APBH DMA Channel 4 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 4 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x2C0+0x60)++0x03
|
|
line.long 0x00 "APBH_CH4_DEBUG2,AHB to APBH DMA Channel 4 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 5"
|
|
rgroup.long 0x330++0x03
|
|
line.long 0x00 "APBH_CH5_CURCMDAR,APBH DMA Channel 5 Current Command Address Register"
|
|
group.long (0x330+0x10)++0x03
|
|
line.long 0x00 "APBH_CH5_NXTCMDAR,APBH DMA Channel 5 Next Command Address Register"
|
|
rgroup.long (0x330+0x20)++0x03
|
|
line.long 0x00 "APBH_CH5_CMD,APBH DMA Channel 5 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x330+0x30)++0x03
|
|
line.long 0x00 "APBH_CH5_BAR,APBH DMA Channel 5 Buffer Address Register"
|
|
group.long (0x330+0x40)++0x03
|
|
line.long 0x00 "APBH_CH5_SEMA,APBH DMA Channel 5 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x330+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH5_DEBUG1,AHB to APBH DMA Channel 5 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 5 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x330+0x60)++0x03
|
|
line.long 0x00 "APBH_CH5_DEBUG2,AHB to APBH DMA Channel 5 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 6"
|
|
rgroup.long 0x3A0++0x03
|
|
line.long 0x00 "APBH_CH6_CURCMDAR,APBH DMA Channel 6 Current Command Address Register"
|
|
group.long (0x3A0+0x10)++0x03
|
|
line.long 0x00 "APBH_CH6_NXTCMDAR,APBH DMA Channel 6 Next Command Address Register"
|
|
rgroup.long (0x3A0+0x20)++0x03
|
|
line.long 0x00 "APBH_CH6_CMD,APBH DMA Channel 6 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x3A0+0x30)++0x03
|
|
line.long 0x00 "APBH_CH6_BAR,APBH DMA Channel 6 Buffer Address Register"
|
|
group.long (0x3A0+0x40)++0x03
|
|
line.long 0x00 "APBH_CH6_SEMA,APBH DMA Channel 6 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x3A0+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH6_DEBUG1,AHB to APBH DMA Channel 6 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 6 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x3A0+0x60)++0x03
|
|
line.long 0x00 "APBH_CH6_DEBUG2,AHB to APBH DMA Channel 6 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 7"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "APBH_CH7_CURCMDAR,APBH DMA Channel 7 Current Command Address Register"
|
|
group.long (0x410+0x10)++0x03
|
|
line.long 0x00 "APBH_CH7_NXTCMDAR,APBH DMA Channel 7 Next Command Address Register"
|
|
rgroup.long (0x410+0x20)++0x03
|
|
line.long 0x00 "APBH_CH7_CMD,APBH DMA Channel 7 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x410+0x30)++0x03
|
|
line.long 0x00 "APBH_CH7_BAR,APBH DMA Channel 7 Buffer Address Register"
|
|
group.long (0x410+0x40)++0x03
|
|
line.long 0x00 "APBH_CH7_SEMA,APBH DMA Channel 7 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x410+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH7_DEBUG1,AHB to APBH DMA Channel 7 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 7 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x410+0x60)++0x03
|
|
line.long 0x00 "APBH_CH7_DEBUG2,AHB to APBH DMA Channel 7 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 8"
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "APBH_CH8_CURCMDAR,APBH DMA Channel 8 Current Command Address Register"
|
|
group.long (0x480+0x10)++0x03
|
|
line.long 0x00 "APBH_CH8_NXTCMDAR,APBH DMA Channel 8 Next Command Address Register"
|
|
rgroup.long (0x480+0x20)++0x03
|
|
line.long 0x00 "APBH_CH8_CMD,APBH DMA Channel 8 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x480+0x30)++0x03
|
|
line.long 0x00 "APBH_CH8_BAR,APBH DMA Channel 8 Buffer Address Register"
|
|
group.long (0x480+0x40)++0x03
|
|
line.long 0x00 "APBH_CH8_SEMA,APBH DMA Channel 8 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x480+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH8_DEBUG1,AHB to APBH DMA Channel 8 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 8 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x480+0x60)++0x03
|
|
line.long 0x00 "APBH_CH8_DEBUG2,AHB to APBH DMA Channel 8 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 9"
|
|
rgroup.long 0x4F0++0x03
|
|
line.long 0x00 "APBH_CH9_CURCMDAR,APBH DMA Channel 9 Current Command Address Register"
|
|
group.long (0x4F0+0x10)++0x03
|
|
line.long 0x00 "APBH_CH9_NXTCMDAR,APBH DMA Channel 9 Next Command Address Register"
|
|
rgroup.long (0x4F0+0x20)++0x03
|
|
line.long 0x00 "APBH_CH9_CMD,APBH DMA Channel 9 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x4F0+0x30)++0x03
|
|
line.long 0x00 "APBH_CH9_BAR,APBH DMA Channel 9 Buffer Address Register"
|
|
group.long (0x4F0+0x40)++0x03
|
|
line.long 0x00 "APBH_CH9_SEMA,APBH DMA Channel 9 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x4F0+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH9_DEBUG1,AHB to APBH DMA Channel 9 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 9 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x4F0+0x60)++0x03
|
|
line.long 0x00 "APBH_CH9_DEBUG2,AHB to APBH DMA Channel 9 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 10"
|
|
rgroup.long 0x560++0x03
|
|
line.long 0x00 "APBH_CH10_CURCMDAR,APBH DMA Channel 10 Current Command Address Register"
|
|
group.long (0x560+0x10)++0x03
|
|
line.long 0x00 "APBH_CH10_NXTCMDAR,APBH DMA Channel 10 Next Command Address Register"
|
|
rgroup.long (0x560+0x20)++0x03
|
|
line.long 0x00 "APBH_CH10_CMD,APBH DMA Channel 10 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x560+0x30)++0x03
|
|
line.long 0x00 "APBH_CH10_BAR,APBH DMA Channel 10 Buffer Address Register"
|
|
group.long (0x560+0x40)++0x03
|
|
line.long 0x00 "APBH_CH10_SEMA,APBH DMA Channel 10 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x560+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH10_DEBUG1,AHB to APBH DMA Channel 10 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 10 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x560+0x60)++0x03
|
|
line.long 0x00 "APBH_CH10_DEBUG2,AHB to APBH DMA Channel 10 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 11"
|
|
rgroup.long 0x5D0++0x03
|
|
line.long 0x00 "APBH_CH11_CURCMDAR,APBH DMA Channel 11 Current Command Address Register"
|
|
group.long (0x5D0+0x10)++0x03
|
|
line.long 0x00 "APBH_CH11_NXTCMDAR,APBH DMA Channel 11 Next Command Address Register"
|
|
rgroup.long (0x5D0+0x20)++0x03
|
|
line.long 0x00 "APBH_CH11_CMD,APBH DMA Channel 11 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x5D0+0x30)++0x03
|
|
line.long 0x00 "APBH_CH11_BAR,APBH DMA Channel 11 Buffer Address Register"
|
|
group.long (0x5D0+0x40)++0x03
|
|
line.long 0x00 "APBH_CH11_SEMA,APBH DMA Channel 11 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x5D0+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH11_DEBUG1,AHB to APBH DMA Channel 11 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 11 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x5D0+0x60)++0x03
|
|
line.long 0x00 "APBH_CH11_DEBUG2,AHB to APBH DMA Channel 11 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 12"
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "APBH_CH12_CURCMDAR,APBH DMA Channel 12 Current Command Address Register"
|
|
group.long (0x640+0x10)++0x03
|
|
line.long 0x00 "APBH_CH12_NXTCMDAR,APBH DMA Channel 12 Next Command Address Register"
|
|
rgroup.long (0x640+0x20)++0x03
|
|
line.long 0x00 "APBH_CH12_CMD,APBH DMA Channel 12 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x640+0x30)++0x03
|
|
line.long 0x00 "APBH_CH12_BAR,APBH DMA Channel 12 Buffer Address Register"
|
|
group.long (0x640+0x40)++0x03
|
|
line.long 0x00 "APBH_CH12_SEMA,APBH DMA Channel 12 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x640+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH12_DEBUG1,AHB to APBH DMA Channel 12 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 12 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x640+0x60)++0x03
|
|
line.long 0x00 "APBH_CH12_DEBUG2,AHB to APBH DMA Channel 12 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 13"
|
|
rgroup.long 0x6B0++0x03
|
|
line.long 0x00 "APBH_CH13_CURCMDAR,APBH DMA Channel 13 Current Command Address Register"
|
|
group.long (0x6B0+0x10)++0x03
|
|
line.long 0x00 "APBH_CH13_NXTCMDAR,APBH DMA Channel 13 Next Command Address Register"
|
|
rgroup.long (0x6B0+0x20)++0x03
|
|
line.long 0x00 "APBH_CH13_CMD,APBH DMA Channel 13 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x6B0+0x30)++0x03
|
|
line.long 0x00 "APBH_CH13_BAR,APBH DMA Channel 13 Buffer Address Register"
|
|
group.long (0x6B0+0x40)++0x03
|
|
line.long 0x00 "APBH_CH13_SEMA,APBH DMA Channel 13 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x6B0+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH13_DEBUG1,AHB to APBH DMA Channel 13 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 13 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x6B0+0x60)++0x03
|
|
line.long 0x00 "APBH_CH13_DEBUG2,AHB to APBH DMA Channel 13 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 14"
|
|
rgroup.long 0x720++0x03
|
|
line.long 0x00 "APBH_CH14_CURCMDAR,APBH DMA Channel 14 Current Command Address Register"
|
|
group.long (0x720+0x10)++0x03
|
|
line.long 0x00 "APBH_CH14_NXTCMDAR,APBH DMA Channel 14 Next Command Address Register"
|
|
rgroup.long (0x720+0x20)++0x03
|
|
line.long 0x00 "APBH_CH14_CMD,APBH DMA Channel 14 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x720+0x30)++0x03
|
|
line.long 0x00 "APBH_CH14_BAR,APBH DMA Channel 14 Buffer Address Register"
|
|
group.long (0x720+0x40)++0x03
|
|
line.long 0x00 "APBH_CH14_SEMA,APBH DMA Channel 14 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x720+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH14_DEBUG1,AHB to APBH DMA Channel 14 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 14 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x720+0x60)++0x03
|
|
line.long 0x00 "APBH_CH14_DEBUG2,AHB to APBH DMA Channel 14 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
tree "APBH DMA Channel 15"
|
|
rgroup.long 0x790++0x03
|
|
line.long 0x00 "APBH_CH15_CURCMDAR,APBH DMA Channel 15 Current Command Address Register"
|
|
group.long (0x790+0x10)++0x03
|
|
line.long 0x00 "APBH_CH15_NXTCMDAR,APBH DMA Channel 15 Next Command Address Register"
|
|
rgroup.long (0x790+0x20)++0x03
|
|
line.long 0x00 "APBH_CH15_CMD,APBH DMA Channel 15 Command Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer in the GPMI0 device"
|
|
bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HALTONTERMINATE ,Halt DMA channel on terminate" "Not halted,Halted"
|
|
bitfld.long 0x00 7. " WAIT4ENDCMD ,Wait for end of command to be sent to the DMA" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SEMAPHORE ,Decrement semaphore at the completion of the current command structure" "Not decremented,Decremented"
|
|
bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for device ready signal" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " IRQONCMPLT ,Set interrupt status bit upon completion of the current command" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Another command is chained onto the end of the current command structure" "Not chained,Chained"
|
|
bitfld.long 0x00 0.--1. " COMMAND ,Current command" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE"
|
|
rgroup.long (0x790+0x30)++0x03
|
|
line.long 0x00 "APBH_CH15_BAR,APBH DMA Channel 15 Buffer Address Register"
|
|
group.long (0x790+0x40)++0x03
|
|
line.long 0x00 "APBH_CH15_SEMA,APBH DMA Channel 15 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHORE ,Value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Value added to the semaphore count"
|
|
rgroup.long (0x790+0x50)++0x03
|
|
line.long 0x00 "HW_APBH_CH15_DEBUG1,AHB to APBH DMA Channel 15 Debug Register 1"
|
|
bitfld.long 0x00 31. " REQ ,DMA Request Signal status" "0,1"
|
|
bitfld.long 0x00 30. " BURST ,DMA Burst Signa status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " KICK ,DMA Kick Signal status" "0,1"
|
|
bitfld.long 0x00 28. " END ,DMA End Command status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEXTCMDADDRVALID ,Next command adress is valid" "0,1"
|
|
bitfld.long 0x00 23. " RD_FIFO_EMPTY ,DMA Channel Read FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RD_FIFO_FULL ,DMA Channel Read FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 21. " WR_FIFO_EMPTY ,DMA Channel Write FIFO Empty signal status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_FIFO_FULL ,DMA Channel Write FIFO Full signal status" "0,1"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 15 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY"
|
|
rgroup.long (0x790+0x60)++0x03
|
|
line.long 0x00 "APBH_CH15_DEBUG2,AHB to APBH DMA Channel 15 Debug Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,APB bytes remaining to be transfered in the current transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,AHB bytes remaining to be transfered in the current transfer"
|
|
tree.end
|
|
rgroup.long (0x800)++0x03
|
|
line.long 0x00 "APBH_VERSION,APBH Bridge Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,MAJOR field of the RTL version"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,MINOR field of the RTL version"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " STEP ,Stepping of the RTL version"
|
|
width 0xB
|
|
tree.end
|
|
tree "AUDMUX (Digital Audio Multiplexer)"
|
|
base ad:0x63FD0000
|
|
width 7.
|
|
group.long (0x00+0x0)++0x07 "Port 1"
|
|
line.long 0x00 "PTCR1,Port Timing Control Register 1"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR1,Port Data Control Register 1"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
group.long (0x00+0x8)++0x07 "Port 2"
|
|
line.long 0x00 "PTCR2,Port Timing Control Register 2"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR2,Port Data Control Register 2"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
group.long (0x00+0x10)++0x07 "Port 3"
|
|
line.long 0x00 "PTCR3,Port Timing Control Register 3"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR3,Port Data Control Register 3"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
group.long (0x00+0x18)++0x07 "Port 4"
|
|
line.long 0x00 "PTCR4,Port Timing Control Register 4"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR4,Port Data Control Register 4"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
group.long (0x00+0x20)++0x07 "Port 5"
|
|
line.long 0x00 "PTCR5,Port Timing Control Register 5"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR5,Port Data Control Register 5"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
group.long (0x00+0x28)++0x07 "Port 6"
|
|
line.long 0x00 "PTCR6,Port Timing Control Register 6"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR6,Port Data Control Register 6"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
width 0xb
|
|
tree.end
|
|
tree "BCH (32-Bit Correcting ECC Accelerator)"
|
|
base ad:0x41008000
|
|
width 11.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "CTRL,Hardware BCH ECC Accelerator Control Register"
|
|
bitfld.long 0x00 31. " SFTRST ,BCH software reset" "No reset,Reset"
|
|
bitfld.long 0x00 30. " CLKGATE ,Clock BCH gates" "Clocked,Not clocked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DEBUGSYNDROME ,Debug syndromes enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " M2M_ENCODE ,Encode/decode mode for memory-to-memory operations" "0,1"
|
|
bitfld.long 0x00 16. " M2M_ENABLE ,M2M enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DEBUG_STALL_IRQ_EN ,Debug stall mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " COMPLETE_IRQ_EN ,Completion of correction interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " DEBUG_STALL_IRQ ,Debug stall Interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMPLETE_IRQ ,External interrupt line status" "No interrupt,Interrupt"
|
|
line.long 0x04 "CTRL_SET,Hardware BCH ECC Accelerator Control Set Register"
|
|
bitfld.long 0x04 31. " SFTRST ,BCH software reset" "No effect,Set"
|
|
bitfld.long 0x04 30. " CLKGATE ,Clock BCH gates" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " DEBUGSYNDROME ,Debug syndromes enable" "No effect,Set"
|
|
bitfld.long 0x04 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 17. " M2M_ENCODE ,Encode/decode mode for memory-to-memory operations" "0,1"
|
|
bitfld.long 0x04 16. " M2M_ENABLE ,M2M enable" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DEBUG_STALL_IRQ_EN ,Debug stall mode interrupt enable" "No effect,Set"
|
|
bitfld.long 0x04 8. " COMPLETE_IRQ_EN ,Completion of correction interrupt enable" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt status" "No effect,Set"
|
|
bitfld.long 0x04 2. " DEBUG_STALL_IRQ ,Debug stall Interrupt status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 0. " COMPLETE_IRQ ,External interrupt line status" "No effect,Set"
|
|
line.long 0x08 "CTRL_CLR,Hardware BCH ECC Accelerator Control Clear Register"
|
|
bitfld.long 0x08 31. " SFTRST ,BCH software reset" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " CLKGATE ,Clock BCH gates" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 22. " DEBUGSYNDROME ,Debug syndromes enable" "No effect,Cleared"
|
|
bitfld.long 0x08 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 17. " M2M_ENCODE ,Encode/decode mode for memory-to-memory operations" "0,1"
|
|
bitfld.long 0x08 16. " M2M_ENABLE ,M2M enable" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DEBUG_STALL_IRQ_EN ,Debug stall mode interrupt enable" "No effect,Cleared"
|
|
bitfld.long 0x08 8. " COMPLETE_IRQ_EN ,Completion of correction interrupt enable" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt status" "No effect,Cleared"
|
|
bitfld.long 0x08 2. " DEBUG_STALL_IRQ ,Debug stall Interrupt status" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 0. " COMPLETE_IRQ ,External interrupt line status" "No effect,Cleared"
|
|
line.long 0x0C "CTRL_TOG,Hardware BCH ECC Accelerator Control Toggle Register"
|
|
bitfld.long 0x0C 31. " SFTRST ,BCH software reset" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 30. " CLKGATE ,Clock BCH gates" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " DEBUGSYNDROME ,Debug syndromes enable" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " M2M_ENCODE ,Encode/decode mode for memory-to-memory operations" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 16. " M2M_ENABLE ,M2M enable" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " DEBUG_STALL_IRQ_EN ,Debug stall mode interrupt enable" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 8. " COMPLETE_IRQ_EN ,Completion of correction interrupt enable" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt status" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2. " DEBUG_STALL_IRQ ,Debug stall Interrupt status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " COMPLETE_IRQ ,External interrupt line status" "Not toggled,Toggled"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "STATUS0,Hardware ECC Accelerator Status Register 0"
|
|
hexmask.long.word 0x00 20.--31. 1. " HANDLE ,12 bit handle"
|
|
bitfld.long 0x00 16.--19. " COMPLETED_CE ,Chip enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " STATUS_BLK0 ,BLK0 status"
|
|
bitfld.long 0x00 4. " ALLONES ,Set all transaction bits to ones" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CORRECTED ,At least one correctable error encountered" "Not encountered,Encountered"
|
|
bitfld.long 0x00 2. " UNCORRECTABLE ,Uncorrectable error encountered" "Not encountered,Encountered"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "MODE,Hardware ECC Accelerator Mode Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ERASE_THRESHOLD ,Maximum number of zero bits on a flash page"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "ENCODEPTR,Hardware BCH ECC Loopback Encode Buffer Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DATAPTR,Hardware BCH ECC Loopback Data Buffer Register"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "METAPTR,Hardware BCH ECC Loopback Metadata Buffer Register"
|
|
width 17.
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "LAYOUTSELECT,Hardware ECC Accelerator Layout Select Register"
|
|
bitfld.long 0x00 30.--31. " CS15_SELECT ,Chip 15 layout select" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CS14_SELECT ,Chip 14 layout select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS13_SELECT ,Chip 13 layout select" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " CS12_SELECT ,Chip 12 layout select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CS11_SELECT ,Chip 11 layout select" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " CS10_SELECT ,Chip 10 layout select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " CS9_SELECT ,Chip 9 layout select" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " CS8_SELECT ,Chip 8 layout select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CS7_SELECT ,Chip 7 layout select" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " CS6_SELECT ,Chip 6 layout select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CS5_SELECT ,Chip 5 layout select" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " CS4_SELECT ,Chip 4 layout select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CS3_SELECT ,Chip 3 layout select" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " CS2_SELECT ,Chip 2 layout select" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CS1_SELECT ,Chip 1 layout select" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " CS0_SELECT ,Chip 0 layout select" "0,1,2,3"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "FLASH0LAYOUT0,Hardware BCH ECC Flash 0 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page"
|
|
hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Metadata size"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,?..."
|
|
bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Data 0 block size"
|
|
group.long (0x80+0x10)++0x3
|
|
line.long 0x00 "FLASH0LAYOUT1,Hardware BCH ECC Flash 0 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Flash page size"
|
|
bitfld.long 0x00 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14"
|
|
hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "FLASH1LAYOUT0,Hardware BCH ECC Flash 1 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page"
|
|
hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Metadata size"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,?..."
|
|
bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Data 0 block size"
|
|
group.long (0xA0+0x10)++0x3
|
|
line.long 0x00 "FLASH1LAYOUT1,Hardware BCH ECC Flash 1 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Flash page size"
|
|
bitfld.long 0x00 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14"
|
|
hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "FLASH2LAYOUT0,Hardware BCH ECC Flash 2 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page"
|
|
hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Metadata size"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,?..."
|
|
bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Data 0 block size"
|
|
group.long (0xC0+0x10)++0x3
|
|
line.long 0x00 "FLASH2LAYOUT1,Hardware BCH ECC Flash 2 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Flash page size"
|
|
bitfld.long 0x00 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14"
|
|
hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks"
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "FLASH3LAYOUT0,Hardware BCH ECC Flash 3 Layout 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page"
|
|
hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Metadata size"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " ECC0 ,ECC level for block 0" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,?..."
|
|
bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " DATA0_SIZE ,Data 0 block size"
|
|
group.long (0xE0+0x10)++0x3
|
|
line.long 0x00 "FLASH3LAYOUT1,Hardware BCH ECC Flash 3 Layout 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Flash page size"
|
|
bitfld.long 0x00 11.--15. " ECCN ,ECC level for blocks 0-n" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,ECC22,ECC24,ECC26,ECC28,ECC30,ECC32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " GF13_0_GF14_1 ,GF13/GF14 select" "GF13,GF14"
|
|
hexmask.long.word 0x00 0.--9. 1. " DATAN_SIZE ,Size of the subsequent data blocks"
|
|
width 12.
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "DEBUG0,Hardware BCH ECC Debug Register 0"
|
|
hexmask.long.word 0x00 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " KES_DEBUG_SHIFT_SYND_set/clr ,KES debug syndrome shift" "Not shifted,Shifted"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " KES_DEBUG_PAYLOAD_FLAG_set/clr ,KES debug payload flag" "0,1"
|
|
setclrfld.long 0x00 13. 0x04 15. 0x08 15. " KES_DEBUG_MODE4K_set/clr ,KES debug input mode" "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 15. 0x08 15. " KES_DEBUG_KICK_set/clr ,KES debug kick" "Not kicked,Kicked"
|
|
setclrfld.long 0x00 11. 0x04 15. 0x08 15. " KES_STANDALONE_set/clr ,KES standalone" "Normal,TEST_MODE"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " KES_DEBUG_STEP_set/clr ,KES debug step" "Not stepped,Stepped"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " KES_DEBUG_STALL_set/clr ,KES debug stall" "Normal,Wait"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " BM_KES_TEST_BYPASS_set/clr ,BM KES test bypass" "Normal,TEST_MODE"
|
|
bitfld.long 0x00 0.--5. " DEBUG_REG_SELECT_SET/CLR ,Internal register state view value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "DEBUG0_SET,Hardware BCH ECC Debug SET Register0"
|
|
hexmask.long.word 0x04 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol"
|
|
bitfld.long 0x04 0.--5. " DEBUG_REG_SELECT ,Internal register state view value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "DEBUG0_CLR,Hardware BCH ECC Debug CLR Register0"
|
|
hexmask.long.word 0x08 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol"
|
|
bitfld.long 0x08 0.--5. " DEBUG_REG_SELECT ,Internal register state view value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "DEBUG0_TOG,Hardware BCH ECC Debug Tooggle Register 0"
|
|
hexmask.long.word 0x0C 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol"
|
|
bitfld.long 0x0C 15. " KES_DEBUG_SHIFT_SYND ,KES debug syndrome shift" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " KES_DEBUG_PAYLOAD_FLAG ,KES debug payload flag" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 13. " KES_DEBUG_MODE4K ,KES debug input mode" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " KES_DEBUG_KICK ,KES debug kick" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 11. " KES_STANDALONE ,KES standalone" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " KES_DEBUG_STEP ,KES debug step" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 9. " KES_DEBUG_STALL ,KES debug stall" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " BM_KES_TEST_BYPASS ,BM KES test bypass" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 0.--5. " DEBUG_REG_SELECT ,Internal register state view value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 12.
|
|
rgroup.long 0x110++0x3
|
|
line.long 0x00 "DBGKESREAD,KES Debug Read Register"
|
|
rgroup.long 0x150++0x3
|
|
line.long 0x00 "BLOCKNAME,Block Name Register"
|
|
rgroup.long 0x160++0x3
|
|
line.long 0x00 "VERSION,BCH Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,MAJOR field of the RTL version"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,MINOR field of the RTL version"
|
|
hexmask.long.word 0x00 0.--15. 1. " STEP ,Stepping of the RTL version"
|
|
width 0xb
|
|
tree.end
|
|
tree "CSPI (Configurable Serial Peripheral Interface)"
|
|
base ad:0x63FC0000
|
|
width 11.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "RXDATA,Receive Data Register"
|
|
in
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "TXDATA,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " TXDATA ,Transmit Data"
|
|
if ((per.long(ad:0x63FC0000+0x8)&0x02)==0x02)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONREG,Control Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst Length"
|
|
bitfld.long 0x00 16.--18. " DATA_RATE ,SPI Data Rate Control" "Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128,Div by 256,Div by 512"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CHIP_SELECT ,Select one of four external SPI Master/Slave Devices" "/SS0,/SS1,/SS2,/SS3"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 8.--9. " DRCTL ,SPI Data Ready Control" "Ignore,Failing /SPI_RDY,Low level /SPI_RDY,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " DRCTL ,SPI Data Ready Control" "Ignore,Failing /SPI_RDY,Low level /SPI_RDY,/RSV"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SSPOL ,SPI SS Polarity Select" "Low,High"
|
|
bitfld.long 0x00 6. " SSCTL ,SPI SS Wave Form Select" "Only one,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PHA ,SPI Clock/Data Phase Control" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 4. " POL ,SPI Clock Polarity Control" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMC ,Start Mode Control" "After write 1 to XCH,Immediately"
|
|
bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Exchanged/Busy"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MODE ,SPI Function Mode Select" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,SPI Module Enable Control" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONREG,Control Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst Length"
|
|
sif (cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&!cpuis("IMX50*"))
|
|
bitfld.long 0x00 16.--18. " DATA_RATE ,SPI Data Rate Control" "Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128,Div by 256,Div by 512"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CHIP_SELECT ,Select one of four external SPI Master/Slave Devices" "/SS0,/SS1,/SS2,/SS3"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SSPOL ,SPI SS Polarity Select" "Low,High"
|
|
bitfld.long 0x00 6. " SSCTL ,SPI SS Wave Form Select" "BURST LENGTH+1,/SS edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PHA ,SPI Clock/Data Phase Control" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 4. " POL ,SPI Clock Polarity Control" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MODE ,SPI Function Mode Select" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,SPI Module Enable Control" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x0c++0x0f
|
|
line.long 0x00 "INTREG,Interrupt Control Register"
|
|
bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RHEN ,RXFIFO Half Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " THEN ,TXFIFO Half Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMAREG,DMA Control Register"
|
|
bitfld.long 0x04 5. " RFDEN ,RXFIFO Full DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RHDEN ,RXFIFO Half Full DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " THDEN ,TXFIFO Half Empty DMA Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled"
|
|
line.long 0x08 "STATREG,Status Register"
|
|
eventfld.long 0x08 7. " TC , Transfer Completed" "Busy,Completed"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x08 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
else
|
|
bitfld.long 0x08 6. " RO ,RXFIFO Overflow" "Available,Overflow"
|
|
bitfld.long 0x08 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 4. " RH ,RXFIFO Half Full" "Less than 4,4 or more"
|
|
bitfld.long 0x08 3. " RR ,RXFIFO Ready" "No data,More than 1 word"
|
|
bitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TH ,TXFIFO Half Empty" "More than 4 words,4 or fewer words"
|
|
bitfld.long 0x08 0. " TE ,TXFIFO Empty" "Not empty,Empty"
|
|
line.long 0x0c "PERIODREG,Sample Period Control Register"
|
|
sif (cpuis("IMX50*"))
|
|
bitfld.long 0x0c 15. " CSRC ,Clock Source Control" "SCLK,32.768kHz"
|
|
else
|
|
bitfld.long 0x0c 15. " CSRC ,Clock Source Control" "SPI Clock,CKIL"
|
|
endif
|
|
hexmask.long.word 0x0c 0.--14. 1. " SAMPLEPERIOD ,Sample Period Control"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
if ((per.long(ad:0x63FC0000+0x8)&0x02)==0x02)
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TESTREG,Test Control Register"
|
|
bitfld.long 0x00 15. " SWAP ,Data Swap" "Unchanged,Swapped"
|
|
bitfld.long 0x00 14. " LBC ,Loop Back Control" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " RXCNT ,RXFIFO Counter" "0 words,1 word,Reserved,Reserved,Reserved,Reserved,Reserved,7 words,8 words,?..."
|
|
bitfld.long 0x00 0.--3. " TXCNT ,TXFIFO Counter" "0 words,1 word,Reserved,Reserved,Reserved,Reserved,Reserved,7 words,8 words,?..."
|
|
else
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TESTREG,Test Control Register"
|
|
bitfld.long 0x00 15. " SWAP ,Data Swap" "Unchanged,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " RXCNT ,RXFIFO Counter" "0 words,1 word,Reserved,Reserved,Reserved,Reserved,Reserved,7 words,8 words,?..."
|
|
bitfld.long 0x00 0.--3. " TXCNT ,TXFIFO Counter" "0 words,1 word,Reserved,Reserved,Reserved,Reserved,Reserved,7 words,8 words,?..."
|
|
endif
|
|
else
|
|
if ((per.long(ad:0x63FC0000+0x8)&0x02)==0x02)
|
|
group.long 0x1c0++0x03
|
|
line.long 0x00 "TESTREG,Test Control Register"
|
|
bitfld.long 0x00 15. " SWAP ,Data Swap" "Unchanged,Swapped"
|
|
bitfld.long 0x00 14. " LBC ,Loop Back Control" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SMSTATUS ,State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " RXCNT ,RXFIFO Counter" "0 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,?..."
|
|
bitfld.long 0x00 0.--3. " TXCNT ,TXFIFO Counter" "0 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,?..."
|
|
else
|
|
group.long 0x1c0++0x03
|
|
line.long 0x00 "TESTREG,Test Control Register"
|
|
bitfld.long 0x00 15. " SWAP ,Data Swap" "Unchanged,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SMSTATUS ,State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " RXCNT ,RXFIFO Counter" "0 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,?..."
|
|
bitfld.long 0x00 0.--3. " TXCNT ,TXFIFO Counter" "0 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,?..."
|
|
endif
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "DCP (Data Co-Processor)"
|
|
base ad:0x4100E000
|
|
width 21.
|
|
group.long 0x00++0x33
|
|
line.long 0x00 "DCP_CTRL,DCP Control Register 0"
|
|
bitfld.long 0x00 31. " SFTRST ,Enable normal DCP operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CLKGATE ,This bit must be set to zero for normal operation" "Not gated,Gated"
|
|
textline " "
|
|
rbitfld.long 0x00 29. " PRESENT_CRYPTO ,Indicates whether the crypto (Cipher/Hash) functions are present" "Absent,Present"
|
|
rbitfld.long 0x00 28. " PRESENT_SHA ,Indicates whether the SHA1/SHA2 functions are present" "Absent,Present"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GATHER_RESIDUAL_WRITES ,Software should set this bit to enable ragged writes to unaligned buffers to be gathered between multiple write operations" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENABLE_CONTEXT_CACHING ,Software should set this bit to enable caching of contexts between operations" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHANNEL_INTERRUPT_ENABLE[3] ,Per-channel interrupt enable bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CHANNEL_INTERRUPT_ENABLE[2] ,Per-channel interrupt enable bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHANNEL_INTERRUPT_ENABLE[1] ,Per-channel interrupt enable bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CHANNEL_INTERRUPT_ENABLE[0] ,Per-channel interrupt enable bit 0" "Disabled,Enabled"
|
|
line.long 0x04 "DCP_CTRL_SET,DCP Control Set Register 0"
|
|
bitfld.long 0x04 31. " SFTRST ,Enable normal DCP operation" "No effect,Enabled"
|
|
bitfld.long 0x04 30. " CLKGATE ,This bit must be set to zero for normal operation" "No effect,Gated"
|
|
textline " "
|
|
rbitfld.long 0x04 29. " PRESENT_CRYPTO ,Indicates whether the crypto (Cipher/Hash) functions are present" "Absent,Present"
|
|
rbitfld.long 0x04 28. " PRESENT_SHA ,Indicates whether the SHA1/SHA2 functions are present" "Absent,Present"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GATHER_RESIDUAL_WRITES ,Software should set this bit to enable ragged writes to unaligned buffers to be gathered between multiple write operations" "No effect,Enabled"
|
|
bitfld.long 0x04 22. " ENABLE_CONTEXT_CACHING ,Software should set this bit to enable caching of contexts between operations" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CHANNEL_INTERRUPT_ENABLE[3] ,Per-channel interrupt enable bit 3" "No effect,Enabled"
|
|
bitfld.long 0x04 2. " CHANNEL_INTERRUPT_ENABLE[2] ,Per-channel interrupt enable bit 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHANNEL_INTERRUPT_ENABLE[1] ,Per-channel interrupt enable bit 1" "No effect,Enabled"
|
|
bitfld.long 0x04 0. " CHANNEL_INTERRUPT_ENABLE[0] ,Per-channel interrupt enable bit 0" "No effect,Enabled"
|
|
line.long 0x08 "DCP_CTRL_CLR,DCP Control Clear Register 0"
|
|
bitfld.long 0x08 31. " SFTRST ,Enable normal DCP operation" "No effect,Enabled"
|
|
bitfld.long 0x08 30. " CLKGATE ,This bit must be set to zero for normal operation" "No effect,Gated"
|
|
textline " "
|
|
rbitfld.long 0x08 29. " PRESENT_CRYPTO ,Indicates whether the crypto (Cipher/Hash) functions are present" "Absent,Present"
|
|
rbitfld.long 0x08 28. " PRESENT_SHA ,Indicates whether the SHA1/SHA2 functions are present" "Absent,Present"
|
|
textline " "
|
|
bitfld.long 0x08 23. " GATHER_RESIDUAL_WRITES ,Software should set this bit to enable ragged writes to unaligned buffers to be gathered between multiple write operations" "No effect,Enabled"
|
|
bitfld.long 0x08 22. " ENABLE_CONTEXT_CACHING ,Software should set this bit to enable caching of contexts between operations" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CHANNEL_INTERRUPT_ENABLE[3] ,Per-channel interrupt enable bit 3" "No effect,Enabled"
|
|
bitfld.long 0x08 2. " CHANNEL_INTERRUPT_ENABLE[2] ,Per-channel interrupt enable bit 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CHANNEL_INTERRUPT_ENABLE[1] ,Per-channel interrupt enable bit 1" "No effect,Enabled"
|
|
bitfld.long 0x08 0. " CHANNEL_INTERRUPT_ENABLE[0] ,Per-channel interrupt enable bit 0" "No effect,Enabled"
|
|
line.long 0x0C "DCP_CTRL_TOOGLE,DCP Control toggle Register 0"
|
|
bitfld.long 0x0C 31. " SFTRST ,Enable normal DCP operation" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 30. " CLKGATE ,This bit must be set to zero for normal operation" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x0C 29. " PRESENT_CRYPTO ,Indicates whether the crypto (Cipher/Hash) functions are present" "Not toggled,Toggled"
|
|
rbitfld.long 0x0C 28. " PRESENT_SHA ,Indicates whether the SHA1/SHA2 functions are present" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " GATHER_RESIDUAL_WRITES ,Software should set this bit to enable ragged writes to unaligned buffers to be gathered between multiple write operations" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 22. " ENABLE_CONTEXT_CACHING ,Software should set this bit to enable caching of contexts between operations" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " CHANNEL_INTERRUPT_ENABLE[3] ,Per-channel interrupt enable bit 3" "No effect,Enabled"
|
|
bitfld.long 0x0C 2. " CHANNEL_INTERRUPT_ENABLE[2] ,Per-channel interrupt enable bit 2" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CHANNEL_INTERRUPT_ENABLE[1] ,Per-channel interrupt enable bit 1" "No effect,Enabled"
|
|
bitfld.long 0x0C 0. " CHANNEL_INTERRUPT_ENABLE[0] ,Per-channel interrupt enable bit 0" "No effect,Enabled"
|
|
line.long 0x10 "DCP_STAT,DCP Status Register"
|
|
rbitfld.long 0x10 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "Not ready,Ready"
|
|
rbitfld.long 0x10 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,CH0,CH1,CH2,CH3,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x10 16.--23. 1. " READY_CHANNELS ,Indicates which channels are ready to proceed with a transfer"
|
|
bitfld.long 0x10 0.--3. " IRQ ,Indicates which channels have pending interrupt requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "DCP_STAT_SET,DCP Status set Register"
|
|
rbitfld.long 0x14 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "Not ready,Ready"
|
|
rbitfld.long 0x14 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,CH0,CH1,CH2,CH3,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x14 16.--23. 1. " READY_CHANNELS ,Indicates which channels are ready to proceed with a transfer"
|
|
bitfld.long 0x14 0.--3. " IRQ ,Indicates which channels have pending interrupt requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "DCP_STAT_CLR,DCP Status clr Register"
|
|
rbitfld.long 0x18 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "Not ready,Ready"
|
|
rbitfld.long 0x18 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,CH0,CH1,CH2,CH3,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x18 16.--23. 1. " READY_CHANNELS ,Indicates which channels are ready to proceed with a transfer"
|
|
bitfld.long 0x18 0.--3. " IRQ ,Indicates which channels have pending interrupt requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x1C "DCP_STAT_TOG,DCP Status Register"
|
|
rbitfld.long 0x1C 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "Not ready,Ready"
|
|
rbitfld.long 0x1C 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,CH0,CH1,CH2,CH3,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x1C 16.--23. 1. " READY_CHANNELS ,Indicates which channels are ready to proceed with a transfer"
|
|
bitfld.long 0x1C 0.--3. " IRQ ,Indicates which channels have pending interrupt requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "DCP_CHANNELCTRL,DCP Channel Control Register"
|
|
bitfld.long 0x20 16. " CH0_IRQ_MERGED ,Indicates that the interrupt for channel 0 should be merged with the other interrupts on the shared dcp_irq interrupt" "Not indicated,Indicated"
|
|
textline " "
|
|
bitfld.long 0x20 11. " HIGH_PRIORITY_CHANNEL[3] ,Causes the corresponding channel to have high-priority arbitration" "Not caused,Caused"
|
|
bitfld.long 0x20 10. " HIGH_PRIORITY_CHANNEL[2] ,Causes the corresponding channel to have high-priority arbitration" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x20 9. " HIGH_PRIORITY_CHANNEL[1] ,Causes the corresponding channel to have high-priority arbitration" "Not caused,Caused"
|
|
bitfld.long 0x20 8. " HIGH_PRIORITY_CHANNEL[0] ,Causes the corresponding channel to have high-priority arbitration" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x20 3. " ENABLE_CHANNEL[3] ,Enable the DMA channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " ENABLE_CHANNEL[2] ,Enable the DMA channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 1. " ENABLE_CHANNEL[1] ,Enable the DMA channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " ENABLE_CHANNEL[0] ,Enable the DMA channel 0" "Disabled,Enabled"
|
|
line.long 0x24 "DCP_CHANNELCTRL_SET,DCP Channel Control Set Register"
|
|
bitfld.long 0x24 16. " CH0_IRQ_MERGED ,Indicates that the interrupt for channel 0 should be merged with the other interrupts on the shared dcp_irq interrupt" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 11. " HIGH_PRIORITY_CHANNEL[3] ,Causes the corresponding channel to have high-priority arbitration" "No effect,Set"
|
|
bitfld.long 0x24 10. " HIGH_PRIORITY_CHANNEL[2] ,Causes the corresponding channel to have high-priority arbitration" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 9. " HIGH_PRIORITY_CHANNEL[1] ,Causes the corresponding channel to have high-priority arbitration" "No effect,Set"
|
|
bitfld.long 0x24 8. " HIGH_PRIORITY_CHANNEL[0] ,Causes the corresponding channel to have high-priority arbitration" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 3. " ENABLE_CHANNEL[3] ,Enable the DMA channel 3" "No effect,Set"
|
|
bitfld.long 0x24 2. " ENABLE_CHANNEL[2] ,Enable the DMA channel 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x24 1. " ENABLE_CHANNEL[1] ,Enable the DMA channel 1" "No effect,Set"
|
|
bitfld.long 0x24 0. " ENABLE_CHANNEL[0] ,Enable the DMA channel 0" "No effect,Set"
|
|
line.long 0x28 "DCP_CHANNELCTRL_CLR,DCP Channel Control Clear Register"
|
|
bitfld.long 0x28 16. " CH0_IRQ_MERGED ,Indicates that the interrupt for channel 0 should be merged with the other interrupts on the shared dcp_irq interrupt" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x28 11. " HIGH_PRIORITY_CHANNEL[3] ,Causes the corresponding channel to have high-priority arbitration" "No effect,Cleared"
|
|
bitfld.long 0x28 10. " HIGH_PRIORITY_CHANNEL[2] ,Causes the corresponding channel to have high-priority arbitration" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x28 9. " HIGH_PRIORITY_CHANNEL[1] ,Causes the corresponding channel to have high-priority arbitration" "No effect,Cleared"
|
|
bitfld.long 0x28 8. " HIGH_PRIORITY_CHANNEL[0] ,Causes the corresponding channel to have high-priority arbitration" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x28 3. " ENABLE_CHANNEL[3] ,Enable the DMA channel 3" "No effect,Cleared"
|
|
bitfld.long 0x28 2. " ENABLE_CHANNEL[2] ,Enable the DMA channel 2" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x28 1. " ENABLE_CHANNEL[1] ,Enable the DMA channel 1" "No effect,Cleared"
|
|
bitfld.long 0x28 0. " ENABLE_CHANNEL[0] ,Enable the DMA channel 0" "No effect,Cleared"
|
|
line.long 0x2C "DCP_CHANNELCTRL_TOG,DCP Channel Control Toggle Register"
|
|
bitfld.long 0x2C 16. " CH0_IRQ_MERGED ,Indicates that the interrupt for channel 0 should be merged with the other interrupts on the shared dcp_irq interrupt" "Not toggled,Toggled"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " HIGH_PRIORITY_CHANNEL ,Causes the corresponding channel to have high-priority arbitration"
|
|
textline " "
|
|
bitfld.long 0x2C 11. " HIGH_PRIORITY_CHANNEL[3] ,Causes the corresponding channel to have high-priority arbitration" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 10. " HIGH_PRIORITY_CHANNEL[2] ,Causes the corresponding channel to have high-priority arbitration" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " HIGH_PRIORITY_CHANNEL[1] ,Causes the corresponding channel to have high-priority arbitration" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 8. " HIGH_PRIORITY_CHANNEL[0] ,Causes the corresponding channel to have high-priority arbitration" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " ENABLE_CHANNEL[3] ,Enable the DMA channel 3" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 2. " ENABLE_CHANNEL[2] ,Enable the DMA channel 2" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " ENABLE_CHANNEL[1] ,Enable the DMA channel 1" "Not toggled,Toggled"
|
|
bitfld.long 0x2C 0. " ENABLE_CHANNEL[0] ,Enable the DMA channel 0" "Not toggled,Toggled"
|
|
line.long 0x30 "DCP_CAPABILITY0,DCP Capability 0 Register"
|
|
bitfld.long 0x30 31. " DISABLE_DECRYPT ,Disable decryption" "No,Yes"
|
|
bitfld.long 0x30 29. " DISABLE_UNIQUE_KEY ,Disable the per-device unique key" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x30 8.--11. " NUM_CHANNELS ,Encoded value indicating the number of channels implemented in the design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x30 0.--7. 1. " NUM_KEYS ,Encoded value indicating the number of key storage locations implemented in the design"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "DCP_CAPABILITY1,DCP Capability 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HASH_ALGORITHMS ,One-hot field indicating which hashing features are implemented in HW"
|
|
hexmask.long.word 0x00 0.--15. 1. " CIPHER_ALGORITHMS ,One-hot field indicating which cipher algorithms are available"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DCP_CONTEXT,DCP Context Buffer Pointer"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DCP_KEY,DCP Key Index"
|
|
bitfld.long 0x00 4.--5. " INDEX ,Key index pointer" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " SUBWORD ,Key subword pointer" "0,1,2,3"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DCP_KEYDATA,DCP_KEYDATA field descriptions"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "DCP_PACKET0,DCP Work Packet 0 Status Register"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "DCP_PACKET1,DCP Work Packet 1 Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TAG ,Packet Tag"
|
|
bitfld.long 0x00 23. " OUTPUT_WORDSWAP ,Reflects whether the DCP engine will wordswap output data (big-endian data)." "Not reflected,Reflected"
|
|
textline " "
|
|
bitfld.long 0x00 22. " OUTPUT_BYTESWAP ,Reflects whether the DCP engine will byteswap output data (big-endian data)" "Not reflected,Reflected"
|
|
bitfld.long 0x00 21. " INPUT_WORDSWAP ,Reflects whether the DCP engine will wordswap input data (big-endian data)" "Not reflected,Reflected"
|
|
textline " "
|
|
bitfld.long 0x00 20. " INPUT_BYTESWAP ,Reflects whether the DCP engine will byteswap input data (big-endian data)" "Not reflected,Reflected"
|
|
bitfld.long 0x00 19. " KEY_WORDSWAP ,Reflects whether the DCP engine will swap key words (big-endian key)" "Not reflected,Reflected"
|
|
textline " "
|
|
bitfld.long 0x00 18. " KEY_BYTESWAP ,Reflects whether the DCP engine will swap key bytes (big-endian key)" "Not reflected,Reflected"
|
|
bitfld.long 0x00 17. " TEST_SEMA_IRQ ,Test the channel semaphore transition to 0 - FOR TEST USE ONLY" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONSTANT_FILL ,DCP simply fill the destination buffer with the value found in the" "0,1"
|
|
bitfld.long 0x00 15. " HASH_OUTPUT ,Controls whether the input or output data is hashed" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHECK_HASH ,Reflects whether the calculated hash value should be compared against the hash provided in the payload" "Not reflected,Reflected"
|
|
bitfld.long 0x00 13. " HASH_TERM ,Reflects whether the current hashing block is the final block in the hashing operation" "Not reflected,Reflected"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HASH_INIT ,Reflects whether the current hashing block is the initial block in the hashing operation" "Not reflected,Reflected"
|
|
bitfld.long 0x00 11. " PAYLOAD_KEY ,Indicates the payload contains the key" "Not contained,Contained"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OTP_KEY ,Reflects whether a hardware-based key should be used." "Not reflected,Reflected"
|
|
bitfld.long 0x00 9. " CIPHER_INIT ,Reflects whether the cipher block should load the initialization vector from the payload for this operation" "Not reflected,Reflected"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CIPHER_ENCRYPT ,Indicates whether the operation is encryption or decryption" "Decrypt,Encrypt"
|
|
bitfld.long 0x00 7. " ENABLE_BLIT ,Reflects whether the DCP should perform a blit operation" "Not reflected,Reflected"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENABLE_HASH ,Reflects whether the selected hashing function should be enabled for this operation" "Not reflected,Reflected"
|
|
bitfld.long 0x00 5. " ENABLE_CIPHER ,Reflects whether the selected cipher function should be enabled for this operation" "Not reflected,Reflected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENABLE_MEMCOPY ,Reflects whether the selected hashing function should be enabled for this operation" "Not reflected,Reflected"
|
|
bitfld.long 0x00 3. " CHAIN_CONTIGUOUS ,Reflects whether the next packet's address is located following this packet's payload" "Not reflected,Reflected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CHAIN ,Reflects whether the next command pointer register should be loaded into the channel's current descriptor pointer" "Not reflected,Reflected"
|
|
bitfld.long 0x00 1. " DECR_SEMAPHORE ,Reflects whether the channel's semaphore should be decremented at the end of the current operation" "Not reflected,Reflected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INTERRUPT ,Reflects whether the channel should issue an interrupt upon completion of the packet" "Not reflected,Reflected"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "DCP_PACKET2,DCP Work Packet 2 Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CIPHER_CFG ,Cipher configuration bits"
|
|
bitfld.long 0x00 16.--19. " HASH_SELECT ,Hash Selection Field" "SHA1,CRC32,SHA256,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " KEY_SELECT ,Key Selection Field"
|
|
bitfld.long 0x00 4.--7. " CIPHER_MODE ,Cipher Mode Selection Field" "ECB,CBC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CIPHER_SELECT ,Cipher Selection Field" "AES128,?..."
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "DCP_PACKET3,DCP Work Packet 3 Status Register"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "DCP_PACKET4,DCP Work Packet 4 Status Register"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "DCP_PACKET5,DCP Work Packet 5 Status Register"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "DCP_PACKET6,DCP Work Packet 6 Status Register"
|
|
tree " Channel 0"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DCP_CH0CMDPTR,DCP Channel 0 Command Pointer Address Register"
|
|
group.long (0x100+0x10)++0x03
|
|
line.long 0x00 "DCP_CH0SEMA,DCP Channel 0 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Read-only field shows the current (instantaneous) value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,Value written to this field is added to the semaphore count"
|
|
group.long (0x100+0x20)++0x0F
|
|
line.long 0x00 "DCP_CH0STAT,DCP Channel 0 Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x00 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No error,Error"
|
|
bitfld.long 0x00 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error"
|
|
bitfld.long 0x00 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "Not mismatched,Mismatched"
|
|
bitfld.long 0x00 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "Not completed,Completed"
|
|
line.long 0x04 "DCP_CH0STAT_SET,DCP Channel 0 Status Set Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x04 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No effect,Set"
|
|
bitfld.long 0x04 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set"
|
|
bitfld.long 0x04 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "No effect,Set"
|
|
bitfld.long 0x04 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "No effect,Set"
|
|
line.long 0x08 "DCP_CH0STAT_CLR,DCP Channel 0 Status Clear Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x08 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No effect,Clear"
|
|
bitfld.long 0x08 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear"
|
|
bitfld.long 0x08 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "No effect,Clear"
|
|
bitfld.long 0x08 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "No effect,Clear"
|
|
line.long 0x0C "DCP_CH0STAT_TOG,DCP Channel 0 Status Toggle Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x0C 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "Not toggled,Toggled"
|
|
group.long (0x100+0x30)++0x0F
|
|
line.long 0x00 "DCP_CH0OPTS,DCP Channel 0 Options Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x04 "DCP_CH0OPTS_SET,DCP Channel 0 Options Set Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x08 "DCP_CH0OPTS_CLR,DCP Channel 0 Options Clr Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x0C "DCP_CH0OPTS_TOG,DCP Channel 0 Options Toggle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
tree.end
|
|
tree " Channel 1"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DCP_CH1CMDPTR,DCP Channel 1 Command Pointer Address Register"
|
|
group.long (0x140+0x10)++0x03
|
|
line.long 0x00 "DCP_CH1SEMA,DCP Channel 1 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Read-only field shows the current (instantaneous) value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,Value written to this field is added to the semaphore count"
|
|
group.long (0x140+0x20)++0x0F
|
|
line.long 0x00 "DCP_CH1STAT,DCP Channel 1 Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x00 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No error,Error"
|
|
bitfld.long 0x00 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error"
|
|
bitfld.long 0x00 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "Not mismatched,Mismatched"
|
|
bitfld.long 0x00 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "Not completed,Completed"
|
|
line.long 0x04 "DCP_CH1STAT_SET,DCP Channel 1 Status Set Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x04 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No effect,Set"
|
|
bitfld.long 0x04 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set"
|
|
bitfld.long 0x04 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "No effect,Set"
|
|
bitfld.long 0x04 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "No effect,Set"
|
|
line.long 0x08 "DCP_CH1STAT_CLR,DCP Channel 1 Status Clear Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x08 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No effect,Clear"
|
|
bitfld.long 0x08 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear"
|
|
bitfld.long 0x08 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "No effect,Clear"
|
|
bitfld.long 0x08 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "No effect,Clear"
|
|
line.long 0x0C "DCP_CH1STAT_TOG,DCP Channel 1 Status Toggle Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x0C 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "Not toggled,Toggled"
|
|
group.long (0x140+0x30)++0x0F
|
|
line.long 0x00 "DCP_CH1OPTS,DCP Channel 1 Options Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x04 "DCP_CH1OPTS_SET,DCP Channel 1 Options Set Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x08 "DCP_CH1OPTS_CLR,DCP Channel 1 Options Clr Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x0C "DCP_CH1OPTS_TOG,DCP Channel 1 Options Toggle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
tree.end
|
|
tree " Channel 2"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DCP_CH2CMDPTR,DCP Channel 2 Command Pointer Address Register"
|
|
group.long (0x180+0x10)++0x03
|
|
line.long 0x00 "DCP_CH2SEMA,DCP Channel 2 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Read-only field shows the current (instantaneous) value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,Value written to this field is added to the semaphore count"
|
|
group.long (0x180+0x20)++0x0F
|
|
line.long 0x00 "DCP_CH2STAT,DCP Channel 2 Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x00 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No error,Error"
|
|
bitfld.long 0x00 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error"
|
|
bitfld.long 0x00 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "Not mismatched,Mismatched"
|
|
bitfld.long 0x00 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "Not completed,Completed"
|
|
line.long 0x04 "DCP_CH2STAT_SET,DCP Channel 2 Status Set Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x04 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No effect,Set"
|
|
bitfld.long 0x04 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set"
|
|
bitfld.long 0x04 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "No effect,Set"
|
|
bitfld.long 0x04 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "No effect,Set"
|
|
line.long 0x08 "DCP_CH2STAT_CLR,DCP Channel 2 Status Clear Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x08 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No effect,Clear"
|
|
bitfld.long 0x08 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear"
|
|
bitfld.long 0x08 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "No effect,Clear"
|
|
bitfld.long 0x08 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "No effect,Clear"
|
|
line.long 0x0C "DCP_CH2STAT_TOG,DCP Channel 2 Status Toggle Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x0C 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "Not toggled,Toggled"
|
|
group.long (0x180+0x30)++0x0F
|
|
line.long 0x00 "DCP_CH2OPTS,DCP Channel 2 Options Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x04 "DCP_CH2OPTS_SET,DCP Channel 2 Options Set Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x08 "DCP_CH2OPTS_CLR,DCP Channel 2 Options Clr Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x0C "DCP_CH2OPTS_TOG,DCP Channel 2 Options Toggle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
tree.end
|
|
tree " Channel 3"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "DCP_CH3CMDPTR,DCP Channel 3 Command Pointer Address Register"
|
|
group.long (0x1C0+0x10)++0x03
|
|
line.long 0x00 "DCP_CH3SEMA,DCP Channel 3 Semaphore Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Read-only field shows the current (instantaneous) value of the semaphore counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,Value written to this field is added to the semaphore count"
|
|
group.long (0x1C0+0x20)++0x0F
|
|
line.long 0x00 "DCP_CH3STAT,DCP Channel 3 Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x00 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No error,Error"
|
|
bitfld.long 0x00 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error"
|
|
bitfld.long 0x00 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "Not mismatched,Mismatched"
|
|
bitfld.long 0x00 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "Not completed,Completed"
|
|
line.long 0x04 "DCP_CH3STAT_SET,DCP Channel 3 Status Set Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x04 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No effect,Set"
|
|
bitfld.long 0x04 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set"
|
|
bitfld.long 0x04 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "No effect,Set"
|
|
bitfld.long 0x04 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "No effect,Set"
|
|
line.long 0x08 "DCP_CH3STAT_CLR,DCP Channel 3 Status Clear Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x08 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "No effect,Clear"
|
|
bitfld.long 0x08 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear"
|
|
bitfld.long 0x08 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "No effect,Clear"
|
|
bitfld.long 0x08 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "No effect,Clear"
|
|
line.long 0x0C "DCP_CH3STAT_TOG,DCP Channel 3 Status Toggle Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " TAG ,Indicates the tag from the last completed packet in the command structure"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ERROR_CODE ,Indicates additional error codes for some error conditions"
|
|
bitfld.long 0x0C 6. " ERROR_PAGEFAULT ,Indicates a page fault occurred while converting a virtual address to a physical address" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ERROR_DST ,Indicates a bus error occurred when storing to the destination buffer" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 4. " ERROR_SRC ,Indicates a bus error occurred when reading from the source buffer" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ERROR_PACKET ,Indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2. " ERROR_SETUP ,Indicates that the hardware has detected an invalid programming configuration such as a buffer length that is not a multiple of the natural data size for the operation" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " HASH_MISMATCH ,Indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 0. " RSVD_COMPLETE ,Packet status field after processing of the packet has completed" "Not toggled,Toggled"
|
|
group.long (0x1C0+0x30)++0x0F
|
|
line.long 0x00 "DCP_CH3OPTS,DCP Channel 3 Options Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x04 "DCP_CH3OPTS_SET,DCP Channel 3 Options Set Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x08 "DCP_CH3OPTS_CLR,DCP Channel 3 Options Clr Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
line.long 0x0C "DCP_CH3OPTS_TOG,DCP Channel 3 Options Toggle Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " RECOVERY_TIMER ,Indicates the recovery time for the channel"
|
|
tree.end
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "DCP_DBGSELECT,DCP Debug Select Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INDEX ,Selects a value to read via the debug data register"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "DCP_DBGDATA,DCP Debug Data Register"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "DCP_PAGETABLE,DCP Page Table Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Page Table Base Address"
|
|
bitfld.long 0x00 1. " FLUSH ,Page Table Flush control" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Page Table Enable control" "Disabled,Enabled"
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "DCP_VERSION,DCP Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-onlyl value reflecting the MAJOR version of the design implementation"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-onlyl value reflecting the MINOR version of the design implementation"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-onlyl value reflecting the stepping of version of the design implementation"
|
|
width 0x0b
|
|
tree.end
|
|
tree "DIGCTL (Digital Control)"
|
|
base ad:0x41004000
|
|
width 25.
|
|
group.long 0x00++0x2F
|
|
line.long 0x00 "DIGCTL_CTRL,DIGCTL Control Register"
|
|
bitfld.long 0x00 31. " SFTRST ,Enable/disable normal DIGCTL operation" "No reset,Reset"
|
|
bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Not gated,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ESDHC_VERSION ,Version of the eSDHC block to use" "ESDHCv3,USDHC"
|
|
line.long 0x04 "DIGCTL_CTRL_SET,DIGCTL Control Set Register"
|
|
bitfld.long 0x04 31. " SFTRST ,Enable/disable normal DIGCTL operation" "No effect,Set"
|
|
bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ESDHC_VERSION ,Version of the eSDHC block to use" "No effect,Set"
|
|
line.long 0x08 "DIGCTL_CTRL_CLR,DIGCTL Control Clear Register"
|
|
bitfld.long 0x08 31. " SFTRST ,Enable/disable normal DIGCTL operation" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ESDHC_VERSION ,Version of the eSDHC block to use" "No effect,Cleared"
|
|
line.long 0x0C "DIGCTL_CTRL_TOG,DIGCTL Control Toggle Register"
|
|
bitfld.long 0x0C 31. " SFTRST ,Enable/disable normal DIGCTL operation" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " ESDHC_VERSION ,Version of the eSDHC block to use" "Not toggled,Toggled"
|
|
line.long 0x10 "DIGCTL_OCRAM,DIGCTL OCRAM Register"
|
|
rbitfld.long 0x10 19. " WR_ADDR_PIPE_EN_STAT ,Write Address Pipeline Enable Status" "Not busy,Busy"
|
|
rbitfld.long 0x10 18. " WR_DATA_PIPE_EN_STAT ,Write Data Pipeline Enable Status" "Not busy,Busy"
|
|
textline " "
|
|
rbitfld.long 0x10 17. " RD_ADDR_PIPE_EN_STAT ,Read Address Pipeline Enable Status" "Not busy,Busy"
|
|
rbitfld.long 0x10 16. " RD_DATA_WAIT_EN_STAT ,Read Data Wait Enable Status" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x10 3. " WR_ADDR_PIPE_EN ,Write Data Pipeline Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " WR_DATA_PIPE_EN ,Write Data Pipeline Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " RD_ADDR_PIPE_EN ,Read Address Pipeline Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " RD_DATA_WAIT_EN ,Read Data Wait Enable" "Disabled,Enabled"
|
|
line.long 0x14 "DIGCTL_OCRAM_SET,DIGCTL OCRAM Set Register"
|
|
rbitfld.long 0x14 19. " WR_ADDR_PIPE_EN_STAT ,Write Address Pipeline Enable Status" "No effect,Set"
|
|
rbitfld.long 0x14 18. " WR_DATA_PIPE_EN_STAT ,Write Data Pipeline Enable Status" "No effect,Set"
|
|
textline " "
|
|
rbitfld.long 0x14 17. " RD_ADDR_PIPE_EN_STAT ,Read Address Pipeline Enable Status" "No effect,Set"
|
|
rbitfld.long 0x14 16. " RD_DATA_WAIT_EN_STAT ,Read Data Wait Enable Status" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 3. " WR_ADDR_PIPE_EN ,Write Data Pipeline Enable" "No effect,Set"
|
|
bitfld.long 0x14 2. " WR_DATA_PIPE_EN ,Write Data Pipeline Enable" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 1. " RD_ADDR_PIPE_EN ,Read Address Pipeline Enable" "No effect,Set"
|
|
bitfld.long 0x14 0. " RD_DATA_WAIT_EN ,Read Data Wait Enable" "No effect,Set"
|
|
line.long 0x18 "DIGCTL_OCRAM_CLR,DIGCTL OCRAM Clear Register"
|
|
rbitfld.long 0x18 19. " WR_ADDR_PIPE_EN_STAT ,Write Address Pipeline Enable Status" "No effect,Cleared"
|
|
rbitfld.long 0x18 18. " WR_DATA_PIPE_EN_STAT ,Write Data Pipeline Enable Status" "No effect,Cleared"
|
|
textline " "
|
|
rbitfld.long 0x18 17. " RD_ADDR_PIPE_EN_STAT ,Read Address Pipeline Enable Status" "No effect,Cleared"
|
|
rbitfld.long 0x18 16. " RD_DATA_WAIT_EN_STAT ,Read Data Wait Enable Status" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x18 3. " WR_ADDR_PIPE_EN ,Write Data Pipeline Enable" "No effect,Cleared"
|
|
bitfld.long 0x18 2. " WR_DATA_PIPE_EN ,Write Data Pipeline Enable" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x18 1. " RD_ADDR_PIPE_EN ,Read Address Pipeline Enable" "No effect,Cleared"
|
|
bitfld.long 0x18 0. " RD_DATA_WAIT_EN ,Read Data Wait Enable" "No effect,Cleared"
|
|
line.long 0x1C "DIGCTL_OCRAM_TOG,DIGCTL OCRAM Toggle Register"
|
|
rbitfld.long 0x1C 19. " WR_ADDR_PIPE_EN_STAT ,Write Address Pipeline Enable Status" "Not toggled,Toggled"
|
|
rbitfld.long 0x1C 18. " WR_DATA_PIPE_EN_STAT ,Write Data Pipeline Enable Status" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x1C 17. " RD_ADDR_PIPE_EN_STAT ,Read Address Pipeline Enable Status" "Not toggled,Toggled"
|
|
rbitfld.long 0x1C 16. " RD_DATA_WAIT_EN_STAT ,Read Data Wait Enable Status" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " WR_ADDR_PIPE_EN ,Write Data Pipeline Enable" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 2. " WR_DATA_PIPE_EN ,Write Data Pipeline Enable" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " RD_ADDR_PIPE_EN ,Read Address Pipeline Enable" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 0. " RD_DATA_WAIT_EN ,Read Data Wait Enable" "Not toggled,Toggled"
|
|
line.long 0x20 "DIGCTL_SPEEDCTL,Transistor Speed Control Register"
|
|
bitfld.long 0x20 4.--7. " SELECT ,Speed Sensor Status Select" "Sensor 0,Sensor 1,?..."
|
|
bitfld.long 0x20 0.--1. " CTRL ,Speed Control bits" "Off,Enabled,Reserved,Enabled measurement"
|
|
line.long 0x24 "DIGCTL_SPEEDCTL_SET,Transistor Speed Control Set Register"
|
|
bitfld.long 0x24 4.--7. " SELECT ,Speed Sensor Status Select" "Sensor 0,Sensor 1,?..."
|
|
bitfld.long 0x24 0.--1. " CTRL ,Speed Control bits" "Off,Enabled,Reserved,Enabled measurement"
|
|
line.long 0x28 "DIGCTL_SPEEDCTL_CLR,Transistor Speed Control Clear Register"
|
|
bitfld.long 0x28 4.--7. " SELECT ,Speed Sensor Status Select" "Sensor 0,Sensor 1,?..."
|
|
bitfld.long 0x28 0.--1. " CTRL ,Speed Control bits" "Off,Enabled,Reserved,Enabled measurement"
|
|
line.long 0x2C "DIGCTL_SPEEDCTL_TOG,Transistor Speed Control Tog Register"
|
|
bitfld.long 0x2C 4.--7. " SELECT ,Speed Sensor Status Select" "Sensor 0,Sensor 1,?..."
|
|
bitfld.long 0x2C 0.--1. " CTRL ,Speed Control bits" "Off,Enabled,Reserved,Enabled measurement"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DIGCTL_DIGCTL_SPEEDSTAT,Transistor Speed Status Register"
|
|
width 0x0b
|
|
tree.end
|
|
tree.open "DPLLC (DPLL Controller)"
|
|
tree "DPLL1"
|
|
base ad:0x63F80000
|
|
width 13.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "DP_CTL,DPLL Control Register"
|
|
bitfld.long 0x00 13. " MUL_CTRL ,Multiple Control" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DPDCK0_2_EN ,Dpdck0_2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " REF_CLK_DIV ,Ref Clk Division factor" "Div by 1,Div by 2"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Reserved,Reserved,Clock2 (24MHz oscillator clock),?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Clk0,Clk1,Clk2,Clk3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " HFSM ,HFS-Mode Status" "LFS,HFS"
|
|
bitfld.long 0x00 6. " PRE ,Power Up Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " UPEN ,PLL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RST ,Restart" "Not restarted,Restarted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCP ,Reference Clock Polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 2. " PLM ,Phase Lock Mode" "Frequency,Frequency/Phase"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BRMO ,BRM Order" "First,Second"
|
|
bitfld.long 0x00 0. " LRF ,Lock Ready Flag" "Not locked,Locked"
|
|
line.long 0x04 "DP_CONFIG,DPLL Config Register"
|
|
bitfld.long 0x04 1. " AREN ,Auto Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LDREQ ,Load Request" "Not requested,Requested"
|
|
line.long 0x08 "DP_OP,DPLL Operation Register"
|
|
bitfld.long 0x08 4.--7. " MFI[3:0] ,Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x0c "DP_MFD,DPLL MFD Register"
|
|
hexmask.long 0x0c 0.--26. 1. " MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x10 "DP_MFN,DPLL MFN Register"
|
|
hexmask.long 0x10 0.--26. 1. " MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x14 "DP_MFNMINUS,DPLL MFNMINUS Register"
|
|
hexmask.long 0x14 0.--26. 1. " MFNMINUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x18 "DP_MFNPLUS,DPLL MFNPLUS Register"
|
|
hexmask.long 0x18 0.--26. 1. " MFNPLUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x1c "DP_HFS_OP,DPLL High Frequency Support Operation Register"
|
|
bitfld.long 0x1c 4.--7. " HFS_MFI[3:0] ,HFS Mode - Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x20 "DP_HFS_MFD,DPLL HFS MFD Register"
|
|
hexmask.long 0x20 0.--26. 1. " HFS_MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x24 "DP_HFS_MFN,DPLL HFS MFN Register"
|
|
hexmask.long 0x24 0.--26. 1. " HFS_MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x28 "DP_MFN_TOGC,DPLL Toggle Control Register"
|
|
bitfld.long 0x28 17. " TOG_DIS ,Desense Disable" "No,Yes"
|
|
bitfld.long 0x28 16. " TOG_EN ,Desense On" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--15. 1. " TOG_CNT[15:0] ,Toggle Counter Value"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "DP_DESTAT,Desense Status Register"
|
|
bitfld.long 0x0 31. " TOG_SEL ,Toggle Sel Status" "Inactive,Active"
|
|
hexmask.long 0x0 0.--26. 1. " TOG_MFN[26:0] ,MFN Value"
|
|
width 0xb
|
|
tree.end
|
|
tree "DPLL2"
|
|
base ad:0x63F84000
|
|
width 13.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "DP_CTL,DPLL Control Register"
|
|
bitfld.long 0x00 13. " MUL_CTRL ,Multiple Control" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DPDCK0_2_EN ,Dpdck0_2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " REF_CLK_DIV ,Ref Clk Division factor" "Div by 1,Div by 2"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Reserved,Reserved,Clock2 (24MHz oscillator clock),?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Clk0,Clk1,Clk2,Clk3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " HFSM ,HFS-Mode Status" "LFS,HFS"
|
|
bitfld.long 0x00 6. " PRE ,Power Up Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " UPEN ,PLL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RST ,Restart" "Not restarted,Restarted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCP ,Reference Clock Polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 2. " PLM ,Phase Lock Mode" "Frequency,Frequency/Phase"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BRMO ,BRM Order" "First,Second"
|
|
bitfld.long 0x00 0. " LRF ,Lock Ready Flag" "Not locked,Locked"
|
|
line.long 0x04 "DP_CONFIG,DPLL Config Register"
|
|
bitfld.long 0x04 1. " AREN ,Auto Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LDREQ ,Load Request" "Not requested,Requested"
|
|
line.long 0x08 "DP_OP,DPLL Operation Register"
|
|
bitfld.long 0x08 4.--7. " MFI[3:0] ,Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x0c "DP_MFD,DPLL MFD Register"
|
|
hexmask.long 0x0c 0.--26. 1. " MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x10 "DP_MFN,DPLL MFN Register"
|
|
hexmask.long 0x10 0.--26. 1. " MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x14 "DP_MFNMINUS,DPLL MFNMINUS Register"
|
|
hexmask.long 0x14 0.--26. 1. " MFNMINUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x18 "DP_MFNPLUS,DPLL MFNPLUS Register"
|
|
hexmask.long 0x18 0.--26. 1. " MFNPLUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x1c "DP_HFS_OP,DPLL High Frequency Support Operation Register"
|
|
bitfld.long 0x1c 4.--7. " HFS_MFI[3:0] ,HFS Mode - Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x20 "DP_HFS_MFD,DPLL HFS MFD Register"
|
|
hexmask.long 0x20 0.--26. 1. " HFS_MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x24 "DP_HFS_MFN,DPLL HFS MFN Register"
|
|
hexmask.long 0x24 0.--26. 1. " HFS_MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x28 "DP_MFN_TOGC,DPLL Toggle Control Register"
|
|
bitfld.long 0x28 17. " TOG_DIS ,Desense Disable" "No,Yes"
|
|
bitfld.long 0x28 16. " TOG_EN ,Desense On" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--15. 1. " TOG_CNT[15:0] ,Toggle Counter Value"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "DP_DESTAT,Desense Status Register"
|
|
bitfld.long 0x0 31. " TOG_SEL ,Toggle Sel Status" "Inactive,Active"
|
|
hexmask.long 0x0 0.--26. 1. " TOG_MFN[26:0] ,MFN Value"
|
|
width 0xb
|
|
tree.end
|
|
tree "DPLL3"
|
|
base ad:0x63F88000
|
|
width 13.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "DP_CTL,DPLL Control Register"
|
|
bitfld.long 0x00 13. " MUL_CTRL ,Multiple Control" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DPDCK0_2_EN ,Dpdck0_2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " REF_CLK_DIV ,Ref Clk Division factor" "Div by 1,Div by 2"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Reserved,Reserved,Clock2 (24MHz oscillator clock),?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Clk0,Clk1,Clk2,Clk3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " HFSM ,HFS-Mode Status" "LFS,HFS"
|
|
bitfld.long 0x00 6. " PRE ,Power Up Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " UPEN ,PLL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RST ,Restart" "Not restarted,Restarted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCP ,Reference Clock Polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 2. " PLM ,Phase Lock Mode" "Frequency,Frequency/Phase"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BRMO ,BRM Order" "First,Second"
|
|
bitfld.long 0x00 0. " LRF ,Lock Ready Flag" "Not locked,Locked"
|
|
line.long 0x04 "DP_CONFIG,DPLL Config Register"
|
|
bitfld.long 0x04 1. " AREN ,Auto Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LDREQ ,Load Request" "Not requested,Requested"
|
|
line.long 0x08 "DP_OP,DPLL Operation Register"
|
|
bitfld.long 0x08 4.--7. " MFI[3:0] ,Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x0c "DP_MFD,DPLL MFD Register"
|
|
hexmask.long 0x0c 0.--26. 1. " MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x10 "DP_MFN,DPLL MFN Register"
|
|
hexmask.long 0x10 0.--26. 1. " MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x14 "DP_MFNMINUS,DPLL MFNMINUS Register"
|
|
hexmask.long 0x14 0.--26. 1. " MFNMINUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x18 "DP_MFNPLUS,DPLL MFNPLUS Register"
|
|
hexmask.long 0x18 0.--26. 1. " MFNPLUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x1c "DP_HFS_OP,DPLL High Frequency Support Operation Register"
|
|
bitfld.long 0x1c 4.--7. " HFS_MFI[3:0] ,HFS Mode - Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x20 "DP_HFS_MFD,DPLL HFS MFD Register"
|
|
hexmask.long 0x20 0.--26. 1. " HFS_MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x24 "DP_HFS_MFN,DPLL HFS MFN Register"
|
|
hexmask.long 0x24 0.--26. 1. " HFS_MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x28 "DP_MFN_TOGC,DPLL Toggle Control Register"
|
|
bitfld.long 0x28 17. " TOG_DIS ,Desense Disable" "No,Yes"
|
|
bitfld.long 0x28 16. " TOG_EN ,Desense On" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--15. 1. " TOG_CNT[15:0] ,Toggle Counter Value"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "DP_DESTAT,Desense Status Register"
|
|
bitfld.long 0x0 31. " TOG_SEL ,Toggle Sel Status" "Inactive,Active"
|
|
hexmask.long 0x0 0.--26. 1. " TOG_MFN[26:0] ,MFN Value"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "DRAM MC (DRAM Memory Controller)"
|
|
base ad:0x14000000
|
|
width 7.
|
|
tree "CTL00 - CTL09 Registers"
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CTL00,DRAM CTL Register 00"
|
|
hexmask.long.word 0x00 16.--31. 0x1 " VERSION ,Controller version number"
|
|
bitfld.long 0x00 8.--11. " DRAM_CLASS ,Controller operation mode" "Reserved,LPDDR1,Reserved,Reserved,DDR2,LPDDR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,Controller Operation" "Inactive,Active"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CTL01,DRAM CTL Register 01"
|
|
bitfld.long 0x00 16.--17. " MAX_CS_REG ,Maximum chip select number" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. " MAX_COL_REG ,Maximum column addresses width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MAX_ROW_REG ,Maximum address bus width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
; CTL00 -> DRAM_CLASS = "LPDDR2"
|
|
if (d.l(ad:0x14000000)&0xF00)==0x500
|
|
group.long 0x08++0x0F
|
|
line.long 0x00 "CTL02,DRAM CTL Register 02"
|
|
hexmask.long.tbyte 0x00 0.--23. 0x1 " TINIT ,DRAM Initialization Time (in cycles)"
|
|
line.long 0x04 "CTL03,DRAM CTL Register 03"
|
|
hexmask.long.tbyte 0x04 0.--23. 0x1 " TINIT3 ,Required time between CKE assertion and memory reset (in cycles)"
|
|
line.long 0x08 "CTL04,DRAM CTL Register 04"
|
|
hexmask.long.tbyte 0x08 0.--23. 0x1 " TINIT4 ,Required time between memory reset and MRR command (in cycles)"
|
|
line.long 0x0C "CTL05,DRAM CTL Register 05"
|
|
hexmask.long.tbyte 0x0C 0.--23. 0x1 " TINIT5 ,Required time between memory reset and initialization complete (in cycles)"
|
|
; CTL00 -> DRAM_CLASS = "LPDDR1"
|
|
; or CTL00 -> DRAM_CLASS = "DDR2"
|
|
elif (d.l(ad:0x14000000)&0xF00)==0x100||(d.l(ad:0x14000000)&0xF00)==0x400
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTL05,DRAM CTL Register 05"
|
|
bitfld.long 0x00 24.--27. " INITAREF ,Required auto-refresh commands number for initialization sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
; CTL00 -> DRAM_CLASS = "LPDDR1"
|
|
if (d.l(ad:0x14000000)&0xF00)==0x100
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTL06,DRAM CTL Register 06"
|
|
bitfld.long 0x00 24.--28. " TCCD ,Minimum delay between CAS commands (in cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--19. " WRLAT ,Latency between issuing write command and presenting write data to DRAM device (in cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CASLAT_LIN_GATE ,Meaningless parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1.--4. " CASLAT_LIN[4:1] ,CAS latency linear value" "Reserved,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " CASLAT_LIN[0] ,Additional CAS latency linear value increment" "+0 cycles,+0.5 cycle"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTL06,DRAM CTL Register 06"
|
|
bitfld.long 0x00 24.--28. " TCCD ,Minimum delay between CAS commands (in cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--19. " WRLAT ,Latency between issuing write command and presenting write data to DRAM device (in cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CASLAT_LIN_GATE ,Meaningless parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "CTL07,DRAM CTL Register 07"
|
|
hexmask.long.byte 0x00 24.--31. 0x1 " TRAS_MIN ,DRAM minimum row activate time (in cycles)"
|
|
bitfld.long 0x00 16.--21. " TRC ,DRAM period between active commands for the same bank (in cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TRRD ,DRAM activate to activate delay for different banks (in cycles)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " TBST_INT_INTERVAL ,Memory burst interrupt level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CTL08,DRAM CTL Register 08"
|
|
bitfld.long 0x04 24.--28. " TMRD ,Minimum number of cycles required between two mode register write commands (in cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--18. " TRTP ,DRAM read to precharge time (in cycles)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--12. " TRP ,DRAM pre-charge command time (in cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--3. " TWTR ,number of cycles needed to switch from a write to a read operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "CTL09,DRAM CTL Register 09"
|
|
bitfld.long 0x08 24. " WRITEINTERP ,Support for interrupting write burst with a read command" "Not supported,Supported"
|
|
hexmask.long.word 0x08 8.--23. 0x1 " TRANS_MAX ,DRAM maximum row active time (in cycles)"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 0x1 " TMOD ,Required wait time between mode and nonmode register write command"
|
|
tree.end
|
|
tree "CTL10 - CTL19 Registers"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "CTL10,DRAM CTL Register 10"
|
|
bitfld.long 0x00 24. " CONCURRENTAP ,Concurrent auto pre-charge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AP ,DRAM auto pre-charge mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " TCKESR ,Minimum CKE low pulse width during a self-refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " TCKE ,Minimum CKE pulse width" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CTL11,DRAM CTL Register 11"
|
|
bitfld.long 0x4 24.--28. " TDAL ,DRAM TDAL parameter (in cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x4 16.--20. " TWR_INT ,Defines the DRAM write recovery time (in cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.long.byte 0x4 8.--15. 1. " TRCD_INT ,Defines the DRAM RAS to CAS delay (in cycles)"
|
|
bitfld.long 0x4 0. " TRAS_LOCKOUT ,tRAS lockout setting for the DRAM device" "Not supported,Supported"
|
|
; CTL00 -> DRAM_CLASS = "LPDDR1"
|
|
; or CTL00 -> DRAM_CLASS = "DDR2"
|
|
if (d.l(ad:0x14000000)&0xF00)==0x100||(d.l(ad:0x14000000)&0xF00)==0x400
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CTL12,DRAM CTL Register 12"
|
|
bitfld.long 0x00 24.--27. " TMRR ,DRAM tMRR Term in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " NO_CMD_INIT ,DRAM Commands Disable until DLL Init Complete and tdll expiry" "Not disabled,Disabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TDLL ,TDLL Parameter in cycles"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CTL12,DRAM CTL Register 12"
|
|
bitfld.long 0x00 24.--27. " TMRR ,DRAM tMRR Term in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TDLL ,TDLL Parameter in cycles"
|
|
endif
|
|
; CTL00 -> DRAM_CLASS = "LPDDR1"
|
|
if (d.l(ad:0x14000000)&0xF00)==0x100
|
|
group.long 0x34++0x7
|
|
line.long 0x00 "CTL13,DRAM CTL Register 13"
|
|
hexmask.long.word 0x00 16.--31. 1. " TCPD ,DRAM TCPD parameter (in cycles)"
|
|
bitfld.long 0x00 8.--13. " TFAW ,DRAM TFAW parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " BSTLEN ,Defines the memory burst length encoding for the MC" "Reserved,2 words,4 words,8 words,?..."
|
|
; CTL00 -> DRAM_CLASS = "DDR2"
|
|
elif (d.l(ad:0x14000000)&0xF00)==0x400
|
|
group.long 0x34++0x7
|
|
line.long 0x00 "CTL13,DRAM CTL Register 13"
|
|
hexmask.long.word 0x00 16.--31. 1. " TCPD ,DRAM TCPD parameter (in cycles)"
|
|
bitfld.long 0x00 8.--13. " TFAW ,DRAM TFAW parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " BSTLEN ,Defines the memory burst length encoding for the MC" "Reserved,Reserved,4 words,?..."
|
|
; CTL00 -> DRAM_CLASS = "LPDDR2"
|
|
elif (d.l(ad:0x14000000)&0xF00)==0x500
|
|
group.long 0x34++0x7
|
|
line.long 0x00 "CTL13,DRAM CTL Register 13"
|
|
hexmask.long.word 0x00 16.--31. 1. " TCPD ,DRAM TCPD parameter (in cycles)"
|
|
bitfld.long 0x00 8.--13. " TFAW ,DRAM TFAW parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " BSTLEN ,Defines the memory burst length encoding for the MC" "Reserved,Reserved,4 words,8 words,?..."
|
|
else
|
|
group.long 0x34++0x7
|
|
line.long 0x00 "CTL13,DRAM CTL Register 13"
|
|
hexmask.long.word 0x00 16.--31. 1. " TCPD ,DRAM TCPD parameter (in cycles)"
|
|
bitfld.long 0x00 8.--13. " TFAW ,DRAM TFAW parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
width 7.
|
|
group.long 0x38++0x17
|
|
line.long 0x00 "CTL14,DRAM CTL Register 14"
|
|
bitfld.long 0x00 24. " AUTO_REFRESH_MODE ,Sets the mode for when the automatic refresh will occur" "Next memory burst,Next command"
|
|
bitfld.long 0x00 16. " AREFRESH ,Initiates an automatic refresh to the DRAM devices based on the setting of the auto_refresh_mode parameter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " REG_DIMM_ENABLE ,Enables registered DIMM operations to control the address and command pipeline of the memory controller" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " TRP_AB ,Defines the DRAM TRP time for all banks (in cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "CTL15,DRAM CTL Register 15"
|
|
hexmask.long.word 0x04 8.--17. 1. " TRFC ,Defines the DRAM refresh command time (in cycles)"
|
|
bitfld.long 0x04 0. " TREF_ENABLE ,Enables refresh commands" "Disabled,Enabled"
|
|
line.long 0x08 "CTL16,DRAM CTL Register 16"
|
|
hexmask.long.word 0x08 16.--29. 0x1 " TREF_INTERVAL ,Time delay between refresh commands issued for different chip selects (in clock cycles)"
|
|
hexmask.long.word 0x08 0.--15. 0x1 " TREF ,DRAM cycles between refresh commands"
|
|
line.long 0x0C "CTL17,DRAM CTL Register 17"
|
|
hexmask.long.word 0x0C 8.--23. 1. " TPDEX ,Defines the DRAM power-down exit command period (in cycles)"
|
|
bitfld.long 0x0C 0. " POWER_DOWN ,Power down state" "Poweren up,Powered down"
|
|
line.long 0x10 "CTL18,DRAM CTL Register 18"
|
|
hexmask.long.word 0x10 16.--31. 0x1 " TXSNR ,Defines the DRAM time from a selfrefresh exit to a command that does not require the memory DLL to be locked"
|
|
hexmask.long.word 0x10 0.--15. 0x1 " TXSR ,Defines the DRAM time from a selfrefresh exit to an active command that requires the memory DLL to be locked"
|
|
line.long 0x14 "CTL19,DRAM CTL Register 19"
|
|
bitfld.long 0x14 24.--26. " CKE_DELAY ,Sets the number of additional cycles of delay to include in the CKE signal cke_status for status reporting" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 16. " ENABLE_QUICK_REFRESH ,Initialization sequence self-refresh interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " PWRUP_SREFRESH_EXIT ,Power-down mode exit with self-refresh enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " SREFRESH ,Self-refresh mode enable" "Disable,Enable"
|
|
tree.end
|
|
tree "CTL20 - CTL29 Registers"
|
|
group.long 0x50++0x13
|
|
line.long 0x00 "CTL20,DRAM CTL Register 20"
|
|
hexmask.long.word 0x00 8.--23. 0x1 " LOWPOWER_POWER_DOWN_CNT ,Counts the number of idle cycles before memory power-down or power-down with memory clock gating low power mode"
|
|
bitfld.long 0x00 4. " LOWPOWER_CONTROL[4] ,Memory power-down mode low power mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LOWPOWER_CONTROL[3] ,Memory power-down with memory clock gating mode low power mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LOWPOWER_CONTROL[2] ,Memory self-refresh mode low power mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOWPOWER_CONTROL[1] ,Memory self-refresh with memory clock gating mode low power mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LOWPOWER_CONTROL[0] ,Memory self-refresh with memory and controller clock gating mode low power mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "CTL21,DRAM CTL Register 21"
|
|
hexmask.long.word 0x04 16.--31. 0x1 " LOWPOWER_EXTERNAL_CNT ,Counts the number of idle cycles before memory self-refresh with memory clock gating low power mode"
|
|
hexmask.long.word 0x04 0.--15. 0x1 " LOWPOWER_SELF_REFRESH_CNT ,Counts the number of cycles to the next memory self-refresh low power mode"
|
|
line.long 0x08 "CTL22,DRAM CTL Register 22"
|
|
hexmask.long.word 0x08 8.--23. 0x1 " LOWPOWER_INTERNAL_CNT ,Counts the number of idle cycles before memory self-refresh with memory and controller clock gating low power mode"
|
|
bitfld.long 0x08 4. " LOWPOWER_AUTO_ENABLE[4] ,Memory power-down mode low power mode automatic entry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " LOWPOWER_AUTO_ENABLE[3] ,Memory power-down with memory clock gating mode low power mode automatic entry enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " LOWPOWER_AUTO_ENABLE[2] ,Memory self-refresh mode low power mode automatic entry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " LOWPOWER_AUTO_ENABLE[1] ,Memory self-refresh with memory clock gating mode low power mode automatic entry enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " LOWPOWER_AUTO_ENABLE[0] ,Memory self-refresh with memory and controller clock gating mode low power mode automatic entry enable" "Disabled,Enabled"
|
|
line.long 0x0C "CTL23,DRAM CTL Register 23"
|
|
bitfld.long 0x0C 24.--27. " CKSRE ,Sets the number of cycles to hold the clock stable after entering self-refresh mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 17. " LOWPOWER_REFRESH_ENABLE[1] ,Sets whether refreshes will occur while the memory controller is in one of the power-down modes for CS1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " LOWPOWER_REFRESH_ENABLE[0] ,Sets whether refreshes will occur while the memory controller is in one of the power-down modes for CS0" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 0.--15. 0x1 " LOWPOWER_REFRESH_HOLD ,Sets the number of cycles that the MC will wait before attempting to re-lock the DLL when using the Memory Self-Refresh with Memory and Controller Clock Gating low power mode"
|
|
line.long 0x10 "CTL24,DRAM CTL Register 24"
|
|
bitfld.long 0x10 8. " WRITE_MODEREG ,Writes mode register information into the memory devices" "0,1"
|
|
bitfld.long 0x10 0.--3. " CKSRX ,Sets the number of cycles to hold the clock stable before exiting self-refresh mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "CTL25,DRAM CTL Register 25"
|
|
bitfld.long 0x00 16. " READ_MODEREG[16] ,Read from the mode register MRx - Trigger the mode register read" "Not triggered,Triggered"
|
|
hexmask.long.byte 0x00 8.--15. 0x1 " READ_MODEREG[15:8] ,Read from the mode register MRx - Defines the chip select for which to read the command"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 0x1 " READ_MODEREG[7:0] ,Read from the mode register MRx - Defines the mode register number being requested"
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "CTL26,DRAM CTL Register 26"
|
|
hexmask.long.word 0x00 16.--30. 0x1 " MR0_DATA_0 ,Holds the memory mode register 0 data for chip select 0 written during memory initialization or when the write_modereg parameter is asserted"
|
|
hexmask.long.byte 0x00 8.--15. 0x1 " PERIPHERAL_MRR_DATA[15:8] ,MRR chip information"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 0x1 " PERIPHERAL_MRR_DATA[7:0] ,Mode register data"
|
|
line.long 0x04 "CTL27,DRAM CTL Register 27"
|
|
hexmask.long.word 0x04 16.--30. 0x1 " MR2_DATA_0 ,Holds the memory mode register 2 data for chip select 0 written during memory initialization"
|
|
hexmask.long.word 0x04 0.--14. 0x1 " MR1_DATA_0 ,Holds the memory mode register 1 data for chip select 0 written during memory initialization"
|
|
line.long 0x08 "CTL28,DRAM CTL Register 28"
|
|
hexmask.long.word 0x08 16.--30. 0x1 " MR16_DATA_0 ,Holds the memory mode register 16 data for chip select 0 written during memory initialization"
|
|
hexmask.long.word 0x08 0.--14. 0x1 " MR3_DATA_0 ,Holds the memory mode register 3 data for chip select 0 written during memory initialization"
|
|
line.long 0x0C "CTL29,DRAM CTL Register 29"
|
|
hexmask.long.word 0x0C 16.--30. 0x1 " MR0_DATA_1 ,MRS data to program to memory mode register 0 for chip select 1"
|
|
hexmask.long.word 0x0C 0.--14. 0x1 " MR17_DATA_0 ,Holds the memory mode register 17 data for chip select 0 written during memory initialization"
|
|
tree.end
|
|
tree "CTL30 - CTL39 Registers"
|
|
group.long 0x78++0x07
|
|
line.long 0x00 "CTL30,DRAM CTL Register 30"
|
|
hexmask.long.word 0x00 16.--30. 1. " MR2_DATA_1 ,Data to program into memory mode register 2 for chip select 1"
|
|
hexmask.long.word 0x00 0.--14. 1. " MR1_DATA_1 ,Data to program into memory mode register 1 for chip select 1"
|
|
line.long 0x04 "CTL31,DRAM CTL Register 31"
|
|
hexmask.long.word 0x04 16.--30. 1. " MR16_DATA_1 ,Data to program into memory mode register 16 for chip select 1"
|
|
hexmask.long.word 0x04 0.--14. 1. " MR3_DATA_1 ,Data to program into memory mode register 3 for chip select 1"
|
|
; CTL00 -> DRAM_CLASS = "LPDDR2"
|
|
if (d.l(ad:0x14000000)&0xF00)==0x500
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "CTL32,DRAM CTL Register 32"
|
|
hexmask.long.word 0x00 16.--27. 1. " ZQINIT ,Specifies the duration of wait time, in cycles, required for the memory devices to complete a ZQ command during initialization"
|
|
hexmask.long.word 0x00 0.--14. 1. " MR17_DATA_1 ,Data to program into memory mode register 17 for chip select 1"
|
|
line.long 0x04 "CTL33,DRAM CTL Register 33"
|
|
bitfld.long 0x04 19. " ZQ_REQ[3] ,Triggers a ZQ reset to all chip selects in the system" "No trigger,Trigger"
|
|
bitfld.long 0x04 18. " ZQ_REQ[2] ,Triggers a ZQ initialization to all chip selects in the system" "No trigger,Trigger"
|
|
textline " "
|
|
bitfld.long 0x04 17. " ZQ_REQ[1] ,Triggers a long ZQ calibration to all chip selects in the system" "No trigger,Trigger"
|
|
bitfld.long 0x04 16. " ZQ_REQ[0] ,Triggers a short ZQ calibration" "No trigger,Triggere"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--11. 1. " ZQCL ,Wait time to complete a long ZQ calibration command"
|
|
line.long 0x08 "CTL34,DRAM CTL Register 34"
|
|
bitfld.long 0x08 27. " ZQ_ON_SREF_EXIT[3] ,Triggers a ZQ reset to all chip selects in the system on self-refresh exit" "Not trigger,Trigger"
|
|
bitfld.long 0x08 26. " ZQ_ON_SREF_EXIT[2] ,Triggers a ZQ initialization to all chip selects in the system on selfrefresh exit" "Not trigger,Trigger"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ZQ_ON_SREF_EXIT[1] ,Triggers a long ZQ calibration to all chip selects in the system on selfrefresh exit" "Not trigger,Trigger"
|
|
bitfld.long 0x08 24. " ZQ_ON_SREF_EXIT[0] ,Triggers a short ZQ calibration" "Not trigger,Trigger"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--23. 1. " REFRESH_PER_ZQ ,Sets the maximum number of refreshes allowed between automatic ZQCS commands"
|
|
hexmask.long.word 0x08 0.--11. 1. " ZQCS ,Specifies the duration of wait time, in cycles, required for the memory devices to complete a short ZQ calibration command"
|
|
line.long 0x0C "CTL35,DRAM CTL Register 35"
|
|
bitfld.long 0x0C 24. " ZQCS_ROTATE ,Defines the behavior of short ZQ calibrations" "Calibrate all CSes,Calibrate one CS"
|
|
hexmask.long.word 0x0C 8.--19. 1. " ZQRESET ,Specifies the duration of wait time, in cycles, required for the memory devices to complete a ZQRESET command"
|
|
textline " "
|
|
rbitfld.long 0x0C 0. " ZQ_IN_PROGRESS ,Indicates that a ZQ command is currently in progress" "Completed,In progress"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CTL32,DRAM CTL Register 32"
|
|
hexmask.long.word 0x00 0.--14. 1. " MR17_DATA_1 ,Data to program into memory mode register 17 for chip select 1"
|
|
endif
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CTL36,DRAM CTL Register 36"
|
|
bitfld.long 0x00 24.--27. " APREBIT ,Defines the location of the auto precharge bit in the DRAM address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--18. " COLUMN_SIZE ,Shows the difference between the maximum column width available (10) and the actual number of column pins being used" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " ADDR_PINS ,Defines the difference between the maximum number of address pins configured (15) and the actual number of pins being used" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EIGHT_BANK_MODE ,Indicates that the memory devices have eight banks" "4 banks,8 banks"
|
|
;if CTL38 -> PRIORITY_EN = "Enabled"
|
|
if (d.l((ad:0x14000000)+0x98)&0x100)==0x100
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CTL37,DRAM CTL Register 37"
|
|
bitfld.long 0x00 24. " BANK_SPLIT_EN ,Enables bank splitting as a condition when using the placement logic to fill the command queue" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ADDR_CMP_EN ,Enables address collision/data coherency detection as a condition when using the placement logic to fill the command queue" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " COMMAND_AGE_COUNT ,Holds the initial value of the command aging counters associated with each command in the command queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " AGE_COUNT ,Holds the initial value of the master aging-rate counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CTL37,DRAM CTL Register 37"
|
|
bitfld.long 0x00 24. " BANK_SPLIT_EN ,Enables bank splitting as a condition when using the placement logic to fill the command queue" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ADDR_CMP_EN ,Enables address collision/data coherency detection as a condition when using the placement logic to fill the command queue" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x98++0x07
|
|
line.long 0x00 "CTL38,DRAM CTL Register 38"
|
|
bitfld.long 0x00 24. " SWAP_EN ,Enables swapping of the active command for a new higher-priority command when using the placement logic" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RW_SAME_EN ,Enables read/write grouping as a condition when using the placement logic to fill the command queue" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PRIORITY_EN ,Enables priority as a condition when using the placement logic to fill the command queue" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PLACEMENT_EN ,Enables using the placement logic to fill the command queue" "Disabled,Enabled"
|
|
line.long 0x04 "CTL39,DRAM CTL Register 39"
|
|
bitfld.long 0x04 24. " REDUC ,Allows the MC to be used with memory devices with a smaller datapath (16-bit)" "Full bus,Half width"
|
|
bitfld.long 0x04 16.--17. " CS_MAP ,Sets the mask that determines which chip select pins are active, with each bit representing a different chip select" "None,CS[0],CS[1],Both"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SWAP_PORT_RW_SAME_EN ,User must set SWAP_PORT_RW_SAME_EN = 0 for this MC" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DISABLE_RW_GROUP_W_BNK_CONFLICT[1] ,Prohibits placement into a command queue entry 2 entries away (before or after) from a command with a bank conflict" "Allowed,Prohibited"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DISABLE_RW_GROUP_W_BNK_CONFLICT[0] ,Prohibits placement into a command queue entry immediately before or immediately after a command with a bank conflict" "Allowed,Prohibited"
|
|
tree.end
|
|
tree "CTL40 - CTL49 Registers"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "CTL40,DRAM CTL Register 40"
|
|
bitfld.long 0x00 24. " FAST_WRITE ,Controls when the write commands are issued to the DRAM devices" "After burst,After first word"
|
|
bitfld.long 0x00 16. " LPDDR2_S4 ,Indicates the type of LPDDR2 device being used" "LPDDR2-S2/LPDDR-NVM,LPDDR2-S4"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WRDATALAT_REDUC_EN ,Enables data path latency reduction for the I/O cells of the PHY" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CMDLAT_REDUC_EN ,Enables reducing the latency of the command path in the MC by one clock cycle" "Disabled,Enabled"
|
|
line.long 0x04 "CTL41,DRAM CTL Register 41"
|
|
bitfld.long 0x04 16. " RESYNC_DLL_PER_AREF_EN ,Enables an automatic re-synchronization of the DLL after every refresh" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RESYNC_DLL ,Initiates a re-synchronization of the DLL" "No resync,Resync"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " Q_FULLNESS ,Defines quantity of data that will be considered full for the command queue" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "CTL42,DRAM CTL Register 42"
|
|
bitfld.long 0x08 25. " INT_ACK[9] ,User-initiated DLL resync is finished clear" "No clear,clear"
|
|
bitfld.long 0x08 24. " INT_ACK[8] ,dfi_init_complete state change detected clear" "No clear,clear"
|
|
textline " "
|
|
bitfld.long 0x08 23. " INT_ACK[7] ,Indicates that a register interface mode register write has finished and that another register interface mode register write may be issued" "No clear,clear"
|
|
bitfld.long 0x08 22. " INT_ACK[6] ,Indicates that a peripheral register interface mode register read has finished and that the mode register data and chip can be found in the param_peripheral_mrr_data register" "No clear,clear"
|
|
textline " "
|
|
bitfld.long 0x08 21. " INT_ACK[5] ,ODT enabled and CAS Latency 3 programmed error detected" "No clear,clear"
|
|
bitfld.long 0x08 20. " INT_ACK[4] ,DRAM initialization complete clear" "No clear,clear"
|
|
textline " "
|
|
bitfld.long 0x08 19. " INT_ACK[3] ,Error was found with command data channel in a port" "No clear,clear"
|
|
bitfld.long 0x08 18. " INT_ACK[2] ,Error was found with command channel in a port" "No clear,clear"
|
|
textline " "
|
|
bitfld.long 0x08 17. " INT_ACK[1] ,Multiple accesses outside the defined PHYSICAL memory space detected" "No clear,clear"
|
|
bitfld.long 0x08 16. " INT_ACK[0] ,A single access outside the defined PHYSICAL memory space detected" "No clear,clear"
|
|
textline " "
|
|
rbitfld.long 0x08 10. " INT_STATUS[10] ,Logical OR of all lower bits interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 9. " INT_STATUS[9] ,User-initiated DLL resync is finished interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 8. " INT_STATUS[8] ,dfi_init_complete state change detected interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 7. " INT_STATUS[7] ,Indicates that a register interface mode register write has finished and that another register interface mode register write may be issued" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 6. " INT_STATUS[6] ,Indicates that a peripheral register interface mode register read has finished and that the mode register data and chip can be found in the param_peripheral_mrr_data register" "No interrupt,Interrupt"
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rbitfld.long 0x08 5. " INT_STATUS[5] ,ODT enabled and CAS Latency 3 programmed error detected" "No interrupt,Interrupt"
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textline " "
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rbitfld.long 0x08 4. " INT_STATUS[4] ,DRAM initialization complete interrupt" "No interrupt,Interrupt"
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rbitfld.long 0x08 3. " INT_STATUS[3] ,Error was found with command data channel in a port" "No interrupt,Interrupt"
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textline " "
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rbitfld.long 0x08 2. " INT_STATUS[2] ,Error was found with command channel in a port" "No interrupt,Interrupt"
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rbitfld.long 0x08 1. " INT_STATUS[1] ,Multiple accesses outside the defined PHYSICAL memory space detected" "No interrupt,Interrupt"
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textline " "
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rbitfld.long 0x08 0. " INT_STATUS[0] ,A single access outside the defined PHYSICAL memory space detected" "No interrupt,Interrupt"
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line.long 0x0C "CTL43,DRAM CTL Register 43"
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bitfld.long 0x0C 10. " INT_MASK[10] ,Logical OR of all lower bits" "Not masked,Masked"
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bitfld.long 0x0C 9. " INT_MASK[9] ,User-initiated DLL resync is finished" "Not masked,Masked"
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textline " "
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bitfld.long 0x0C 8. " INT_MASK[8] ,dfi_init_complete state change detected" "Not masked,Masked"
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bitfld.long 0x0C 7. " INT_MASK[7] ,Indicates that a register interface mode register write has finished and that another register interface mode register write may be issued" "Not masked,Masked"
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textline " "
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bitfld.long 0x0C 6. " INT_MASK[6] ,Indicates that a peripheral register interface mode register read has finished and that the mode register data and chip can be found in the param_peripheral_mrr_data register" "Not masked,Masked"
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bitfld.long 0x0C 5. " INT_MASK[5] ,ODT enabled and CAS Latency 3 programmed error detected" "Not masked,Masked"
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textline " "
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bitfld.long 0x0C 4. " INT_MASK[4] ,DRAM initialization complete" "Not masked,Masked"
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bitfld.long 0x0C 3. " INT_MASK[3] ,Error was found with command data channel in a port" "Not masked,Masked"
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textline " "
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bitfld.long 0x0C 2. " INT_MASK[2] ,Error was found with command channel in a port" "Not masked,Masked"
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bitfld.long 0x0C 1. " INT_MASK[1] ,Multiple accesses outside the defined PHYSICAL memory space detected" "Not masked,Masked"
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textline " "
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bitfld.long 0x0C 0. " INT_MASK[0] ,A single access outside the defined PHYSICAL memory space detected" "Not masked,Masked"
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rgroup.long 0xB0++0x17
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line.long 0x00 "CTL44,DRAM CTL Register 44"
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hexmask.long 0x00 0.--30. 1. " OUT_OF_RANGE_ADDR ,Holds the address of the command that caused an out-of-range interrupt request to the memory devices"
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line.long 0x04 "CTL45,DRAM CTL Register 45"
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hexmask.long.byte 0x04 8.--13. 0x1 " OUT_OF_RANGE_TYPE ,Holds the type of command that caused an out-of-range interrupt request to the memory devices"
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hexmask.long.byte 0x04 0.--6. 0x1 " OUT_OF_RANGE_LENGTH ,Holds the length of the command that caused an out-of-range interrupt request to the memory devices"
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line.long 0x08 "CTL46,DRAM CTL Register 46"
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hexmask.long.tbyte 0x08 0.--16. 1. " OUT_OF_RANGE_SOURCE_ID ,Holds the Source ID of the command that caused an out-of-range interrupt request to the memory devices"
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line.long 0x0C "CTL47,DRAM CTL Register 47"
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hexmask.long 0x0C 0.--30. 1. " PORT_CMD_ERROR_ADDR ,Holds the address of the command that caused a port command error condition"
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line.long 0x10 "CTL48,DRAM CTL Register 48"
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bitfld.long 0x10 27. " PORT_CMD_ERROR_TYPE[3] ,Narrow transfer requested for a requestor from port Y whose axiY_en_size_lt_width_instr parameter is clear" "No error,Error"
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hexmask.long.word 0x10 0.--16. 0x1 " PORT_CMD_ERROR_ID ,Holds the source ID of the command that caused a port command error condition"
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line.long 0x14 "CTL49,DRAM CTL Register 49"
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hexmask.long.word 0x14 0.--16. 0x1 " PORT_DATA_ERROR_ID ,Holds the source ID of the command that caused a port data error condition"
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tree.end
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tree "CTL50 - CTL 59 Registers"
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group.long 0xC8++0x27
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line.long 0x00 "CTL50,DRAM CTL Register 50"
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bitfld.long 0x00 24.--25. " ODT_WR_MAP_CS1 ,Sets up which (if any) chip(s) will have their ODT termination active while a write occurs on chip select 1" "None,CS0,CS1,Both"
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bitfld.long 0x00 16.--17. " ODT_RD_MAP_CS1 ,Sets up which chip(s) will have their ODT termination active while a read occurs on chip select 1" "None,CS0,CS1,Both"
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textline " "
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bitfld.long 0x00 8.--9. " ODT_WR_MAP_CS0 ,Sets up which (if any) chip(s) will have their ODT termination active while a write occurs on chip select 0" "None,CS0,CS1,Both"
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bitfld.long 0x00 0.--1. " ODT_RD_MAP_CS0 ,Sets up which chip(s) will have their ODT termination active while a read occurs on chip select 0" "None,CS0,CS1,Both"
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line.long 0x04 "CTL51,DRAM CTL Register 51"
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bitfld.long 0x04 24.--27. " ADD_ODT_CLK_SAMETYPE_DIFFCS ,Defines the number of additional clocks of delay to insert between commands of the same type (read to read, write to write) to different chip selects to meet ODT timing requirements" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--20. " ADD_ODT_CLK_DIFFTYPE_DIFFCS ,Defines the number of additional clocks of delay to insert between commands of different types (read to write, write to read) to different chip selects to meet ODT timing requirements" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
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textline " "
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bitfld.long 0x04 8.--11. " ADD_ODT_CLK_W2R_SAMECS ,Defines the number of additional clocks of delay to insert after a write command before a read command to the same chip select to meet ODT timing requirements" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " ADD_ODT_CLK_R2W_SAMECS ,Defines the number of additional clocks of delay to insert after a read command before a write command to the same chip select to meet ODT timing requirements" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CTL52,DRAM CTL Register 52"
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bitfld.long 0x08 24.--26. " W2W_DIFFCS_DLY ,Defines the number of additional clocks of delay to insert from a write command to one chip select to a write command to a different chip select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16.--18. " W2R_DIFFCS_DLY ,Defines the number of additional clocks of delay to insert from a write command to one chip select to a read command to a different chip select" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x08 8.--10. " R2W_DIFFCS_DLY ,Defines the number of additional clocks of delay to insert from a read command to one chip select to a write command to a different chip select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 0.--2. " R2R_DIFFCS_DLY ,Defines the number of additional clocks of delay to insert from a read command to one chip select to a read command to a different chip select" "0,1,2,3,4,5,6,7"
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line.long 0x0C "CTL53,DRAM CTL Register 53"
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bitfld.long 0x0C 24.--26. " W2W_SAMECS_DLY ,Defines the number of additional clocks of delay to insert between two write commands to the same chip select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 16.--18. " W2R_SAMECS_DLY ,Defines the number of additional clocks of delay to insert from a write command to a read command to the same chip select" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x0C 8.--10. " R2W_SAMECS_DLY ,Defines the number of additional clocks of delay to insert from a read command to a write command to the same chip select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 0.--2. " R2R_SAMECS_DLY ,Defines the number of additional clocks of delay to insert between two read commands to the same chip select" "0,1,2,3,4,5,6,7"
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line.long 0x10 "CTL54,DRAM CTL Register 54"
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bitfld.long 0x10 8.--9. " TDQSCK_MIN ,Additional delay needed for tDQSCK" "0,1,2,3"
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bitfld.long 0x10 0.--1. " TDQSCK_MAX ,Additional delay needed for tDQSCK" "0,1,2,3"
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line.long 0x14 "CTL55,DRAM CTL Register 55"
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bitfld.long 0x14 16.--17. " AXI0_FIFO_TYPE_REG ,Sets the relativity of the clock domains between AXI port Y and the MC core clock" "Asynchronous,Reserved,Reserved,Synchronous"
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textline " "
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bitfld.long 0x14 15. " AXI0_EN_SIZE_LT_WIDTH_INSTR[15] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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bitfld.long 0x14 14. " AXI0_EN_SIZE_LT_WIDTH_INSTR[14] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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textline " "
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bitfld.long 0x14 13. " AXI0_EN_SIZE_LT_WIDTH_INSTR[13] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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bitfld.long 0x14 12. " AXI0_EN_SIZE_LT_WIDTH_INSTR[12] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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textline " "
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bitfld.long 0x14 11. " AXI0_EN_SIZE_LT_WIDTH_INSTR[11] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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bitfld.long 0x14 10. " AXI0_EN_SIZE_LT_WIDTH_INSTR[10] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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textline " "
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bitfld.long 0x14 9. " AXI0_EN_SIZE_LT_WIDTH_INSTR[9] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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bitfld.long 0x14 8. " AXI0_EN_SIZE_LT_WIDTH_INSTR[8] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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textline " "
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bitfld.long 0x14 7. " AXI0_EN_SIZE_LT_WIDTH_INSTR[7] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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bitfld.long 0x14 6. " AXI0_EN_SIZE_LT_WIDTH_INSTR[6] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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textline " "
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bitfld.long 0x14 5. " AXI0_EN_SIZE_LT_WIDTH_INSTR[5] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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bitfld.long 0x14 4. " AXI0_EN_SIZE_LT_WIDTH_INSTR[4] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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textline " "
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bitfld.long 0x14 3. " AXI0_EN_SIZE_LT_WIDTH_INSTR[3] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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bitfld.long 0x14 2. " AXI0_EN_SIZE_LT_WIDTH_INSTR[2] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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textline " "
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bitfld.long 0x14 1. " AXI0_EN_SIZE_LT_WIDTH_INSTR[1] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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bitfld.long 0x14 0. " AXI0_EN_SIZE_LT_WIDTH_INSTR[0] ,Allows the port to accept size less than width transactions on AXI port 0 from requestors with the lowest four bits set to Z" "size==width,size<=width"
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line.long 0x18 "CTL56,DRAM CTL Register 56"
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bitfld.long 0x18 24. " WEIGHTED_ROUND_ROBIN_LATENCY_CONTROL ,Controls the weighted round-robin latency option" "Running on waiting command,Always running"
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line.long 0x1C "CTL57,DRAM CTL Register 57"
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bitfld.long 0x1C 24.--27. " AXI0_PRIORITY1_RELATIVE_PRIORITY ,Holds the relative priority of the AXI port 0 for priority 1 commands in weighted round robin arbitration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. " AXI0_PRIORITY0_RELATIVE_PRIORITY ,Holds the relative priority of the AXI port 0 for priority 0 commands in weighted round robin arbitration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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rbitfld.long 0x1C 11. " WRR_PARAM_VALUE_ERR[3] ,The port ordering parameter values for paired ports is not sequential error" "No error,Error"
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rbitfld.long 0x1C 10. " WRR_PARAM_VALUE_ERR[2] ,The relative priority values for any of the ports paired through the weighted_round_robin_weight_sharing parameter are not identical error" "No error,Error"
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textline " "
|
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rbitfld.long 0x1C 9. " WRR_PARAM_VALUE_ERR[1] ,Any of the relative priority parameters have been programmed with a zero value" "No error,Error"
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rbitfld.long 0x1C 8. " WRR_PARAM_VALUE_ERR[0] ,The port ordering parameters do not all contain unique values" "No error,Error"
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textline " "
|
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bitfld.long 0x1C 0. " WEIGHTED_ROUND_ROBIN_WEIGHT_SHARING ,Indicates that the port pair is tied together in arbitration decisions in weighted round-robin arbitration" "Not shared,Shared"
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line.long 0x20 "CTL58,DRAM CTL Register 58"
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bitfld.long 0x20 24.--27. " AXI0_PRIORITY5_RELATIVE_PRIORITY ,Holds the relative priority of the AXI port 0 for priority 5 commands in weighted round robin arbitration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. " AXI0_PRIORITY4_RELATIVE_PRIORITY ,Holds the relative priority of the AXI port 0 for priority 4 commands in weighted round robin arbitration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x20 8.--11. " AXI0_PRIORITY3_RELATIVE_PRIORITY ,Holds the relative priority of the AXI port 0 for priority 3 commands in weighted round robin arbitration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 0.--3. " AXI0_PRIORITY2_RELATIVE_PRIORITY ,Holds the relative priority of the AXI port 0 for priority 2 commands in weighted round robin arbitration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x24 "CTL59,DRAM CTL Register 59"
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bitfld.long 0x24 16. " AXI0_PORT_ORDERING ,Used in weighted round-robin arbitration to modify the order than the ports are scanned when multiple commands are at the same priority level and have the same relative priorities" "Normal,Modified"
|
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textline " "
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bitfld.long 0x24 8.--11. " AXI0_PRIORITY7_RELATIVE_PRIORITY ,Holds the relative priority of the AXI port 0 for priority 7 commands in weighted round robin arbitration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0.--3. " AXI0_PRIORITY6_RELATIVE_PRIORITY ,Holds the relative priority of the AXI port 0 for priority 6 commands in weighted round robin arbitration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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tree.end
|
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tree "CTL60 - CTL69 Registers"
|
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group.long 0xF0++0x03
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line.long 0x00 "CTL60,DRAM CTL Register 60"
|
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hexmask.long.word 0x00 0.--9. 1. " AXI0_PRIORITY_RELAX ,Holds the counter value for AXI port Y at which the priority relax condition is triggered in weighted round robin arbitration"
|
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hgroup.long 0xF4++0x07
|
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hide.long 0x00 "CTL61,DRAM CTL Register 61"
|
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hide.long 0x04 "CTL62,DRAM CTL Register 62"
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group.long 0xFC++0x1B
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line.long 0x00 "CTL63,DRAM CTL Register 63"
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rbitfld.long 0x00 16. " CLE_STATUS ,Provides the value of the cke_status signal in a parameter" "Low,High"
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line.long 0x04 "CTL64,DRAM CTL Register 64"
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rbitfld.long 0x04 24.--27. " TDFI_PHY_WRLAT ,Holds the calculated DFI tPHY_WRLAT timing parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x04 16.--23. 1. " DLL_RST_ADJ_DLY ,Specifies the minimum number of cycles after the master delay value is programmed before the DLL reset may be asserted"
|
|
textline " "
|
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hexmask.long.word 0x04 0.--15. 1. " DLL_RST_DELAY ,Sets the number of cycles that the reset must be held asserted for the DLL"
|
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line.long 0x08 "CTL65,DRAM CTL Register 65"
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bitfld.long 0x8 24.--28. " TDFI_RDDATA_EN_BASE ,Sets DFI base value for the tRDDATA_EN timing parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x8 16.--20. " TDFI_RDDATA_EN ,Holds the calculated DFI tRDDATA_EN timing parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x8 8.--12. " TDFI_PHY_RDLAT ,Holds the tPHY_RDLAT timing parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x8 0.--3. " TDFI_PHY_WRLAT_BASE ,Sets DFI base value for the tPHY_WRLAT timing parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x0C "CTL66,DRAM CTL Register 66"
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hexmask.long.word 0x0C 16.--31. 1. " TDFI_CTRLUPD_MAX ,Defines the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert"
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rbitfld.long 0x0C 8.--11. " TDFI_CTRLUPD_MIN ,Holds the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
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textline " "
|
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bitfld.long 0x0C 1. " DRAM_CLK_DISABLE[1] ,Sets value for the DFI output signal dfi_dram_clk_disable for CS1" "No,Yes"
|
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bitfld.long 0x0C 0. " DRAM_CLK_DISABLE[0] ,Sets value for the DFI output signal dfi_dram_clk_disable for CS0" "No,Yes"
|
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line.long 0x10 "CTL67,DRAM CTL Register 67"
|
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hexmask.long.word 0x10 16.--31. 1. " TDFI_PHYUPD_TYPE1 ,Maximum number of DFI clock cycles for dfi_phyupd_type1"
|
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hexmask.long.word 0x10 0.--15. 1. " TDFI_PHYUPD_TYPE0 ,Maximum number of DFI clock cycles for dfi_phyupd_type0"
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line.long 0x14 "CTL68,DRAM CTL Register 68"
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hexmask.long.word 0x14 16.--31. 1. " TDFI_PHYUPD_TYPE3 ,Maximum number of DFI clock cycles for dfi_phyupd_type3"
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hexmask.long.word 0x14 0.--15. 1. " TDFI_PHYUPD_TYPE2 ,Maximum number of DFI clock cycles for dfi_phyupd_type2"
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line.long 0x18 "CTL69,DRAM CTL Register 69"
|
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bitfld.long 0x18 24.--27. " WRLAT_ADJ ,Adjusts the relative timing between DFI write commands and the dfi_wrdata_en signal to conform to PHY timing requirements" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--20. " RDLAT_ADJ ,Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal to conform to PHY timing requirements" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
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textline " "
|
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hexmask.long.word 0x18 0.--15. 1. " TDFI_PHYUPD_RESP ,Defines the maximum number of DFI clock cycles after the assertion of the dfi_phyupd_req signal to the assertion of the dfi_phyupd_ack signal"
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tree.end
|
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tree "CTL70 - CTL79 Registers"
|
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group.long 0x118++0xB
|
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line.long 0x00 "CTL70,DRAM CTL Register 70"
|
|
bitfld.long 0x00 24. " ODT_ALT_EN ,ODT Support with CAS latency 3 support setting" "Not supported,Supported"
|
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bitfld.long 0x00 16.--19. " TDFI_DRAM_CLK_ENABLE ,Delay from DFI clock enable to memory clock enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
|
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bitfld.long 0x00 8.--10. " TDFI_DRAM_CLK_DISABLE ,Delay from DFI clock disable to memory clock disable" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 0.--3. " TDFI_CTRL_DELAY ,Delay from DFI command to memory command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "CTL71,DRAM CTL Register 71"
|
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bitfld.long 0x04 12. " AXI0_HIDE_BRESP ,Hide extra latency of axi response" "Not hidden,Hidden"
|
|
bitfld.long 0x04 8. " MDDR_CKE_SEL ,Select the CKE init status for MDDR" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " AXI0_AWCOBUF ,Coherent bufferable write command" "Not issued,Issued"
|
|
line.long 0x08 "CTL72,DRAM CTL Register 72"
|
|
bitfld.long 0x08 8. " AXI0_MON_CAPTURE ,Test purpose: capture debug data" "Not captured,Captured"
|
|
bitfld.long 0x08 4. " AXI0_MON_DIS ,Test purpose: disable the axi0 monitor" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 0. " AXI0_SLV_ERR ,Test purpose: force slave error on axi0" "No error,Force error"
|
|
if (d.l((ad:0x14000000)+0x124)&0x200000)==0x200000
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CTL73,DRAM CTL Register 73"
|
|
bitfld.long 0x00 21. " ZQ_LOAD_SEL ,Select the mode of on-chip ZQ loading" "Hardware Controlled,Software Controlled"
|
|
bitfld.long 0x00 20. " ZQ_SW_LOAD ,Load ZQ Values into ZQ Buffers software command" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ZQ_COMPARE_EN ,Enable the on-chip ZQ comparator" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZQ_HW_EN ,Enable the on-chip ZQ hardware controlled loading" "Disabled,Enabled"
|
|
elif (d.l((ad:0x14000000)+0x124)&0x200001)==0x1
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CTL73,DRAM CTL Register 73"
|
|
bitfld.long 0x00 21. " ZQ_LOAD_SEL ,Select the mode of on-chip ZQ loading" "Hardware Controlled,Software Controlled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ZQ_COMPARE_EN ,Enable the on-chip ZQ comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ZQ_HW_LOAD ,Hardware ZQ loading routine start" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZQ_HW_EN ,Enable the on-chip ZQ hardware controlled loading" "Disabled,Enabled"
|
|
else
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CTL73,DRAM CTL Register 73"
|
|
bitfld.long 0x00 21. " ZQ_LOAD_SEL ,Select the mode of on-chip ZQ loading" "Hardware Controlled,Software Controlled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ZQ_COMPARE_EN ,Enable the on-chip ZQ comparator" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZQ_HW_EN ,Enable the on-chip ZQ hardware controlled loading" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x128++0x13
|
|
line.long 0x00 "CTL74,DRAM CTL Register 74"
|
|
bitfld.long 0x00 24.--27. " ZQ_PD_M1 ,The PD minus 1 value for on-chip ZQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " ZQ_PU_M1 ,The PU minus 1 value for on-chip ZQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " ZQ_PUPD_SEL ,Select the PU or PD to be calibrated or loading buffer" "PU calibration/loading,PD calibration/loading"
|
|
line.long 0x04 "CTL75,DRAM CTL Register 75"
|
|
bitfld.long 0x04 8.--11. " ZQ_PD ,The PD value for on-chip ZQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--4. " ZQ_PU ,The PU value for on-chip ZQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "CTL76,DRAM CTL Register 76 - User-defined output 5"
|
|
line.long 0x0C "CTL77,DRAM CTL Register 77 - User-defined output 6"
|
|
line.long 0x10 "CTL78,DRAM CTL Register 78 - User-defined output 7"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "CTL79,DRAM CTL Register 79"
|
|
bitfld.long 0x00 24. " Q_ALMOST_FULL ,Indicate the command queue is almost full" "Not full,Almost full"
|
|
bitfld.long 0x00 12. " MON_AXI0_BUSY ,AXI0 port monitor busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CTL_BUSY ,Controller busy" "Not busy,Busy"
|
|
tree.end
|
|
tree "CTL80 - CTL86 Registers"
|
|
rgroup.long 0x140++0x1B
|
|
line.long 0x00 "CTL80,DRAM CTL Register 80 - User-defined input 1"
|
|
line.long 0x04 "CTL81,DRAM CTL Register 81 - Test purpose: debug data 0"
|
|
line.long 0x08 "CTL82,DRAM CTL Register 82 - Test purpose: debug data 1"
|
|
line.long 0x0C "CTL83,DRAM CTL Register 83"
|
|
bitfld.long 0x0C 0. " ZQ_COM_OUT ,ZQ comparator output" "Low,High"
|
|
line.long 0x10 "CTL84,DRAM CTL Register 84 - User-defined input 5"
|
|
line.long 0x14 "CTL85,DRAM CTL Register 85 - User-defined input 6"
|
|
line.long 0x18 "CTL86,DRAM CTL Register 86 - User-defined input 7"
|
|
tree.end
|
|
tree "PHY00 - PHY09 Registers"
|
|
hgroup.long 0x200++0x03
|
|
hide.long 0x00 "PHY00,DRAM PHY Register 00 - Reserved"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "PHY01,DRAM PHY Register 01 - PHY Parameters for Data Slice 0"
|
|
bitfld.long 0x00 12.--14. " PAD_ODT_VAL_B3 ,DDR IO ODT settings for ddr data byte 3" "ODT Disabled,150 Ohm ODT,75 Ohm ODT,50 Ohm ODT,?..."
|
|
bitfld.long 0x00 8.--10. " PAD_ODT_VAL_B2 ,DDR IO ODT settings for ddr data byte 2" "ODT Disabled,150 Ohm ODT,75 Ohm ODT,50 Ohm ODT,?..."
|
|
bitfld.long 0x00 4.--6. " PAD_ODT_VAL_B1 ,DDR IO ODT settings for ddr data byte 1" "ODT Disabled,150 Ohm ODT,75 Ohm ODT,50 Ohm ODT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PAD_ODT_VAL_B0 ,DDR IO ODT settings for ddr data byte 0" "ODT Disabled,150 Ohm ODT,75 Ohm ODT,50 Ohm ODT,?..."
|
|
group.long 0x208++0x07
|
|
line.long 0x00 "PHY02,DRAM PHY Register 02 - Data Slice 0 PHY Parameters 0"
|
|
bitfld.long 0x00 31. " DM_TSEL_EN ,Enables on-chip pad ODT for the DM pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DQ_TSEL_EN ,Enables on-chip pad ODT for the DQ pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DQS_RATIO ,Controls on-chip pad ODT for the DM pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ECHO_GATE_EN ,Echo gate control for data slice X" "dfi_rddata_en used,echo_gate created"
|
|
bitfld.long 0x00 24.--26. " RD_DLY_SEL ,Defines the read data delay" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PAD_OE_POLARITY ,Sets the pad output enable polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENABLE_HALF_CAS ,Subtracts 1/2 cycle from the DQS gate value programmed into phy_ctrl_reg_1_X [2:0] by 1/2 cycle" "Not adjusted,Adjusted"
|
|
bitfld.long 0x00 12.--15. " DQS_OE_START ,Adjusts the starting point of the DQS pad output enable window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DQS_OE_END ,Adjusts the ending point of the DQS pad output enable window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DATA_OE_START ,Adjusts the starting point of the DQ pad output enable window" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DATA_OE_END ,Adjusts the ending point of the DQ pad output enable window" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PHY03,DRAM PHY Register 03 - Data Slice 0 PHY Parameters 1"
|
|
bitfld.long 0x04 28.--31. " TSEL_START ,Defines the on-chip pad ODT enable time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " TSEL_END ,Defines the on-chip pad ODT disable time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 23. " DQS_TSEL_EN ,Enables on-chip pad ODT for the DQS pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " POLARITY ,Controls the polarity of the tsel signal for the DQS and DM pads" "Negative,Positive"
|
|
bitfld.long 0x04 21. " LPBK_ERR_CHECK ,Triggers a data return to the memory controller" "No action,Data return"
|
|
bitfld.long 0x04 20. " LPBK_FAIL_SEL ,Selects data output type for den_phy_obs_reg_0_X [23:8]" "Return expected data,Return actual data"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LPBK_CTRL ,Loopback control" "Normal mode,lpbk_start,lpbk_stop,clear"
|
|
bitfld.long 0x04 17. " LPBK_INTERNAL ,Controls the loopback read multiplexer" "External,Internal"
|
|
bitfld.long 0x04 16. " LPBK_EN ,Controls the internal write multiplexer" "Normal operation,Loopback enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " LPBK_ERR_DELAY ,Sets the cycle delay between the LFSR and loopback error check logic" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 6.--8. " GATE_ERR_DELAY ,Defines the number of cycles of margin allowed for the final DQS falling edge of a read burst" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--5. " GATE_CLOSE_CFG ,DQS gate closing time extension" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " GATE_CFG ,Coarse adjust of gate open time" "0,1,2,3,4,5,6,7"
|
|
group.long 0x210++0x07
|
|
line.long 0x00 "PHY04,DRAM PHY Register 04 - Data Slice 1 PHY Parameters 0"
|
|
bitfld.long 0x00 31. " DM_TSEL_EN ,Enables on-chip pad ODT for the DM pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DQ_TSEL_EN ,Enables on-chip pad ODT for the DQ pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DQS_RATIO ,Controls on-chip pad ODT for the DM pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ECHO_GATE_EN ,Echo gate control for data slice X" "dfi_rddata_en used,echo_gate created"
|
|
bitfld.long 0x00 24.--26. " RD_DLY_SEL ,Defines the read data delay" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PAD_OE_POLARITY ,Sets the pad output enable polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENABLE_HALF_CAS ,Subtracts 1/2 cycle from the DQS gate value programmed into phy_ctrl_reg_1_X [2:0] by 1/2 cycle" "Not adjusted,Adjusted"
|
|
bitfld.long 0x00 12.--15. " DQS_OE_START ,Adjusts the starting point of the DQS pad output enable window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DQS_OE_END ,Adjusts the ending point of the DQS pad output enable window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DATA_OE_START ,Adjusts the starting point of the DQ pad output enable window" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DATA_OE_END ,Adjusts the ending point of the DQ pad output enable window" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PHY05,DRAM PHY Register 05 - Data Slice 1 PHY Parameters 1"
|
|
bitfld.long 0x04 28.--31. " TSEL_START ,Defines the on-chip pad ODT enable time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " TSEL_END ,Defines the on-chip pad ODT disable time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 23. " DQS_TSEL_EN ,Enables on-chip pad ODT for the DQS pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " POLARITY ,Controls the polarity of the tsel signal for the DQS and DM pads" "Negative,Positive"
|
|
bitfld.long 0x04 21. " LPBK_ERR_CHECK ,Triggers a data return to the memory controller" "No action,Data return"
|
|
bitfld.long 0x04 20. " LPBK_FAIL_SEL ,Selects data output type for den_phy_obs_reg_0_X [23:8]" "Return expected data,Return actual data"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LPBK_CTRL ,Loopback control" "Normal mode,lpbk_start,lpbk_stop,clear"
|
|
bitfld.long 0x04 17. " LPBK_INTERNAL ,Controls the loopback read multiplexer" "External,Internal"
|
|
bitfld.long 0x04 16. " LPBK_EN ,Controls the internal write multiplexer" "Normal operation,Loopback enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " LPBK_ERR_DELAY ,Sets the cycle delay between the LFSR and loopback error check logic" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 6.--8. " GATE_ERR_DELAY ,Defines the number of cycles of margin allowed for the final DQS falling edge of a read burst" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--5. " GATE_CLOSE_CFG ,DQS gate closing time extension" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " GATE_CFG ,Coarse adjust of gate open time" "0,1,2,3,4,5,6,7"
|
|
group.long 0x218++0x07
|
|
line.long 0x00 "PHY06,DRAM PHY Register 06 - Data Slice 2 PHY Parameters 0"
|
|
bitfld.long 0x00 31. " DM_TSEL_EN ,Enables on-chip pad ODT for the DM pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DQ_TSEL_EN ,Enables on-chip pad ODT for the DQ pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DQS_RATIO ,Controls on-chip pad ODT for the DM pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ECHO_GATE_EN ,Echo gate control for data slice X" "dfi_rddata_en used,echo_gate created"
|
|
bitfld.long 0x00 24.--26. " RD_DLY_SEL ,Defines the read data delay" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PAD_OE_POLARITY ,Sets the pad output enable polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENABLE_HALF_CAS ,Subtracts 1/2 cycle from the DQS gate value programmed into phy_ctrl_reg_1_X [2:0] by 1/2 cycle" "Not adjusted,Adjusted"
|
|
bitfld.long 0x00 12.--15. " DQS_OE_START ,Adjusts the starting point of the DQS pad output enable window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DQS_OE_END ,Adjusts the ending point of the DQS pad output enable window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DATA_OE_START ,Adjusts the starting point of the DQ pad output enable window" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DATA_OE_END ,Adjusts the ending point of the DQ pad output enable window" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PHY07,DRAM PHY Register 07 - Data Slice 2 PHY Parameters 1"
|
|
bitfld.long 0x04 28.--31. " TSEL_START ,Defines the on-chip pad ODT enable time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " TSEL_END ,Defines the on-chip pad ODT disable time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 23. " DQS_TSEL_EN ,Enables on-chip pad ODT for the DQS pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " POLARITY ,Controls the polarity of the tsel signal for the DQS and DM pads" "Negative,Positive"
|
|
bitfld.long 0x04 21. " LPBK_ERR_CHECK ,Triggers a data return to the memory controller" "No action,Data return"
|
|
bitfld.long 0x04 20. " LPBK_FAIL_SEL ,Selects data output type for den_phy_obs_reg_0_X [23:8]" "Return expected data,Return actual data"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LPBK_CTRL ,Loopback control" "Normal mode,lpbk_start,lpbk_stop,clear"
|
|
bitfld.long 0x04 17. " LPBK_INTERNAL ,Controls the loopback read multiplexer" "External,Internal"
|
|
bitfld.long 0x04 16. " LPBK_EN ,Controls the internal write multiplexer" "Normal operation,Loopback enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " LPBK_ERR_DELAY ,Sets the cycle delay between the LFSR and loopback error check logic" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 6.--8. " GATE_ERR_DELAY ,Defines the number of cycles of margin allowed for the final DQS falling edge of a read burst" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--5. " GATE_CLOSE_CFG ,DQS gate closing time extension" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " GATE_CFG ,Coarse adjust of gate open time" "0,1,2,3,4,5,6,7"
|
|
group.long 0x220++0x07
|
|
line.long 0x00 "PHY08,DRAM PHY Register 08 - Data Slice 3 PHY Parameters 0"
|
|
bitfld.long 0x00 31. " DM_TSEL_EN ,Enables on-chip pad ODT for the DM pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DQ_TSEL_EN ,Enables on-chip pad ODT for the DQ pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DQS_RATIO ,Controls on-chip pad ODT for the DM pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ECHO_GATE_EN ,Echo gate control for data slice X" "dfi_rddata_en used,echo_gate created"
|
|
bitfld.long 0x00 24.--26. " RD_DLY_SEL ,Defines the read data delay" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PAD_OE_POLARITY ,Sets the pad output enable polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENABLE_HALF_CAS ,Subtracts 1/2 cycle from the DQS gate value programmed into phy_ctrl_reg_1_X [2:0] by 1/2 cycle" "Not adjusted,Adjusted"
|
|
bitfld.long 0x00 12.--15. " DQS_OE_START ,Adjusts the starting point of the DQS pad output enable window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DQS_OE_END ,Adjusts the ending point of the DQS pad output enable window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DATA_OE_START ,Adjusts the starting point of the DQ pad output enable window" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DATA_OE_END ,Adjusts the ending point of the DQ pad output enable window" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PHY09,DRAM PHY Register 09 - Data Slice 3 PHY Parameters 1"
|
|
bitfld.long 0x04 28.--31. " TSEL_START ,Defines the on-chip pad ODT enable time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " TSEL_END ,Defines the on-chip pad ODT disable time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 23. " DQS_TSEL_EN ,Enables on-chip pad ODT for the DQS pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " POLARITY ,Controls the polarity of the tsel signal for the DQS and DM pads" "Negative,Positive"
|
|
bitfld.long 0x04 21. " LPBK_ERR_CHECK ,Triggers a data return to the memory controller" "No action,Data return"
|
|
bitfld.long 0x04 20. " LPBK_FAIL_SEL ,Selects data output type for den_phy_obs_reg_0_X [23:8]" "Return expected data,Return actual data"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LPBK_CTRL ,Loopback control" "Normal mode,lpbk_start,lpbk_stop,clear"
|
|
bitfld.long 0x04 17. " LPBK_INTERNAL ,Controls the loopback read multiplexer" "External,Internal"
|
|
bitfld.long 0x04 16. " LPBK_EN ,Controls the internal write multiplexer" "Normal operation,Loopback enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " LPBK_ERR_DELAY ,Sets the cycle delay between the LFSR and loopback error check logic" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 6.--8. " GATE_ERR_DELAY ,Defines the number of cycles of margin allowed for the final DQS falling edge of a read burst" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--5. " GATE_CLOSE_CFG ,DQS gate closing time extension" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " GATE_CFG ,Coarse adjust of gate open time" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "PHY10 - PHY 19 Registers"
|
|
group.long 0x228++0x07
|
|
line.long 0x00 "PHY10,DRAM PHY Register 10 - Data Slice CA PHY Parameters 0"
|
|
bitfld.long 0x00 31. " DM_TSEL_EN ,Enables on-chip pad ODT for the DM pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DQ_TSEL_EN ,Enables on-chip pad ODT for the DQ pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DQS_RATIO ,Controls on-chip pad ODT for the DM pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ECHO_GATE_EN ,Echo gate control for data slice X" "dfi_rddata_en used,echo_gate created"
|
|
bitfld.long 0x00 24.--26. " RD_DLY_SEL ,Defines the read data delay" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PAD_OE_POLARITY ,Sets the pad output enable polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENABLE_HALF_CAS ,Subtracts 1/2 cycle from the DQS gate value programmed into phy_ctrl_reg_1_X [2:0] by 1/2 cycle" "Not adjusted,Adjusted"
|
|
bitfld.long 0x00 12.--15. " DQS_OE_START ,Adjusts the starting point of the DQS pad output enable window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DQS_OE_END ,Adjusts the ending point of the DQS pad output enable window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DATA_OE_START ,Adjusts the starting point of the DQ pad output enable window" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DATA_OE_END ,Adjusts the ending point of the DQ pad output enable window" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PHY11,DRAM PHY Register 11 - Data Slice CA PHY Parameters 1"
|
|
bitfld.long 0x04 28.--31. " TSEL_START ,Defines the on-chip pad ODT enable time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " TSEL_END ,Defines the on-chip pad ODT disable time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 23. " DQS_TSEL_EN ,Enables on-chip pad ODT for the DQS pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " POLARITY ,Controls the polarity of the tsel signal for the DQS and DM pads" "Negative,Positive"
|
|
bitfld.long 0x04 21. " LPBK_ERR_CHECK ,Triggers a data return to the memory controller" "No action,Data return"
|
|
bitfld.long 0x04 20. " LPBK_FAIL_SEL ,Selects data output type for den_phy_obs_reg_0_X [23:8]" "Return expected data,Return actual data"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " LPBK_CTRL ,Loopback control" "Normal mode,lpbk_start,lpbk_stop,clear"
|
|
bitfld.long 0x04 17. " LPBK_INTERNAL ,Controls the loopback read multiplexer" "External,Internal"
|
|
bitfld.long 0x04 16. " LPBK_EN ,Controls the internal write multiplexer" "Normal operation,Loopback enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " LPBK_ERR_DELAY ,Sets the cycle delay between the LFSR and loopback error check logic" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 6.--8. " GATE_ERR_DELAY ,Defines the number of cycles of margin allowed for the final DQS falling edge of a read burst" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--5. " GATE_CLOSE_CFG ,DQS gate closing time extension" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " GATE_CFG ,Coarse adjust of gate open time" "0,1,2,3,4,5,6,7"
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "PHY12,DRAM PHY Register 12 - Reserved"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "PHY13,DRAM PHY Register 13"
|
|
bitfld.long 0x00 23. " DFI_MOBILE_EN ,DFI control for Mobile ddr devices" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DDR_SEL ,Controls the PHY memory system mode" "non-LPDDR2,LPDDR2"
|
|
bitfld.long 0x00 5. " LPBK_RD_EN ,Loopback Read Data Mode Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LPBK_WR_EN ,Loopback Write Data Mode Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DFI_RDDATA_VALID ,Sets the dfi_rddata_valid delay relative to dfi_rddata_en" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x238++0x07
|
|
line.long 0x00 "PHY14,DRAM PHY Register 14"
|
|
bitfld.long 0x00 29.--31. " PHASE_DETECT_SEL ,DLL Phase Detect Selector for the master delay line" "1 element,2 elements,3 elements,4 elements,5 elements,6 elements,7 elements,8 elements"
|
|
bitfld.long 0x00 28. " DLL_BYPASS_MODE ,DLL bypass mode control" "Normal mode,Bypass mode"
|
|
hexmask.long.word 0x00 15.--23. 1. " DLL_RD_DELAY_BYPASS ,Holds the read DQS delay for bypass mode"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " DLL_RD_DELAY ,Holds the read DQS delay for normal mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL_START_POINT ,This value is loaded into the DLL at initialization and is the value at which the DLL will begin searching for a lock"
|
|
line.long 0x04 "PHY15,DRAM PHY Register 15"
|
|
hexmask.long.word 0x04 15.--23. 1. " DLL_WR_DELAY_BYPASS ,Holds the clk_wr delay setting when the DLL is operating in bypass mode"
|
|
hexmask.long.byte 0x04 8.--14. 1. " DLL_WR_DELAY ,Holds the clk_wr delay setting in normal mode"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLL_INCR ,DLL Increment Value"
|
|
group.long 0x240++0x07
|
|
line.long 0x00 "PHY16,DRAM PHY Register 16"
|
|
bitfld.long 0x00 29.--31. " PHASE_DETECT_SEL ,DLL Phase Detect Selector for the master delay line" "1 element,2 elements,3 elements,4 elements,5 elements,6 elements,7 elements,8 elements"
|
|
bitfld.long 0x00 28. " DLL_BYPASS_MODE ,DLL bypass mode control" "Normal mode,Bypass mode"
|
|
hexmask.long.word 0x00 15.--23. 1. " DLL_RD_DELAY_BYPASS ,Holds the read DQS delay for bypass mode"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " DLL_RD_DELAY ,Holds the read DQS delay for normal mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL_START_POINT ,This value is loaded into the DLL at initialization and is the value at which the DLL will begin searching for a lock"
|
|
line.long 0x04 "PHY17,DRAM PHY Register 17"
|
|
hexmask.long.word 0x04 15.--23. 1. " DLL_WR_DELAY_BYPASS ,Holds the clk_wr delay setting when the DLL is operating in bypass mode"
|
|
hexmask.long.byte 0x04 8.--14. 1. " DLL_WR_DELAY ,Holds the clk_wr delay setting in normal mode"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLL_INCR ,DLL Increment Value"
|
|
group.long 0x248++0x07
|
|
line.long 0x00 "PHY18,DRAM PHY Register 18"
|
|
bitfld.long 0x00 29.--31. " PHASE_DETECT_SEL ,DLL Phase Detect Selector for the master delay line" "1 element,2 elements,3 elements,4 elements,5 elements,6 elements,7 elements,8 elements"
|
|
bitfld.long 0x00 28. " DLL_BYPASS_MODE ,DLL bypass mode control" "Normal mode,Bypass mode"
|
|
hexmask.long.word 0x00 15.--23. 1. " DLL_RD_DELAY_BYPASS ,Holds the read DQS delay for bypass mode"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " DLL_RD_DELAY ,Holds the read DQS delay for normal mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL_START_POINT ,This value is loaded into the DLL at initialization and is the value at which the DLL will begin searching for a lock"
|
|
line.long 0x04 "PHY19,DRAM PHY Register 19"
|
|
hexmask.long.word 0x04 15.--23. 1. " DLL_WR_DELAY_BYPASS ,Holds the clk_wr delay setting when the DLL is operating in bypass mode"
|
|
hexmask.long.byte 0x04 8.--14. 1. " DLL_WR_DELAY ,Holds the clk_wr delay setting in normal mode"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLL_INCR ,DLL Increment Value"
|
|
tree.end
|
|
tree "PHY20 - PHY29 Registers"
|
|
group.long 0x250++0x07
|
|
line.long 0x00 "PHY20,DRAM PHY Register 20"
|
|
bitfld.long 0x00 29.--31. " PHASE_DETECT_SEL ,DLL Phase Detect Selector for the master delay line" "1 element,2 elements,3 elements,4 elements,5 elements,6 elements,7 elements,8 elements"
|
|
bitfld.long 0x00 28. " DLL_BYPASS_MODE ,DLL bypass mode control" "Normal mode,Bypass mode"
|
|
hexmask.long.word 0x00 15.--23. 1. " DLL_RD_DELAY_BYPASS ,Holds the read DQS delay for bypass mode"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " DLL_RD_DELAY ,Holds the read DQS delay for normal mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL_START_POINT ,This value is loaded into the DLL at initialization and is the value at which the DLL will begin searching for a lock"
|
|
line.long 0x04 "PHY21,DRAM PHY Register 21"
|
|
hexmask.long.word 0x04 15.--23. 1. " DLL_WR_DELAY_BYPASS ,Holds the clk_wr delay setting when the DLL is operating in bypass mode"
|
|
hexmask.long.byte 0x04 8.--14. 1. " DLL_WR_DELAY ,Holds the clk_wr delay setting in normal mode"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLL_INCR ,DLL Increment Value"
|
|
group.long 0x258++0x07
|
|
line.long 0x00 "PHY22,DRAM PHY Register 22"
|
|
bitfld.long 0x00 29.--31. " PHASE_DETECT_SEL ,DLL Phase Detect Selector for the master delay line" "1 element,2 elements,3 elements,4 elements,5 elements,6 elements,7 elements,8 elements"
|
|
bitfld.long 0x00 28. " DLL_BYPASS_MODE ,DLL bypass mode control" "Normal mode,Bypass mode"
|
|
hexmask.long.word 0x00 15.--23. 1. " DLL_RD_DELAY_BYPASS ,Holds the read DQS delay for bypass mode"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " DLL_RD_DELAY ,Holds the read DQS delay for normal mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL_START_POINT ,This value is loaded into the DLL at initialization and is the value at which the DLL will begin searching for a lock"
|
|
line.long 0x04 "PHY23,DRAM PHY Register 23"
|
|
hexmask.long.word 0x04 15.--23. 1. " DLL_WR_DELAY_BYPASS ,Holds the clk_wr delay setting when the DLL is operating in bypass mode"
|
|
hexmask.long.byte 0x04 8.--14. 1. " DLL_WR_DELAY ,Holds the clk_wr delay setting in normal mode"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLL_INCR ,DLL Increment Value"
|
|
rgroup.long 0x260++0x0B
|
|
line.long 0x00 "PHY24,DRAM PHY Register 24"
|
|
bitfld.long 0x00 24. " LPBK_ERR_OUT ,Status signal to indicate that the logic gate had to be forced closed" "Not occurred,Occurred"
|
|
hexmask.long.word 0x00 8.--23. 1. " LPBK_DQ_DATA ,Reports the actual data or expected data, depending on the setting of the den_phy_ctrl_reg_1_X[20] parameter bit"
|
|
bitfld.long 0x00 4.--7. " LPBK_DM_DATAT ,Reports the actual data mask or the expected data mask, depending on the setting of the den_phy_ctrl_reg_1_X[20] parameter bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBK_STATUS ,Reports status of loopback errors" "No error,Error"
|
|
bitfld.long 0x00 0. " LPBK_START ,Defines the status of the loopback mode" "Disabled,Enabled"
|
|
line.long 0x04 "PHY25,DRAM PHY Register 25"
|
|
hexmask.long 0x04 1.--31. 1. " DLL_LOCK_VAL ,Reports the DLL encoder value from the master DLL to the slave DLLs"
|
|
bitfld.long 0x04 0. " DLL_LOCK ,Indicates status of the DLL" "Not locked,Locked"
|
|
line.long 0x08 "PHY26,DRAM PHY Register 26"
|
|
hexmask.long.byte 0x08 15.--22. 1. " WR_DELAY_VAL ,Holds the encoded value for the clk_wr delay line for this slice"
|
|
hexmask.long.byte 0x08 0.--7. 1. " RD_DELAY_VAL ,Holds the encoded value for the read delay line for this slice"
|
|
rgroup.long 0x26C++0x0B
|
|
line.long 0x00 "PHY27,DRAM PHY Register 27"
|
|
bitfld.long 0x00 24. " LPBK_ERR_OUT ,Status signal to indicate that the logic gate had to be forced closed" "Not occurred,Occurred"
|
|
hexmask.long.word 0x00 8.--23. 1. " LPBK_DQ_DATA ,Reports the actual data or expected data, depending on the setting of the den_phy_ctrl_reg_1_X[20] parameter bit"
|
|
bitfld.long 0x00 4.--7. " LPBK_DM_DATAT ,Reports the actual data mask or the expected data mask, depending on the setting of the den_phy_ctrl_reg_1_X[20] parameter bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBK_STATUS ,Reports status of loopback errors" "No error,Error"
|
|
bitfld.long 0x00 0. " LPBK_START ,Defines the status of the loopback mode" "Disabled,Enabled"
|
|
line.long 0x04 "PHY28,DRAM PHY Register 28"
|
|
hexmask.long 0x04 1.--31. 1. " DLL_LOCK_VAL ,Reports the DLL encoder value from the master DLL to the slave DLLs"
|
|
bitfld.long 0x04 0. " DLL_LOCK ,Indicates status of the DLL" "Not locked,Locked"
|
|
line.long 0x08 "PHY29,DRAM PHY Register 29"
|
|
hexmask.long.byte 0x08 15.--22. 1. " WR_DELAY_VAL ,Holds the encoded value for the clk_wr delay line for this slice"
|
|
hexmask.long.byte 0x08 0.--7. 1. " RD_DELAY_VAL ,Holds the encoded value for the read delay line for this slice"
|
|
tree.end
|
|
tree "PHY30 - PHY38 Registers"
|
|
rgroup.long 0x278++0x0B
|
|
line.long 0x00 "PHY30,DRAM PHY Register 30"
|
|
bitfld.long 0x00 24. " LPBK_ERR_OUT ,Status signal to indicate that the logic gate had to be forced closed" "Not occurred,Occurred"
|
|
hexmask.long.word 0x00 8.--23. 1. " LPBK_DQ_DATA ,Reports the actual data or expected data, depending on the setting of the den_phy_ctrl_reg_1_X[20] parameter bit"
|
|
bitfld.long 0x00 4.--7. " LPBK_DM_DATAT ,Reports the actual data mask or the expected data mask, depending on the setting of the den_phy_ctrl_reg_1_X[20] parameter bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBK_STATUS ,Reports status of loopback errors" "No error,Error"
|
|
bitfld.long 0x00 0. " LPBK_START ,Defines the status of the loopback mode" "Disabled,Enabled"
|
|
line.long 0x04 "PHY31,DRAM PHY Register 31"
|
|
hexmask.long 0x04 1.--31. 1. " DLL_LOCK_VAL ,Reports the DLL encoder value from the master DLL to the slave DLLs"
|
|
bitfld.long 0x04 0. " DLL_LOCK ,Indicates status of the DLL" "Not locked,Locked"
|
|
line.long 0x08 "PHY32,DRAM PHY Register 32"
|
|
hexmask.long.byte 0x08 15.--22. 1. " WR_DELAY_VAL ,Holds the encoded value for the clk_wr delay line for this slice"
|
|
hexmask.long.byte 0x08 0.--7. 1. " RD_DELAY_VAL ,Holds the encoded value for the read delay line for this slice"
|
|
rgroup.long 0x284++0x0B
|
|
line.long 0x00 "PHY33,DRAM PHY Register 33"
|
|
bitfld.long 0x00 24. " LPBK_ERR_OUT ,Status signal to indicate that the logic gate had to be forced closed" "Not occurred,Occurred"
|
|
hexmask.long.word 0x00 8.--23. 1. " LPBK_DQ_DATA ,Reports the actual data or expected data, depending on the setting of the den_phy_ctrl_reg_1_X[20] parameter bit"
|
|
bitfld.long 0x00 4.--7. " LPBK_DM_DATAT ,Reports the actual data mask or the expected data mask, depending on the setting of the den_phy_ctrl_reg_1_X[20] parameter bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBK_STATUS ,Reports status of loopback errors" "No error,Error"
|
|
bitfld.long 0x00 0. " LPBK_START ,Defines the status of the loopback mode" "Disabled,Enabled"
|
|
line.long 0x04 "PHY34,DRAM PHY Register 34"
|
|
hexmask.long 0x04 1.--31. 1. " DLL_LOCK_VAL ,Reports the DLL encoder value from the master DLL to the slave DLLs"
|
|
bitfld.long 0x04 0. " DLL_LOCK ,Indicates status of the DLL" "Not locked,Locked"
|
|
line.long 0x08 "PHY35,DRAM PHY Register 35"
|
|
hexmask.long.byte 0x08 15.--22. 1. " WR_DELAY_VAL ,Holds the encoded value for the clk_wr delay line for this slice"
|
|
hexmask.long.byte 0x08 0.--7. 1. " RD_DELAY_VAL ,Holds the encoded value for the read delay line for this slice"
|
|
rgroup.long 0x290++0x0B
|
|
line.long 0x00 "PHY36,DRAM PHY Register 36"
|
|
bitfld.long 0x00 24. " LPBK_ERR_OUT ,Status signal to indicate that the logic gate had to be forced closed" "Not occurred,Occurred"
|
|
hexmask.long.word 0x00 8.--23. 1. " LPBK_DQ_DATA ,Reports the actual data or expected data, depending on the setting of the den_phy_ctrl_reg_1_X[20] parameter bit"
|
|
bitfld.long 0x00 4.--7. " LPBK_DM_DATAT ,Reports the actual data mask or the expected data mask, depending on the setting of the den_phy_ctrl_reg_1_X[20] parameter bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBK_STATUS ,Reports status of loopback errors" "No error,Error"
|
|
bitfld.long 0x00 0. " LPBK_START ,Defines the status of the loopback mode" "Disabled,Enabled"
|
|
line.long 0x04 "PHY37,DRAM PHY Register 37"
|
|
hexmask.long 0x04 1.--31. 1. " DLL_LOCK_VAL ,Reports the DLL encoder value from the master DLL to the slave DLLs"
|
|
bitfld.long 0x04 0. " DLL_LOCK ,Indicates status of the DLL" "Not locked,Locked"
|
|
line.long 0x08 "PHY38,DRAM PHY Register 38"
|
|
hexmask.long.byte 0x08 15.--22. 1. " WR_DELAY_VAL ,Holds the encoded value for the clk_wr delay line for this slice"
|
|
hexmask.long.byte 0x08 0.--7. 1. " RD_DELAY_VAL ,Holds the encoded value for the read delay line for this slice"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "DVFSC (Dynamic Voltage Frequency Scaling)"
|
|
base ad:0x53fdC17F
|
|
width 12.
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "DVFSTHRS,DVFSTHRS Register"
|
|
hexmask.long.byte 0x00 22.--27. 1. " UPTHR ,Upper treshold for load tracking"
|
|
hexmask.long.byte 0x00 16.--21. 1. " DWTHR ,Down treshold for load tracking"
|
|
hexmask.long.byte 0x00 0.--5. 1. " PNCTHR ,Panic treshold for load tracking"
|
|
line.long 0x04 "DVFSCOUN,DVFSCOUN Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DNCNT ,Down counter threshold value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " UPCNT ,UP counter threshold value"
|
|
line.long 0x08 "DVFSSIG1,DVFSSIG1 Register"
|
|
bitfld.long 0x08 29.--31. " WSW15 ,General purpose load tracking signal weight dvfs_w_sig[15]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 26.--28. " WSW14 ,General purpose load tracking signal weight dvfs_w_sig[14]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 23.--25. " WSW13 ,General purpose load tracking signal weight dvfs_w_sig[13]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 20.--22. " WSW12 ,General purpose load tracking signal weight dvfs_w_sig[12]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 17.--19. " WSW11 ,General purpose load tracking signal weight dvfs_w_sig[11]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 14.--16. " WSW10 ,General purpose load tracking signal weight dvfs_w_sig[10]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 11.--13. " WSW9 ,General purpose load tracking signal weight dvfs_w_sig[9]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " WSW8 ,General purpose load tracking signal weight dvfs_w_sig[8]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " WSW7 ,General purpose load tracking signal weight dvfs_w_sig[7]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 2.--4. " WSW6 ,General purpose load tracking signal weight dvfs_w_sig[6]" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0c "DVFSSIG0,DVFSSIG0 Register"
|
|
bitfld.long 0x0C 29.--31. " WSW5 ,General purpose load tracking signal weight dvfs_w_sig[5]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 26.--28. " WSW4 ,General purpose load tracking signal weight dvfs_w_sig[4]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 23.--25. " WSW3 ,General purpose load tracking signal weight dvfs_w_sig[3]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 20.--22. " WSW2 ,General purpose load tracking signal weight dvfs_w_sig[2]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--11. " WSW1 ,General purpose load tracking signal weight dvfs_w_sig[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 0.--5. " WSW0 ,General purpose load tracking signal weight dvfs_w_sig[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DVFSGPC0,DVFSGPC0 Register"
|
|
bitfld.long 0x10 31. " C0STRT ,Counter 0 start" "Not started,Started"
|
|
rbitfld.long 0x10 30. " C0ACT ,Counter 0 active indicator" "Reached,Not reached"
|
|
hexmask.long.tbyte 0x10 0.--16. 1. " GPBC0 ,General Purpose bits Counter 0"
|
|
line.long 0x14 "DVFSGPC1,DVFSGPC1 Register"
|
|
bitfld.long 0x14 31. " C1STRT ,Counter 1start" "Not started,Started"
|
|
rbitfld.long 0x14 30. " C1ACT ,Counter 1 active indicator" "Reached,Not reached"
|
|
hexmask.long.tbyte 0x14 0.--16. 1. " GPBC1 ,General Purpose bits Counter 1"
|
|
line.long 0x18 "DVFSGPBT,DVFSGPBT Register"
|
|
bitfld.long 0x18 15. " GPB15 ,General purpose bit 15" "Low,High"
|
|
bitfld.long 0x18 14. " GPB14 ,General purpose bit 14" "Low,High"
|
|
bitfld.long 0x18 13. " GPB13 ,General purpose bit 13" "Low,High"
|
|
bitfld.long 0x18 12. " GPB12 ,General purpose bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 11. " GPB11 ,General purpose bit 11" "Low,High"
|
|
bitfld.long 0x18 10. " GPB10 ,General purpose bit 10" "Low,High"
|
|
bitfld.long 0x18 9. " GPB09 ,General purpose bit 9" "Low,High"
|
|
bitfld.long 0x18 8. " GPB08 ,General purpose bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 7. " GPB07 ,General purpose bit 7" "Low,High"
|
|
bitfld.long 0x18 6. " GPB06 ,General purpose bit 6" "Low,High"
|
|
bitfld.long 0x18 5. " GPB05 ,General purpose bit 5" "Low,High"
|
|
bitfld.long 0x18 4. " GPB04 ,General purpose bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 3. " GPB03 ,General purpose bit 3" "Low,High"
|
|
bitfld.long 0x18 2. " GPB02 ,General purpose bit 2" "Low,High"
|
|
bitfld.long 0x18 1. " GPB01 ,General purpose bit 1" "Low,High"
|
|
bitfld.long 0x18 0. " GPB00 ,General purpose bit 0" "Low,High"
|
|
line.long 0x1c "DVFSEMAC,DVFSEMAC Register"
|
|
sif (cpuis("IMX6*"))
|
|
sif (cpu()!="IMX6SOLO"&&cpu()!="IMX6SOLOLITE"&&cpu()!="IMX6DUALLITE")
|
|
bitfld.long 0x1C 27. " WFIM3 ,DVFS Wait for Interrupt of core 3 mask" "Not masked,Masked"
|
|
bitfld.long 0x1C 26. " WFIM2 ,DVFS Wait for Interrupt of core 2 mask" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x1C 25. " WFIM1 ,DVFS Wait for Interrupt of core 1 mask" "Not masked,Masked"
|
|
bitfld.long 0x1C 24. " WFIM0 ,DVFS Wait for Interrupt of core 0 mask" "Not masked,Masked"
|
|
else
|
|
bitfld.long 0x1C 24. " WFIM0 ,DVFS Wait for Interrupt of core 0 mask" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLO"&&cpu()!="IMX6SOLOLITE"&&cpu()!="IMX6DUALLITE")
|
|
rbitfld.long 0x1C 22.--23. " FSVAI3 ,DVFS Frequency adjustment status of core 3" "Not changed,Increased,Decreased,Increased immediately"
|
|
rbitfld.long 0x1C 20.--21. " FSVAI2 ,DVFS Frequency adjustment status of core 2" "Not changed,Increased,Decreased,Increased immediately"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
rbitfld.long 0x1C 18.--19. " FSVAI1 ,DVFS Frequency adjustment status of core 1" "Not changed,Increased,Decreased,Increased immediately"
|
|
rbitfld.long 0x1C 16.--17. " FSVAI0 ,DVFS Frequency adjustment status of core 0" "Not changed,Increased,Decreased,Increased immediately"
|
|
else
|
|
rbitfld.long 0x1C 16.--17. " FSVAI0 ,DVFS Frequency adjustment status of core 0" "Not changed,Increased,Decreased,Increased immediately"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLO"&&cpu()!="IMX6SOLOLITE"&&cpu()!="IMX6DUALLITE")
|
|
bitfld.long 0x1C 12. " DVFEN3 ,DVFS tracking for core3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " DVFEN2 ,DVFS tracking for core2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x1C 10. " DVFEN1 ,DVFS tracking for core1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " DVFEN0 ,DVFS tracking for core0 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x1C 9. " DVFEN0 ,DVFS tracking for core0 enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x1c 0.--8. 1. " EMAC ,EMA control value"
|
|
line.long 0x20 "DVFSCNTR,DVFS Register"
|
|
bitfld.long 0x20 29.--31. " DIV3CK ,Div_3_clk division ratio inside the DVFS module" "1,4,16,64,256,1024,?..."
|
|
bitfld.long 0x20 28. " DVFEV ,DVFS event" "Not given,Given"
|
|
bitfld.long 0x20 27. " LBMI ,Load buffer full mask interrupt" "Not masked,Masked"
|
|
eventfld.long 0x20 26. " LBFL1 ,Load buffer 1" "Not full,Full"
|
|
textline " "
|
|
eventfld.long 0x20 25. " LBFL0 ,Load buffer 0" "Not full,Full"
|
|
bitfld.long 0x20 24. " DVFIS ,DVFS Interrupt select" "SDMA,MCU"
|
|
eventfld.long 0x20 23. " PIRQS ,Pattern IRQ Sourse" "No pattern,Pattern"
|
|
bitfld.long 0x20 22. " FSVAIM ,DVFS Frequency adjustment interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
rbitfld.long 0x20 20.--21. " FSVAI ,DVFS Frequency adjustment interrupt" "No interrupt,Increased,Decreased,Increased immediately"
|
|
textline " "
|
|
sif (!cpuis("IMX6*"))
|
|
bitfld.long 0x20 19. " WFIM ,DVFS Wait for Interrupt mask bit" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 18. " MAXF ,Maximum frequency reached" "Not reached,Reached"
|
|
bitfld.long 0x20 17. " MINF ,Minimum frequency reached" "Not reached,Reached"
|
|
bitfld.long 0x20 11.--16. " DIV_RATO ,Divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x20 9. " PFUE ,Period Frequency Update Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x20 6.--8. " PFUS ,Periodic Frequency Update Status" "No update,,,,DVFSPT0,DVFSPT1,DVFSPT2,DVFSPT3"
|
|
bitfld.long 0x20 5. " LTBRSH ,Load Tracking Buffer Register Shift" "[5:2] value,[4:1] value"
|
|
bitfld.long 0x20 3.--4. " LTBRSR ,Load Tracking Buffer Register Source" "Pre_ld_add,Ld_add,After ema,?..."
|
|
sif (!cpuis("IMX6*"))
|
|
textline " "
|
|
bitfld.long 0x20 0. " DVFEN ,DVFS enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x24++0x0f
|
|
line.long 0x00 "DVFSLTR0_0,DVFSLTR0_0 Register"
|
|
bitfld.long 0x00 28.--31. " LTS0_7 ,Load Tracking Sample 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " LTS0_6 ,Load Tracking Sample 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " LTS0_5 ,Load Tracking Sample 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " LTS0_4 ,Load Tracking Sample 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " LTS0_3 ,Load Tracking Sample 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " LTS0_2 ,Load Tracking Sample 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " LTS0_1 ,Load Tracking Sample 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LTS0_0 ,Load Tracking Sample 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "DVFSLTR0_1,DVFSLTR0_1 Register"
|
|
bitfld.long 0x04 28.--31. " LTS0_15 ,Load Tracking Sample 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " LTS0_14 ,Load Tracking Sample 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. " LTS0_13 ,Load Tracking Sample 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " LTS0_12 ,Load Tracking Sample 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " LTS0_11 ,Load Tracking Sample 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " LTS0_10 ,Load Tracking Sample 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " LTS0_9 ,Load Tracking Sample 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " LTS0_8 ,Load Tracking Sample 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "DVFSLTR1_0,DVFSLTR1_0 Register"
|
|
bitfld.long 0x08 28.--31. " LTS1_7 ,Load Tracking Sample 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " LTS1_6 ,Load Tracking Sample 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 20.--23. " LTS1_5 ,Load Tracking Sample 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. " LTS1_4 ,Load Tracking Sample 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " LTS1_3 ,Load Tracking Sample 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " LTS1_2 ,Load Tracking Sample 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 4.--7. " LTS1_1 ,Load Tracking Sample 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " LTS1_0 ,Load Tracking Sample 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0c "DVFSLTR1_1,DVFSLTR1_1 Register"
|
|
bitfld.long 0x0c 28.--31. " LTS1_15 ,Load Tracking Sample 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 24.--27. " LTS1_14 ,Load Tracking Sample 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 20.--23. " LTS1_13 ,Load Tracking Sample 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " LTS1_12 ,Load Tracking Sample 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12.--15. " LTS1_11 ,Load Tracking Sample 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 8.--11. " LTS1_10 ,Load Tracking Sample 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 4.--7. " LTS1_9 ,Load Tracking Sample 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " LTS1_8 ,Load Tracking Sample 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x0f
|
|
line.long 0x00 "DVFSPT0,DVFSPT0 Register"
|
|
rbitfld.long 0x00 17. " PT0A ,Pattern 0 currently active" "Not active,Active"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " FPTN0 ,Frequency pattern 0 counter"
|
|
line.long 0x04 "DVFSPT1,DVFSPT1 Register"
|
|
rbitfld.long 0x04 17. " PT1A ,Pattern 1 currently active" "Not active,Active"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " FPTN1 ,Frequency pattern 1 counter"
|
|
line.long 0x08 "DVFSPT2,DVFSPT2 Register"
|
|
bitfld.long 0x08 26.--31. " P2THR ,Pattern 2 Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x08 17. " PT2A ,Pattern 2 currently active" "Not active,Active"
|
|
hexmask.long.tbyte 0x08 0.--16. 1. " FPTN2 ,Frequency pattern 2 counter"
|
|
line.long 0x0c "DVFSPT3,DVFSPT3 Register"
|
|
rbitfld.long 0x0C 17. " PT3A ,Pattern 3 currently active" "Not active,Active"
|
|
hexmask.long.tbyte 0x0C 0.--16. 1. " FPTN3 ,Frequency pattern 3 counter"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "eCSPI (Enhanced Configurable Serial Peripheral Interface)"
|
|
tree "eCSPI 1"
|
|
base ad:0x50010000
|
|
width 15.
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RXDATA1,Receive Data Register 1"
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "RXDATA1,Receive Data Register 1"
|
|
in
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "TXDATA1,Transmit Data Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " TXDATA ,Transmit Data"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONTROLEG1,Control Register 1"
|
|
hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst Length"
|
|
bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI Channel Select" "0,1,2,3"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,/RSV"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHANNEL_MODE[3] ,Mode of each SPI channel 3" "Slave,Master"
|
|
bitfld.long 0x00 6. " CHANNEL_MODE[2] ,Mode of each SPI channel 2" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHANNEL_MODE[1] ,Mode of each SPI channel 1" "Slave,Master"
|
|
bitfld.long 0x00 4. " CHANNEL_MODE[0] ,Mode of each SPI channel 0" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMC ,Start Mode Control" "Normal,Automatic"
|
|
bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Exchanged/Busy"
|
|
textline " "
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 1. " HW ,HW Trigger Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 0. " EN ,SPI Module Enable Control" "Disabled,Enabled"
|
|
if (((per.l(ad:0x50010000+0x08))&0xf0)==0x00)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0x20)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0x30)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0x40)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0x50)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0x60)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0x70)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0x80)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0x90)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0xa0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0xb0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0xc0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0xd0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x50010000+0x08))&0xf0)==0xe0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
else
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "INTREG1,Interrupt Control Register 1"
|
|
bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMAREG1,DMA Control Register 1"
|
|
bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x04 24.--26. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x04 16.--21. " RX_THRESHOLD ,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--5. " TX_THRESHOLD ,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x04 16.--21. " RX_WATER_MARK ,RX WATER MARK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TXDEN ,TXFIFO DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--5. " TX_WATER_MARK ,TX WATER MARK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((per.l(ad:0x50010000+0x14))&0x80000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "STATREG1,Status Register 1"
|
|
eventfld.long 0x00 7. " TC ,Transfer Completed" "Busy,Completed"
|
|
eventfld.long 0x00 6. " RO ,RXFIFO Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<=RX THRESHOLD,>RX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<RX DMA WATER MARK,>RX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RR ,RXFIFO Ready" "No valid data,>=1 word"
|
|
rbitfld.long 0x00 2. " TF ,TXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX THRESHOLD,<=TX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX DMA WATER MARK,<=TX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 0. " TE ,TXFIFO Empty" "Not empty,Empty"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "STATREG1,Status Register 1"
|
|
eventfld.long 0x00 7. " TC ,Transfer Completed" "Busy,Completed"
|
|
eventfld.long 0x00 6. " RO ,RXFIFO Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("iMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<=RX THRESHOLD,>RX THRESHOLD/DMA TAIL DMA"
|
|
else
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Full" "<RX DMA WATER MARK,>RX DMA WATER MARK/DMA TAIL DMA matched"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RR ,RXFIFO Ready" "No valid data,>=1 word"
|
|
rbitfld.long 0x00 2. " TF ,TXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX THRESHOLD,<=TX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX DMA WATER MARK,<=TX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 0. " TE ,TXFIFO Empty" "Not empty,Empty"
|
|
endif
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "PERIODREG1,Sample Period Control Register 1"
|
|
bitfld.long 0x00 16.--21. " CSD_CTRL ,Chip Select Delay Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Frequency Ref. Clock"
|
|
else
|
|
bitfld.long 0x00 15. " CSRC ,Clock Source Control" "SPI Clock,CKIL"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--14. 1. " SAMPLE_PERIOD ,Sample Period Control"
|
|
line.long 0x04 "TESTREG1,Test Control Register 1"
|
|
bitfld.long 0x04 31. " LBC ,Loop Back Control" "Not connected,Connected"
|
|
sif (!(cpuis("IMX6*"))&&cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
bitfld.long 0x04 28.--29. " CL ,Catch Latency" "Normal,Half cycle,One cycle,One & half cycle"
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " RXCNT ,RXFIFO Counter"
|
|
hexmask.long.byte 0x04 0.--6. 1. " TXCNT ,TXFIFO Counter"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "MSGDATA1,Message Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "eCSPI 2"
|
|
base ad:0x63fac000
|
|
width 15.
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RXDATA2,Receive Data Register 2"
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "RXDATA2,Receive Data Register 2"
|
|
in
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "TXDATA2,Transmit Data Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " TXDATA ,Transmit Data"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONTROLEG2,Control Register 2"
|
|
hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst Length"
|
|
bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI Channel Select" "0,1,2,3"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,/RSV"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHANNEL_MODE[3] ,Mode of each SPI channel 3" "Slave,Master"
|
|
bitfld.long 0x00 6. " CHANNEL_MODE[2] ,Mode of each SPI channel 2" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHANNEL_MODE[1] ,Mode of each SPI channel 1" "Slave,Master"
|
|
bitfld.long 0x00 4. " CHANNEL_MODE[0] ,Mode of each SPI channel 0" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMC ,Start Mode Control" "Normal,Automatic"
|
|
bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Exchanged/Busy"
|
|
textline " "
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 1. " HW ,HW Trigger Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 0. " EN ,SPI Module Enable Control" "Disabled,Enabled"
|
|
if (((per.l(ad:0x63fac000+0x08))&0xf0)==0x00)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0x20)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0x30)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0x40)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0x50)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0x60)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0x70)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0x80)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0x90)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0xa0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0xb0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0xc0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0xd0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x63fac000+0x08))&0xf0)==0xe0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
else
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "INTREG2,Interrupt Control Register 2"
|
|
bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMAREG2,DMA Control Register 2"
|
|
bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x04 24.--26. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x04 16.--21. " RX_THRESHOLD ,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--5. " TX_THRESHOLD ,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x04 16.--21. " RX_WATER_MARK ,RX WATER MARK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TXDEN ,TXFIFO DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--5. " TX_WATER_MARK ,TX WATER MARK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((per.l(ad:0x63fac000+0x14))&0x80000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "STATREG2,Status Register 2"
|
|
eventfld.long 0x00 7. " TC ,Transfer Completed" "Busy,Completed"
|
|
eventfld.long 0x00 6. " RO ,RXFIFO Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<=RX THRESHOLD,>RX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<RX DMA WATER MARK,>RX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RR ,RXFIFO Ready" "No valid data,>=1 word"
|
|
rbitfld.long 0x00 2. " TF ,TXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX THRESHOLD,<=TX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX DMA WATER MARK,<=TX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 0. " TE ,TXFIFO Empty" "Not empty,Empty"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "STATREG2,Status Register 2"
|
|
eventfld.long 0x00 7. " TC ,Transfer Completed" "Busy,Completed"
|
|
eventfld.long 0x00 6. " RO ,RXFIFO Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("iMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<=RX THRESHOLD,>RX THRESHOLD/DMA TAIL DMA"
|
|
else
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Full" "<RX DMA WATER MARK,>RX DMA WATER MARK/DMA TAIL DMA matched"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RR ,RXFIFO Ready" "No valid data,>=1 word"
|
|
rbitfld.long 0x00 2. " TF ,TXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX THRESHOLD,<=TX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX DMA WATER MARK,<=TX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 0. " TE ,TXFIFO Empty" "Not empty,Empty"
|
|
endif
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "PERIODREG2,Sample Period Control Register 2"
|
|
bitfld.long 0x00 16.--21. " CSD_CTRL ,Chip Select Delay Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Frequency Ref. Clock"
|
|
else
|
|
bitfld.long 0x00 15. " CSRC ,Clock Source Control" "SPI Clock,CKIL"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--14. 1. " SAMPLE_PERIOD ,Sample Period Control"
|
|
line.long 0x04 "TESTREG2,Test Control Register 2"
|
|
bitfld.long 0x04 31. " LBC ,Loop Back Control" "Not connected,Connected"
|
|
sif (!(cpuis("IMX6*"))&&cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
bitfld.long 0x04 28.--29. " CL ,Catch Latency" "Normal,Half cycle,One cycle,One & half cycle"
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " RXCNT ,RXFIFO Counter"
|
|
hexmask.long.byte 0x04 0.--6. 1. " TXCNT ,TXFIFO Counter"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "MSGDATA2,Message Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "EIM (External Interface Module)"
|
|
base ad:0x63FD8000
|
|
width 9.
|
|
if (((per.l(ad:0x63FD8000+0x0))&0x06)==0x00)
|
|
group.long 0x0++0x3 "CS0"
|
|
line.long 0x00 "CS0GCR1,Chip Select 0 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x63FD8000+0x0))&0x06)==0x02)
|
|
group.long 0x0++0x3 "CS0"
|
|
line.long 0x00 "CS0GCR1,Chip Select 0 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x63FD8000+0x0))&0x06)==0x04)
|
|
group.long 0x0++0x3 "CS0"
|
|
line.long 0x00 "CS0GCR1,Chip Select 0 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x3 "CS0"
|
|
line.long 0x00 "CS0GCR1,Chip Select 0 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x0+0x04)++0x3
|
|
line.long 0x00 "CS0GCR2,Chip Select 0 General Control Register 2"
|
|
bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant"
|
|
bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..."
|
|
group.long (0x0+0x08)++0x3
|
|
line.long 0x00 "CS0RCR1,Chip Select 0 Read Control Register 1"
|
|
bitfld.long 0x00 24.--29. " RWSC ,Read Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " RADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RAL ,Read ADV Low" "RADVN,Ignored"
|
|
bitfld.long 0x00 16.--18. " RADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OEA ,OE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 8.--10. " OEN ,OE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " RCSA ,Read CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " RCSN ,Read CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
if (((per.l(ad:0x63FD8000+0x0))&0x3000)==0x0)
|
|
group.long (0x0+0x0C)++0x3
|
|
line.long 0x00 "CS0RCR2,Chip Select 0 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1,2,3,4"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long (0x0+0x0C)++0x3
|
|
line.long 0x00 "CS0RCR2,Chip Select 0 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1.5,2.5,3.5,4.5"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
if (((per.l(ad:0x63FD8000+0x0))&0x2)==0x0)
|
|
group.long (0x0+0x10)++0x3
|
|
line.long 0x00 "CS0WCR1,Chip Select 0 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " WBEA ,BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 6.--8. " WEN ,WE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " WCSN ,Write CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long (0x0+0x10)++0x3
|
|
line.long 0x00 "CS0WCR1,Chip Select 0 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
group.long (0x0+0x14)++0x3
|
|
line.long 0x00 "CS0WCR2,Chip Select 0 Write Configuration Register 2"
|
|
bitfld.long 0x00 0. " WBCDD ,Write Burst Clock Divisor Decrement" "No effect,Preformed"
|
|
if (((per.l(ad:0x63FD8000+0x18))&0x06)==0x00)
|
|
group.long 0x18++0x3 "CS1"
|
|
line.long 0x00 "CS1GCR1,Chip Select 1 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x63FD8000+0x18))&0x06)==0x02)
|
|
group.long 0x18++0x3 "CS1"
|
|
line.long 0x00 "CS1GCR1,Chip Select 1 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x63FD8000+0x18))&0x06)==0x04)
|
|
group.long 0x18++0x3 "CS1"
|
|
line.long 0x00 "CS1GCR1,Chip Select 1 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x3 "CS1"
|
|
line.long 0x00 "CS1GCR1,Chip Select 1 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x18+0x04)++0x3
|
|
line.long 0x00 "CS1GCR2,Chip Select 1 General Control Register 2"
|
|
bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant"
|
|
bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..."
|
|
group.long (0x18+0x08)++0x3
|
|
line.long 0x00 "CS1RCR1,Chip Select 1 Read Control Register 1"
|
|
bitfld.long 0x00 24.--29. " RWSC ,Read Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " RADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RAL ,Read ADV Low" "RADVN,Ignored"
|
|
bitfld.long 0x00 16.--18. " RADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OEA ,OE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 8.--10. " OEN ,OE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " RCSA ,Read CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " RCSN ,Read CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
if (((per.l(ad:0x63FD8000+0x18))&0x3000)==0x0)
|
|
group.long (0x18+0x0C)++0x3
|
|
line.long 0x00 "CS1RCR2,Chip Select 1 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1,2,3,4"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long (0x18+0x0C)++0x3
|
|
line.long 0x00 "CS1RCR2,Chip Select 1 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1.5,2.5,3.5,4.5"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
if (((per.l(ad:0x63FD8000+0x18))&0x2)==0x0)
|
|
group.long (0x18+0x10)++0x3
|
|
line.long 0x00 "CS1WCR1,Chip Select 1 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " WBEA ,BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 6.--8. " WEN ,WE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " WCSN ,Write CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long (0x18+0x10)++0x3
|
|
line.long 0x00 "CS1WCR1,Chip Select 1 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
group.long (0x18+0x14)++0x3
|
|
line.long 0x00 "CS1WCR2,Chip Select 1 Write Configuration Register 2"
|
|
bitfld.long 0x00 0. " WBCDD ,Write Burst Clock Divisor Decrement" "No effect,Preformed"
|
|
if (((per.l(ad:0x63FD8000+0x30))&0x06)==0x00)
|
|
group.long 0x30++0x3 "CS2"
|
|
line.long 0x00 "CS2GCR1,Chip Select 2 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x63FD8000+0x30))&0x06)==0x02)
|
|
group.long 0x30++0x3 "CS2"
|
|
line.long 0x00 "CS2GCR1,Chip Select 2 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x63FD8000+0x30))&0x06)==0x04)
|
|
group.long 0x30++0x3 "CS2"
|
|
line.long 0x00 "CS2GCR1,Chip Select 2 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x30++0x3 "CS2"
|
|
line.long 0x00 "CS2GCR1,Chip Select 2 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x30+0x04)++0x3
|
|
line.long 0x00 "CS2GCR2,Chip Select 2 General Control Register 2"
|
|
bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant"
|
|
bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..."
|
|
group.long (0x30+0x08)++0x3
|
|
line.long 0x00 "CS2RCR1,Chip Select 2 Read Control Register 1"
|
|
bitfld.long 0x00 24.--29. " RWSC ,Read Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " RADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RAL ,Read ADV Low" "RADVN,Ignored"
|
|
bitfld.long 0x00 16.--18. " RADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OEA ,OE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 8.--10. " OEN ,OE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " RCSA ,Read CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " RCSN ,Read CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
if (((per.l(ad:0x63FD8000+0x30))&0x3000)==0x0)
|
|
group.long (0x30+0x0C)++0x3
|
|
line.long 0x00 "CS2RCR2,Chip Select 2 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1,2,3,4"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long (0x30+0x0C)++0x3
|
|
line.long 0x00 "CS2RCR2,Chip Select 2 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1.5,2.5,3.5,4.5"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
if (((per.l(ad:0x63FD8000+0x30))&0x2)==0x0)
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x00 "CS2WCR1,Chip Select 2 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " WBEA ,BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 6.--8. " WEN ,WE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " WCSN ,Write CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long (0x30+0x10)++0x3
|
|
line.long 0x00 "CS2WCR1,Chip Select 2 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
group.long (0x30+0x14)++0x3
|
|
line.long 0x00 "CS2WCR2,Chip Select 2 Write Configuration Register 2"
|
|
bitfld.long 0x00 0. " WBCDD ,Write Burst Clock Divisor Decrement" "No effect,Preformed"
|
|
if (((per.l(ad:0x63FD8000+0x48))&0x06)==0x00)
|
|
group.long 0x48++0x3 "CS3"
|
|
line.long 0x00 "CS3GCR1,Chip Select 3 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x63FD8000+0x48))&0x06)==0x02)
|
|
group.long 0x48++0x3 "CS3"
|
|
line.long 0x00 "CS3GCR1,Chip Select 3 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x63FD8000+0x48))&0x06)==0x04)
|
|
group.long 0x48++0x3 "CS3"
|
|
line.long 0x00 "CS3GCR1,Chip Select 3 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x3 "CS3"
|
|
line.long 0x00 "CS3GCR1,Chip Select 3 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x00 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" ",16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Configuration register enable polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Configuration register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x48+0x04)++0x3
|
|
line.long 0x00 "CS3GCR2,Chip Select 3 General Control Register 2"
|
|
bitfld.long 0x00 12. " MUX16_BYP_GRANT ,Muxed 16 bypass grant" "Wait for grant,Ignore grant"
|
|
bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..."
|
|
group.long (0x48+0x08)++0x3
|
|
line.long 0x00 "CS3RCR1,Chip Select 3 Read Control Register 1"
|
|
bitfld.long 0x00 24.--29. " RWSC ,Read Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " RADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RAL ,Read ADV Low" "RADVN,Ignored"
|
|
bitfld.long 0x00 16.--18. " RADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OEA ,OE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 8.--10. " OEN ,OE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " RCSA ,Read CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " RCSN ,Read CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
if (((per.l(ad:0x63FD8000+0x48))&0x3000)==0x0)
|
|
group.long (0x48+0x0C)++0x3
|
|
line.long 0x00 "CS3RCR2,Chip Select 3 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1,2,3,4"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long (0x48+0x0C)++0x3
|
|
line.long 0x00 "CS3RCR2,Chip Select 3 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1.5,2.5,3.5,4.5"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
if (((per.l(ad:0x63FD8000+0x48))&0x2)==0x0)
|
|
group.long (0x48+0x10)++0x3
|
|
line.long 0x00 "CS3WCR1,Chip Select 3 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " WBEA ,BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 6.--8. " WEN ,WE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " WCSN ,Write CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long (0x48+0x10)++0x3
|
|
line.long 0x00 "CS3WCR1,Chip Select 3 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
group.long (0x48+0x14)++0x3
|
|
line.long 0x00 "CS3WCR2,Chip Select 3 Write Configuration Register 2"
|
|
bitfld.long 0x00 0. " WBCDD ,Write Burst Clock Divisor Decrement" "No effect,Preformed"
|
|
sif (cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6DUALLITE")
|
|
group.long 0x90++0x3 "Common"
|
|
line.long 0x00 "WCR,EIM Configuration Register"
|
|
bitfld.long 0x00 11. " FRUN_ACLK_EN ,Free run ACLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " WDOG_LIMIT ,Memory Wdog cycle limit" "128 cycles,256 cycles,512 cycles,1024 cycles"
|
|
bitfld.long 0x00 8. " WDOG_EN ,Memory Wdog enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTPOL ,Interrupt Polarity" "Active low,Active high"
|
|
bitfld.long 0x00 4. " INTEN ,Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT_BCLK_SEL ,Continuous BCLK select" "BCLK,BCLK Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " GBCD ,General Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 0. " BCM ,Burst Clock Mode" "Depend on CS config,When aclk active"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "DCR,DLL Control Register"
|
|
bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT ,Reference DLL Update Interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23.--27. " DLL_CTRL_SLV_UPDATE_INT ,Slave DLL Update Interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " DLL_CTRL_REF_INTIAL_VAL ,Reference DLL Initial Value"
|
|
hexmask.long.byte 0x00 9.--15. 1. " DLL_CTRL_SLV_OVERRIDE_VAL ,Slave DLL Override Value"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DLL_CTRL_SLV_OVVERIDE ,Enable slave DLL override" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,Gate DLL Update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DLL_CTRL_SLV_OFFSET_DEC ,Slave DLL offset" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,Slave DLL force update" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DLL_CTRL_RESET ,Reset DLL" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,Enable DLL" "Disabled,Enabled"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "DSR,DLL Status Register"
|
|
hexmask.long.byte 0x00 9.--15. 1. " DLL_STS_REF_SEL ,Reference DLL Selection"
|
|
hexmask.long.byte 0x00 2.--8. 1. " DLL_STS_SLV_SEL ,Slave DLL Selection"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL Lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave DLL Lock" "Not locked,Locked"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "WIAR,WEIM IP Access Register"
|
|
bitfld.long 0x00 4. " ACLK_EN ,ACLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ERRST ,Enable READY After Reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT ,Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IPS_ACK ,WEIM is ready for ips access" "Not accessed,Accessed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPS_REQ ,IPS request" "Not requested,Requested"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "EAR,Error Address Register"
|
|
else
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x00 "EAR,Error Address Register"
|
|
endif
|
|
else
|
|
group.long 0x90++0x3 "Common"
|
|
line.long 0x00 "WCR,WEIM Configuration Register"
|
|
bitfld.long 0x00 9.--10. " WDOG_LIMIT ,Memory Wdog cycle limit" "128 cycles,256 cycles,512 cycles,1024 cycles"
|
|
bitfld.long 0x00 8. " WDOG_EN ,Memory Wdog enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTPOL ,Interrupt Polarity" "Active low,Active high"
|
|
bitfld.long 0x00 4. " INTEN ,Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " GBCD ,General Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 0. " BCM ,Burst Clock Mode" "Depend on CS config,When aclk active"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "WIAR,WEIM IP Access Register"
|
|
bitfld.long 0x00 4. " ACLK_EN ,ACLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ERRST ,Enable READY After Reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT ,Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IPS_ACK ,WEIM is ready for ips access" "Not accessed,Accessed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPS_REQ ,IPS request" "Not requested,Requested"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x00 "EAR,Error Address Register"
|
|
endif
|
|
sif !cpuis("IMX50*")
|
|
width 5.
|
|
tree "Chip Select Memory"
|
|
base ad:0xF0000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS0,EIM CS0 Memory Region"
|
|
button "CS0 " "d ad:0xF0000000--ad:0xffffffff /long"
|
|
base ad:0xf0000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS1,EIM CS1 Memory Region"
|
|
button "CS1 " "d ad:0xF0000000--ad:0xffffffff /long"
|
|
base ad:0xf0000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS2,EIM CS2 Memory Region"
|
|
button "CS2 " "d ad:0xF0000000--ad:0xffffffff /long"
|
|
base ad:0xf0000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS3,EIM CS3 Memory Region"
|
|
button "CS3 " "d ad:0xF0000000--ad:0xffffffff /long"
|
|
base ad:0xf0000000
|
|
sif (!cpuis("IMX6*"))
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS4,EIM CS4 Memory Region"
|
|
button "CS4 " "d ad:0xf0000000--ad:0xffffffff /long"
|
|
base ad:0xf0000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS5,EIM CS5 Memory Region"
|
|
button "CS5 " "d ad:0xf0000000--ad:0xffffffff /long"
|
|
endif
|
|
tree.end
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("IMX503*")||!cpuis("IMX502*")
|
|
tree "EPDC (Electrophoretic Display Controller)"
|
|
base ad:0x41010000
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "CTRL,EPDC Control Register"
|
|
bitfld.long 0x00 31. " SFTRST ,Normal EPDC operation" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Not gated,Gated"
|
|
bitfld.long 0x00 8. " SRAM_PD ,Power-down of embedded SRAM memories" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BURST_LEN_8 ,Length of bursts" "16,8"
|
|
line.long 0x04 "CTRL_SET,EPDC Control Set Register"
|
|
bitfld.long 0x04 31. " SFTRST ,Normal EPDC operation" "No effect,Set"
|
|
bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set"
|
|
bitfld.long 0x04 8. " SRAM_PD ,Power-down of embedded SRAM memories" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap of the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap of the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped"
|
|
textline " "
|
|
bitfld.long 0x04 0. " BURST_LEN_8 ,Length of bursts" "No effect,Set"
|
|
line.long 0x08 "CTRL_CLR,EPDC Control Clear Register"
|
|
bitfld.long 0x08 31. " SFTRST ,Normal EPDC operation" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Cleared"
|
|
bitfld.long 0x08 8. " SRAM_PD ,Power-down of embedded SRAM memories" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped"
|
|
textline " "
|
|
bitfld.long 0x08 0. " BURST_LEN_8 ,Length of bursts" "No effect,Cleared"
|
|
line.long 0x0C "CTRL_TOG,EPDC Control Toggle Register"
|
|
bitfld.long 0x0C 31. " SFTRST ,Normal EPDC operation" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 8. " SRAM_PD ,Power-down of embedded SRAM memories" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " UPD_DATA_SWIZZLE ,Mode of swap the bytes for the UPD data before the WB construction" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " LUT_DATA_SWIZZLE ,Mode of swap the bytes for the LUT data before store to LUTRAM" "Not swapped,All bytes swapped,Half-word swapped,Bytes within each half-word swapped"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " BURST_LEN_8 ,Length of bursts" "Not toggled,Toggled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "WVADDR,EPDC Waveform Address Pointer"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "WB_ADDR,EPDC Working Buffer Address"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RES,EPDC Screen Resolution"
|
|
hexmask.long.word 0x00 16.--28. 1. " VERTICAL ,Vertical Resoltion (in pixels)"
|
|
hexmask.long.word 0x00 0.--12. 1. " HORIZONTAL ,Horizontal Resolution (in pixels)"
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "FORMAT,EPDC Format Control Register"
|
|
bitfld.long 0x00 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "Truncate,Rounding"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value"
|
|
bitfld.long 0x00 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TFT_PIX_FOR ,EPDC TFT Pixel Format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM"
|
|
line.long 0x04 "FORMAT_SET,EPDC Format Control Set Register"
|
|
bitfld.long 0x04 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "No effect,Set"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value"
|
|
bitfld.long 0x04 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " TFT_PIX_FOR ,EPDC TFT Pixel Format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM"
|
|
line.long 0x08 "FORMAT_CLR,EPDC Format Control Clear Register"
|
|
bitfld.long 0x08 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "No effect,Cleared"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value"
|
|
bitfld.long 0x08 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " TFT_PIX_FOR ,EPDC TFT Pixel Format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM"
|
|
line.long 0x0C "FORMAT_TOG,EPDC Format Control Toggle Register"
|
|
bitfld.long 0x0C 24. " BUF_PIX_SCALE ,Method of conversion from 8-bit input" "Not toggled,Toggled"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " DEFAULT_TFT_PIX ,Default TFT pixel value"
|
|
bitfld.long 0x0C 8.--10. " BUF_PIX_FOR ,EPDC Input Buffer Pixel format" "Reserved,Reserved,2-bit,3-bit,4-bit,5-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " TFT_PIX_FOR ,EPDC TFT Pixel Format" "2-bit,2-bit & VCOM,4-bit,4-bit & VCOM"
|
|
group.long 0xA0++0x0F
|
|
line.long 0x00 "FIFOCTRL,EPDC FIFO control register"
|
|
bitfld.long 0x00 31. " EN_PRIOR ,Watermark-based priority elevation mechanism" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark"
|
|
line.long 0x04 "FIFOCTRL_SET,EPDC FIFO control set register"
|
|
bitfld.long 0x04 31. " EN_PRIOR ,Watermark-based priority elevation mechanism" "No effect,Set"
|
|
hexmask.long.byte 0x04 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo"
|
|
hexmask.long.byte 0x04 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark"
|
|
line.long 0x08 "FIFOCTRL_CLR,EPDC FIFO control clear register"
|
|
bitfld.long 0x08 31. " EN_PRIOR ,Watermark-based priority elevation mechanism" "No effect,Cleared"
|
|
hexmask.long.byte 0x08 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo"
|
|
hexmask.long.byte 0x08 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark"
|
|
line.long 0x0C "FIFOCTRL_TOG,EPDC FIFO control toggle register"
|
|
bitfld.long 0x0C 31. " EN_PRIOR ,Watermark-based priority elevation mechanism" "Not toggled,Toggled"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " FIFO_INIT_LEV ,Watermark for the pixel-fifo"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " FIFO_H_LEV ,Upper level value of FIFO watermark"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " FIFO_L_LEV ,Lower level value of FIFO watermark"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UPD_ADDR,EPDC Update Region Address"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "UPD_CORD,EPDC Update Command Co-ordinate"
|
|
hexmask.long.word 0x00 16.--28. 1. " YCORD ,Y co-ordinate for incoming region update"
|
|
hexmask.long.word 0x00 0.--12. 1. " XCORD ,X co-ordinate for incoming region update"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UPD_SIZE,EPDC Update Command Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " HEIGHT ,Height (in pixels)"
|
|
hexmask.long.word 0x00 0.--12. 1. " WIDTH ,Width (in pixels)"
|
|
group.long 0x160++0x0F
|
|
line.long 0x00 "UPD_CTRL,EPDC Update Command Control"
|
|
bitfld.long 0x00 31. " USE_FIXED ,Use fixed pixel values" "Not used,Used"
|
|
bitfld.long 0x00 16.--19. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WAVEFORM_MODE ,Waveform Mode"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UPDATE_MODE ,Update Mode" "Partial,Full"
|
|
line.long 0x04 "UPD_CTRL_SET,EPDC Update Command Control Set"
|
|
bitfld.long 0x04 31. " USE_FIXED ,Use fixed pixel values" "No effect,Set"
|
|
bitfld.long 0x04 16.--19. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 8.--15. 1. " WAVEFORM_MODE ,Waveform Mode"
|
|
textline " "
|
|
bitfld.long 0x04 0. " UPDATE_MODE ,Update Mode" "No effect,Set"
|
|
line.long 0x08 "UPD_CTRL_CLR,EPDC Update Command Control Clear"
|
|
bitfld.long 0x08 31. " USE_FIXED ,Use fixed pixel values" "No effect,Cleared"
|
|
bitfld.long 0x08 16.--19. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x08 8.--15. 1. " WAVEFORM_MODE ,Waveform Mode"
|
|
textline " "
|
|
bitfld.long 0x08 0. " UPDATE_MODE ,Update Mode" "No effect,Cleared"
|
|
line.long 0x0C "UPD_CTRL_TOG,EPDC Update Command Control Toggle"
|
|
bitfld.long 0x0C 31. " USE_FIXED ,Use fixed pixel values" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 16.--19. " LUT_SEL ,LUT select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " WAVEFORM_MODE ,Waveform Mode"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " UPDATE_MODE ,Update Mode" "Not toggled,Toggled"
|
|
group.long 0x180++0x0F
|
|
line.long 0x00 "UPD_FIXED,EPDC Update Fixed Pixel Control"
|
|
bitfld.long 0x00 31. " FIXNP_EN ,Update region with NP value in FIXNP" "Not updated,Updated"
|
|
bitfld.long 0x00 30. " FIXCP_EN ,Update region with CP value in FIXCP" "Not updated,Updated"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FIXNP ,NP value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " FIXCP ,CP value"
|
|
line.long 0x04 "UPD_FIXED_SET,EPDC Update Fixed Pixel Control Set"
|
|
bitfld.long 0x04 31. " FIXNP_EN ,Update region with NP value in FIXNP" "No effect,Set"
|
|
bitfld.long 0x04 30. " FIXCP_EN ,Update region with CP value in FIXCP" "No effect,Set"
|
|
hexmask.long.byte 0x04 8.--15. 1. " FIXNP ,NP value"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " FIXCP ,CP value"
|
|
line.long 0x08 "UPD_FIXED_CLR,EPDC Update Fixed Pixel Control Clear"
|
|
bitfld.long 0x08 31. " FIXNP_EN ,Update region with NP value in FIXNP" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " FIXCP_EN ,Update region with CP value in FIXCP" "No effect,Cleared"
|
|
hexmask.long.byte 0x08 8.--15. 1. " FIXNP ,NP value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " FIXCP ,CP value"
|
|
line.long 0x0C "UPD_FIXED_TOG,EPDC Update Fixed Pixel Control Toggle"
|
|
bitfld.long 0x0C 31. " FIXNP_EN ,Update region with NP value in FIXNP" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 30. " FIXCP_EN ,Update region with CP value in FIXCP" "Not toggled,Toggled"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " FIXNP ,NP value"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " FIXCP ,CP value"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TEMP,EPDC Temperature Register"
|
|
if ((((d.l(ad:0x41010000+0x200))&0x04)==0x04)&&(((d.l(ad:0x41010000+0x200))&0x40)==0x40))
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "TCE_CTRL,EPDC Timing Control Engine Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x00 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x00 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Manual,Auto"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "Not drove,Drove"
|
|
bitfld.long 0x00 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "Not drove,Drove"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "Not used,Used"
|
|
bitfld.long 0x00 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Up,Down"
|
|
bitfld.long 0x00 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "8-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
line.long 0x04 "TCE_CTRL_SET,EPDC Timing Control Engine Control Set Register"
|
|
hexmask.long.word 0x04 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x04 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x04 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "No effect,Set"
|
|
bitfld.long 0x04 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "No effect,Set"
|
|
bitfld.long 0x04 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Set"
|
|
bitfld.long 0x04 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "No effect,Set"
|
|
bitfld.long 0x04 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
line.long 0x08 "TCE_CTRL_CLR,EPDC Timing Control Engine Control Clear Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x08 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x08 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "No effect,Cleared"
|
|
bitfld.long 0x08 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "No effect,Cleared"
|
|
bitfld.long 0x08 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "No effect,Cleared"
|
|
bitfld.long 0x08 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
line.long 0x0C "TCE_CTRL_TOG,EPDC Timing Control Engine Control Toggle Register"
|
|
hexmask.long.word 0x0C 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x0C 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x0C 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " DDR_MODE ,SDDO data is driven on both positive and negative edges of SDCLK" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 7. " LVDS_MODE_CE ,SDCE[9:5] drives as the differential inverse of SDCE[4:0]" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
elif ((((d.l(ad:0x41010000+0x200))&0x04)==0x04)&&(((d.l(ad:0x41010000+0x200))&0x40)==0x00))
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "TCE_CTRL,EPDC Timing Control Engine Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x00 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x00 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Manual,Auto"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "Not used,Used"
|
|
bitfld.long 0x00 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Up,Down"
|
|
bitfld.long 0x00 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "8-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
line.long 0x04 "TCE_CTRL_SET,EPDC Timing Control Engine Control Set Register"
|
|
hexmask.long.word 0x04 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x04 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x04 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "No effect,Set"
|
|
bitfld.long 0x04 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Set"
|
|
bitfld.long 0x04 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "No effect,Set"
|
|
bitfld.long 0x04 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
line.long 0x08 "TCE_CTRL_CLR,EPDC Timing Control Engine Control Clear Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x08 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x08 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "No effect,Cleared"
|
|
bitfld.long 0x08 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "No effect,Cleared"
|
|
bitfld.long 0x08 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
line.long 0x0C "TCE_CTRL_TOG,EPDC Timing Control Engine Control Toggle Register"
|
|
hexmask.long.word 0x0C 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x0C 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x0C 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " LVDS_MODE ,Upper 8-bit of the SDDO bus are used for LVDS differential signalling" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DUAL_SCAN ,Dual scan-mode applies to each 8-bit segment of the SDDO bus" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
else
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "TCE_CTRL,EPDC Timing Control Engine Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x00 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x00 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Manual,Auto"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Up,Down"
|
|
bitfld.long 0x00 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "8-bit,16-bit"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
line.long 0x04 "TCE_CTRL_SET,EPDC Timing Control Engine Control Set Register"
|
|
hexmask.long.word 0x04 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x04 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x04 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Set"
|
|
bitfld.long 0x04 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
line.long 0x08 "TCE_CTRL_CLR,EPDC Timing Control Engine Control Clear Register"
|
|
hexmask.long.word 0x08 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x08 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x08 9. " VCOM_MODE ,Method used to drive the VCOM signal" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
line.long 0x0C "TCE_CTRL_TOG,EPDC Timing Control Engine Control Toggle Register"
|
|
hexmask.long.word 0x0C 16.--24. 1. " VSCAN_HOLDOFF ,Portion of the vertical blanking available for new LUTs to be activated"
|
|
bitfld.long 0x0C 10.--11. " VCOM_VAL ,VCOM value for the VCOM[1:0] pins" "0,1,2,3"
|
|
bitfld.long 0x0C 9. " VCOM_MODE ,Method used to drive the VCOM signal" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " SCAN_DIR_1 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 4. " SCAN_DIR_0 ,Scan direction for each half of the TFT panel" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SDDO_WIDTH ,SDDO bus format (in bits)" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PIXELS_PER_SDCLK ,Number of TFT pixels per SDCLK period" "Reserved,Two,Four,Eight"
|
|
endif
|
|
group.long 0x220++0x0F
|
|
line.long 0x00 "TCE_SDCFG,EPDC Timing Control Engine Source-Driver Config Register"
|
|
bitfld.long 0x00 21. " SDCLK_HOLD ,Holds the SDCLK low during line_BEGIN" "Not held,Held"
|
|
bitfld.long 0x00 20. " SDSHR ,Value for source-driver shift direction output port" "Low,High"
|
|
bitfld.long 0x00 16.--19. " NUM_CE ,Number of source driver IC chip-enables" "Reserved,1,2,3,4,5,6,7,8,9,10,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..."
|
|
bitfld.long 0x00 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "Not reversed,Reversed"
|
|
hexmask.long.word 0x00 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (outputs) per source-driver IC"
|
|
line.long 0x04 "TCE_SDCFG_SET,EPDC Timing Control Engine Source-Driver Config Set Register"
|
|
bitfld.long 0x04 21. " SDCLK_HOLD ,Holds the SDCLK low during line_BEGIN" "No effect,Set"
|
|
bitfld.long 0x04 20. " SDSHR ,Value for source-driver shift direction output port" "No effect,Set"
|
|
bitfld.long 0x04 16.--19. " NUM_CE ,Number of source driver IC chip-enables" "Reserved,1,2,3,4,5,6,7,8,9,10,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..."
|
|
bitfld.long 0x04 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "No effect,Set"
|
|
hexmask.long.word 0x04 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (outputs) per source-driver IC"
|
|
line.long 0x08 "TCE_SDCFG_CLR,EPDC Timing Control Engine Source-Driver Config Clear Register"
|
|
bitfld.long 0x08 21. " SDCLK_HOLD ,Holds the SDCLK low during line_BEGIN" "No effect,Cleared"
|
|
bitfld.long 0x08 20. " SDSHR ,Value for source-driver shift direction output port" "No effect,Cleared"
|
|
bitfld.long 0x08 16.--19. " NUM_CE ,Number of source driver IC chip-enables" "Reserved,1,2,3,4,5,6,7,8,9,10,?..."
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..."
|
|
bitfld.long 0x08 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "No effect,Cleared"
|
|
hexmask.long.word 0x08 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (outputs) per source-driver IC"
|
|
line.long 0x0C "TCE_SDCFG_TOG,EPDC Timing Control Engine Source-Driver Config Toggle Register"
|
|
bitfld.long 0x0C 21. " SDCLK_HOLD ,Holds the SDCLK low during line_BEGIN" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 20. " SDSHR ,Value for source-driver shift direction output port" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 16.--19. " NUM_CE ,Number of source driver IC chip-enables" "Reserved,1,2,3,4,5,6,7,8,9,10,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " SDDO_REFORMAT ,Re-formatting options to enable more flexibility in the source-driver interface" "STANDARD,FLIP_PIXELS,?..."
|
|
bitfld.long 0x0C 13. " SDDO_INVERT ,Reverses the polarity of each SDDO bit" "Not toggled,Toggled"
|
|
hexmask.long.word 0x0C 0.--12. 1. " PIXELS_PER_CE ,Number of pixels (outputs) per source-driver IC"
|
|
group.long 0x240++0x0F
|
|
line.long 0x00 "TCE_GDCFG,EPDC Timing Control Engine Gate-Driver Config Register"
|
|
bitfld.long 0x00 4. " GDRL ,Value for gate-driver right/left shift output port" "Low,High"
|
|
bitfld.long 0x00 1. " GDOE_MODE ,Method for driving GDOE signal" "All times,Delayed"
|
|
bitfld.long 0x00 0. " GDSP_MODE ,Method for driving GDSP pulse" "Fixed,FRAME_SYNC"
|
|
line.long 0x04 "TCE_GDCFG_SET,EPDC Timing Control Engine Gate-Driver Config Set Register"
|
|
bitfld.long 0x04 4. " GDRL ,Value for gate-driver right/left shift output port" "No effect,Set"
|
|
bitfld.long 0x04 1. " GDOE_MODE ,Method for driving GDOE signal" "No effect,Set"
|
|
bitfld.long 0x04 0. " GDSP_MODE ,Method for driving GDSP pulse" "No effect,Set"
|
|
line.long 0x08 "TCE_GDCFG_CLR,EPDC Timing Control Engine Gate-Driver Config Clear Register"
|
|
bitfld.long 0x08 4. " GDRL ,Value for gate-driver right/left shift output port" "No effect,Cleared"
|
|
bitfld.long 0x08 1. " GDOE_MODE ,Method for driving GDOE signal" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " GDSP_MODE ,Method for driving GDSP pulse" "No effect,Cleared"
|
|
line.long 0x0C "TCE_GDCFG_TOG,EPDC Timing Control Engine Gate-Driver Config Toggle Register"
|
|
bitfld.long 0x0C 4. " GDRL ,Value for gate-driver right/left shift output port" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 1. " GDOE_MODE ,Method for driving GDOE signal" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 0. " GDSP_MODE ,Method for driving GDSP pulse" "Not toggled,Toggled"
|
|
group.long 0x260++0x0F
|
|
line.long 0x00 "TCE_HSCAN1,EPDC Timing Control Engine Horizontal Timing Register 1"
|
|
hexmask.long.word 0x00 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time"
|
|
hexmask.long.word 0x00 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration"
|
|
line.long 0x04 "TCE_HSCAN1_SET,EPDC Timing Control Engine Horizontal Timing Set Register 1"
|
|
hexmask.long.word 0x04 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time"
|
|
hexmask.long.word 0x04 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration"
|
|
line.long 0x08 "TCE_HSCAN1_CLR,EPDC Timing Control Engine Horizontal Timing Clear Register 1"
|
|
hexmask.long.word 0x08 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time"
|
|
hexmask.long.word 0x08 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration"
|
|
line.long 0x0C "TCE_HSCAN1_TOG,EPDC Timing Control Engine Horizontal Timing Toggle Register 1"
|
|
hexmask.long.word 0x0C 16.--27. 1. " LINE_SYNC_WIDTH ,Number of PIXCLK cycles for the SDLE active time"
|
|
hexmask.long.word 0x0C 0.--11. 1. " LINE_SYNC ,Number of PIXCLK cycles for line sync duration"
|
|
group.long 0x280++0x0F
|
|
line.long 0x00 "TCE_HSCAN2,EPDC Timing Control Engine Horizontal Timing Register 2"
|
|
hexmask.long.word 0x00 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration"
|
|
hexmask.long.word 0x00 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration"
|
|
line.long 0x04 "TCE_HSCAN2_SET,EPDC Timing Control Engine Horizontal Timing Set Register 2"
|
|
hexmask.long.word 0x04 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration"
|
|
hexmask.long.word 0x04 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration"
|
|
line.long 0x08 "TCE_HSCAN2_CLR,EPDC Timing Control Engine Horizontal Timing Clear Register 2"
|
|
hexmask.long.word 0x08 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration"
|
|
hexmask.long.word 0x08 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration"
|
|
line.long 0x0C "TCE_HSCAN2_TOG,EPDC Timing Control Engine Horizontal Timing Toggle Register 2"
|
|
hexmask.long.word 0x0C 16.--27. 1. " LINE_END ,Number of PIXCLK cycles for line end duration"
|
|
hexmask.long.word 0x0C 0.--11. 1. " LINE_BEGIN ,Number of PIXCLK cycles for line begin duration"
|
|
group.long 0x2A0++0x0F
|
|
line.long 0x00 "TCE_VSCAN,EPDC Timing Control Engine Vertical Timing Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FRAME_END ,Number of lines for frame end duration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration"
|
|
line.long 0x04 "TCE_VSCAN_SET,EPDC Timing Control Engine Vertical Timing Set Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " FRAME_END ,Number of lines for frame end duration"
|
|
hexmask.long.byte 0x04 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration"
|
|
line.long 0x08 "TCE_VSCAN_CLR,EPDC Timing Control Engine Vertical Timing Clear Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " FRAME_END ,Number of lines for frame end duration"
|
|
hexmask.long.byte 0x08 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration"
|
|
hexmask.long.byte 0x08 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration"
|
|
line.long 0x0C "TCE_VSCAN_TOG,EPDC Timing Control Engine Vertical Timing Toggle Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " FRAME_END ,Number of lines for frame end duration"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " FRAME_BEGIN ,Number of lines for frame begin duration"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " FRAME_SYNC ,Number of lines for frame sync duration"
|
|
group.long 0x2C0++0x0F
|
|
line.long 0x00 "TCE_OE,EPDC Timing Control Engine OE timing control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising"
|
|
line.long 0x04 "TCE_OE_SET,EPDC Timing Control Engine OE timing control set Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising"
|
|
line.long 0x08 "TCE_OE_CLR,EPDC Timing Control Engine OE timing control clear Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling"
|
|
hexmask.long.byte 0x08 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising"
|
|
line.long 0x0C "TCE_OE_TOG,EPDC Timing Control Engine OE timing control toggle Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " SDOED_WIDTH ,Number of PIXCLK cycles from SDOED high to SDOED falling"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " SDOED_DLY ,Number of PIXCLK cycles from SDOEZ low to SDOED rising"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " SDOEZ_WIDTH ,Number of PIXCLK cycles from SDOEZ high to SDOEZ falling"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " SDOEZ_DLY ,Number of PIXCLK cycles from SDLE falling edge to SDOEZ rising"
|
|
group.long 0x2E0++0x0F
|
|
line.long 0x00 "TCE_POLARITY,EPDC Timing Control Engine Driver Polarity Register"
|
|
bitfld.long 0x00 4. " GDSP_POL ,GDSP output" "Active Low,Active High"
|
|
bitfld.long 0x00 3. " GDOE_POL ,GDOE output" "Active Low,Active High"
|
|
bitfld.long 0x00 2. " SDOE_POL ,SDOE" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SDLE_POL ,SDLE output" "Active Low,Active High"
|
|
bitfld.long 0x00 0. " SDCE_POL ,All 10 SDCE outputs" "Active Low,Active High"
|
|
line.long 0x04 "TCE_POLARITY_SET,EPDC Timing Control Engine Driver Polarity Register"
|
|
bitfld.long 0x04 4. " GDSP_POL ,GDSP output" "No effect,Set"
|
|
bitfld.long 0x04 3. " GDOE_POL ,GDOE output" "No effect,Set"
|
|
bitfld.long 0x04 2. " SDOE_POL ,SDOE" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SDLE_POL ,SDLE output" "No effect,Set"
|
|
bitfld.long 0x04 0. " SDCE_POL ,All 10 SDCE outputs" "No effect,Set"
|
|
line.long 0x08 "TCE_POLARITY_CLR,EPDC Timing Control Engine Driver Polarity Register"
|
|
bitfld.long 0x08 4. " GDSP_POL ,GDSP output" "No effect,Clear"
|
|
bitfld.long 0x08 3. " GDOE_POL ,GDOE output" "No effect,Clear"
|
|
bitfld.long 0x08 2. " SDOE_POL ,SDOE" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SDLE_POL ,SDLE output" "No effect,Clear"
|
|
bitfld.long 0x08 0. " SDCE_POL ,All 10 SDCE outputs" "No effect,Clear"
|
|
line.long 0x0C "TCE_POLARITY_TOG,EPDC Timing Control Engine Driver Polarity Register"
|
|
bitfld.long 0x0C 4. " GDSP_POL ,GDSP output" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 3. " GDOE_POL ,GDOE output" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2. " SDOE_POL ,SDOE" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SDLE_POL ,SDLE output" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 0. " SDCE_POL ,All 10 SDCE outputs" "Not toggled,Toggled"
|
|
group.long 0x300++0x2F
|
|
line.long 0x00 "TCE_TIMING1,EPDC Timing Control Engine Timing Register 1"
|
|
bitfld.long 0x00 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles"
|
|
bitfld.long 0x00 3. " SDCLK_INVERT ,Invert phase of SDCLK" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles"
|
|
line.long 0x04 "TCE_TIMING1_SET,EPDC Timing Control Engine Timing Set Register 1"
|
|
bitfld.long 0x04 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles"
|
|
bitfld.long 0x04 3. " SDCLK_INVERT ,Invert phase of SDCLK" "Not set,Set"
|
|
bitfld.long 0x04 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles"
|
|
line.long 0x08 "TCE_TIMING1_CLR,EPDC Timing Control Engine Timing Clear Register 1"
|
|
bitfld.long 0x08 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles"
|
|
bitfld.long 0x08 3. " SDCLK_INVERT ,Invert phase of SDCLK" "Not cleared,Cleared"
|
|
bitfld.long 0x08 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles"
|
|
line.long 0x0C "TCE_TIMING1_TOG,EPDC Timing Control Engine Timing Toggle Register 1"
|
|
bitfld.long 0x0C 4.--5. " SDLE_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 3 PIXCLK cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles"
|
|
bitfld.long 0x0C 3. " SDCLK_INVERT ,Invert phase of SDCLK" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 0.--1. " SDCLK_SHIFT ,Implement additional timing setup/hold adjustment of source driver signals by adjusting the SDCLK up to 4 cycles" "No shift,1 pixclk cycle,2 pixclk cycles,3 pixclk cycles"
|
|
line.long 0x10 "TCE_TIMING2,EPDC Timing Control Engine Timing Register 2"
|
|
hexmask.long.word 0x10 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width"
|
|
hexmask.long.word 0x10 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by N PIXCLKs"
|
|
line.long 0x14 "TCE_TIMING2_SET,EPDC Timing Control Engine Timing Set Register 2"
|
|
hexmask.long.word 0x14 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width"
|
|
hexmask.long.word 0x14 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by N PIXCLKs"
|
|
line.long 0x18 "TCE_TIMING2_CLR,EPDC Timing Control Engine Timing Clear Register 2"
|
|
hexmask.long.word 0x18 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width"
|
|
hexmask.long.word 0x18 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by N PIXCLKs"
|
|
line.long 0x1C "TCE_TIMING2_TOG,EPDC Timing Control Engine Timing Register 2"
|
|
hexmask.long.word 0x1C 16.--31. 1. " GDCLK_HP ,GDCLK high-pulse width"
|
|
hexmask.long.word 0x1C 0.--15. 1. " GDSP_OFFSET ,Shift the GDSP pulse by N PIXCLKs"
|
|
line.long 0x20 "TCE_TIMING3,EPDC Timing Control Engine Timing Register 3"
|
|
hexmask.long.word 0x20 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of N PIXCLK cycles"
|
|
hexmask.long.word 0x20 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by N PIXCLK cycles"
|
|
line.long 0x24 "TCE_TIMING3_SET,EPDC Timing Control Engine Timing Register 3"
|
|
hexmask.long.word 0x24 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of N PIXCLK cycles"
|
|
hexmask.long.word 0x24 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by N PIXCLK cycles"
|
|
line.long 0x28 "TCE_TIMING3_CLR,EPDC Timing Control Engine Timing Register 3"
|
|
hexmask.long.word 0x28 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of N PIXCLK cycles"
|
|
hexmask.long.word 0x28 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by N PIXCLK cycles"
|
|
line.long 0x2C "TCE_TIMING3_TOG,EPDC Timing Control Engine Timing Register 3"
|
|
hexmask.long.word 0x2C 16.--31. 1. " GDOE_OFFSET ,Delay from GDCLK to the GDOE in terms of N PIXCLK cycles"
|
|
hexmask.long.word 0x2C 0.--15. 1. " GDCLK_OFFSET ,Shift the GDCLK from the line time by N PIXCLK cycles"
|
|
group.long 0x400++0x0F
|
|
line.long 0x00 "IRQ_MASK,EPDC IRQ Mask Register"
|
|
bitfld.long 0x00 21. " TCE_IDLE_IRQ_EN ,Enable TCE Idle interrupt detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BUS_ERROR_IRQ_EN ,Enable AXI BUS ERROR interrupt detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FRAME_END_IRQ_EN ,Current Frame End Interrupt Assertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TCE_UNDERRUN_IRQ_EN ,Enable pixel FIFO under-run condition detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " COL_IRQ_EN ,Enable collision detection interrupts for all LUTs" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " WB_CMPLT_IRQ_EN ,Enable WB complete interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LUT15_CMPLT_IRQ_EN ,LUT15 Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LUT14_CMPLT_IRQ_EN ,LUT14 Complete Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LUT13_CMPLT_IRQ_EN ,LUT13 Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LUT12_CMPLT_IRQ_EN ,LUT12 Complete Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LUT11_CMPLT_IRQ_EN ,LUT11 Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LUT10_CMPLT_IRQ_EN ,LUT10 Complete Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LUT9_CMPLT_IRQ_EN ,LUT9 Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LUT8_CMPLT_IRQ_EN ,LUT8 Complete Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LUT7_CMPLT_IRQ_EN ,LUT7 Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LUT6_CMPLT_IRQ_EN ,LUT6 Complete Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LUT5_CMPLT_IRQ_EN ,LUT5 Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LUT4_CMPLT_IRQ_EN ,LUT4 Complete Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LUT3_CMPLT_IRQ_EN ,LUT3 Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LUT2_CMPLT_IRQ_EN ,LUT2 Complete Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LUT1_CMPLT_IRQ_EN ,LUT1 Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LUT0_CMPLT_IRQ_EN ,LUT0 Complete Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ_MASK_SET,EPDC IRQ Mask Register"
|
|
bitfld.long 0x04 21. " TCE_IDLE_IRQ_EN ,Set TCE Idle interrupt detection" "No effect,Set"
|
|
bitfld.long 0x04 20. " BUS_ERROR_IRQ_EN ,Set AXI BUS ERROR interrupt detection" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FRAME_END_IRQ_EN ,Current Frame End Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 18. " TCE_UNDERRUN_IRQ_EN ,Set pixel FIFO under-run condition detection" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 17. " COL_IRQ_EN ,Set collision detection interrupts for all LUTs" "No effect,Set"
|
|
bitfld.long 0x04 16. " WB_CMPLT_IRQ_EN ,Set WB complete interrupt" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LUT15_CMPLT_IRQ_EN ,LUT15 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 14. " LUT14_CMPLT_IRQ_EN ,LUT14 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 13. " LUT13_CMPLT_IRQ_EN ,LUT13 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 12. " LUT12_CMPLT_IRQ_EN ,LUT12 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LUT11_CMPLT_IRQ_EN ,LUT11 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 10. " LUT10_CMPLT_IRQ_EN ,LUT10 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LUT9_CMPLT_IRQ_EN ,LUT9 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 8. " LUT8_CMPLT_IRQ_EN ,LUT8 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LUT7_CMPLT_IRQ_EN ,LUT7 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 6. " LUT6_CMPLT_IRQ_EN ,LUT6 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " LUT5_CMPLT_IRQ_EN ,LUT5 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 4. " LUT4_CMPLT_IRQ_EN ,LUT4 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LUT3_CMPLT_IRQ_EN ,LUT3 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 2. " LUT2_CMPLT_IRQ_EN ,LUT2 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LUT1_CMPLT_IRQ_EN ,LUT1 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 0. " LUT0_CMPLT_IRQ_EN ,LUT0 Complete Interrupt Set" "No effect,Set"
|
|
line.long 0x08 "IRQ_MASK_CLR,EPDC IRQ Mask Register"
|
|
bitfld.long 0x08 21. " TCE_IDLE_IRQ_EN ,Clear TCE Idle interrupt detection" "No effect,Cleared"
|
|
bitfld.long 0x08 20. " BUS_ERROR_IRQ_EN ,Clear AXI BUS ERROR interrupt detection" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " FRAME_END_IRQ_EN ,Current Frame End Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 18. " TCE_UNDERRUN_IRQ_EN ,Clear pixel FIFO under-run condition detection" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " COL_IRQ_EN ,Clear collision detection interrupts for all LUTs" "No effect,Cleared"
|
|
bitfld.long 0x08 16. " WB_CMPLT_IRQ_EN ,Clear WB complete interrupt" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " LUT15_CMPLT_IRQ_EN ,LUT15 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 14. " LUT14_CMPLT_IRQ_EN ,LUT14 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " LUT13_CMPLT_IRQ_EN ,LUT13 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 12. " LUT12_CMPLT_IRQ_EN ,LUT12 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " LUT11_CMPLT_IRQ_EN ,LUT11 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 10. " LUT10_CMPLT_IRQ_EN ,LUT10 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " LUT9_CMPLT_IRQ_EN ,LUT9 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 8. " LUT8_CMPLT_IRQ_EN ,LUT8 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " LUT7_CMPLT_IRQ_EN ,LUT7 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 6. " LUT6_CMPLT_IRQ_EN ,LUT6 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " LUT5_CMPLT_IRQ_EN ,LUT5 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " LUT4_CMPLT_IRQ_EN ,LUT4 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " LUT3_CMPLT_IRQ_EN ,LUT3 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 2. " LUT2_CMPLT_IRQ_EN ,LUT2 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " LUT1_CMPLT_IRQ_EN ,LUT1 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " LUT0_CMPLT_IRQ_EN ,LUT0 Complete Interrupt Clear" "No effect,Cleared"
|
|
line.long 0x0C "IRQ_MASK_TOG,EPDC IRQ Mask Register"
|
|
bitfld.long 0x0C 21. " TCE_IDLE_IRQ_EN ,Toggle TCE Idle interrupt detection" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 20. " BUS_ERROR_IRQ_EN ,Toggle AXI BUS ERROR interrupt detection" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " FRAME_END_IRQ_EN ,Current Frame End Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 18. " TCE_UNDERRUN_IRQ_EN ,Toggle pixel FIFO under-run condition detection" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " COL_IRQ_EN ,Toggle collision detection interrupts for all LUTs" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 16. " WB_CMPLT_IRQ_EN ,Toggle WB complete interrupt" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " LUT15_CMPLT_IRQ_EN ,LUT15 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 14. " LUT14_CMPLT_IRQ_EN ,LUT14 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " LUT13_CMPLT_IRQ_EN ,LUT13 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 12. " LUT12_CMPLT_IRQ_EN ,LUT12 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " LUT11_CMPLT_IRQ_EN ,LUT11 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 10. " LUT10_CMPLT_IRQ_EN ,LUT10 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " LUT9_CMPLT_IRQ_EN ,LUT9 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 8. " LUT8_CMPLT_IRQ_EN ,LUT8 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " LUT7_CMPLT_IRQ_EN ,LUT7 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 6. " LUT6_CMPLT_IRQ_EN ,LUT6 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " LUT5_CMPLT_IRQ_EN ,LUT5 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 4. " LUT4_CMPLT_IRQ_EN ,LUT4 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " LUT3_CMPLT_IRQ_EN ,LUT3 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2. " LUT2_CMPLT_IRQ_EN ,LUT2 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " LUT1_CMPLT_IRQ_EN ,LUT1 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 0. " LUT0_CMPLT_IRQ_EN ,LUT0 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
group.long 0x420++0x0F
|
|
line.long 0x00 "IRQ,EPDC IRQ Mask Register"
|
|
bitfld.long 0x00 21. " TCE_IDLE_IRQ ,TCE Idle interrupt detection" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " BUS_ERROR_IRQ ,AXI BUS ERROR interrupt detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FRAME_END_IRQ ,Current Frame End Interrupt Assertion" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " TCE_UNDERRUN_IRQ ,Pixel FIFO under-run condition detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " COL_IRQ ,Collision detection interrupts for all LUTs" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " WB_CMPLT_IRQ ,WB complete interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LUT15_CMPLT_IRQ ,LUT15 Complete Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " LUT14_CMPLT_IRQ ,LUT14 Complete Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LUT13_CMPLT_IRQ ,LUT13 Complete Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " LUT12_CMPLT_IRQ ,LUT12 Complete Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LUT11_CMPLT_IRQ ,LUT11 Complete Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " LUT10_CMPLT_IRQ ,LUT10 Complete Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LUT9_CMPLT_IRQ ,LUT9 Complete Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " LUT8_CMPLT_IRQ ,LUT8 Complete Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LUT7_CMPLT_IRQ ,LUT7 Complete Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " LUT6_CMPLT_IRQ ,LUT6 Complete Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LUT5_CMPLT_IRQ ,LUT5 Complete Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " LUT4_CMPLT_IRQ ,LUT4 Complete Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LUT3_CMPLT_IRQ ,LUT3 Complete Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " LUT2_CMPLT_IRQ ,LUT2 Complete Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LUT1_CMPLT_IRQ ,LUT1 Complete Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " LUT0_CMPLT_IRQ ,LUT0 Complete Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRQ_SET,EPDC IRQ Mask Register"
|
|
bitfld.long 0x04 21. " TCE_IDLE_IRQ ,Set TCE Idle interrupt detection" "No effect,Set"
|
|
bitfld.long 0x04 20. " BUS_ERROR_IRQ ,Set AXI BUS ERROR interrupt detection" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FRAME_END_IRQ ,Current Frame End Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 18. " TCE_UNDERRUN_IRQ ,Set pixel FIFO under-run condition detection" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 17. " COL_IRQ ,Set collision detection interrupts for all LUTs" "No effect,Set"
|
|
bitfld.long 0x04 16. " WB_CMPLT_IRQ ,Set WB complete interrupt" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LUT15_CMPLT_IRQ ,LUT15 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 14. " LUT14_CMPLT_IRQ ,LUT14 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 13. " LUT13_CMPLT_IRQ ,LUT13 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 12. " LUT12_CMPLT_IRQ ,LUT12 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LUT11_CMPLT_IRQ ,LUT11 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 10. " LUT10_CMPLT_IRQ ,LUT10 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LUT9_CMPLT_IRQ ,LUT9 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 8. " LUT8_CMPLT_IRQ ,LUT8 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LUT7_CMPLT_IRQ ,LUT7 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 6. " LUT6_CMPLT_IRQ ,LUT6 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " LUT5_CMPLT_IRQ ,LUT5 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 4. " LUT4_CMPLT_IRQ ,LUT4 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LUT3_CMPLT_IRQ ,LUT3 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 2. " LUT2_CMPLT_IRQ ,LUT2 Complete Interrupt Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LUT1_CMPLT_IRQ ,LUT1 Complete Interrupt Set" "No effect,Set"
|
|
bitfld.long 0x04 0. " LUT0_CMPLT_IRQ ,LUT0 Complete Interrupt Set" "No effect,Set"
|
|
line.long 0x08 "IRQ_CLR,EPDC IRQ Mask Register"
|
|
bitfld.long 0x08 21. " TCE_IDLE_IRQ ,Clear TCE Idle interrupt detection" "No effect,Cleared"
|
|
bitfld.long 0x08 20. " BUS_ERROR_IRQ ,Clear AXI BUS ERROR interrupt detection" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " FRAME_END_IRQ ,Current Frame End Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 18. " TCE_UNDERRUN_IRQ ,Clear pixel FIFO under-run condition detection" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " COL_IRQ ,Clear collision detection interrupts for all LUTs" "No effect,Cleared"
|
|
bitfld.long 0x08 16. " WB_CMPLT_IRQ ,Clear WB complete interrupt" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " LUT15_CMPLT_IRQ ,LUT15 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 14. " LUT14_CMPLT_IRQ ,LUT14 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " LUT13_CMPLT_IRQ ,LUT13 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 12. " LUT12_CMPLT_IRQ ,LUT12 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " LUT11_CMPLT_IRQ ,LUT11 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 10. " LUT10_CMPLT_IRQ ,LUT10 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " LUT9_CMPLT_IRQ ,LUT9 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 8. " LUT8_CMPLT_IRQ ,LUT8 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " LUT7_CMPLT_IRQ ,LUT7 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 6. " LUT6_CMPLT_IRQ ,LUT6 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " LUT5_CMPLT_IRQ ,LUT5 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " LUT4_CMPLT_IRQ ,LUT4 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " LUT3_CMPLT_IRQ ,LUT3 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 2. " LUT2_CMPLT_IRQ ,LUT2 Complete Interrupt Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " LUT1_CMPLT_IRQ ,LUT1 Complete Interrupt Clear" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " LUT0_CMPLT_IRQ ,LUT0 Complete Interrupt Clear" "No effect,Cleared"
|
|
line.long 0x0C "IRQ_TOG,EPDC IRQ Mask Register"
|
|
bitfld.long 0x0C 21. " TCE_IDLE_IRQ ,Toggle TCE Idle interrupt detection" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 20. " BUS_ERROR_IRQ ,Toggle AXI BUS ERROR interrupt detection" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " FRAME_END_IRQ ,Current Frame End Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 18. " TCE_UNDERRUN_IRQ ,Toggle pixel FIFO under-run condition detection" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " COL_IRQ ,Toggle collision detection interrupts for all LUTs" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 16. " WB_CMPLT_IRQ ,Toggle WB complete interrupt" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " LUT15_CMPLT_IRQ ,LUT15 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 14. " LUT14_CMPLT_IRQ ,LUT14 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " LUT13_CMPLT_IRQ ,LUT13 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 12. " LUT12_CMPLT_IRQ ,LUT12 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " LUT11_CMPLT_IRQ ,LUT11 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 10. " LUT10_CMPLT_IRQ ,LUT10 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " LUT9_CMPLT_IRQ ,LUT9 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 8. " LUT8_CMPLT_IRQ ,LUT8 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " LUT7_CMPLT_IRQ ,LUT7 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 6. " LUT6_CMPLT_IRQ ,LUT6 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " LUT5_CMPLT_IRQ ,LUT5 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 4. " LUT4_CMPLT_IRQ ,LUT4 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " LUT3_CMPLT_IRQ ,LUT3 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2. " LUT2_CMPLT_IRQ ,LUT2 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " LUT1_CMPLT_IRQ ,LUT1 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 0. " LUT0_CMPLT_IRQ ,LUT0 Complete Interrupt Toggle" "Not toggled,Toggled"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "STATUS_LUTS,EPDC Status Register - LUTs"
|
|
bitfld.long 0x00 15. " LUTN_STS ,LUT15 Status" "Idle,Active"
|
|
bitfld.long 0x00 14. " LUTN_STS ,LUT14 Status" "Idle,Active"
|
|
bitfld.long 0x00 13. " LUTN_STS ,LUT13 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LUTN_STS ,LUT12 Status" "Idle,Active"
|
|
bitfld.long 0x00 11. " LUTN_STS ,LUT11 Status" "Idle,Active"
|
|
bitfld.long 0x00 10. " LUTN_STS ,LUT10 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LUTN_STS ,LUT9 Status" "Idle,Active"
|
|
bitfld.long 0x00 8. " LUTN_STS ,LUT8 Status" "Idle,Active"
|
|
bitfld.long 0x00 7. " LUTN_STS ,LUT7 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LUTN_STS ,LUT6 Status" "Idle,Active"
|
|
bitfld.long 0x00 5. " LUTN_STS ,LUT5 Status" "Idle,Active"
|
|
bitfld.long 0x00 4. " LUTN_STS ,LUT4 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LUTN_STS ,LUT3 Status" "Idle,Active"
|
|
bitfld.long 0x00 2. " LUTN_STS ,LUT2 Status" "Idle,Active"
|
|
bitfld.long 0x00 1. " LUTN_STS ,LUT1 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LUTN_STS ,LUT0 Status" "Idle,Active"
|
|
group.long 0x444++0x0B
|
|
line.long 0x00 "STATUS_LUTS_SET,EPDC Status Set Register - LUTs"
|
|
bitfld.long 0x00 15. " LUTN_STS ,LUT15 Status Set" "No effect,Set"
|
|
bitfld.long 0x00 14. " LUTN_STS ,LUT14 Status Set" "No effect,Set"
|
|
bitfld.long 0x00 13. " LUTN_STS ,LUT13 Status Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LUTN_STS ,LUT12 Status Set" "No effect,Set"
|
|
bitfld.long 0x00 11. " LUTN_STS ,LUT11 Status Set" "No effect,Set"
|
|
bitfld.long 0x00 10. " LUTN_STS ,LUT10 Status Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LUTN_STS ,LUT9 Status Set" "No effect,Set"
|
|
bitfld.long 0x00 8. " LUTN_STS ,LUT8 Status Set" "No effect,Set"
|
|
bitfld.long 0x00 7. " LUTN_STS ,LUT7 Status Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LUTN_STS ,LUT6 Status Set" "No effect,Set"
|
|
bitfld.long 0x00 5. " LUTN_STS ,LUT5 Status Set" "No effect,Set"
|
|
bitfld.long 0x00 4. " LUTN_STS ,LUT4 Status Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LUTN_STS ,LUT3 Status Set" "No effect,Set"
|
|
bitfld.long 0x00 2. " LUTN_STS ,LUT2 Status Set" "No effect,Set"
|
|
bitfld.long 0x00 1. " LUTN_STS ,LUT1 Status Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LUTN_STS ,LUT0 Status Set" "No effect,Set"
|
|
line.long 0x04 "STATUS_LUTS_CLR,EPDC Status Clear Register - LUTs"
|
|
bitfld.long 0x04 15. " LUTN_STS ,LUT15 Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 14. " LUTN_STS ,LUT14 Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 13. " LUTN_STS ,LUT13 Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " LUTN_STS ,LUT12 Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 11. " LUTN_STS ,LUT11 Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 10. " LUTN_STS ,LUT10 Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LUTN_STS ,LUT9 Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 8. " LUTN_STS ,LUT8 Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 7. " LUTN_STS ,LUT7 Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " LUTN_STS ,LUT6 Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 5. " LUTN_STS ,LUT5 Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 4. " LUTN_STS ,LUT4 Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LUTN_STS ,LUT3 Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 2. " LUTN_STS ,LUT2 Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 1. " LUTN_STS ,LUT1 Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 0. " LUTN_STS ,LUT0 Status Clear" "No effect,Cleared"
|
|
line.long 0x08 "STATUS_LUTS_TOG,EPDC Status Toggle Register - LUTs"
|
|
bitfld.long 0x08 15. " LUTN_STS ,LUT15 Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 14. " LUTN_STS ,LUT14 Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 13. " LUTN_STS ,LUT13 Status Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " LUTN_STS ,LUT12 Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 11. " LUTN_STS ,LUT11 Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 10. " LUTN_STS ,LUT10 Status Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " LUTN_STS ,LUT9 Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 8. " LUTN_STS ,LUT8 Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 7. " LUTN_STS ,LUT7 Status Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " LUTN_STS ,LUT6 Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 5. " LUTN_STS ,LUT5 Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 4. " LUTN_STS ,LUT4 Status Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " LUTN_STS ,LUT3 Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 2. " LUTN_STS ,LUT2 Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 1. " LUTN_STS ,LUT1 Status Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " LUTN_STS ,LUT0 Status Toggle" "Not toggled,Toggled"
|
|
rgroup.long 0x460++0x03
|
|
line.long 0x00 "STATUS_NEXTLUT,EPDC Status Register - Next Available LUT"
|
|
bitfld.long 0x00 8. " NEXT_LUT_VALID ,Checks against a LUTs full condition" "Not checked,Checked"
|
|
bitfld.long 0x00 0.--3. " NEXT_LUT ,Next available LUT value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x480++0x03
|
|
line.long 0x00 "STATUS_COL,EPDC LUT Collision Status"
|
|
bitfld.long 0x00 15. " LUTN_COL_STS ,LUT15 Collision Status" "No collision,Collision"
|
|
bitfld.long 0x00 14. " LUTN_COL_STS ,LUT14 Collision Status" "No collision,Collision"
|
|
bitfld.long 0x00 13. " LUTN_COL_STS ,LUT13 Collision Status" "No collision,Collision"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LUTN_COL_STS ,LUT12 Collision Status" "No collision,Collision"
|
|
bitfld.long 0x00 11. " LUTN_COL_STS ,LUT11 Collision Status" "No collision,Collision"
|
|
bitfld.long 0x00 10. " LUTN_COL_STS ,LUT10 Collision Status" "No collision,Collision"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LUTN_COL_STS ,LUT9 Collision Status" "No collision,Collision"
|
|
bitfld.long 0x00 8. " LUTN_COL_STS ,LUT8 Collision Status" "No collision,Collision"
|
|
bitfld.long 0x00 7. " LUTN_COL_STS ,LUT7 Collision Status" "No collision,Collision"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LUTN_COL_STS ,LUT6 Collision Status" "No collision,Collision"
|
|
bitfld.long 0x00 5. " LUTN_COL_STS ,LUT5 Collision Status" "No collision,Collision"
|
|
bitfld.long 0x00 4. " LUTN_COL_STS ,LUT4 Collision Status" "No collision,Collision"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LUTN_COL_STS ,LUT3 Collision Status" "No collision,Collision"
|
|
bitfld.long 0x00 2. " LUTN_COL_STS ,LUT2 Collision Status" "No collision,Collision"
|
|
bitfld.long 0x00 1. " LUTN_COL_STS ,LUT1 Collision Status" "No collision,Collision"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LUTN_COL_STS ,LUT0 Collision Status" "No collision,Collision"
|
|
group.long 0x484++0x0B
|
|
line.long 0x00 "STATUS_COL_SET,EPDC LUT Collision Status Set"
|
|
bitfld.long 0x00 15. " LUTN_COL_STS ,LUT15 Collision Status Set" "No effect,Set"
|
|
bitfld.long 0x00 14. " LUTN_COL_STS ,LUT14 Collision Status Set" "No effect,Set"
|
|
bitfld.long 0x00 13. " LUTN_COL_STS ,LUT13 Collision Status Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LUTN_COL_STS ,LUT12 Collision Status Set" "No effect,Set"
|
|
bitfld.long 0x00 11. " LUTN_COL_STS ,LUT11 Collision Status Set" "No effect,Set"
|
|
bitfld.long 0x00 10. " LUTN_COL_STS ,LUT10 Collision Status Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LUTN_COL_STS ,LUT9 Collision Status Set" "No effect,Set"
|
|
bitfld.long 0x00 8. " LUTN_COL_STS ,LUT8 Collision Status Set" "No effect,Set"
|
|
bitfld.long 0x00 7. " LUTN_COL_STS ,LUT7 Collision Status Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LUTN_COL_STS ,LUT6 Collision Status Set" "No effect,Set"
|
|
bitfld.long 0x00 5. " LUTN_COL_STS ,LUT5 Collision Status Set" "No effect,Set"
|
|
bitfld.long 0x00 4. " LUTN_COL_STS ,LUT4 Collision Status Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LUTN_COL_STS ,LUT3 Collision Status Set" "No effect,Set"
|
|
bitfld.long 0x00 2. " LUTN_COL_STS ,LUT2 Collision Status Set" "No effect,Set"
|
|
bitfld.long 0x00 1. " LUTN_COL_STS ,LUT1 Collision Status Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LUTN_COL_STS ,LUT0 Collision Status Set" "No effect,Set"
|
|
line.long 0x04 "STATUS_COL_CLR,EPDC LUT Collision Status Clear"
|
|
bitfld.long 0x04 15. " LUTN_COL_STS ,LUT15 Collision Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 14. " LUTN_COL_STS ,LUT14 Collision Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 13. " LUTN_COL_STS ,LUT13 Collision Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " LUTN_COL_STS ,LUT12 Collision Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 11. " LUTN_COL_STS ,LUT11 Collision Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 10. " LUTN_COL_STS ,LUT10 Collision Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LUTN_COL_STS ,LUT9 Collision Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 8. " LUTN_COL_STS ,LUT8 Collision Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 7. " LUTN_COL_STS ,LUT7 Collision Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " LUTN_COL_STS ,LUT6 Collision Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 5. " LUTN_COL_STS ,LUT5 Collision Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 4. " LUTN_COL_STS ,LUT4 Collision Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LUTN_COL_STS ,LUT3 Collision Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 2. " LUTN_COL_STS ,LUT2 Collision Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 1. " LUTN_COL_STS ,LUT1 Collision Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 0. " LUTN_COL_STS ,LUT0 Collision Status Clear" "No effect,Cleared"
|
|
line.long 0x08 "STATUS_COL_TOG,EPDC LUT Collision Status Toggle"
|
|
bitfld.long 0x08 15. " LUTN_COL_STS ,LUT15 Collision Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 14. " LUTN_COL_STS ,LUT14 Collision Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 13. " LUTN_COL_STS ,LUT13 Collision Status Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " LUTN_COL_STS ,LUT12 Collision Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 11. " LUTN_COL_STS ,LUT11 Collision Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 10. " LUTN_COL_STS ,LUT10 Collision Status Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " LUTN_COL_STS ,LUT9 Collision Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 8. " LUTN_COL_STS ,LUT8 Collision Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 7. " LUTN_COL_STS ,LUT7 Collision Status Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " LUTN_COL_STS ,LUT6 Collision Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 5. " LUTN_COL_STS ,LUT5 Collision Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 4. " LUTN_COL_STS ,LUT4 Collision Status Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " LUTN_COL_STS ,LUT3 Collision Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 2. " LUTN_COL_STS ,LUT2 Collision Status Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x08 1. " LUTN_COL_STS ,LUT1 Collision Status Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " LUTN_COL_STS ,LUT0 Collision Status Toggle" "Not toggled,Toggled"
|
|
rgroup.long 0x4A0++0x03
|
|
line.long 0x00 "STATUS,EPDC General Status Register"
|
|
bitfld.long 0x00 2. " LUTS_UNDERRUN ,Status of LUT fill" "Completed all,Not enough time"
|
|
bitfld.long 0x00 1. " LUTS_BUSY ,Status of LUTs" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WB_BUSY ,Working buffer process" "Not busy,Busy"
|
|
group.long 0x4A4++0x0B
|
|
line.long 0x00 "STATUS_SET,EPDC General Status Set Register"
|
|
bitfld.long 0x00 2. " LUTS_UNDERRUN ,Status of LUT fill" "No effect,Set"
|
|
bitfld.long 0x00 1. " LUTS_BUSY ,Status of LUTs" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WB_BUSY ,Working buffer process" "No effect,Set"
|
|
line.long 0x04 "STATUS_CLR,EPDC General Status Clear Register"
|
|
bitfld.long 0x04 2. " LUTS_UNDERRUN ,Status of LUT fill" "No effect,Cleared"
|
|
bitfld.long 0x04 1. " LUTS_BUSY ,Status of LUTs" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 0. " WB_BUSY ,Working buffer process" "No effect,Cleared"
|
|
line.long 0x08 "STATUS_TOG,EPDC General Status Toggle Register"
|
|
bitfld.long 0x08 2. " LUTS_UNDERRUN ,Status of LUT fill" "Not toggled,Toggled"
|
|
bitfld.long 0x08 1. " LUTS_BUSY ,Status of LUTs" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " WB_BUSY ,Working buffer process" "Not toggled,Toggled"
|
|
group.long 0x500++0x0F
|
|
line.long 0x00 "DEBUG,EPDC Debug Register"
|
|
bitfld.long 0x00 1. " UNDERRUN_RECOVER ,Display recover at next VSYNC after FIFO underrun enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COLLISION_OFF ,Collision detection bypass enable" "Disabled,Enabled"
|
|
line.long 0x04 "DEBUG_SET,EPDC Debug Register"
|
|
bitfld.long 0x04 1. " UNDERRUN_RECOVER ,Display recover at next VSYNC after FIFO underrun set" "No effect,Set"
|
|
bitfld.long 0x04 0. " COLLISION_OFF ,Collision detection bypass set" "No effect,Set"
|
|
line.long 0x08 "DEBUG_CLR,EPDC Debug Register"
|
|
bitfld.long 0x08 1. " UNDERRUN_RECOVER ,Display recover at next VSYNC after FIFO underrun clear" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " COLLISION_OFF ,Collision detection bypass clear" "No effect,Cleared"
|
|
line.long 0x0C "DEBUG_TOG,EPDC Debug Register"
|
|
bitfld.long 0x0C 1. " UNDERRUN_RECOVER ,Display recover at next VSYNC after FIFO underrun toggle" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 0. " COLLISION_OFF ,Collision detection bypass toggle" "Not toggled,Toggled"
|
|
rgroup.long 0x540++0x03
|
|
line.long 0x00 "DEBUG_LUT0,EPDC LUT0 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT0 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x550++0x03
|
|
line.long 0x00 "DEBUG_LUT1,EPDC LUT1 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT1 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x560++0x03
|
|
line.long 0x00 "DEBUG_LUT2,EPDC LUT2 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT2 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x570++0x03
|
|
line.long 0x00 "DEBUG_LUT3,EPDC LUT3 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT3 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x580++0x03
|
|
line.long 0x00 "DEBUG_LUT4,EPDC LUT4 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT4 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x590++0x03
|
|
line.long 0x00 "DEBUG_LUT5,EPDC LUT5 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT5 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x5A0++0x03
|
|
line.long 0x00 "DEBUG_LUT6,EPDC LUT6 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT6 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x5B0++0x03
|
|
line.long 0x00 "DEBUG_LUT7,EPDC LUT7 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT7 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x5C0++0x03
|
|
line.long 0x00 "DEBUG_LUT8,EPDC LUT8 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT8 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x5D0++0x03
|
|
line.long 0x00 "DEBUG_LUT9,EPDC LUT9 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT9 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x5E0++0x03
|
|
line.long 0x00 "DEBUG_LUT10,EPDC LUT10 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT10 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x5F0++0x03
|
|
line.long 0x00 "DEBUG_LUT11,EPDC LUT11 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT11 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "DEBUG_LUT12,EPDC LUT12 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT12 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x610++0x03
|
|
line.long 0x00 "DEBUG_LUT13,EPDC LUT13 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT13 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x620++0x03
|
|
line.long 0x00 "DEBUG_LUT14,EPDC LUT14 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT14 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
rgroup.long 0x630++0x03
|
|
line.long 0x00 "DEBUG_LUT15,EPDC LUT15 Debug Information register"
|
|
hexmask.long.word 0x00 16.--25. 0x1 " LUTADDR ,LUT address to be filled"
|
|
hexmask.long.word 0x00 5.--14. 0x1 " FRAME ,The remaining number of frames for this update"
|
|
bitfld.long 0x00 0.--4. " STATEMACHINE ,LUT15 state machine" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F,10,11,12,13,14,15,16,17,18,19,1A,1B,1C,1D,1E,1F"
|
|
group.long 0x700++0x0F
|
|
line.long 0x00 "GPIO,EPDC General Purpose I/O Debug register"
|
|
bitfld.long 0x00 6. " PWRCOM ,ipp_epdc_pwrcom output control" "0,1"
|
|
bitfld.long 0x00 2.--5. " PWRCTRL ,ipp_epdc_pwrctrl[3:0] output control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--1. " BDR ,ipp_epdc_bdr[1:0] output control" "0,1,2,3"
|
|
line.long 0x04 "GPIO_SET,EPDC General Purpose I/O Debug register"
|
|
bitfld.long 0x04 6. " PWRCOM ,ipp_epdc_pwrcom output control" "No effect,Set"
|
|
bitfld.long 0x04 2.--5. " PWRCTRL ,ipp_epdc_pwrctrl[3:0] output control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--1. " BDR ,ipp_epdc_bdr[1:0] output control" "0,1,2,3"
|
|
line.long 0x08 "GPIO_CLR,EPDC General Purpose I/O Debug register"
|
|
bitfld.long 0x08 6. " PWRCOM ,ipp_epdc_pwrcom output control" "No effect,Clear"
|
|
bitfld.long 0x08 2.--5. " PWRCTRL ,ipp_epdc_pwrctrl[3:0] output control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--1. " BDR ,ipp_epdc_bdr[1:0] output control" "0,1,2,3"
|
|
line.long 0x0C "GPIO_TOG,EPDC General Purpose I/O Debug register"
|
|
bitfld.long 0x0C 6. " PWRCOM ,ipp_epdc_pwrcom output control" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2.--5. " PWRCTRL ,ipp_epdc_pwrctrl[3:0] output control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--1. " BDR ,ipp_epdc_bdr[1:0] output control" "0,1,2,3"
|
|
rgroup.long 0x7F0++0x03
|
|
line.long 0x00 "VERSION,EPDC Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version"
|
|
hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "EPIT (Enhanced Periodic Interrupt Timer)"
|
|
base ad:0x53fac000
|
|
width 12.
|
|
if ((per.l(ad:0x53fac000)&0x8)==0x8)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EPITCR1,EPIT Control Register"
|
|
sif (cpuis("IMX6*")||cpuis("IMX50*"))
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Clock Source" "Clock is off,Peripheral clock,High-frequency reference clock,Low-frequency reference clock"
|
|
else
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Select Clock Source" "Clock is off,Ipg_clk,Ipg_clk_highfreq,Ipg_clk_32k"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OM ,EPIT Output Configuration" "Disconnected,Toggled,Cleared,Set"
|
|
bitfld.long 0x00 21. " STOPEN ,EPIT Stop Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WAITEN ,EPIT Wait Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DBGEN ,Debug Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOVW ,EPIT Counter Overwrite Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SWR ,Software Reset" "Out of reset,Reset"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value"
|
|
bitfld.long 0x00 3. " RLD ,Counter Reload Control" "Free running,Set and Forget"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OCIEN ,Output Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENMOD ,EPIT Enable Mode" "Current value,Load value"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,EPIT Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EPITCR1,EPIT Control Register"
|
|
sif (cpuis("IMX6*")||cpuis("IMX50*"))
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Clock Source" "Clock is off,Peripheral clock,High-frequency reference clock,Low-frequency reference clock"
|
|
else
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Select Clock Source" "Clock is off,Ipg_clk,Ipg_clk_highfreq,Ipg_clk_32k"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OM ,EPIT Output Configuration" "Disconnected,Toggled,Cleared,Set"
|
|
bitfld.long 0x00 21. " STOPEN ,EPIT Stop Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WAITEN ,EPIT Wait Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DBGEN ,Debug Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOVW ,EPIT Counter Overwrite Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SWR ,Software Reset" "Out of reset,Reset"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value"
|
|
bitfld.long 0x00 3. " RLD ,Counter Reload Control" "Free running,Set and Forget"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OCIEN ,Output Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENMOD ,EPIT Enable Mode" "Current value,0xFFFFFFFF"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,EPIT Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x0b
|
|
line.long 0x00 "EPITSR1,EPIT Status Register"
|
|
eventfld.long 0x00 0. " OCIF ,Output Compare Interrupt Flag" "Not occurred,Occurred"
|
|
line.long 0x04 "EPITLR1,EPIT Load Register"
|
|
line.long 0x08 "EPITCMPR1,EPIT Compare Register"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "EPITCNR1,EPIT Counter Register"
|
|
width 0xb
|
|
tree.end
|
|
tree.open "eSDHC (Enhanced Secure Digital Host Controller)"
|
|
tree "eSDHC 1"
|
|
base ad:0x50004000
|
|
width 12.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "DSADDR,DMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DS_ADDR ,DMA System Address"
|
|
line.long 0x04 "BLKATTR,Block Attributes Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer"
|
|
hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size"
|
|
line.long 0x08 "CMDARG,Command Argument Register"
|
|
line.long 0x0C "XFERTYP,Transfer Type Register"
|
|
hexmask.long.byte 0x0C 24.--29. 1. " CMDINX ,Command Index"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " CMDTYP ,Command Type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present"
|
|
bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No Response,Length 136,Length 48,Length 48 check busy"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " MSBSEL ,Multi / Single Block Select" "Single,Multiple"
|
|
bitfld.long 0x0C 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read"
|
|
textline " "
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
bitfld.long 0x0C 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " BCEN ,Block Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
if (((per.long(ad:0x50004000+0x0c))&0x30000)==0x00)
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CMDRSP0,Command Response 0"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
elif (((per.long(ad:0x50004000+0x0c))&0x30000)==0x10000)
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R2 response"
|
|
line.long 0x04 "CMDRSP1,Command Response 1"
|
|
hexmask.long 0x04 0.--31. 1. " CMDRSP1 ,R2 response"
|
|
line.long 0x08 "CMDRSP2,Command Response 2"
|
|
hexmask.long 0x08 0.--31. 1. " CMDRSP2 ,R2 response"
|
|
line.long 0x0C "CMDRSP3,Command Response 3"
|
|
hexmask.long.tbyte 0x0c 0.--23. 1. " CMDRSP3 ,R2[23:0] response"
|
|
elif (((per.long(ad:0x50004000+0x0c))&0x30000)==0x20000)
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1/R3/R4/R5/R6 response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1b/R5b response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "CMDRSP3,Command Response 3"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP3 ,R1b response"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DATPORT,Buffer Data Port Register"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "PRSSTAT,Present State Register"
|
|
bitfld.long 0x00 31. " DLSL[7] ,Line 7 Signal Level" "Low,High"
|
|
bitfld.long 0x00 30. " DLSL[6] ,Line 6 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DLSL[5] ,Line 5 Signal Level" "Low,High"
|
|
bitfld.long 0x00 28. " DLSL[4] ,Line 4 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DLSL[3] ,Line 3 Signal Level" "Low,High"
|
|
bitfld.long 0x00 26. " DLSL[2] ,Line 2 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DLSL[1] ,Line 1 Signal Level" "Low,High"
|
|
bitfld.long 0x00 24. " DLSL[0] ,Line 0 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "No card,Card present"
|
|
bitfld.long 0x00 16. " CINS ,Card Inserted" "No card/Reset/Power on,Card inserted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RTA ,Read Transfer Active" "No data,Transferring"
|
|
bitfld.long 0x00 8. " WTA ,Write Transfer Active" "No data,Transferring"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Not stable,Stable"
|
|
bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Can issue,Cannot issue"
|
|
bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Can issue,Cannot issue"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "PROCTL,Protocol Control Register"
|
|
bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transfer,Stop"
|
|
bitfld.long 0x00 8.--9. " DMAS ,DMA Select" "No/Simple DMA,ADMA1,ADMA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Level,Test level"
|
|
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "No card,Card present"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian,?..."
|
|
bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " DTW ,Data Transfer Width" "1-bit,4-bit,8-bit,?..."
|
|
bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx213,SDCLKx214,SDCLKx215,SDCLKx216,SDCLKx217,SDCLKx218,SDCLKx219,SDCLKx220,SDCLKx221,SDCLKx222,SDCLKx223,SDCLKx224,SDCLKx225,SDCLKx226,SDCLKx227,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,SD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx2^13,SDCLKx2^14,SDCLKx2^15,SDCLKx2^16,SDCLKx2^17,SDCLKx2^18,SDCLKx2^19,SDCLKx2^20,SDCLKx2^21,SDCLKx2^22,SDCLKx2^23,SDCLKx2^24,SDCLKx2^25,SDCLKx2^26,SDCLKx2^27,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,PSD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
endif
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "IRQSTAT,Interrupt Status Register"
|
|
eventfld.long 0x00 28. " DMAE ,DMA Error" "No error,Error"
|
|
eventfld.long 0x00 24. " AC12E ,Auto CMD12 Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 22. " DEBE ,Data End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 21. " DCE ,Data CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 20. " DTOE ,Data Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 19. " CIE ,Command Index Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " CEBE ,Command End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 17. " CCE ,Command CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CTOE ,Command Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 8. " CINT ,Card Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CRM ,Card Removal" "Unstable/Inserted,Removed"
|
|
eventfld.long 0x00 6. " CINS ,Card Insertion" "Unstable/Removed,Inserted"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BRR ,Buffer Read Ready" "Not ready,Ready"
|
|
eventfld.long 0x00 4. " BWR ,Buffer Write Ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " BGE ,Block Gap Event" "No event,Event occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TC ,Transfer Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " CC ,Command Complete" "Not completed,Completed"
|
|
width 12.
|
|
line.long 0x04 "IRQSTATEN,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " CINSEN ,Card Insertion Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled"
|
|
line.long 0x08 "IRQSIGEN,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CINTIEN ,Card Interrupt Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 6. " CINIEN ,Card Insertion Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled"
|
|
if (((per.long(ad:0x50004000+0x30))&0x1000000)==0x1000000)
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued"
|
|
bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error"
|
|
bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error"
|
|
bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed"
|
|
else
|
|
hgroup.long 0x3C++0x3
|
|
hide.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
endif
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "HOSTCAPBLT,Host Controller Capabilities"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 16.--18. " MBL ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..."
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "WML,Watermark Level Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " WR_BRST_LEN ,Write Burst Length"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WR_WML ,Write Watermark Level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--12. 1. " RD_BRST_LEN ,Read Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RD_WML ,Read Watermark Level"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x00 "FEVT,Force Event Register"
|
|
bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "No effect,Force"
|
|
bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "No effect,Force"
|
|
bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "No effect,Force"
|
|
bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "No effect,Force"
|
|
bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "No effect,Force"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error"
|
|
bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State" "ST_STOP,ST_FDS,ST_CADR,ST_TFR"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADSADDR,ADMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR ,ADMA System Address"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "VENDOR,Vendor Specific Register"
|
|
bitfld.long 0x00 24.--27. " DBG_SEL ,Debug Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 1. " EXACT_BLK_NUM ,Exact block number block read enable for SDIO CMD53" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "MMCBOOT,MMC Boot Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT[15:0] ,Stop At Block Gap value of automatic mode"
|
|
bitfld.long 0x00 7. " AUTO_SABG_EN ,Auto stop at block gap function" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BOOT_EN ,Fast boot" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MMC_BOOT_MODE ,Boot mode select" "Normal,Alternative"
|
|
bitfld.long 0x00 4. " BOOT_ACK ,Boot ack mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DTOCV_ACK[3:0] ,Boot ACK time out counter value" "SDCLK x 2^8,SDCLK x 2^9,SDCLK x 2^10,SDCLK x 2^11,SDCLK x 2^12,SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,?..."
|
|
endif
|
|
rgroup.long 0xfc++0x3
|
|
line.long 0x00 "HOSTVER,Host Controller Version"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VVN[7:0] ,Vendor Version Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SVN[7:0] ,Specification Version Number"
|
|
width 0xb
|
|
tree.end
|
|
tree "eSDHC 2"
|
|
base ad:0x50008000
|
|
width 12.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "DSADDR,DMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DS_ADDR ,DMA System Address"
|
|
line.long 0x04 "BLKATTR,Block Attributes Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer"
|
|
hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size"
|
|
line.long 0x08 "CMDARG,Command Argument Register"
|
|
line.long 0x0C "XFERTYP,Transfer Type Register"
|
|
hexmask.long.byte 0x0C 24.--29. 1. " CMDINX ,Command Index"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " CMDTYP ,Command Type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present"
|
|
bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No Response,Length 136,Length 48,Length 48 check busy"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " MSBSEL ,Multi / Single Block Select" "Single,Multiple"
|
|
bitfld.long 0x0C 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read"
|
|
textline " "
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
bitfld.long 0x0C 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " BCEN ,Block Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
if (((per.long(ad:0x50008000+0x0c))&0x30000)==0x00)
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CMDRSP0,Command Response 0"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
elif (((per.long(ad:0x50008000+0x0c))&0x30000)==0x10000)
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R2 response"
|
|
line.long 0x04 "CMDRSP1,Command Response 1"
|
|
hexmask.long 0x04 0.--31. 1. " CMDRSP1 ,R2 response"
|
|
line.long 0x08 "CMDRSP2,Command Response 2"
|
|
hexmask.long 0x08 0.--31. 1. " CMDRSP2 ,R2 response"
|
|
line.long 0x0C "CMDRSP3,Command Response 3"
|
|
hexmask.long.tbyte 0x0c 0.--23. 1. " CMDRSP3 ,R2[23:0] response"
|
|
elif (((per.long(ad:0x50008000+0x0c))&0x30000)==0x20000)
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1/R3/R4/R5/R6 response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1b/R5b response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "CMDRSP3,Command Response 3"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP3 ,R1b response"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DATPORT,Buffer Data Port Register"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "PRSSTAT,Present State Register"
|
|
bitfld.long 0x00 31. " DLSL[7] ,Line 7 Signal Level" "Low,High"
|
|
bitfld.long 0x00 30. " DLSL[6] ,Line 6 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DLSL[5] ,Line 5 Signal Level" "Low,High"
|
|
bitfld.long 0x00 28. " DLSL[4] ,Line 4 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DLSL[3] ,Line 3 Signal Level" "Low,High"
|
|
bitfld.long 0x00 26. " DLSL[2] ,Line 2 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DLSL[1] ,Line 1 Signal Level" "Low,High"
|
|
bitfld.long 0x00 24. " DLSL[0] ,Line 0 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "No card,Card present"
|
|
bitfld.long 0x00 16. " CINS ,Card Inserted" "No card/Reset/Power on,Card inserted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RTA ,Read Transfer Active" "No data,Transferring"
|
|
bitfld.long 0x00 8. " WTA ,Write Transfer Active" "No data,Transferring"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Not stable,Stable"
|
|
bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Can issue,Cannot issue"
|
|
bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Can issue,Cannot issue"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "PROCTL,Protocol Control Register"
|
|
bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transfer,Stop"
|
|
bitfld.long 0x00 8.--9. " DMAS ,DMA Select" "No/Simple DMA,ADMA1,ADMA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Level,Test level"
|
|
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "No card,Card present"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian,?..."
|
|
bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " DTW ,Data Transfer Width" "1-bit,4-bit,8-bit,?..."
|
|
bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx213,SDCLKx214,SDCLKx215,SDCLKx216,SDCLKx217,SDCLKx218,SDCLKx219,SDCLKx220,SDCLKx221,SDCLKx222,SDCLKx223,SDCLKx224,SDCLKx225,SDCLKx226,SDCLKx227,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,SD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx2^13,SDCLKx2^14,SDCLKx2^15,SDCLKx2^16,SDCLKx2^17,SDCLKx2^18,SDCLKx2^19,SDCLKx2^20,SDCLKx2^21,SDCLKx2^22,SDCLKx2^23,SDCLKx2^24,SDCLKx2^25,SDCLKx2^26,SDCLKx2^27,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,PSD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
endif
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "IRQSTAT,Interrupt Status Register"
|
|
eventfld.long 0x00 28. " DMAE ,DMA Error" "No error,Error"
|
|
eventfld.long 0x00 24. " AC12E ,Auto CMD12 Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 22. " DEBE ,Data End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 21. " DCE ,Data CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 20. " DTOE ,Data Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 19. " CIE ,Command Index Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " CEBE ,Command End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 17. " CCE ,Command CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CTOE ,Command Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 8. " CINT ,Card Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CRM ,Card Removal" "Unstable/Inserted,Removed"
|
|
eventfld.long 0x00 6. " CINS ,Card Insertion" "Unstable/Removed,Inserted"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BRR ,Buffer Read Ready" "Not ready,Ready"
|
|
eventfld.long 0x00 4. " BWR ,Buffer Write Ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " BGE ,Block Gap Event" "No event,Event occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TC ,Transfer Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " CC ,Command Complete" "Not completed,Completed"
|
|
width 12.
|
|
line.long 0x04 "IRQSTATEN,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " CINSEN ,Card Insertion Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled"
|
|
line.long 0x08 "IRQSIGEN,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CINTIEN ,Card Interrupt Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 6. " CINIEN ,Card Insertion Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled"
|
|
if (((per.long(ad:0x50008000+0x30))&0x1000000)==0x1000000)
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued"
|
|
bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error"
|
|
bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error"
|
|
bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed"
|
|
else
|
|
hgroup.long 0x3C++0x3
|
|
hide.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
endif
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "HOSTCAPBLT,Host Controller Capabilities"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 16.--18. " MBL ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..."
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "WML,Watermark Level Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " WR_BRST_LEN ,Write Burst Length"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WR_WML ,Write Watermark Level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--12. 1. " RD_BRST_LEN ,Read Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RD_WML ,Read Watermark Level"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x00 "FEVT,Force Event Register"
|
|
bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "No effect,Force"
|
|
bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "No effect,Force"
|
|
bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "No effect,Force"
|
|
bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "No effect,Force"
|
|
bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "No effect,Force"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error"
|
|
bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State" "ST_STOP,ST_FDS,ST_CADR,ST_TFR"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADSADDR,ADMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR ,ADMA System Address"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "VENDOR,Vendor Specific Register"
|
|
bitfld.long 0x00 24.--27. " DBG_SEL ,Debug Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 1. " EXACT_BLK_NUM ,Exact block number block read enable for SDIO CMD53" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "MMCBOOT,MMC Boot Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT[15:0] ,Stop At Block Gap value of automatic mode"
|
|
bitfld.long 0x00 7. " AUTO_SABG_EN ,Auto stop at block gap function" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BOOT_EN ,Fast boot" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MMC_BOOT_MODE ,Boot mode select" "Normal,Alternative"
|
|
bitfld.long 0x00 4. " BOOT_ACK ,Boot ack mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DTOCV_ACK[3:0] ,Boot ACK time out counter value" "SDCLK x 2^8,SDCLK x 2^9,SDCLK x 2^10,SDCLK x 2^11,SDCLK x 2^12,SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,?..."
|
|
endif
|
|
rgroup.long 0xfc++0x3
|
|
line.long 0x00 "HOSTVER,Host Controller Version"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VVN[7:0] ,Vendor Version Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SVN[7:0] ,Specification Version Number"
|
|
width 0xb
|
|
tree.end
|
|
tree "eSDHC 3"
|
|
base ad:0x50020000
|
|
width 12.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "DSADDR,DMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DS_ADDR ,DMA System Address"
|
|
line.long 0x04 "BLKATTR,Block Attributes Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer"
|
|
hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size"
|
|
line.long 0x08 "CMDARG,Command Argument Register"
|
|
line.long 0x0C "XFERTYP,Transfer Type Register"
|
|
hexmask.long.byte 0x0C 24.--29. 1. " CMDINX ,Command Index"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " CMDTYP ,Command Type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present"
|
|
bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No Response,Length 136,Length 48,Length 48 check busy"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x0C 6. " NIBBLE_POS ,Nibble position" "odd high>even high>odd low>even low,odd high>odd low>even high>even low"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " MSBSEL ,Multi / Single Block Select" "Single,Multiple"
|
|
bitfld.long 0x0C 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read"
|
|
textline " "
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x0C 3. " DDR_EN ,Dual Data Rate mode selection" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " BCEN ,Block Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
if (((per.long(ad:0x50020000+0x0c))&0x30000)==0x00)
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CMDRSP0,Command Response 0"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
elif (((per.long(ad:0x50020000+0x0c))&0x30000)==0x10000)
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R2 response"
|
|
line.long 0x04 "CMDRSP1,Command Response 1"
|
|
hexmask.long 0x04 0.--31. 1. " CMDRSP1 ,R2 response"
|
|
line.long 0x08 "CMDRSP2,Command Response 2"
|
|
hexmask.long 0x08 0.--31. 1. " CMDRSP2 ,R2 response"
|
|
line.long 0x0C "CMDRSP3,Command Response 3"
|
|
hexmask.long.tbyte 0x0c 0.--23. 1. " CMDRSP3 ,R2[23:0] response"
|
|
elif (((per.long(ad:0x50020000+0x0c))&0x30000)==0x20000)
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1/R3/R4/R5/R6 response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1b/R5b response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "CMDRSP3,Command Response 3"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP3 ,R1b response"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DATPORT,Buffer Data Port Register"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "PRSSTAT,Present State Register"
|
|
bitfld.long 0x00 31. " DLSL[7] ,Line 7 Signal Level" "Low,High"
|
|
bitfld.long 0x00 30. " DLSL[6] ,Line 6 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DLSL[5] ,Line 5 Signal Level" "Low,High"
|
|
bitfld.long 0x00 28. " DLSL[4] ,Line 4 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DLSL[3] ,Line 3 Signal Level" "Low,High"
|
|
bitfld.long 0x00 26. " DLSL[2] ,Line 2 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DLSL[1] ,Line 1 Signal Level" "Low,High"
|
|
bitfld.long 0x00 24. " DLSL[0] ,Line 0 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "No card,Card present"
|
|
bitfld.long 0x00 16. " CINS ,Card Inserted" "No card/Reset/Power on,Card inserted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RTA ,Read Transfer Active" "No data,Transferring"
|
|
bitfld.long 0x00 8. " WTA ,Write Transfer Active" "No data,Transferring"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Not stable,Stable"
|
|
bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Can issue,Cannot issue"
|
|
bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Can issue,Cannot issue"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "PROCTL,Protocol Control Register"
|
|
bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transfer,Stop"
|
|
bitfld.long 0x00 8.--9. " DMAS ,DMA Select" "No/Simple DMA,ADMA1,ADMA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Level,Test level"
|
|
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "No card,Card present"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian,?..."
|
|
bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " DTW ,Data Transfer Width" "1-bit,4-bit,8-bit,?..."
|
|
bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
if ((per.long(ad:0x50020000+0x0C)&0x8)==0x8)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IPP_RST_N ,Output to the CARD through the pad for hardware reset" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx212,SDCLKx213,SDCLKx214,SDCLKx215,SDCLKx216,SDCLKx217,SDCLKx218,SDCLKx219,SDCLKx220,SDCLKx221,SDCLKx222,SDCLKx223,SDCLKx224,SDCLKx225,SDCLKx226,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,SD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IPP_RST_N ,Output to the CARD through the pad for hardware reset" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx213,SDCLKx214,SDCLKx215,SDCLKx216,SDCLKx217,SDCLKx218,SDCLKx219,SDCLKx220,SDCLKx221,SDCLKx222,SDCLKx223,SDCLKx224,SDCLKx225,SDCLKx226,SDCLKx227,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,SD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
endif
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx2^13,SDCLKx2^14,SDCLKx2^15,SDCLKx2^16,SDCLKx2^17,SDCLKx2^18,SDCLKx2^19,SDCLKx2^20,SDCLKx2^21,SDCLKx2^22,SDCLKx2^23,SDCLKx2^24,SDCLKx2^25,SDCLKx2^26,SDCLKx2^27,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,PSD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
endif
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "IRQSTAT,Interrupt Status Register"
|
|
eventfld.long 0x00 28. " DMAE ,DMA Error" "No error,Error"
|
|
eventfld.long 0x00 24. " AC12E ,Auto CMD12 Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 22. " DEBE ,Data End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 21. " DCE ,Data CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 20. " DTOE ,Data Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 19. " CIE ,Command Index Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " CEBE ,Command End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 17. " CCE ,Command CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CTOE ,Command Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 8. " CINT ,Card Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CRM ,Card Removal" "Unstable/Inserted,Removed"
|
|
eventfld.long 0x00 6. " CINS ,Card Insertion" "Unstable/Removed,Inserted"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BRR ,Buffer Read Ready" "Not ready,Ready"
|
|
eventfld.long 0x00 4. " BWR ,Buffer Write Ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " BGE ,Block Gap Event" "No event,Event occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TC ,Transfer Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " CC ,Command Complete" "Not completed,Completed"
|
|
width 12.
|
|
line.long 0x04 "IRQSTATEN,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " CINSEN ,Card Insertion Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled"
|
|
line.long 0x08 "IRQSIGEN,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CINTIEN ,Card Interrupt Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 6. " CINIEN ,Card Insertion Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled"
|
|
if (((per.long(ad:0x50020000+0x30))&0x1000000)==0x1000000)
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued"
|
|
bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error"
|
|
bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error"
|
|
bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed"
|
|
else
|
|
hgroup.long 0x3C++0x3
|
|
hide.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
endif
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "HOSTCAPBLT,Host Controller Capabilities"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 16.--18. " MBL ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..."
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "WML,Watermark Level Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " WR_BRST_LEN ,Write Burst Length"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WR_WML ,Write Watermark Level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--12. 1. " RD_BRST_LEN ,Read Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RD_WML ,Read Watermark Level"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x00 "FEVT,Force Event Register"
|
|
bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "No effect,Force"
|
|
bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "No effect,Force"
|
|
bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "No effect,Force"
|
|
bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "No effect,Force"
|
|
bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "No effect,Force"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error"
|
|
bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State" "ST_STOP,ST_FDS,ST_CADR,ST_TFR"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADSADDR,ADMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR ,ADMA System Address"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DLLCTRL,DLL (Delay Line) Control"
|
|
bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT[3:0] ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT[7:0] ,Slave delay line update interval"
|
|
bitfld.long 0x00 10.--15. " DLL_CTRL_SLV_OVERRIDE_VAL[5:0] ,DLL_CTRL_SLV_ OVERRIDE_VAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLL_CTRL_SLV_OVERRIDE ,Manual override" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL auto update" "Enabled,Disabled"
|
|
bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET[3:0] ,Delay target for the ESDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,Force slave delay line update immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL & delay chain" "Disabled,Enabled"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "DLLSTS,DLL Status"
|
|
bitfld.long 0x00 8.--13. " DLL_STS_REF_SEL[5:0] ,Reference delay line select taps" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 2.--7. " DLL_STS_SLV_SEL[5:0] ,Slave delay line select status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "VENDOR,Vendor Specific Register"
|
|
bitfld.long 0x00 24.--27. " DBG_SEL ,Debug Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 1. " EXACT_BLK_NUM ,Exact block number block read enable for SDIO CMD53" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
if ((per.long(ad:0x50020000+0x0C)&0x8)==0x8)
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "MMCBOOT,MMC Boot Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT[15:0] ,Stop At Block Gap value of automatic mode"
|
|
bitfld.long 0x00 7. " AUTO_SABG_EN ,Auto stop at block gap function" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BOOT_EN ,Fast boot" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MMC_BOOT_MODE ,Boot mode select" "Normal,Alternative"
|
|
bitfld.long 0x00 4. " BOOT_ACK ,Boot ack mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DTOCV_ACK[3:0] ,Boot ACK time out counter value" "SDCLK x 2^7,SDCLK x 2^8,SDCLK x 2^9,SDCLK x 2^10,SDCLK x 2^11,SDCLK x 2^12,SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,?..."
|
|
else
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "MMCBOOT,MMC Boot Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT[15:0] ,Stop At Block Gap value of automatic mode"
|
|
bitfld.long 0x00 7. " AUTO_SABG_EN ,Auto stop at block gap function" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BOOT_EN ,Fast boot" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MMC_BOOT_MODE ,Boot mode select" "Normal,Alternative"
|
|
bitfld.long 0x00 4. " BOOT_ACK ,Boot ack mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DTOCV_ACK[3:0] ,Boot ACK time out counter value" "SDCLK x 2^8,SDCLK x 2^9,SDCLK x 2^10,SDCLK x 2^11,SDCLK x 2^12,SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0xfc++0x3
|
|
line.long 0x00 "HOSTVER,Host Controller Version"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VVN[7:0] ,Vendor Version Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SVN[7:0] ,Specification Version Number"
|
|
width 0xb
|
|
tree.end
|
|
tree "eSDHC 4"
|
|
base ad:0x50024000
|
|
width 12.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "DSADDR,DMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DS_ADDR ,DMA System Address"
|
|
line.long 0x04 "BLKATTR,Block Attributes Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer"
|
|
hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size"
|
|
line.long 0x08 "CMDARG,Command Argument Register"
|
|
line.long 0x0C "XFERTYP,Transfer Type Register"
|
|
hexmask.long.byte 0x0C 24.--29. 1. " CMDINX ,Command Index"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " CMDTYP ,Command Type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present"
|
|
bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No Response,Length 136,Length 48,Length 48 check busy"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " MSBSEL ,Multi / Single Block Select" "Single,Multiple"
|
|
bitfld.long 0x0C 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read"
|
|
textline " "
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
bitfld.long 0x0C 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " BCEN ,Block Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
if (((per.long(ad:0x50024000+0x0c))&0x30000)==0x00)
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CMDRSP0,Command Response 0"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
elif (((per.long(ad:0x50024000+0x0c))&0x30000)==0x10000)
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R2 response"
|
|
line.long 0x04 "CMDRSP1,Command Response 1"
|
|
hexmask.long 0x04 0.--31. 1. " CMDRSP1 ,R2 response"
|
|
line.long 0x08 "CMDRSP2,Command Response 2"
|
|
hexmask.long 0x08 0.--31. 1. " CMDRSP2 ,R2 response"
|
|
line.long 0x0C "CMDRSP3,Command Response 3"
|
|
hexmask.long.tbyte 0x0c 0.--23. 1. " CMDRSP3 ,R2[23:0] response"
|
|
elif (((per.long(ad:0x50024000+0x0c))&0x30000)==0x20000)
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1/R3/R4/R5/R6 response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1b/R5b response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "CMDRSP3,Command Response 3"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP3 ,R1b response"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DATPORT,Buffer Data Port Register"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "PRSSTAT,Present State Register"
|
|
bitfld.long 0x00 31. " DLSL[7] ,Line 7 Signal Level" "Low,High"
|
|
bitfld.long 0x00 30. " DLSL[6] ,Line 6 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DLSL[5] ,Line 5 Signal Level" "Low,High"
|
|
bitfld.long 0x00 28. " DLSL[4] ,Line 4 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DLSL[3] ,Line 3 Signal Level" "Low,High"
|
|
bitfld.long 0x00 26. " DLSL[2] ,Line 2 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DLSL[1] ,Line 1 Signal Level" "Low,High"
|
|
bitfld.long 0x00 24. " DLSL[0] ,Line 0 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "No card,Card present"
|
|
bitfld.long 0x00 16. " CINS ,Card Inserted" "No card/Reset/Power on,Card inserted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RTA ,Read Transfer Active" "No data,Transferring"
|
|
bitfld.long 0x00 8. " WTA ,Write Transfer Active" "No data,Transferring"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Not stable,Stable"
|
|
bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Can issue,Cannot issue"
|
|
bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Can issue,Cannot issue"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "PROCTL,Protocol Control Register"
|
|
bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transfer,Stop"
|
|
bitfld.long 0x00 8.--9. " DMAS ,DMA Select" "No/Simple DMA,ADMA1,ADMA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Level,Test level"
|
|
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "No card,Card present"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian,?..."
|
|
bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " DTW ,Data Transfer Width" "1-bit,4-bit,8-bit,?..."
|
|
bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx213,SDCLKx214,SDCLKx215,SDCLKx216,SDCLKx217,SDCLKx218,SDCLKx219,SDCLKx220,SDCLKx221,SDCLKx222,SDCLKx223,SDCLKx224,SDCLKx225,SDCLKx226,SDCLKx227,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,SD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx2^13,SDCLKx2^14,SDCLKx2^15,SDCLKx2^16,SDCLKx2^17,SDCLKx2^18,SDCLKx2^19,SDCLKx2^20,SDCLKx2^21,SDCLKx2^22,SDCLKx2^23,SDCLKx2^24,SDCLKx2^25,SDCLKx2^26,SDCLKx2^27,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,PSD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
endif
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "IRQSTAT,Interrupt Status Register"
|
|
eventfld.long 0x00 28. " DMAE ,DMA Error" "No error,Error"
|
|
eventfld.long 0x00 24. " AC12E ,Auto CMD12 Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 22. " DEBE ,Data End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 21. " DCE ,Data CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 20. " DTOE ,Data Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 19. " CIE ,Command Index Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " CEBE ,Command End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 17. " CCE ,Command CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CTOE ,Command Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 8. " CINT ,Card Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CRM ,Card Removal" "Unstable/Inserted,Removed"
|
|
eventfld.long 0x00 6. " CINS ,Card Insertion" "Unstable/Removed,Inserted"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BRR ,Buffer Read Ready" "Not ready,Ready"
|
|
eventfld.long 0x00 4. " BWR ,Buffer Write Ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " BGE ,Block Gap Event" "No event,Event occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TC ,Transfer Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " CC ,Command Complete" "Not completed,Completed"
|
|
width 12.
|
|
line.long 0x04 "IRQSTATEN,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " CINSEN ,Card Insertion Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled"
|
|
line.long 0x08 "IRQSIGEN,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CINTIEN ,Card Interrupt Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 6. " CINIEN ,Card Insertion Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled"
|
|
if (((per.long(ad:0x50024000+0x30))&0x1000000)==0x1000000)
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued"
|
|
bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error"
|
|
bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error"
|
|
bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed"
|
|
else
|
|
hgroup.long 0x3C++0x3
|
|
hide.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
endif
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "HOSTCAPBLT,Host Controller Capabilities"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 16.--18. " MBL ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..."
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "WML,Watermark Level Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " WR_BRST_LEN ,Write Burst Length"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WR_WML ,Write Watermark Level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--12. 1. " RD_BRST_LEN ,Read Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RD_WML ,Read Watermark Level"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x00 "FEVT,Force Event Register"
|
|
bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "No effect,Force"
|
|
bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "No effect,Force"
|
|
bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "No effect,Force"
|
|
bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "No effect,Force"
|
|
bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "No effect,Force"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error"
|
|
bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State" "ST_STOP,ST_FDS,ST_CADR,ST_TFR"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADSADDR,ADMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR ,ADMA System Address"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "VENDOR,Vendor Specific Register"
|
|
bitfld.long 0x00 24.--27. " DBG_SEL ,Debug Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 1. " EXACT_BLK_NUM ,Exact block number block read enable for SDIO CMD53" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "MMCBOOT,MMC Boot Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT[15:0] ,Stop At Block Gap value of automatic mode"
|
|
bitfld.long 0x00 7. " AUTO_SABG_EN ,Auto stop at block gap function" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BOOT_EN ,Fast boot" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MMC_BOOT_MODE ,Boot mode select" "Normal,Alternative"
|
|
bitfld.long 0x00 4. " BOOT_ACK ,Boot ack mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DTOCV_ACK[3:0] ,Boot ACK time out counter value" "SDCLK x 2^8,SDCLK x 2^9,SDCLK x 2^10,SDCLK x 2^11,SDCLK x 2^12,SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,?..."
|
|
endif
|
|
rgroup.long 0xfc++0x3
|
|
line.long 0x00 "HOSTVER,Host Controller Version"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VVN[7:0] ,Vendor Version Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SVN[7:0] ,Specification Version Number"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "FEC (Fast Ethernet Controller)"
|
|
base ad:0x63fec000
|
|
width 7.
|
|
tree "Control/Status Registers"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "EIR,Ethernet Interrupt Event Register"
|
|
eventfld.long 0x00 31. " HBERR ,Heartbeat error" "No error,Error"
|
|
eventfld.long 0x00 30. " BABR ,Babbling receive error" "No error,Error"
|
|
eventfld.long 0x00 29. " BABT ,Babbling transmit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 28. " GRA ,Graceful stop complete" "Not completed,Completed"
|
|
eventfld.long 0x00 27. " TXF ,Transmit frame interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " TXB ,Transmit buffer interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " RXF ,Receive frame interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " RXB ,Receive buffer interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " MII ,MII interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " EBERR ,Ethernet bus error" "No error,Error"
|
|
eventfld.long 0x00 21. " LC ,Late collision" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " RL ,Collision retry limit" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "Not empty,Empty"
|
|
line.long 0x04 "EIMR,Interrupt Mask Register"
|
|
bitfld.long 0x04 31. " HBERR ,Heartbeat error" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " BABR ,Babbling receive error" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " BABT ,Babbling transmit error" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 28. " GRA ,Graceful stop complete" "Masked,Not masked"
|
|
bitfld.long 0x04 27. " TXF ,Transmit frame interrupt" "Masked,Not masked"
|
|
bitfld.long 0x04 26. " TXB ,Transmit buffer interrupt" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 25. " RXF ,Receive frame interrupt" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " RXB ,Receive buffer interrupt" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " MII ,MII interrupt" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " EBERR ,Ethernet bus error" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " LC ,Late collision" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " RL ,Collision retry limit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " UN ,Transmit FIFO underrun" "Masked,Not masked"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "RDAR,Receive Descriptor Active Register"
|
|
bitfld.long 0x00 24. " R_DES_ACTIVE ,Receive descriptor ring update" "Not received,Received"
|
|
line.long 0x04 "TDAR,Transmit Descriptor Active Register"
|
|
bitfld.long 0x04 24. " X_DES_ACTIVE ,Transmit descriptor ring update" "Not transmitted,Transmitted"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ECR,Ethernet Control Register"
|
|
bitfld.long 0x00 1. " ETHER_EN ,Ethernet enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESET ,Reset" "No reset,Reset"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "MMFR,MII Management Frame Register"
|
|
bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " OP ,Operation code" "Write,Write for MII frame,Read for MII frame,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18.--22. " RA ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " TA ,Turn around" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data"
|
|
line.long 0x04 "MSCR,MII Speed Control Register"
|
|
bitfld.long 0x04 7. " DIS_PREAMBLE ,Preamble not to be prepended to the MII management frame" "Prepended,Not prepended"
|
|
bitfld.long 0x04 1.--6. " MII_SPEED ,Controls the frequency of the MII management interface clock" "Turned off,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "MIBC,MIB Control Register"
|
|
bitfld.long 0x00 31. " MIB_DISABLE ,A read/write control" "Not halted,Halted"
|
|
rbitfld.long 0x00 30. " MB_IDLE ,A read-only status" "Updated,Not updated"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RCR,Receive Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " MAX_FL ,Maximum frame length"
|
|
bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected"
|
|
bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" "7-wire,MII"
|
|
bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LOOP ,Internal loopback" "Not looped,Looped"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TCR,Transmit Control Register"
|
|
bitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not received,Recived"
|
|
bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HBC ,Heartbeat control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped"
|
|
group.long 0xE4++0xb
|
|
line.long 0x00 "PALR,Physical Address Low Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PADDR1_0 ,Byte 0 of the 6 byte destination address"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PADDR1_1 ,Byte 1 of the 6 byte destination address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PADDR1_2 ,Byte 2 of the 6 byte destination address"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PADDR1_3 ,Byte 3 of the 6 byte destination address"
|
|
line.long 0x04 "PAUR,Physical Address High Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PADDR2_4 ,Byte 4 of the 6 byte destination address"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PADDR2_5 ,Byte 5 of the 6 byte destination address"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames"
|
|
line.long 0x08 "OPD,Opcode/Pause Duration Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field used in PAUSE frames"
|
|
hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause Duration field used in PAUSE frames"
|
|
group.long 0x118++0xF
|
|
line.long 0x00 "IAUR,Descriptor Individual Upper Address Registers"
|
|
line.long 0x04 "IALR,Descriptor Individual Lower Address Register"
|
|
line.long 0x08 "GAUR,Descriptor Group Upper Address Register"
|
|
line.long 0x0C "GALR,Descriptor Group Lower Address Register"
|
|
group.long 0x144++0x3
|
|
line.long 0x00 "TFWR,Transmit FIFO Watermark Register"
|
|
bitfld.long 0x00 0.--1. " X_WMRK ,Number of bytes written to transmit FIFO before transmission of a frame begins" "64 bytes,64 bytes,128 bytes,192 bytes"
|
|
rgroup.long 0x14c++0x03
|
|
line.long 0x00 "FRBR,FIFO Receive Bound Register"
|
|
hexmask.long.word 0x00 2.--9. 0x4 " R_BOUND ,Highest valid FIFO RAM address"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "FRSR,FIFO Receive Start Register"
|
|
hexmask.long.word 0x00 2.--9. 0x04 " R_FSTART ,Address of first receive FIFO location"
|
|
group.long 0x180++0x0b
|
|
line.long 0x00 "ERDSR,Receive Buffer Descriptor Ring Start Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " R_DES_START ,Pointer to start of receive buffer descriptor queue"
|
|
line.long 0x04 "ETDSR,Transmit Buffer Descriptor Ring Start Register"
|
|
hexmask.long 0x04 2.--31. 0x4 " X_DES_START ,Pointer to start of transmit buffer descriptor queue"
|
|
line.long 0x08 "EMRBR,Receive Buffer Size Register"
|
|
hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size"
|
|
tree.end
|
|
tree "MIB Block Counters"
|
|
width 20.
|
|
group.long 0x200++0x77
|
|
line.long 0x00 "RMON_T_DROP,Count of frames not counted correctly"
|
|
line.long 0x04 "RMON_T_PACKETS,RMON Tx packet count"
|
|
line.long 0x08 "RMON_T_BC_PKT,RMON Tx Broadcast Packets"
|
|
line.long 0x0c "RMON_T_MC_PKT,RMON Tx Multicast Packets"
|
|
line.long 0x10 "RMON_T_CRC_ALIGN,RMON Tx Packets w CRC/Align error"
|
|
line.long 0x14 "RMON_T_UNDERSIZE,RMON Tx Packets < 64 bytes"
|
|
line.long 0x18 "RMON_T_OVERSIZE,RMON Tx Packets > MAX_FL bytes"
|
|
line.long 0x1c "RMON_T_FRAG,RMON Tx Packets < 64 bytes"
|
|
line.long 0x20 "RMON_T_JAB,RMON Tx Packets > MAX_FL bytes"
|
|
line.long 0x24 "RMON_T_COL,RMON Tx collision count"
|
|
line.long 0x28 "RMON_T_P64,RMON Tx 64 byte packets"
|
|
line.long 0x2c "RMON_T_P65TO127,RMON Tx 65 to 127 byte packets"
|
|
line.long 0x30 "RMON_T_P128TO255,RMON Tx 128 to 255 byte packets"
|
|
line.long 0x34 "RMON_T_P256TO511,RMON Tx 256 to 511 byte packets"
|
|
line.long 0x38 "RMON_T_P512TO1023,RMON Tx 512 to 1023 byte packets"
|
|
line.long 0x3c "RMON_T_P1024TO2047,RMON Tx 1024 to 2047 byte packets"
|
|
line.long 0x40 "RMON_T_P_GTE2048,RMON Tx packets w > 2048 bytes"
|
|
line.long 0x44 "RMON_T_OCTETS,RMON Tx Octets"
|
|
line.long 0x48 "IEEE_T_DROP,Count of frames not counted correctly"
|
|
line.long 0x4c "IEEE_T_FRAME_OK,Frames Transmitted OK"
|
|
line.long 0x50 "IEEE_T_1COL,Frames Transmitted with Single Collision"
|
|
line.long 0x54 "IEEE_T_MCOL,Frames Transmitted with Multiple Collisions"
|
|
line.long 0x58 "EEE_T_DEF,Frames Transmitted after Deferral Delay"
|
|
line.long 0x5c "IEEE_T_LCOL,Frames Transmitted with Late Collision"
|
|
line.long 0x60 "IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions"
|
|
line.long 0x64 "IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun"
|
|
line.long 0x68 "IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error"
|
|
line.long 0x6c "IEEE_T_SQE,Frames Transmitted with SQE Error"
|
|
line.long 0x70 "IEEE_T_FDXFC,Flow Control Pause frames transmitted"
|
|
line.long 0x74 "IEEE_T_OCTETS_OK,Octet count for Frames Transmitted w/o Error"
|
|
group.long 0x284++0x5f
|
|
line.long 0x00 "RMON_R_PACKETS,RMON Rx packet count"
|
|
line.long 0x04 "RMON_R_BC_PKT,RMON Rx Broadcast Packets"
|
|
line.long 0x08 "RMON_R_MC_PKT,RMON Rx Multicast Packets"
|
|
line.long 0x0c "RMON_R_CRC_ALIGN,RMON Rx Packets w CRC/Align error"
|
|
line.long 0x10 "RMON_R_UNDERSIZE,RMON Rx Packets < 64 bytes"
|
|
line.long 0x14 "RMON_R_OVERSIZE,RMON Rx Packets > MAX_FL bytes"
|
|
line.long 0x18 "RMON_R_FRAG,RMON Rx Packets < 64 bytes"
|
|
line.long 0x1c "RMON_R_JAB,RMON Rx Packets > MAX_FL bytes"
|
|
line.long 0x20 "RMON_R_RESVD_0,RMON_R_RESVD_0"
|
|
line.long 0x24 "RMON_R_P64,RMON Rx 64 byte packets"
|
|
line.long 0x28 "RMON_R_P65TO127,RMON Rx 65 to 127 byte packets"
|
|
line.long 0x2c "RMON_R_P128TO255,RMON Rx 128 to 255 byte packets"
|
|
line.long 0x30 "RMON_R_P256TO511,RMON Rx 256 to 511 byte packets"
|
|
line.long 0x34 "RMON_R_P512TO1023,RMON Rx 512 to 1023 byte packets"
|
|
line.long 0x38 "RMON_R_P1024TO2047,RMON Rx 1024 to 2047 byte packets"
|
|
line.long 0x3c "RMON_R_P_GTE2048,RMON Rx packets w > 2048 bytes"
|
|
line.long 0x40 "RMON_R_OCTETS,RMON Rx Octets"
|
|
line.long 0x44 "IEEE_R_DROP,Count of frames not counted correctly"
|
|
line.long 0x48 "IEEE_R_FRAME_OK,Frames Received OK"
|
|
line.long 0x4c "IEEE_R_CRC,Frames Received with CRC Error"
|
|
line.long 0x50 "IEEE_R_ALIGN,Frames Received with Alignment Error"
|
|
line.long 0x54 "IEEE_R_MACERR,Receive Fifo Overflow count"
|
|
line.long 0x58 "IEEE_R_FDXFC,Flow Control Pause frames received"
|
|
line.long 0x5c "IEEE_R_OCTETS_OK,Octet count for Frames Rcvd w/o Error"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "GPC (General Power Controller)"
|
|
base ad:0x53FD8000
|
|
width 6.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CNTR,CNTR Register"
|
|
bitfld.long 0x00 26. " CSPI ,CSPI or I2C use" "I2C,CSPI"
|
|
bitfld.long 0x00 25. " IRQ2M ,Int2 (for I2C) masking" "Not masked,Masked"
|
|
eventfld.long 0x00 24. " IRQ2 ,Interrupt request 2 status bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPCIRQM ,GPC interrupt/event masking" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " GPCIRQ ,GPC will generate ARM IRQ or SDMA event" "SDMA event,ARM IRQ"
|
|
rbitfld.long 0x00 17. " DVFS1CR ,DVFSP Change request" "Not requested,Requested"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " DVFS0CR ,DVFSC Change request" "Not requested,Requested"
|
|
bitfld.long 0x00 15. " ADU ,ARM domain freq/voltage update needed" "PER,ARM"
|
|
bitfld.long 0x00 14. " STRT ,Controller start" "Finished,In progress"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FUPD ,Frequency update needed" "Not needed,Needed"
|
|
bitfld.long 0x00 0.--3. " HTRI ,Hardware Triggering Register Index" "Reg. 0,Reg. 1,Reg. 3,?..."
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "VCR,Voltage Counter Register"
|
|
bitfld.long 0x00 17. " VINC ,Voltage increase" "Decreased,Increased"
|
|
bitfld.long 0x00 16. " VCNTU ,Voltage Count Used" "Not used,Used"
|
|
hexmask.long.word 0x00 0.--14. 1. " VCNT ,Voltage update Count"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "NEON,NEON register"
|
|
rbitfld.long 0x00 4.--5. " NEONFSMST ,Neon FSM status" "Power down acknowledge,Power down request,Power up request,Power up acknowledge/Normal state"
|
|
bitfld.long 0x00 1. " NEONPUR ,NEON Power Up Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " NEONPDR ,NEON Power Down Request" "Not requested,Requested"
|
|
width 0xb
|
|
tree.end
|
|
tree.open "GPIO (General-Purpose Input/Output)"
|
|
tree "GPIO1"
|
|
base ad:0x53F84000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,GPIO Data Register"
|
|
bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High"
|
|
line.long 0x04 "GDIR,GPIO Direction Register"
|
|
bitfld.long 0x04 31. " GDIR31 ,GPIO Direction 31 bit" "Input,Output"
|
|
bitfld.long 0x04 30. " GDIR30 ,GPIO Direction 30 bit" "Input,Output"
|
|
bitfld.long 0x04 29. " GDIR29 ,GPIO Direction 29 bit" "Input,Output"
|
|
bitfld.long 0x04 28. " GDIR28 ,GPIO Direction 28 bit" "Input,Output"
|
|
bitfld.long 0x04 27. " GDIR27 ,GPIO Direction 27 bit" "Input,Output"
|
|
bitfld.long 0x04 26. " GDIR26 ,GPIO Direction 26 bit" "Input,Output"
|
|
bitfld.long 0x04 25. " GDIR25 ,GPIO Direction 25 bit" "Input,Output"
|
|
bitfld.long 0x04 24. " GDIR24 ,GPIO Direction 24 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GDIR23 ,GPIO Direction 23 bit" "Input,Output"
|
|
bitfld.long 0x04 22. " GDIR22 ,GPIO Direction 22 bit" "Input,Output"
|
|
bitfld.long 0x04 21. " GDIR21 ,GPIO Direction 21 bit" "Input,Output"
|
|
bitfld.long 0x04 20. " GDIR20 ,GPIO Direction 20 bit" "Input,Output"
|
|
bitfld.long 0x04 19. " GDIR19 ,GPIO Direction 19 bit" "Input,Output"
|
|
bitfld.long 0x04 18. " GDIR18 ,GPIO Direction 18 bit" "Input,Output"
|
|
bitfld.long 0x04 17. " GDIR17 ,GPIO Direction 17 bit" "Input,Output"
|
|
bitfld.long 0x04 16. " GDIR16 ,GPIO Direction 16 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GDIR15 ,GPIO Direction 15 bit" "Input,Output"
|
|
bitfld.long 0x04 14. " GDIR14 ,GPIO Direction 14 bit" "Input,Output"
|
|
bitfld.long 0x04 13. " GDIR13 ,GPIO Direction 13 bit" "Input,Output"
|
|
bitfld.long 0x04 12. " GDIR12 ,GPIO Direction 12 bit" "Input,Output"
|
|
bitfld.long 0x04 11. " GDIR11 ,GPIO Direction 11 bit" "Input,Output"
|
|
bitfld.long 0x04 10. " GDIR10 ,GPIO Direction 10 bit" "Input,Output"
|
|
bitfld.long 0x04 9. " GDIR9 ,GPIO Direction 9 bit" "Input,Output"
|
|
bitfld.long 0x04 8. " GDIR8 ,GPIO Direction 8 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " GDIR7 ,GPIO Direction 7 bit" "Input,Output"
|
|
bitfld.long 0x04 6. " GDIR6 ,GPIO Direction 6 bit" "Input,Output"
|
|
bitfld.long 0x04 5. " GDIR5 ,GPIO Direction 5 bit" "Input,Output"
|
|
bitfld.long 0x04 4. " GDIR4 ,GPIO Direction 4 bit" "Input,Output"
|
|
bitfld.long 0x04 3. " GDIR3 ,GPIO Direction 3 bit" "Input,Output"
|
|
bitfld.long 0x04 2. " GDIR2 ,GPIO Direction 2 bit" "Input,Output"
|
|
bitfld.long 0x04 1. " GDIR1 ,GPIO Direction 1 bit" "Input,Output"
|
|
bitfld.long 0x04 0. " GDIR0 ,GPIO Direction 0 bit" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "PSR,GPIO Pad Status Register"
|
|
bitfld.long 0x00 31. " PSR31 ,GPIO Pad Status bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PSR30 ,GPIO Pad Status bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PSR29 ,GPIO Pad Status bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " PSR28 ,GPIO Pad Status bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PSR27 ,GPIO Pad Status bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PSR26 ,GPIO Pad Status bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " PSR25 ,GPIO Pad Status bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PSR24 ,GPIO Pad Status bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PSR23 ,GPIO Pad Status bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " PSR22 ,GPIO Pad Status bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PSR21 ,GPIO Pad Status bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PSR20 ,GPIO Pad Status bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " PSR19 ,GPIO Pad Status bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PSR18 ,GPIO Pad Status bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PSR17 ,GPIO Pad Status bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " PSR16 ,GPIO Pad Status bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PSR15 ,GPIO Pad Status bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PSR14 ,GPIO Pad Status bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " PSR13 ,GPIO Pad Status bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PSR12 ,GPIO Pad Status bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PSR11 ,GPIO Pad Status bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " PSR10 ,GPIO Pad Status bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PSR9 ,GPIO Pad Status bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PSR8 ,GPIO Pad Status bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PSR7 ,GPIO Pad Status bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PSR6 ,GPIO Pad Status bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PSR5 ,GPIO Pad Status bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " PSR4 ,GPIO Pad Status bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PSR3 ,GPIO Pad Status bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PSR2 ,GPIO Pad Status bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " PSR1 ,GPIO Pad Status bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PSR0 ,GPIO Pad Status bit 0" "Low,High"
|
|
tree "GPIO Interrupt Registers"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 30.--31. " ICR1_15 ,Interrupt 15 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 28.--29. " ICR1_14 ,Interrupt 14 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 26.--27. " ICR1_13 ,Interrupt 13 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 24.--25. " ICR1_12 ,Interrupt 12 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 22.--23. " ICR1_11 ,Interrupt 11 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 20.--21. " ICR1_10 ,Interrupt 10 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ICR1_9 ,Interrupt 9 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 16.--17. " ICR1_8 ,Interrupt 8 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 14.--15. " ICR1_7 ,Interrupt 7 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 12.--13. " ICR1_6 ,Interrupt 6 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 10.--11. " ICR1_5 ,Interrupt 5 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 8.--9. " ICR1_4 ,Interrupt 4 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICR1_3 ,Interrupt 3 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 4.--5. " ICR1_2 ,Interrupt 2 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 2.--3. " ICR1_1 ,Interrupt 1 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 0.--1. " ICR1_0 ,Interrupt 0 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 30.--31. " ICR2_31 ,Interrupt 31 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 28.--29. " ICR2_30 ,Interrupt 30 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 26.--27. " ICR2_29 ,Interrupt 29 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 24.--25. " ICR2_28 ,Interrupt 28 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 22.--23. " ICR2_27 ,Interrupt 27 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 20.--21. " ICR2_26 ,Interrupt 26 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " ICR2_25 ,Interrupt 25 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 16.--17. " ICR2_24 ,Interrupt 24 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 14.--15. " ICR2_23 ,Interrupt 23 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 12.--13. " ICR2_22 ,Interrupt 22 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 10.--11. " ICR2_21 ,Interrupt 21 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 8.--9. " ICR2_20 ,Interrupt 20 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " ICR2_19 ,Interrupt 19 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 4.--5. " ICR2_18 ,Interrupt 18 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 2.--3. " ICR2_17 ,Interrupt 17 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 0.--1. " ICR2_16 ,Interrupt 16 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x08 "IMR,GPIO Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " IMR31 ,Interrupt 31 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 30. " IMR30 ,Interrupt 30 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 29. " IMR29 ,Interrupt 29 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 28. " IMR28 ,Interrupt 28 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 27. " IMR27 ,Interrupt 27 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 26. " IMR26 ,Interrupt 26 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IMR25 ,Interrupt 25 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " IMR24 ,Interrupt 24 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " IMR23 ,Interrupt 23 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " IMR22 ,Interrupt 22 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " IMR21 ,Interrupt 21 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " IMR20 ,Interrupt 20 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IMR19 ,Interrupt 19 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " IMR18 ,Interrupt 18 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " IMR17 ,Interrupt 17 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " IMR16 ,Interrupt 16 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 15. " IMR15 ,Interrupt 15 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 14. " IMR14 ,Interrupt 14 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IMR13 ,Interrupt 13 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " IMR12 ,Interrupt 12 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 11. " IMR11 ,Interrupt 11 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 10. " IMR10 ,Interrupt 10 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " IMR9 ,Interrupt 9 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " IMR8 ,Interrupt 8 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IMR7 ,Interrupt 7 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " IMR6 ,Interrupt 6 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " IMR5 ,Interrupt 5 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " IMR4 ,Interrupt 4 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " IMR3 ,Interrupt 3 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " IMR2 ,Interrupt 2 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IMR1 ,Interrupt 1 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " IMR0 ,Interrupt 0 Mask bit" "Masked,Not masked"
|
|
line.long 0x0C "ISR,GPIO Interrupt Status Register"
|
|
eventfld.long 0x0C 31. " ISR31 ,Interrupt 31 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " ISR30 ,Interrupt 30 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " ISR29 ,Interrupt 29 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " ISR28 ,Interrupt 28 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " ISR27 ,Interrupt 27 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " ISR26 ,Interrupt 26 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " ISR25 ,Interrupt 25 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " ISR24 ,Interrupt 24 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 23. " ISR23 ,Interrupt 23 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " ISR22 ,Interrupt 22 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " ISR21 ,Interrupt 21 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " ISR20 ,Interrupt 20 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " ISR19 ,Interrupt 19 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " ISR18 ,Interrupt 18 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " ISR17 ,Interrupt 17 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " ISR16 ,Interrupt 16 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " ISR15 ,Interrupt 15 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " ISR14 ,Interrupt 14 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " ISR13 ,Interrupt 13 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " ISR12 ,Interrupt 12 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " ISR11 ,Interrupt 11 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " ISR10 ,Interrupt 10 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 9. " ISR9 ,Interrupt 9 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " ISR8 ,Interrupt 8 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " ISR7 ,Interrupt 7 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " ISR6 ,Interrupt 6 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " ISR5 ,Interrupt 5 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " ISR4 ,Interrupt 4 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " ISR3 ,Interrupt 3 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " ISR2 ,Interrupt 2 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " ISR1 ,Interrupt 1 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " ISR0 ,Interrupt 0 Status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
width 0x0B
|
|
width 10.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EDGE_SEL,GPIO Edge Select Register"
|
|
bitfld.long 0x00 31. " EDGE_SEL31 ,Edge Selection 31" "ICR_2_31,Any edge"
|
|
bitfld.long 0x00 30. " EDGE_SEL30 ,Edge Selection 30" "ICR_2_30,Any edge"
|
|
bitfld.long 0x00 29. " EDGE_SEL29 ,Edge Selection 29" "ICR_2_29,Any edge"
|
|
bitfld.long 0x00 28. " EDGE_SEL28 ,Edge Selection 28" "ICR_2_28,Any edge"
|
|
bitfld.long 0x00 27. " EDGE_SEL27 ,Edge Selection 27" "ICR_2_27,Any edge"
|
|
bitfld.long 0x00 26. " EDGE_SEL26 ,Edge Selection 26" "ICR_2_26,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EDGE_SEL25 ,Edge Selection 25" "ICR_2_25,Any edge"
|
|
bitfld.long 0x00 24. " EDGE_SEL24 ,Edge Selection 24" "ICR_2_24,Any edge"
|
|
bitfld.long 0x00 23. " EDGE_SEL23 ,Edge Selection 23" "ICR_2_23,Any edge"
|
|
bitfld.long 0x00 22. " EDGE_SEL22 ,Edge Selection 22" "ICR_2_22,Any edge"
|
|
bitfld.long 0x00 21. " EDGE_SEL21 ,Edge Selection 21" "ICR_2_21,Any edge"
|
|
bitfld.long 0x00 20. " EDGE_SEL20 ,Edge Selection 20" "ICR_2_20,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EDGE_SEL19 ,Edge Selection 19" "ICR_2_19,Any edge"
|
|
bitfld.long 0x00 18. " EDGE_SEL18 ,Edge Selection 18" "ICR_2_18,Any edge"
|
|
bitfld.long 0x00 17. " EDGE_SEL17 ,Edge Selection 17" "ICR_2_17,Any edge"
|
|
bitfld.long 0x00 16. " EDGE_SEL16 ,Edge Selection 16" "ICR_2_16,Any edge"
|
|
bitfld.long 0x00 15. " EDGE_SEL15 ,Edge Selection 15" "ICR_1_15,Any edge"
|
|
bitfld.long 0x00 14. " EDGE_SEL14 ,Edge Selection 14" "ICR_1_14,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EDGE_SEL13 ,Edge Selection 13" "ICR_1_13,Any edge"
|
|
bitfld.long 0x00 12. " EDGE_SEL12 ,Edge Selection 12" "ICR_1_12,Any edge"
|
|
bitfld.long 0x00 11. " EDGE_SEL11 ,Edge Selection 11" "ICR_1_11,Any edge"
|
|
bitfld.long 0x00 10. " EDGE_SEL10 ,Edge Selection 10" "ICR_1_10,Any edge"
|
|
bitfld.long 0x00 9. " EDGE_SEL9 ,Edge Selection 9" "ICR_1_9,Any edge"
|
|
bitfld.long 0x00 8. " EDGE_SEL8 ,Edge Selection 8" "ICR_1_8,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDGE_SEL7 ,Edge Selection 7" "ICR_1_7,Any edge"
|
|
bitfld.long 0x00 6. " EDGE_SEL6 ,Edge Selection 6" "ICR_1_6,Any edge"
|
|
bitfld.long 0x00 5. " EDGE_SEL5 ,Edge Selection 5" "ICR_1_5,Any edge"
|
|
bitfld.long 0x00 4. " EDGE_SEL4 ,Edge Selection 4" "ICR_1_4,Any edge"
|
|
bitfld.long 0x00 3. " EDGE_SEL3 ,Edge Selection 3" "ICR_1_3,Any edge"
|
|
bitfld.long 0x00 2. " EDGE_SEL2 ,Edge Selection 2" "ICR_1_2,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDGE_SEL1 ,Edge Selection 1" "ICR_1_1,Any edge"
|
|
bitfld.long 0x00 0. " EDGE_SEL0 ,Edge Selection 0" "ICR_1_0,Any edge"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO2"
|
|
base ad:0x53F88000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,GPIO Data Register"
|
|
bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High"
|
|
line.long 0x04 "GDIR,GPIO Direction Register"
|
|
bitfld.long 0x04 31. " GDIR31 ,GPIO Direction 31 bit" "Input,Output"
|
|
bitfld.long 0x04 30. " GDIR30 ,GPIO Direction 30 bit" "Input,Output"
|
|
bitfld.long 0x04 29. " GDIR29 ,GPIO Direction 29 bit" "Input,Output"
|
|
bitfld.long 0x04 28. " GDIR28 ,GPIO Direction 28 bit" "Input,Output"
|
|
bitfld.long 0x04 27. " GDIR27 ,GPIO Direction 27 bit" "Input,Output"
|
|
bitfld.long 0x04 26. " GDIR26 ,GPIO Direction 26 bit" "Input,Output"
|
|
bitfld.long 0x04 25. " GDIR25 ,GPIO Direction 25 bit" "Input,Output"
|
|
bitfld.long 0x04 24. " GDIR24 ,GPIO Direction 24 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GDIR23 ,GPIO Direction 23 bit" "Input,Output"
|
|
bitfld.long 0x04 22. " GDIR22 ,GPIO Direction 22 bit" "Input,Output"
|
|
bitfld.long 0x04 21. " GDIR21 ,GPIO Direction 21 bit" "Input,Output"
|
|
bitfld.long 0x04 20. " GDIR20 ,GPIO Direction 20 bit" "Input,Output"
|
|
bitfld.long 0x04 19. " GDIR19 ,GPIO Direction 19 bit" "Input,Output"
|
|
bitfld.long 0x04 18. " GDIR18 ,GPIO Direction 18 bit" "Input,Output"
|
|
bitfld.long 0x04 17. " GDIR17 ,GPIO Direction 17 bit" "Input,Output"
|
|
bitfld.long 0x04 16. " GDIR16 ,GPIO Direction 16 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GDIR15 ,GPIO Direction 15 bit" "Input,Output"
|
|
bitfld.long 0x04 14. " GDIR14 ,GPIO Direction 14 bit" "Input,Output"
|
|
bitfld.long 0x04 13. " GDIR13 ,GPIO Direction 13 bit" "Input,Output"
|
|
bitfld.long 0x04 12. " GDIR12 ,GPIO Direction 12 bit" "Input,Output"
|
|
bitfld.long 0x04 11. " GDIR11 ,GPIO Direction 11 bit" "Input,Output"
|
|
bitfld.long 0x04 10. " GDIR10 ,GPIO Direction 10 bit" "Input,Output"
|
|
bitfld.long 0x04 9. " GDIR9 ,GPIO Direction 9 bit" "Input,Output"
|
|
bitfld.long 0x04 8. " GDIR8 ,GPIO Direction 8 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " GDIR7 ,GPIO Direction 7 bit" "Input,Output"
|
|
bitfld.long 0x04 6. " GDIR6 ,GPIO Direction 6 bit" "Input,Output"
|
|
bitfld.long 0x04 5. " GDIR5 ,GPIO Direction 5 bit" "Input,Output"
|
|
bitfld.long 0x04 4. " GDIR4 ,GPIO Direction 4 bit" "Input,Output"
|
|
bitfld.long 0x04 3. " GDIR3 ,GPIO Direction 3 bit" "Input,Output"
|
|
bitfld.long 0x04 2. " GDIR2 ,GPIO Direction 2 bit" "Input,Output"
|
|
bitfld.long 0x04 1. " GDIR1 ,GPIO Direction 1 bit" "Input,Output"
|
|
bitfld.long 0x04 0. " GDIR0 ,GPIO Direction 0 bit" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "PSR,GPIO Pad Status Register"
|
|
bitfld.long 0x00 31. " PSR31 ,GPIO Pad Status bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PSR30 ,GPIO Pad Status bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PSR29 ,GPIO Pad Status bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " PSR28 ,GPIO Pad Status bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PSR27 ,GPIO Pad Status bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PSR26 ,GPIO Pad Status bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " PSR25 ,GPIO Pad Status bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PSR24 ,GPIO Pad Status bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PSR23 ,GPIO Pad Status bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " PSR22 ,GPIO Pad Status bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PSR21 ,GPIO Pad Status bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PSR20 ,GPIO Pad Status bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " PSR19 ,GPIO Pad Status bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PSR18 ,GPIO Pad Status bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PSR17 ,GPIO Pad Status bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " PSR16 ,GPIO Pad Status bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PSR15 ,GPIO Pad Status bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PSR14 ,GPIO Pad Status bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " PSR13 ,GPIO Pad Status bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PSR12 ,GPIO Pad Status bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PSR11 ,GPIO Pad Status bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " PSR10 ,GPIO Pad Status bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PSR9 ,GPIO Pad Status bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PSR8 ,GPIO Pad Status bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PSR7 ,GPIO Pad Status bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PSR6 ,GPIO Pad Status bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PSR5 ,GPIO Pad Status bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " PSR4 ,GPIO Pad Status bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PSR3 ,GPIO Pad Status bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PSR2 ,GPIO Pad Status bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " PSR1 ,GPIO Pad Status bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PSR0 ,GPIO Pad Status bit 0" "Low,High"
|
|
tree "GPIO Interrupt Registers"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 30.--31. " ICR1_15 ,Interrupt 15 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 28.--29. " ICR1_14 ,Interrupt 14 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 26.--27. " ICR1_13 ,Interrupt 13 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 24.--25. " ICR1_12 ,Interrupt 12 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 22.--23. " ICR1_11 ,Interrupt 11 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 20.--21. " ICR1_10 ,Interrupt 10 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ICR1_9 ,Interrupt 9 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 16.--17. " ICR1_8 ,Interrupt 8 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 14.--15. " ICR1_7 ,Interrupt 7 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 12.--13. " ICR1_6 ,Interrupt 6 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 10.--11. " ICR1_5 ,Interrupt 5 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 8.--9. " ICR1_4 ,Interrupt 4 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICR1_3 ,Interrupt 3 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 4.--5. " ICR1_2 ,Interrupt 2 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 2.--3. " ICR1_1 ,Interrupt 1 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 0.--1. " ICR1_0 ,Interrupt 0 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 30.--31. " ICR2_31 ,Interrupt 31 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 28.--29. " ICR2_30 ,Interrupt 30 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 26.--27. " ICR2_29 ,Interrupt 29 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 24.--25. " ICR2_28 ,Interrupt 28 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 22.--23. " ICR2_27 ,Interrupt 27 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 20.--21. " ICR2_26 ,Interrupt 26 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " ICR2_25 ,Interrupt 25 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 16.--17. " ICR2_24 ,Interrupt 24 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 14.--15. " ICR2_23 ,Interrupt 23 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 12.--13. " ICR2_22 ,Interrupt 22 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 10.--11. " ICR2_21 ,Interrupt 21 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 8.--9. " ICR2_20 ,Interrupt 20 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " ICR2_19 ,Interrupt 19 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 4.--5. " ICR2_18 ,Interrupt 18 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 2.--3. " ICR2_17 ,Interrupt 17 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 0.--1. " ICR2_16 ,Interrupt 16 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x08 "IMR,GPIO Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " IMR31 ,Interrupt 31 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 30. " IMR30 ,Interrupt 30 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 29. " IMR29 ,Interrupt 29 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 28. " IMR28 ,Interrupt 28 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 27. " IMR27 ,Interrupt 27 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 26. " IMR26 ,Interrupt 26 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IMR25 ,Interrupt 25 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " IMR24 ,Interrupt 24 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " IMR23 ,Interrupt 23 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " IMR22 ,Interrupt 22 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " IMR21 ,Interrupt 21 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " IMR20 ,Interrupt 20 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IMR19 ,Interrupt 19 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " IMR18 ,Interrupt 18 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " IMR17 ,Interrupt 17 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " IMR16 ,Interrupt 16 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 15. " IMR15 ,Interrupt 15 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 14. " IMR14 ,Interrupt 14 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IMR13 ,Interrupt 13 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " IMR12 ,Interrupt 12 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 11. " IMR11 ,Interrupt 11 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 10. " IMR10 ,Interrupt 10 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " IMR9 ,Interrupt 9 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " IMR8 ,Interrupt 8 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IMR7 ,Interrupt 7 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " IMR6 ,Interrupt 6 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " IMR5 ,Interrupt 5 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " IMR4 ,Interrupt 4 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " IMR3 ,Interrupt 3 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " IMR2 ,Interrupt 2 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IMR1 ,Interrupt 1 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " IMR0 ,Interrupt 0 Mask bit" "Masked,Not masked"
|
|
line.long 0x0C "ISR,GPIO Interrupt Status Register"
|
|
eventfld.long 0x0C 31. " ISR31 ,Interrupt 31 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " ISR30 ,Interrupt 30 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " ISR29 ,Interrupt 29 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " ISR28 ,Interrupt 28 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " ISR27 ,Interrupt 27 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " ISR26 ,Interrupt 26 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " ISR25 ,Interrupt 25 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " ISR24 ,Interrupt 24 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 23. " ISR23 ,Interrupt 23 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " ISR22 ,Interrupt 22 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " ISR21 ,Interrupt 21 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " ISR20 ,Interrupt 20 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " ISR19 ,Interrupt 19 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " ISR18 ,Interrupt 18 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " ISR17 ,Interrupt 17 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " ISR16 ,Interrupt 16 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " ISR15 ,Interrupt 15 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " ISR14 ,Interrupt 14 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " ISR13 ,Interrupt 13 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " ISR12 ,Interrupt 12 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " ISR11 ,Interrupt 11 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " ISR10 ,Interrupt 10 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 9. " ISR9 ,Interrupt 9 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " ISR8 ,Interrupt 8 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " ISR7 ,Interrupt 7 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " ISR6 ,Interrupt 6 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " ISR5 ,Interrupt 5 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " ISR4 ,Interrupt 4 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " ISR3 ,Interrupt 3 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " ISR2 ,Interrupt 2 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " ISR1 ,Interrupt 1 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " ISR0 ,Interrupt 0 Status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
width 0x0B
|
|
width 10.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EDGE_SEL,GPIO Edge Select Register"
|
|
bitfld.long 0x00 31. " EDGE_SEL31 ,Edge Selection 31" "ICR_2_31,Any edge"
|
|
bitfld.long 0x00 30. " EDGE_SEL30 ,Edge Selection 30" "ICR_2_30,Any edge"
|
|
bitfld.long 0x00 29. " EDGE_SEL29 ,Edge Selection 29" "ICR_2_29,Any edge"
|
|
bitfld.long 0x00 28. " EDGE_SEL28 ,Edge Selection 28" "ICR_2_28,Any edge"
|
|
bitfld.long 0x00 27. " EDGE_SEL27 ,Edge Selection 27" "ICR_2_27,Any edge"
|
|
bitfld.long 0x00 26. " EDGE_SEL26 ,Edge Selection 26" "ICR_2_26,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EDGE_SEL25 ,Edge Selection 25" "ICR_2_25,Any edge"
|
|
bitfld.long 0x00 24. " EDGE_SEL24 ,Edge Selection 24" "ICR_2_24,Any edge"
|
|
bitfld.long 0x00 23. " EDGE_SEL23 ,Edge Selection 23" "ICR_2_23,Any edge"
|
|
bitfld.long 0x00 22. " EDGE_SEL22 ,Edge Selection 22" "ICR_2_22,Any edge"
|
|
bitfld.long 0x00 21. " EDGE_SEL21 ,Edge Selection 21" "ICR_2_21,Any edge"
|
|
bitfld.long 0x00 20. " EDGE_SEL20 ,Edge Selection 20" "ICR_2_20,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EDGE_SEL19 ,Edge Selection 19" "ICR_2_19,Any edge"
|
|
bitfld.long 0x00 18. " EDGE_SEL18 ,Edge Selection 18" "ICR_2_18,Any edge"
|
|
bitfld.long 0x00 17. " EDGE_SEL17 ,Edge Selection 17" "ICR_2_17,Any edge"
|
|
bitfld.long 0x00 16. " EDGE_SEL16 ,Edge Selection 16" "ICR_2_16,Any edge"
|
|
bitfld.long 0x00 15. " EDGE_SEL15 ,Edge Selection 15" "ICR_1_15,Any edge"
|
|
bitfld.long 0x00 14. " EDGE_SEL14 ,Edge Selection 14" "ICR_1_14,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EDGE_SEL13 ,Edge Selection 13" "ICR_1_13,Any edge"
|
|
bitfld.long 0x00 12. " EDGE_SEL12 ,Edge Selection 12" "ICR_1_12,Any edge"
|
|
bitfld.long 0x00 11. " EDGE_SEL11 ,Edge Selection 11" "ICR_1_11,Any edge"
|
|
bitfld.long 0x00 10. " EDGE_SEL10 ,Edge Selection 10" "ICR_1_10,Any edge"
|
|
bitfld.long 0x00 9. " EDGE_SEL9 ,Edge Selection 9" "ICR_1_9,Any edge"
|
|
bitfld.long 0x00 8. " EDGE_SEL8 ,Edge Selection 8" "ICR_1_8,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDGE_SEL7 ,Edge Selection 7" "ICR_1_7,Any edge"
|
|
bitfld.long 0x00 6. " EDGE_SEL6 ,Edge Selection 6" "ICR_1_6,Any edge"
|
|
bitfld.long 0x00 5. " EDGE_SEL5 ,Edge Selection 5" "ICR_1_5,Any edge"
|
|
bitfld.long 0x00 4. " EDGE_SEL4 ,Edge Selection 4" "ICR_1_4,Any edge"
|
|
bitfld.long 0x00 3. " EDGE_SEL3 ,Edge Selection 3" "ICR_1_3,Any edge"
|
|
bitfld.long 0x00 2. " EDGE_SEL2 ,Edge Selection 2" "ICR_1_2,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDGE_SEL1 ,Edge Selection 1" "ICR_1_1,Any edge"
|
|
bitfld.long 0x00 0. " EDGE_SEL0 ,Edge Selection 0" "ICR_1_0,Any edge"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO3"
|
|
base ad:0x53F8C000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,GPIO Data Register"
|
|
bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High"
|
|
line.long 0x04 "GDIR,GPIO Direction Register"
|
|
bitfld.long 0x04 31. " GDIR31 ,GPIO Direction 31 bit" "Input,Output"
|
|
bitfld.long 0x04 30. " GDIR30 ,GPIO Direction 30 bit" "Input,Output"
|
|
bitfld.long 0x04 29. " GDIR29 ,GPIO Direction 29 bit" "Input,Output"
|
|
bitfld.long 0x04 28. " GDIR28 ,GPIO Direction 28 bit" "Input,Output"
|
|
bitfld.long 0x04 27. " GDIR27 ,GPIO Direction 27 bit" "Input,Output"
|
|
bitfld.long 0x04 26. " GDIR26 ,GPIO Direction 26 bit" "Input,Output"
|
|
bitfld.long 0x04 25. " GDIR25 ,GPIO Direction 25 bit" "Input,Output"
|
|
bitfld.long 0x04 24. " GDIR24 ,GPIO Direction 24 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GDIR23 ,GPIO Direction 23 bit" "Input,Output"
|
|
bitfld.long 0x04 22. " GDIR22 ,GPIO Direction 22 bit" "Input,Output"
|
|
bitfld.long 0x04 21. " GDIR21 ,GPIO Direction 21 bit" "Input,Output"
|
|
bitfld.long 0x04 20. " GDIR20 ,GPIO Direction 20 bit" "Input,Output"
|
|
bitfld.long 0x04 19. " GDIR19 ,GPIO Direction 19 bit" "Input,Output"
|
|
bitfld.long 0x04 18. " GDIR18 ,GPIO Direction 18 bit" "Input,Output"
|
|
bitfld.long 0x04 17. " GDIR17 ,GPIO Direction 17 bit" "Input,Output"
|
|
bitfld.long 0x04 16. " GDIR16 ,GPIO Direction 16 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GDIR15 ,GPIO Direction 15 bit" "Input,Output"
|
|
bitfld.long 0x04 14. " GDIR14 ,GPIO Direction 14 bit" "Input,Output"
|
|
bitfld.long 0x04 13. " GDIR13 ,GPIO Direction 13 bit" "Input,Output"
|
|
bitfld.long 0x04 12. " GDIR12 ,GPIO Direction 12 bit" "Input,Output"
|
|
bitfld.long 0x04 11. " GDIR11 ,GPIO Direction 11 bit" "Input,Output"
|
|
bitfld.long 0x04 10. " GDIR10 ,GPIO Direction 10 bit" "Input,Output"
|
|
bitfld.long 0x04 9. " GDIR9 ,GPIO Direction 9 bit" "Input,Output"
|
|
bitfld.long 0x04 8. " GDIR8 ,GPIO Direction 8 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " GDIR7 ,GPIO Direction 7 bit" "Input,Output"
|
|
bitfld.long 0x04 6. " GDIR6 ,GPIO Direction 6 bit" "Input,Output"
|
|
bitfld.long 0x04 5. " GDIR5 ,GPIO Direction 5 bit" "Input,Output"
|
|
bitfld.long 0x04 4. " GDIR4 ,GPIO Direction 4 bit" "Input,Output"
|
|
bitfld.long 0x04 3. " GDIR3 ,GPIO Direction 3 bit" "Input,Output"
|
|
bitfld.long 0x04 2. " GDIR2 ,GPIO Direction 2 bit" "Input,Output"
|
|
bitfld.long 0x04 1. " GDIR1 ,GPIO Direction 1 bit" "Input,Output"
|
|
bitfld.long 0x04 0. " GDIR0 ,GPIO Direction 0 bit" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "PSR,GPIO Pad Status Register"
|
|
bitfld.long 0x00 31. " PSR31 ,GPIO Pad Status bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PSR30 ,GPIO Pad Status bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PSR29 ,GPIO Pad Status bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " PSR28 ,GPIO Pad Status bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PSR27 ,GPIO Pad Status bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PSR26 ,GPIO Pad Status bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " PSR25 ,GPIO Pad Status bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PSR24 ,GPIO Pad Status bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PSR23 ,GPIO Pad Status bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " PSR22 ,GPIO Pad Status bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PSR21 ,GPIO Pad Status bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PSR20 ,GPIO Pad Status bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " PSR19 ,GPIO Pad Status bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PSR18 ,GPIO Pad Status bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PSR17 ,GPIO Pad Status bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " PSR16 ,GPIO Pad Status bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PSR15 ,GPIO Pad Status bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PSR14 ,GPIO Pad Status bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " PSR13 ,GPIO Pad Status bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PSR12 ,GPIO Pad Status bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PSR11 ,GPIO Pad Status bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " PSR10 ,GPIO Pad Status bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PSR9 ,GPIO Pad Status bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PSR8 ,GPIO Pad Status bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PSR7 ,GPIO Pad Status bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PSR6 ,GPIO Pad Status bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PSR5 ,GPIO Pad Status bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " PSR4 ,GPIO Pad Status bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PSR3 ,GPIO Pad Status bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PSR2 ,GPIO Pad Status bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " PSR1 ,GPIO Pad Status bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PSR0 ,GPIO Pad Status bit 0" "Low,High"
|
|
tree "GPIO Interrupt Registers"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 30.--31. " ICR1_15 ,Interrupt 15 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 28.--29. " ICR1_14 ,Interrupt 14 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 26.--27. " ICR1_13 ,Interrupt 13 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 24.--25. " ICR1_12 ,Interrupt 12 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 22.--23. " ICR1_11 ,Interrupt 11 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 20.--21. " ICR1_10 ,Interrupt 10 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ICR1_9 ,Interrupt 9 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 16.--17. " ICR1_8 ,Interrupt 8 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 14.--15. " ICR1_7 ,Interrupt 7 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 12.--13. " ICR1_6 ,Interrupt 6 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 10.--11. " ICR1_5 ,Interrupt 5 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 8.--9. " ICR1_4 ,Interrupt 4 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICR1_3 ,Interrupt 3 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 4.--5. " ICR1_2 ,Interrupt 2 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 2.--3. " ICR1_1 ,Interrupt 1 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 0.--1. " ICR1_0 ,Interrupt 0 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 30.--31. " ICR2_31 ,Interrupt 31 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 28.--29. " ICR2_30 ,Interrupt 30 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 26.--27. " ICR2_29 ,Interrupt 29 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 24.--25. " ICR2_28 ,Interrupt 28 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 22.--23. " ICR2_27 ,Interrupt 27 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 20.--21. " ICR2_26 ,Interrupt 26 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " ICR2_25 ,Interrupt 25 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 16.--17. " ICR2_24 ,Interrupt 24 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 14.--15. " ICR2_23 ,Interrupt 23 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 12.--13. " ICR2_22 ,Interrupt 22 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 10.--11. " ICR2_21 ,Interrupt 21 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 8.--9. " ICR2_20 ,Interrupt 20 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " ICR2_19 ,Interrupt 19 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 4.--5. " ICR2_18 ,Interrupt 18 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 2.--3. " ICR2_17 ,Interrupt 17 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 0.--1. " ICR2_16 ,Interrupt 16 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x08 "IMR,GPIO Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " IMR31 ,Interrupt 31 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 30. " IMR30 ,Interrupt 30 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 29. " IMR29 ,Interrupt 29 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 28. " IMR28 ,Interrupt 28 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 27. " IMR27 ,Interrupt 27 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 26. " IMR26 ,Interrupt 26 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IMR25 ,Interrupt 25 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " IMR24 ,Interrupt 24 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " IMR23 ,Interrupt 23 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " IMR22 ,Interrupt 22 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " IMR21 ,Interrupt 21 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " IMR20 ,Interrupt 20 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IMR19 ,Interrupt 19 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " IMR18 ,Interrupt 18 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " IMR17 ,Interrupt 17 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " IMR16 ,Interrupt 16 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 15. " IMR15 ,Interrupt 15 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 14. " IMR14 ,Interrupt 14 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IMR13 ,Interrupt 13 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " IMR12 ,Interrupt 12 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 11. " IMR11 ,Interrupt 11 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 10. " IMR10 ,Interrupt 10 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " IMR9 ,Interrupt 9 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " IMR8 ,Interrupt 8 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IMR7 ,Interrupt 7 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " IMR6 ,Interrupt 6 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " IMR5 ,Interrupt 5 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " IMR4 ,Interrupt 4 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " IMR3 ,Interrupt 3 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " IMR2 ,Interrupt 2 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IMR1 ,Interrupt 1 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " IMR0 ,Interrupt 0 Mask bit" "Masked,Not masked"
|
|
line.long 0x0C "ISR,GPIO Interrupt Status Register"
|
|
eventfld.long 0x0C 31. " ISR31 ,Interrupt 31 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " ISR30 ,Interrupt 30 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " ISR29 ,Interrupt 29 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " ISR28 ,Interrupt 28 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " ISR27 ,Interrupt 27 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " ISR26 ,Interrupt 26 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " ISR25 ,Interrupt 25 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " ISR24 ,Interrupt 24 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 23. " ISR23 ,Interrupt 23 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " ISR22 ,Interrupt 22 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " ISR21 ,Interrupt 21 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " ISR20 ,Interrupt 20 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " ISR19 ,Interrupt 19 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " ISR18 ,Interrupt 18 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " ISR17 ,Interrupt 17 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " ISR16 ,Interrupt 16 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " ISR15 ,Interrupt 15 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " ISR14 ,Interrupt 14 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " ISR13 ,Interrupt 13 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " ISR12 ,Interrupt 12 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " ISR11 ,Interrupt 11 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " ISR10 ,Interrupt 10 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 9. " ISR9 ,Interrupt 9 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " ISR8 ,Interrupt 8 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " ISR7 ,Interrupt 7 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " ISR6 ,Interrupt 6 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " ISR5 ,Interrupt 5 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " ISR4 ,Interrupt 4 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " ISR3 ,Interrupt 3 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " ISR2 ,Interrupt 2 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " ISR1 ,Interrupt 1 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " ISR0 ,Interrupt 0 Status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
width 0x0B
|
|
width 10.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EDGE_SEL,GPIO Edge Select Register"
|
|
bitfld.long 0x00 31. " EDGE_SEL31 ,Edge Selection 31" "ICR_2_31,Any edge"
|
|
bitfld.long 0x00 30. " EDGE_SEL30 ,Edge Selection 30" "ICR_2_30,Any edge"
|
|
bitfld.long 0x00 29. " EDGE_SEL29 ,Edge Selection 29" "ICR_2_29,Any edge"
|
|
bitfld.long 0x00 28. " EDGE_SEL28 ,Edge Selection 28" "ICR_2_28,Any edge"
|
|
bitfld.long 0x00 27. " EDGE_SEL27 ,Edge Selection 27" "ICR_2_27,Any edge"
|
|
bitfld.long 0x00 26. " EDGE_SEL26 ,Edge Selection 26" "ICR_2_26,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EDGE_SEL25 ,Edge Selection 25" "ICR_2_25,Any edge"
|
|
bitfld.long 0x00 24. " EDGE_SEL24 ,Edge Selection 24" "ICR_2_24,Any edge"
|
|
bitfld.long 0x00 23. " EDGE_SEL23 ,Edge Selection 23" "ICR_2_23,Any edge"
|
|
bitfld.long 0x00 22. " EDGE_SEL22 ,Edge Selection 22" "ICR_2_22,Any edge"
|
|
bitfld.long 0x00 21. " EDGE_SEL21 ,Edge Selection 21" "ICR_2_21,Any edge"
|
|
bitfld.long 0x00 20. " EDGE_SEL20 ,Edge Selection 20" "ICR_2_20,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EDGE_SEL19 ,Edge Selection 19" "ICR_2_19,Any edge"
|
|
bitfld.long 0x00 18. " EDGE_SEL18 ,Edge Selection 18" "ICR_2_18,Any edge"
|
|
bitfld.long 0x00 17. " EDGE_SEL17 ,Edge Selection 17" "ICR_2_17,Any edge"
|
|
bitfld.long 0x00 16. " EDGE_SEL16 ,Edge Selection 16" "ICR_2_16,Any edge"
|
|
bitfld.long 0x00 15. " EDGE_SEL15 ,Edge Selection 15" "ICR_1_15,Any edge"
|
|
bitfld.long 0x00 14. " EDGE_SEL14 ,Edge Selection 14" "ICR_1_14,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EDGE_SEL13 ,Edge Selection 13" "ICR_1_13,Any edge"
|
|
bitfld.long 0x00 12. " EDGE_SEL12 ,Edge Selection 12" "ICR_1_12,Any edge"
|
|
bitfld.long 0x00 11. " EDGE_SEL11 ,Edge Selection 11" "ICR_1_11,Any edge"
|
|
bitfld.long 0x00 10. " EDGE_SEL10 ,Edge Selection 10" "ICR_1_10,Any edge"
|
|
bitfld.long 0x00 9. " EDGE_SEL9 ,Edge Selection 9" "ICR_1_9,Any edge"
|
|
bitfld.long 0x00 8. " EDGE_SEL8 ,Edge Selection 8" "ICR_1_8,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDGE_SEL7 ,Edge Selection 7" "ICR_1_7,Any edge"
|
|
bitfld.long 0x00 6. " EDGE_SEL6 ,Edge Selection 6" "ICR_1_6,Any edge"
|
|
bitfld.long 0x00 5. " EDGE_SEL5 ,Edge Selection 5" "ICR_1_5,Any edge"
|
|
bitfld.long 0x00 4. " EDGE_SEL4 ,Edge Selection 4" "ICR_1_4,Any edge"
|
|
bitfld.long 0x00 3. " EDGE_SEL3 ,Edge Selection 3" "ICR_1_3,Any edge"
|
|
bitfld.long 0x00 2. " EDGE_SEL2 ,Edge Selection 2" "ICR_1_2,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDGE_SEL1 ,Edge Selection 1" "ICR_1_1,Any edge"
|
|
bitfld.long 0x00 0. " EDGE_SEL0 ,Edge Selection 0" "ICR_1_0,Any edge"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO4"
|
|
base ad:0x53F90000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,GPIO Data Register"
|
|
bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High"
|
|
line.long 0x04 "GDIR,GPIO Direction Register"
|
|
bitfld.long 0x04 31. " GDIR31 ,GPIO Direction 31 bit" "Input,Output"
|
|
bitfld.long 0x04 30. " GDIR30 ,GPIO Direction 30 bit" "Input,Output"
|
|
bitfld.long 0x04 29. " GDIR29 ,GPIO Direction 29 bit" "Input,Output"
|
|
bitfld.long 0x04 28. " GDIR28 ,GPIO Direction 28 bit" "Input,Output"
|
|
bitfld.long 0x04 27. " GDIR27 ,GPIO Direction 27 bit" "Input,Output"
|
|
bitfld.long 0x04 26. " GDIR26 ,GPIO Direction 26 bit" "Input,Output"
|
|
bitfld.long 0x04 25. " GDIR25 ,GPIO Direction 25 bit" "Input,Output"
|
|
bitfld.long 0x04 24. " GDIR24 ,GPIO Direction 24 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GDIR23 ,GPIO Direction 23 bit" "Input,Output"
|
|
bitfld.long 0x04 22. " GDIR22 ,GPIO Direction 22 bit" "Input,Output"
|
|
bitfld.long 0x04 21. " GDIR21 ,GPIO Direction 21 bit" "Input,Output"
|
|
bitfld.long 0x04 20. " GDIR20 ,GPIO Direction 20 bit" "Input,Output"
|
|
bitfld.long 0x04 19. " GDIR19 ,GPIO Direction 19 bit" "Input,Output"
|
|
bitfld.long 0x04 18. " GDIR18 ,GPIO Direction 18 bit" "Input,Output"
|
|
bitfld.long 0x04 17. " GDIR17 ,GPIO Direction 17 bit" "Input,Output"
|
|
bitfld.long 0x04 16. " GDIR16 ,GPIO Direction 16 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GDIR15 ,GPIO Direction 15 bit" "Input,Output"
|
|
bitfld.long 0x04 14. " GDIR14 ,GPIO Direction 14 bit" "Input,Output"
|
|
bitfld.long 0x04 13. " GDIR13 ,GPIO Direction 13 bit" "Input,Output"
|
|
bitfld.long 0x04 12. " GDIR12 ,GPIO Direction 12 bit" "Input,Output"
|
|
bitfld.long 0x04 11. " GDIR11 ,GPIO Direction 11 bit" "Input,Output"
|
|
bitfld.long 0x04 10. " GDIR10 ,GPIO Direction 10 bit" "Input,Output"
|
|
bitfld.long 0x04 9. " GDIR9 ,GPIO Direction 9 bit" "Input,Output"
|
|
bitfld.long 0x04 8. " GDIR8 ,GPIO Direction 8 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " GDIR7 ,GPIO Direction 7 bit" "Input,Output"
|
|
bitfld.long 0x04 6. " GDIR6 ,GPIO Direction 6 bit" "Input,Output"
|
|
bitfld.long 0x04 5. " GDIR5 ,GPIO Direction 5 bit" "Input,Output"
|
|
bitfld.long 0x04 4. " GDIR4 ,GPIO Direction 4 bit" "Input,Output"
|
|
bitfld.long 0x04 3. " GDIR3 ,GPIO Direction 3 bit" "Input,Output"
|
|
bitfld.long 0x04 2. " GDIR2 ,GPIO Direction 2 bit" "Input,Output"
|
|
bitfld.long 0x04 1. " GDIR1 ,GPIO Direction 1 bit" "Input,Output"
|
|
bitfld.long 0x04 0. " GDIR0 ,GPIO Direction 0 bit" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "PSR,GPIO Pad Status Register"
|
|
bitfld.long 0x00 31. " PSR31 ,GPIO Pad Status bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PSR30 ,GPIO Pad Status bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PSR29 ,GPIO Pad Status bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " PSR28 ,GPIO Pad Status bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PSR27 ,GPIO Pad Status bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PSR26 ,GPIO Pad Status bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " PSR25 ,GPIO Pad Status bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PSR24 ,GPIO Pad Status bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PSR23 ,GPIO Pad Status bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " PSR22 ,GPIO Pad Status bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PSR21 ,GPIO Pad Status bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PSR20 ,GPIO Pad Status bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " PSR19 ,GPIO Pad Status bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PSR18 ,GPIO Pad Status bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PSR17 ,GPIO Pad Status bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " PSR16 ,GPIO Pad Status bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PSR15 ,GPIO Pad Status bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PSR14 ,GPIO Pad Status bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " PSR13 ,GPIO Pad Status bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PSR12 ,GPIO Pad Status bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PSR11 ,GPIO Pad Status bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " PSR10 ,GPIO Pad Status bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PSR9 ,GPIO Pad Status bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PSR8 ,GPIO Pad Status bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PSR7 ,GPIO Pad Status bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PSR6 ,GPIO Pad Status bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PSR5 ,GPIO Pad Status bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " PSR4 ,GPIO Pad Status bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PSR3 ,GPIO Pad Status bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PSR2 ,GPIO Pad Status bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " PSR1 ,GPIO Pad Status bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PSR0 ,GPIO Pad Status bit 0" "Low,High"
|
|
tree "GPIO Interrupt Registers"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 30.--31. " ICR1_15 ,Interrupt 15 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 28.--29. " ICR1_14 ,Interrupt 14 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 26.--27. " ICR1_13 ,Interrupt 13 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 24.--25. " ICR1_12 ,Interrupt 12 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 22.--23. " ICR1_11 ,Interrupt 11 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 20.--21. " ICR1_10 ,Interrupt 10 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ICR1_9 ,Interrupt 9 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 16.--17. " ICR1_8 ,Interrupt 8 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 14.--15. " ICR1_7 ,Interrupt 7 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 12.--13. " ICR1_6 ,Interrupt 6 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 10.--11. " ICR1_5 ,Interrupt 5 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 8.--9. " ICR1_4 ,Interrupt 4 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICR1_3 ,Interrupt 3 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 4.--5. " ICR1_2 ,Interrupt 2 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 2.--3. " ICR1_1 ,Interrupt 1 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 0.--1. " ICR1_0 ,Interrupt 0 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 30.--31. " ICR2_31 ,Interrupt 31 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 28.--29. " ICR2_30 ,Interrupt 30 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 26.--27. " ICR2_29 ,Interrupt 29 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 24.--25. " ICR2_28 ,Interrupt 28 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 22.--23. " ICR2_27 ,Interrupt 27 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 20.--21. " ICR2_26 ,Interrupt 26 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " ICR2_25 ,Interrupt 25 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 16.--17. " ICR2_24 ,Interrupt 24 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 14.--15. " ICR2_23 ,Interrupt 23 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 12.--13. " ICR2_22 ,Interrupt 22 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 10.--11. " ICR2_21 ,Interrupt 21 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 8.--9. " ICR2_20 ,Interrupt 20 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " ICR2_19 ,Interrupt 19 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 4.--5. " ICR2_18 ,Interrupt 18 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 2.--3. " ICR2_17 ,Interrupt 17 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 0.--1. " ICR2_16 ,Interrupt 16 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x08 "IMR,GPIO Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " IMR31 ,Interrupt 31 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 30. " IMR30 ,Interrupt 30 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 29. " IMR29 ,Interrupt 29 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 28. " IMR28 ,Interrupt 28 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 27. " IMR27 ,Interrupt 27 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 26. " IMR26 ,Interrupt 26 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IMR25 ,Interrupt 25 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " IMR24 ,Interrupt 24 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " IMR23 ,Interrupt 23 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " IMR22 ,Interrupt 22 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " IMR21 ,Interrupt 21 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " IMR20 ,Interrupt 20 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IMR19 ,Interrupt 19 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " IMR18 ,Interrupt 18 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " IMR17 ,Interrupt 17 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " IMR16 ,Interrupt 16 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 15. " IMR15 ,Interrupt 15 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 14. " IMR14 ,Interrupt 14 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IMR13 ,Interrupt 13 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " IMR12 ,Interrupt 12 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 11. " IMR11 ,Interrupt 11 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 10. " IMR10 ,Interrupt 10 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " IMR9 ,Interrupt 9 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " IMR8 ,Interrupt 8 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IMR7 ,Interrupt 7 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " IMR6 ,Interrupt 6 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " IMR5 ,Interrupt 5 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " IMR4 ,Interrupt 4 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " IMR3 ,Interrupt 3 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " IMR2 ,Interrupt 2 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IMR1 ,Interrupt 1 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " IMR0 ,Interrupt 0 Mask bit" "Masked,Not masked"
|
|
line.long 0x0C "ISR,GPIO Interrupt Status Register"
|
|
eventfld.long 0x0C 31. " ISR31 ,Interrupt 31 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " ISR30 ,Interrupt 30 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " ISR29 ,Interrupt 29 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " ISR28 ,Interrupt 28 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " ISR27 ,Interrupt 27 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " ISR26 ,Interrupt 26 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " ISR25 ,Interrupt 25 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " ISR24 ,Interrupt 24 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 23. " ISR23 ,Interrupt 23 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " ISR22 ,Interrupt 22 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " ISR21 ,Interrupt 21 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " ISR20 ,Interrupt 20 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " ISR19 ,Interrupt 19 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " ISR18 ,Interrupt 18 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " ISR17 ,Interrupt 17 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " ISR16 ,Interrupt 16 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " ISR15 ,Interrupt 15 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " ISR14 ,Interrupt 14 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " ISR13 ,Interrupt 13 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " ISR12 ,Interrupt 12 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " ISR11 ,Interrupt 11 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " ISR10 ,Interrupt 10 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 9. " ISR9 ,Interrupt 9 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " ISR8 ,Interrupt 8 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " ISR7 ,Interrupt 7 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " ISR6 ,Interrupt 6 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " ISR5 ,Interrupt 5 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " ISR4 ,Interrupt 4 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " ISR3 ,Interrupt 3 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " ISR2 ,Interrupt 2 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " ISR1 ,Interrupt 1 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " ISR0 ,Interrupt 0 Status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
width 0x0B
|
|
width 10.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EDGE_SEL,GPIO Edge Select Register"
|
|
bitfld.long 0x00 31. " EDGE_SEL31 ,Edge Selection 31" "ICR_2_31,Any edge"
|
|
bitfld.long 0x00 30. " EDGE_SEL30 ,Edge Selection 30" "ICR_2_30,Any edge"
|
|
bitfld.long 0x00 29. " EDGE_SEL29 ,Edge Selection 29" "ICR_2_29,Any edge"
|
|
bitfld.long 0x00 28. " EDGE_SEL28 ,Edge Selection 28" "ICR_2_28,Any edge"
|
|
bitfld.long 0x00 27. " EDGE_SEL27 ,Edge Selection 27" "ICR_2_27,Any edge"
|
|
bitfld.long 0x00 26. " EDGE_SEL26 ,Edge Selection 26" "ICR_2_26,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EDGE_SEL25 ,Edge Selection 25" "ICR_2_25,Any edge"
|
|
bitfld.long 0x00 24. " EDGE_SEL24 ,Edge Selection 24" "ICR_2_24,Any edge"
|
|
bitfld.long 0x00 23. " EDGE_SEL23 ,Edge Selection 23" "ICR_2_23,Any edge"
|
|
bitfld.long 0x00 22. " EDGE_SEL22 ,Edge Selection 22" "ICR_2_22,Any edge"
|
|
bitfld.long 0x00 21. " EDGE_SEL21 ,Edge Selection 21" "ICR_2_21,Any edge"
|
|
bitfld.long 0x00 20. " EDGE_SEL20 ,Edge Selection 20" "ICR_2_20,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EDGE_SEL19 ,Edge Selection 19" "ICR_2_19,Any edge"
|
|
bitfld.long 0x00 18. " EDGE_SEL18 ,Edge Selection 18" "ICR_2_18,Any edge"
|
|
bitfld.long 0x00 17. " EDGE_SEL17 ,Edge Selection 17" "ICR_2_17,Any edge"
|
|
bitfld.long 0x00 16. " EDGE_SEL16 ,Edge Selection 16" "ICR_2_16,Any edge"
|
|
bitfld.long 0x00 15. " EDGE_SEL15 ,Edge Selection 15" "ICR_1_15,Any edge"
|
|
bitfld.long 0x00 14. " EDGE_SEL14 ,Edge Selection 14" "ICR_1_14,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EDGE_SEL13 ,Edge Selection 13" "ICR_1_13,Any edge"
|
|
bitfld.long 0x00 12. " EDGE_SEL12 ,Edge Selection 12" "ICR_1_12,Any edge"
|
|
bitfld.long 0x00 11. " EDGE_SEL11 ,Edge Selection 11" "ICR_1_11,Any edge"
|
|
bitfld.long 0x00 10. " EDGE_SEL10 ,Edge Selection 10" "ICR_1_10,Any edge"
|
|
bitfld.long 0x00 9. " EDGE_SEL9 ,Edge Selection 9" "ICR_1_9,Any edge"
|
|
bitfld.long 0x00 8. " EDGE_SEL8 ,Edge Selection 8" "ICR_1_8,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDGE_SEL7 ,Edge Selection 7" "ICR_1_7,Any edge"
|
|
bitfld.long 0x00 6. " EDGE_SEL6 ,Edge Selection 6" "ICR_1_6,Any edge"
|
|
bitfld.long 0x00 5. " EDGE_SEL5 ,Edge Selection 5" "ICR_1_5,Any edge"
|
|
bitfld.long 0x00 4. " EDGE_SEL4 ,Edge Selection 4" "ICR_1_4,Any edge"
|
|
bitfld.long 0x00 3. " EDGE_SEL3 ,Edge Selection 3" "ICR_1_3,Any edge"
|
|
bitfld.long 0x00 2. " EDGE_SEL2 ,Edge Selection 2" "ICR_1_2,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDGE_SEL1 ,Edge Selection 1" "ICR_1_1,Any edge"
|
|
bitfld.long 0x00 0. " EDGE_SEL0 ,Edge Selection 0" "ICR_1_0,Any edge"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO5"
|
|
base ad:0x53FDC000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,GPIO Data Register"
|
|
bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High"
|
|
line.long 0x04 "GDIR,GPIO Direction Register"
|
|
bitfld.long 0x04 31. " GDIR31 ,GPIO Direction 31 bit" "Input,Output"
|
|
bitfld.long 0x04 30. " GDIR30 ,GPIO Direction 30 bit" "Input,Output"
|
|
bitfld.long 0x04 29. " GDIR29 ,GPIO Direction 29 bit" "Input,Output"
|
|
bitfld.long 0x04 28. " GDIR28 ,GPIO Direction 28 bit" "Input,Output"
|
|
bitfld.long 0x04 27. " GDIR27 ,GPIO Direction 27 bit" "Input,Output"
|
|
bitfld.long 0x04 26. " GDIR26 ,GPIO Direction 26 bit" "Input,Output"
|
|
bitfld.long 0x04 25. " GDIR25 ,GPIO Direction 25 bit" "Input,Output"
|
|
bitfld.long 0x04 24. " GDIR24 ,GPIO Direction 24 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GDIR23 ,GPIO Direction 23 bit" "Input,Output"
|
|
bitfld.long 0x04 22. " GDIR22 ,GPIO Direction 22 bit" "Input,Output"
|
|
bitfld.long 0x04 21. " GDIR21 ,GPIO Direction 21 bit" "Input,Output"
|
|
bitfld.long 0x04 20. " GDIR20 ,GPIO Direction 20 bit" "Input,Output"
|
|
bitfld.long 0x04 19. " GDIR19 ,GPIO Direction 19 bit" "Input,Output"
|
|
bitfld.long 0x04 18. " GDIR18 ,GPIO Direction 18 bit" "Input,Output"
|
|
bitfld.long 0x04 17. " GDIR17 ,GPIO Direction 17 bit" "Input,Output"
|
|
bitfld.long 0x04 16. " GDIR16 ,GPIO Direction 16 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GDIR15 ,GPIO Direction 15 bit" "Input,Output"
|
|
bitfld.long 0x04 14. " GDIR14 ,GPIO Direction 14 bit" "Input,Output"
|
|
bitfld.long 0x04 13. " GDIR13 ,GPIO Direction 13 bit" "Input,Output"
|
|
bitfld.long 0x04 12. " GDIR12 ,GPIO Direction 12 bit" "Input,Output"
|
|
bitfld.long 0x04 11. " GDIR11 ,GPIO Direction 11 bit" "Input,Output"
|
|
bitfld.long 0x04 10. " GDIR10 ,GPIO Direction 10 bit" "Input,Output"
|
|
bitfld.long 0x04 9. " GDIR9 ,GPIO Direction 9 bit" "Input,Output"
|
|
bitfld.long 0x04 8. " GDIR8 ,GPIO Direction 8 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " GDIR7 ,GPIO Direction 7 bit" "Input,Output"
|
|
bitfld.long 0x04 6. " GDIR6 ,GPIO Direction 6 bit" "Input,Output"
|
|
bitfld.long 0x04 5. " GDIR5 ,GPIO Direction 5 bit" "Input,Output"
|
|
bitfld.long 0x04 4. " GDIR4 ,GPIO Direction 4 bit" "Input,Output"
|
|
bitfld.long 0x04 3. " GDIR3 ,GPIO Direction 3 bit" "Input,Output"
|
|
bitfld.long 0x04 2. " GDIR2 ,GPIO Direction 2 bit" "Input,Output"
|
|
bitfld.long 0x04 1. " GDIR1 ,GPIO Direction 1 bit" "Input,Output"
|
|
bitfld.long 0x04 0. " GDIR0 ,GPIO Direction 0 bit" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "PSR,GPIO Pad Status Register"
|
|
bitfld.long 0x00 31. " PSR31 ,GPIO Pad Status bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PSR30 ,GPIO Pad Status bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PSR29 ,GPIO Pad Status bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " PSR28 ,GPIO Pad Status bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PSR27 ,GPIO Pad Status bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PSR26 ,GPIO Pad Status bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " PSR25 ,GPIO Pad Status bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PSR24 ,GPIO Pad Status bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PSR23 ,GPIO Pad Status bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " PSR22 ,GPIO Pad Status bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PSR21 ,GPIO Pad Status bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PSR20 ,GPIO Pad Status bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " PSR19 ,GPIO Pad Status bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PSR18 ,GPIO Pad Status bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PSR17 ,GPIO Pad Status bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " PSR16 ,GPIO Pad Status bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PSR15 ,GPIO Pad Status bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PSR14 ,GPIO Pad Status bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " PSR13 ,GPIO Pad Status bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PSR12 ,GPIO Pad Status bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PSR11 ,GPIO Pad Status bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " PSR10 ,GPIO Pad Status bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PSR9 ,GPIO Pad Status bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PSR8 ,GPIO Pad Status bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PSR7 ,GPIO Pad Status bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PSR6 ,GPIO Pad Status bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PSR5 ,GPIO Pad Status bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " PSR4 ,GPIO Pad Status bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PSR3 ,GPIO Pad Status bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PSR2 ,GPIO Pad Status bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " PSR1 ,GPIO Pad Status bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PSR0 ,GPIO Pad Status bit 0" "Low,High"
|
|
tree "GPIO Interrupt Registers"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 30.--31. " ICR1_15 ,Interrupt 15 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 28.--29. " ICR1_14 ,Interrupt 14 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 26.--27. " ICR1_13 ,Interrupt 13 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 24.--25. " ICR1_12 ,Interrupt 12 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 22.--23. " ICR1_11 ,Interrupt 11 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 20.--21. " ICR1_10 ,Interrupt 10 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ICR1_9 ,Interrupt 9 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 16.--17. " ICR1_8 ,Interrupt 8 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 14.--15. " ICR1_7 ,Interrupt 7 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 12.--13. " ICR1_6 ,Interrupt 6 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 10.--11. " ICR1_5 ,Interrupt 5 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 8.--9. " ICR1_4 ,Interrupt 4 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICR1_3 ,Interrupt 3 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 4.--5. " ICR1_2 ,Interrupt 2 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 2.--3. " ICR1_1 ,Interrupt 1 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 0.--1. " ICR1_0 ,Interrupt 0 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 30.--31. " ICR2_31 ,Interrupt 31 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 28.--29. " ICR2_30 ,Interrupt 30 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 26.--27. " ICR2_29 ,Interrupt 29 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 24.--25. " ICR2_28 ,Interrupt 28 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 22.--23. " ICR2_27 ,Interrupt 27 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 20.--21. " ICR2_26 ,Interrupt 26 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " ICR2_25 ,Interrupt 25 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 16.--17. " ICR2_24 ,Interrupt 24 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 14.--15. " ICR2_23 ,Interrupt 23 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 12.--13. " ICR2_22 ,Interrupt 22 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 10.--11. " ICR2_21 ,Interrupt 21 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 8.--9. " ICR2_20 ,Interrupt 20 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " ICR2_19 ,Interrupt 19 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 4.--5. " ICR2_18 ,Interrupt 18 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 2.--3. " ICR2_17 ,Interrupt 17 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 0.--1. " ICR2_16 ,Interrupt 16 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x08 "IMR,GPIO Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " IMR31 ,Interrupt 31 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 30. " IMR30 ,Interrupt 30 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 29. " IMR29 ,Interrupt 29 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 28. " IMR28 ,Interrupt 28 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 27. " IMR27 ,Interrupt 27 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 26. " IMR26 ,Interrupt 26 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IMR25 ,Interrupt 25 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " IMR24 ,Interrupt 24 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " IMR23 ,Interrupt 23 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " IMR22 ,Interrupt 22 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " IMR21 ,Interrupt 21 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " IMR20 ,Interrupt 20 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IMR19 ,Interrupt 19 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " IMR18 ,Interrupt 18 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " IMR17 ,Interrupt 17 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " IMR16 ,Interrupt 16 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 15. " IMR15 ,Interrupt 15 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 14. " IMR14 ,Interrupt 14 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IMR13 ,Interrupt 13 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " IMR12 ,Interrupt 12 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 11. " IMR11 ,Interrupt 11 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 10. " IMR10 ,Interrupt 10 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " IMR9 ,Interrupt 9 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " IMR8 ,Interrupt 8 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IMR7 ,Interrupt 7 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " IMR6 ,Interrupt 6 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " IMR5 ,Interrupt 5 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " IMR4 ,Interrupt 4 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " IMR3 ,Interrupt 3 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " IMR2 ,Interrupt 2 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IMR1 ,Interrupt 1 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " IMR0 ,Interrupt 0 Mask bit" "Masked,Not masked"
|
|
line.long 0x0C "ISR,GPIO Interrupt Status Register"
|
|
eventfld.long 0x0C 31. " ISR31 ,Interrupt 31 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " ISR30 ,Interrupt 30 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " ISR29 ,Interrupt 29 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " ISR28 ,Interrupt 28 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " ISR27 ,Interrupt 27 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " ISR26 ,Interrupt 26 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " ISR25 ,Interrupt 25 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " ISR24 ,Interrupt 24 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 23. " ISR23 ,Interrupt 23 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " ISR22 ,Interrupt 22 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " ISR21 ,Interrupt 21 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " ISR20 ,Interrupt 20 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " ISR19 ,Interrupt 19 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " ISR18 ,Interrupt 18 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " ISR17 ,Interrupt 17 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " ISR16 ,Interrupt 16 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " ISR15 ,Interrupt 15 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " ISR14 ,Interrupt 14 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " ISR13 ,Interrupt 13 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " ISR12 ,Interrupt 12 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " ISR11 ,Interrupt 11 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " ISR10 ,Interrupt 10 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 9. " ISR9 ,Interrupt 9 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " ISR8 ,Interrupt 8 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " ISR7 ,Interrupt 7 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " ISR6 ,Interrupt 6 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " ISR5 ,Interrupt 5 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " ISR4 ,Interrupt 4 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " ISR3 ,Interrupt 3 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " ISR2 ,Interrupt 2 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " ISR1 ,Interrupt 1 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " ISR0 ,Interrupt 0 Status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
width 0x0B
|
|
width 10.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EDGE_SEL,GPIO Edge Select Register"
|
|
bitfld.long 0x00 31. " EDGE_SEL31 ,Edge Selection 31" "ICR_2_31,Any edge"
|
|
bitfld.long 0x00 30. " EDGE_SEL30 ,Edge Selection 30" "ICR_2_30,Any edge"
|
|
bitfld.long 0x00 29. " EDGE_SEL29 ,Edge Selection 29" "ICR_2_29,Any edge"
|
|
bitfld.long 0x00 28. " EDGE_SEL28 ,Edge Selection 28" "ICR_2_28,Any edge"
|
|
bitfld.long 0x00 27. " EDGE_SEL27 ,Edge Selection 27" "ICR_2_27,Any edge"
|
|
bitfld.long 0x00 26. " EDGE_SEL26 ,Edge Selection 26" "ICR_2_26,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EDGE_SEL25 ,Edge Selection 25" "ICR_2_25,Any edge"
|
|
bitfld.long 0x00 24. " EDGE_SEL24 ,Edge Selection 24" "ICR_2_24,Any edge"
|
|
bitfld.long 0x00 23. " EDGE_SEL23 ,Edge Selection 23" "ICR_2_23,Any edge"
|
|
bitfld.long 0x00 22. " EDGE_SEL22 ,Edge Selection 22" "ICR_2_22,Any edge"
|
|
bitfld.long 0x00 21. " EDGE_SEL21 ,Edge Selection 21" "ICR_2_21,Any edge"
|
|
bitfld.long 0x00 20. " EDGE_SEL20 ,Edge Selection 20" "ICR_2_20,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EDGE_SEL19 ,Edge Selection 19" "ICR_2_19,Any edge"
|
|
bitfld.long 0x00 18. " EDGE_SEL18 ,Edge Selection 18" "ICR_2_18,Any edge"
|
|
bitfld.long 0x00 17. " EDGE_SEL17 ,Edge Selection 17" "ICR_2_17,Any edge"
|
|
bitfld.long 0x00 16. " EDGE_SEL16 ,Edge Selection 16" "ICR_2_16,Any edge"
|
|
bitfld.long 0x00 15. " EDGE_SEL15 ,Edge Selection 15" "ICR_1_15,Any edge"
|
|
bitfld.long 0x00 14. " EDGE_SEL14 ,Edge Selection 14" "ICR_1_14,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EDGE_SEL13 ,Edge Selection 13" "ICR_1_13,Any edge"
|
|
bitfld.long 0x00 12. " EDGE_SEL12 ,Edge Selection 12" "ICR_1_12,Any edge"
|
|
bitfld.long 0x00 11. " EDGE_SEL11 ,Edge Selection 11" "ICR_1_11,Any edge"
|
|
bitfld.long 0x00 10. " EDGE_SEL10 ,Edge Selection 10" "ICR_1_10,Any edge"
|
|
bitfld.long 0x00 9. " EDGE_SEL9 ,Edge Selection 9" "ICR_1_9,Any edge"
|
|
bitfld.long 0x00 8. " EDGE_SEL8 ,Edge Selection 8" "ICR_1_8,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDGE_SEL7 ,Edge Selection 7" "ICR_1_7,Any edge"
|
|
bitfld.long 0x00 6. " EDGE_SEL6 ,Edge Selection 6" "ICR_1_6,Any edge"
|
|
bitfld.long 0x00 5. " EDGE_SEL5 ,Edge Selection 5" "ICR_1_5,Any edge"
|
|
bitfld.long 0x00 4. " EDGE_SEL4 ,Edge Selection 4" "ICR_1_4,Any edge"
|
|
bitfld.long 0x00 3. " EDGE_SEL3 ,Edge Selection 3" "ICR_1_3,Any edge"
|
|
bitfld.long 0x00 2. " EDGE_SEL2 ,Edge Selection 2" "ICR_1_2,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDGE_SEL1 ,Edge Selection 1" "ICR_1_1,Any edge"
|
|
bitfld.long 0x00 0. " EDGE_SEL0 ,Edge Selection 0" "ICR_1_0,Any edge"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO6"
|
|
base ad:0x53FE0000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,GPIO Data Register"
|
|
bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High"
|
|
line.long 0x04 "GDIR,GPIO Direction Register"
|
|
bitfld.long 0x04 31. " GDIR31 ,GPIO Direction 31 bit" "Input,Output"
|
|
bitfld.long 0x04 30. " GDIR30 ,GPIO Direction 30 bit" "Input,Output"
|
|
bitfld.long 0x04 29. " GDIR29 ,GPIO Direction 29 bit" "Input,Output"
|
|
bitfld.long 0x04 28. " GDIR28 ,GPIO Direction 28 bit" "Input,Output"
|
|
bitfld.long 0x04 27. " GDIR27 ,GPIO Direction 27 bit" "Input,Output"
|
|
bitfld.long 0x04 26. " GDIR26 ,GPIO Direction 26 bit" "Input,Output"
|
|
bitfld.long 0x04 25. " GDIR25 ,GPIO Direction 25 bit" "Input,Output"
|
|
bitfld.long 0x04 24. " GDIR24 ,GPIO Direction 24 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GDIR23 ,GPIO Direction 23 bit" "Input,Output"
|
|
bitfld.long 0x04 22. " GDIR22 ,GPIO Direction 22 bit" "Input,Output"
|
|
bitfld.long 0x04 21. " GDIR21 ,GPIO Direction 21 bit" "Input,Output"
|
|
bitfld.long 0x04 20. " GDIR20 ,GPIO Direction 20 bit" "Input,Output"
|
|
bitfld.long 0x04 19. " GDIR19 ,GPIO Direction 19 bit" "Input,Output"
|
|
bitfld.long 0x04 18. " GDIR18 ,GPIO Direction 18 bit" "Input,Output"
|
|
bitfld.long 0x04 17. " GDIR17 ,GPIO Direction 17 bit" "Input,Output"
|
|
bitfld.long 0x04 16. " GDIR16 ,GPIO Direction 16 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GDIR15 ,GPIO Direction 15 bit" "Input,Output"
|
|
bitfld.long 0x04 14. " GDIR14 ,GPIO Direction 14 bit" "Input,Output"
|
|
bitfld.long 0x04 13. " GDIR13 ,GPIO Direction 13 bit" "Input,Output"
|
|
bitfld.long 0x04 12. " GDIR12 ,GPIO Direction 12 bit" "Input,Output"
|
|
bitfld.long 0x04 11. " GDIR11 ,GPIO Direction 11 bit" "Input,Output"
|
|
bitfld.long 0x04 10. " GDIR10 ,GPIO Direction 10 bit" "Input,Output"
|
|
bitfld.long 0x04 9. " GDIR9 ,GPIO Direction 9 bit" "Input,Output"
|
|
bitfld.long 0x04 8. " GDIR8 ,GPIO Direction 8 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " GDIR7 ,GPIO Direction 7 bit" "Input,Output"
|
|
bitfld.long 0x04 6. " GDIR6 ,GPIO Direction 6 bit" "Input,Output"
|
|
bitfld.long 0x04 5. " GDIR5 ,GPIO Direction 5 bit" "Input,Output"
|
|
bitfld.long 0x04 4. " GDIR4 ,GPIO Direction 4 bit" "Input,Output"
|
|
bitfld.long 0x04 3. " GDIR3 ,GPIO Direction 3 bit" "Input,Output"
|
|
bitfld.long 0x04 2. " GDIR2 ,GPIO Direction 2 bit" "Input,Output"
|
|
bitfld.long 0x04 1. " GDIR1 ,GPIO Direction 1 bit" "Input,Output"
|
|
bitfld.long 0x04 0. " GDIR0 ,GPIO Direction 0 bit" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "PSR,GPIO Pad Status Register"
|
|
bitfld.long 0x00 31. " PSR31 ,GPIO Pad Status bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PSR30 ,GPIO Pad Status bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PSR29 ,GPIO Pad Status bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " PSR28 ,GPIO Pad Status bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PSR27 ,GPIO Pad Status bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PSR26 ,GPIO Pad Status bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " PSR25 ,GPIO Pad Status bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PSR24 ,GPIO Pad Status bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PSR23 ,GPIO Pad Status bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " PSR22 ,GPIO Pad Status bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PSR21 ,GPIO Pad Status bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PSR20 ,GPIO Pad Status bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " PSR19 ,GPIO Pad Status bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PSR18 ,GPIO Pad Status bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PSR17 ,GPIO Pad Status bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " PSR16 ,GPIO Pad Status bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PSR15 ,GPIO Pad Status bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PSR14 ,GPIO Pad Status bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " PSR13 ,GPIO Pad Status bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PSR12 ,GPIO Pad Status bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PSR11 ,GPIO Pad Status bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " PSR10 ,GPIO Pad Status bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PSR9 ,GPIO Pad Status bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PSR8 ,GPIO Pad Status bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PSR7 ,GPIO Pad Status bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PSR6 ,GPIO Pad Status bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PSR5 ,GPIO Pad Status bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " PSR4 ,GPIO Pad Status bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PSR3 ,GPIO Pad Status bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PSR2 ,GPIO Pad Status bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " PSR1 ,GPIO Pad Status bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PSR0 ,GPIO Pad Status bit 0" "Low,High"
|
|
tree "GPIO Interrupt Registers"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 30.--31. " ICR1_15 ,Interrupt 15 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 28.--29. " ICR1_14 ,Interrupt 14 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 26.--27. " ICR1_13 ,Interrupt 13 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 24.--25. " ICR1_12 ,Interrupt 12 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 22.--23. " ICR1_11 ,Interrupt 11 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 20.--21. " ICR1_10 ,Interrupt 10 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ICR1_9 ,Interrupt 9 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 16.--17. " ICR1_8 ,Interrupt 8 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 14.--15. " ICR1_7 ,Interrupt 7 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 12.--13. " ICR1_6 ,Interrupt 6 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 10.--11. " ICR1_5 ,Interrupt 5 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 8.--9. " ICR1_4 ,Interrupt 4 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICR1_3 ,Interrupt 3 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 4.--5. " ICR1_2 ,Interrupt 2 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 2.--3. " ICR1_1 ,Interrupt 1 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 0.--1. " ICR1_0 ,Interrupt 0 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 30.--31. " ICR2_31 ,Interrupt 31 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
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bitfld.long 0x04 28.--29. " ICR2_30 ,Interrupt 30 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 26.--27. " ICR2_29 ,Interrupt 29 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 24.--25. " ICR2_28 ,Interrupt 28 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 22.--23. " ICR2_27 ,Interrupt 27 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 20.--21. " ICR2_26 ,Interrupt 26 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " ICR2_25 ,Interrupt 25 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 16.--17. " ICR2_24 ,Interrupt 24 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 14.--15. " ICR2_23 ,Interrupt 23 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 12.--13. " ICR2_22 ,Interrupt 22 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 10.--11. " ICR2_21 ,Interrupt 21 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 8.--9. " ICR2_20 ,Interrupt 20 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " ICR2_19 ,Interrupt 19 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 4.--5. " ICR2_18 ,Interrupt 18 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 2.--3. " ICR2_17 ,Interrupt 17 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 0.--1. " ICR2_16 ,Interrupt 16 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x08 "IMR,GPIO Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " IMR31 ,Interrupt 31 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 30. " IMR30 ,Interrupt 30 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 29. " IMR29 ,Interrupt 29 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 28. " IMR28 ,Interrupt 28 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 27. " IMR27 ,Interrupt 27 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 26. " IMR26 ,Interrupt 26 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IMR25 ,Interrupt 25 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " IMR24 ,Interrupt 24 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " IMR23 ,Interrupt 23 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " IMR22 ,Interrupt 22 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " IMR21 ,Interrupt 21 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " IMR20 ,Interrupt 20 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IMR19 ,Interrupt 19 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " IMR18 ,Interrupt 18 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " IMR17 ,Interrupt 17 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " IMR16 ,Interrupt 16 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 15. " IMR15 ,Interrupt 15 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 14. " IMR14 ,Interrupt 14 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IMR13 ,Interrupt 13 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " IMR12 ,Interrupt 12 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 11. " IMR11 ,Interrupt 11 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 10. " IMR10 ,Interrupt 10 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " IMR9 ,Interrupt 9 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " IMR8 ,Interrupt 8 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IMR7 ,Interrupt 7 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " IMR6 ,Interrupt 6 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " IMR5 ,Interrupt 5 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " IMR4 ,Interrupt 4 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " IMR3 ,Interrupt 3 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " IMR2 ,Interrupt 2 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IMR1 ,Interrupt 1 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " IMR0 ,Interrupt 0 Mask bit" "Masked,Not masked"
|
|
line.long 0x0C "ISR,GPIO Interrupt Status Register"
|
|
eventfld.long 0x0C 31. " ISR31 ,Interrupt 31 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " ISR30 ,Interrupt 30 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " ISR29 ,Interrupt 29 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " ISR28 ,Interrupt 28 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " ISR27 ,Interrupt 27 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " ISR26 ,Interrupt 26 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " ISR25 ,Interrupt 25 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " ISR24 ,Interrupt 24 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 23. " ISR23 ,Interrupt 23 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " ISR22 ,Interrupt 22 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " ISR21 ,Interrupt 21 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " ISR20 ,Interrupt 20 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " ISR19 ,Interrupt 19 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " ISR18 ,Interrupt 18 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " ISR17 ,Interrupt 17 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " ISR16 ,Interrupt 16 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " ISR15 ,Interrupt 15 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " ISR14 ,Interrupt 14 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " ISR13 ,Interrupt 13 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " ISR12 ,Interrupt 12 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " ISR11 ,Interrupt 11 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " ISR10 ,Interrupt 10 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 9. " ISR9 ,Interrupt 9 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " ISR8 ,Interrupt 8 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " ISR7 ,Interrupt 7 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " ISR6 ,Interrupt 6 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " ISR5 ,Interrupt 5 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " ISR4 ,Interrupt 4 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " ISR3 ,Interrupt 3 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " ISR2 ,Interrupt 2 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " ISR1 ,Interrupt 1 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " ISR0 ,Interrupt 0 Status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
width 0x0B
|
|
width 10.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EDGE_SEL,GPIO Edge Select Register"
|
|
bitfld.long 0x00 31. " EDGE_SEL31 ,Edge Selection 31" "ICR_2_31,Any edge"
|
|
bitfld.long 0x00 30. " EDGE_SEL30 ,Edge Selection 30" "ICR_2_30,Any edge"
|
|
bitfld.long 0x00 29. " EDGE_SEL29 ,Edge Selection 29" "ICR_2_29,Any edge"
|
|
bitfld.long 0x00 28. " EDGE_SEL28 ,Edge Selection 28" "ICR_2_28,Any edge"
|
|
bitfld.long 0x00 27. " EDGE_SEL27 ,Edge Selection 27" "ICR_2_27,Any edge"
|
|
bitfld.long 0x00 26. " EDGE_SEL26 ,Edge Selection 26" "ICR_2_26,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EDGE_SEL25 ,Edge Selection 25" "ICR_2_25,Any edge"
|
|
bitfld.long 0x00 24. " EDGE_SEL24 ,Edge Selection 24" "ICR_2_24,Any edge"
|
|
bitfld.long 0x00 23. " EDGE_SEL23 ,Edge Selection 23" "ICR_2_23,Any edge"
|
|
bitfld.long 0x00 22. " EDGE_SEL22 ,Edge Selection 22" "ICR_2_22,Any edge"
|
|
bitfld.long 0x00 21. " EDGE_SEL21 ,Edge Selection 21" "ICR_2_21,Any edge"
|
|
bitfld.long 0x00 20. " EDGE_SEL20 ,Edge Selection 20" "ICR_2_20,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EDGE_SEL19 ,Edge Selection 19" "ICR_2_19,Any edge"
|
|
bitfld.long 0x00 18. " EDGE_SEL18 ,Edge Selection 18" "ICR_2_18,Any edge"
|
|
bitfld.long 0x00 17. " EDGE_SEL17 ,Edge Selection 17" "ICR_2_17,Any edge"
|
|
bitfld.long 0x00 16. " EDGE_SEL16 ,Edge Selection 16" "ICR_2_16,Any edge"
|
|
bitfld.long 0x00 15. " EDGE_SEL15 ,Edge Selection 15" "ICR_1_15,Any edge"
|
|
bitfld.long 0x00 14. " EDGE_SEL14 ,Edge Selection 14" "ICR_1_14,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EDGE_SEL13 ,Edge Selection 13" "ICR_1_13,Any edge"
|
|
bitfld.long 0x00 12. " EDGE_SEL12 ,Edge Selection 12" "ICR_1_12,Any edge"
|
|
bitfld.long 0x00 11. " EDGE_SEL11 ,Edge Selection 11" "ICR_1_11,Any edge"
|
|
bitfld.long 0x00 10. " EDGE_SEL10 ,Edge Selection 10" "ICR_1_10,Any edge"
|
|
bitfld.long 0x00 9. " EDGE_SEL9 ,Edge Selection 9" "ICR_1_9,Any edge"
|
|
bitfld.long 0x00 8. " EDGE_SEL8 ,Edge Selection 8" "ICR_1_8,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDGE_SEL7 ,Edge Selection 7" "ICR_1_7,Any edge"
|
|
bitfld.long 0x00 6. " EDGE_SEL6 ,Edge Selection 6" "ICR_1_6,Any edge"
|
|
bitfld.long 0x00 5. " EDGE_SEL5 ,Edge Selection 5" "ICR_1_5,Any edge"
|
|
bitfld.long 0x00 4. " EDGE_SEL4 ,Edge Selection 4" "ICR_1_4,Any edge"
|
|
bitfld.long 0x00 3. " EDGE_SEL3 ,Edge Selection 3" "ICR_1_3,Any edge"
|
|
bitfld.long 0x00 2. " EDGE_SEL2 ,Edge Selection 2" "ICR_1_2,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDGE_SEL1 ,Edge Selection 1" "ICR_1_1,Any edge"
|
|
bitfld.long 0x00 0. " EDGE_SEL0 ,Edge Selection 0" "ICR_1_0,Any edge"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "GPMI (General-Purpose Media Interface)"
|
|
base ad:0x41006000
|
|
width 18.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "GPMI_CTRL0,GPMI Control Register 0"
|
|
bitfld.long 0x00 31. " SFTRST ,Soft reset" "Run,Reset"
|
|
bitfld.long 0x00 30. " CLKGATE ,Clock gate" "Run,No_clks"
|
|
bitfld.long 0x00 29. " RUN ,GPMI busy running" "Idle,Busy"
|
|
bitfld.long 0x00 28. " DEV_IRQ_EN ,DEV IRQ enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LOCK_CS ,Chip select lock bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " UDMA ,ATA-Ultra DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready"
|
|
bitfld.long 0x00 23. " WORD_LENGTH ,Data bus mode" ",8-bit"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,?..."
|
|
bitfld.long 0x00 16. " ADDRESS_INCREMENT ,Adress increment" "Not incremented,Incremented"
|
|
hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command"
|
|
line.long 0x04 "GPMI_CTRL0_SET,GPMI Control Set Register 0"
|
|
bitfld.long 0x04 31. " SFTRST ,Soft reset" "No effect,Set"
|
|
bitfld.long 0x04 30. " CLKGATE ,Clock gate" "No effect,Set"
|
|
bitfld.long 0x04 29. " RUN ,GPMI busy running" "No effect,Set"
|
|
bitfld.long 0x04 28. " DEV_IRQ_EN ,DEV IRQ enable" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 27. " TIMEOUT_IRQ_EN ,Timeout interrupt enable" "No effect,Set"
|
|
bitfld.long 0x04 26. " UDMA ,ATA-Ultra DMA enable" "No effect,Set"
|
|
bitfld.long 0x04 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready"
|
|
bitfld.long 0x04 23. " WORD_LENGTH ,Data bus mode" ",8-bit"
|
|
textline " "
|
|
bitfld.long 0x04 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,?..."
|
|
bitfld.long 0x04 16. " ADDRESS_INCREMENT ,Adress increment" "No effect,Set"
|
|
hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command"
|
|
line.long 0x08 "GPMI_CTRL0_CLR,GPMI Control Clear Register 0"
|
|
bitfld.long 0x08 31. " SFTRST ,Soft reset" "No effect,Clear"
|
|
bitfld.long 0x08 30. " CLKGATE ,Clock gate" "No effect,Clear"
|
|
bitfld.long 0x08 29. " RUN ,GPMI busy running" "No effect,Clear"
|
|
bitfld.long 0x08 28. " DEV_IRQ_EN ,DEV IRQ enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 27. " LOCK_CS ,Chip select lock bit" "No effect,Clear"
|
|
bitfld.long 0x08 26. " UDMA ,ATA-Ultra DMA enable" "No effect,Clear"
|
|
bitfld.long 0x08 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready"
|
|
bitfld.long 0x08 23. " WORD_LENGTH ,Data bus mode" ",8-bit"
|
|
textline " "
|
|
bitfld.long 0x08 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,?..."
|
|
bitfld.long 0x08 16. " ADDRESS_INCREMENT ,Adress increment" "No effect,Clear"
|
|
hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command"
|
|
line.long 0x0c "GPMI_CTRL0_TOG,GPMI Control Toggle Register 0"
|
|
bitfld.long 0x0c 31. " SFTRST ,Soft reset" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 30. " CLKGATE ,Clock gate" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 29. " RUN ,GPMI busy running" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 28. " DEV_IRQ_EN ,DEV IRQ enable" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " LOCK_CS ,Chip select lock bit" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 26. " UDMA ,ATA-Ultra DMA enable" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready"
|
|
bitfld.long 0x0c 23. " WORD_LENGTH ,Data bus mode" ",8-bit"
|
|
textline " "
|
|
bitfld.long 0x0c 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,?..."
|
|
bitfld.long 0x0c 16. " ADDRESS_INCREMENT ,Adress increment" "Not toggled,Toggled"
|
|
hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command"
|
|
line.long 0x10 "GPMI_COMPARE,GPMI Compare Register Description"
|
|
hexmask.long.word 0x10 16.--31. 1. " MASK ,16-bit mask which is applied after the read data is XORed with the REFERENCE bit field"
|
|
hexmask.long.word 0x10 0.--15. 1. " REFERENCE ,16-bit value which is XORed with data read from the NAND device"
|
|
group.long 0x20++0x13
|
|
line.long 0x00 "GPMI_ECCCTRL,GPMI Integrated ECC Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress"
|
|
bitfld.long 0x00 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,?..."
|
|
bitfld.long 0x00 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--8. 1. " BUFFER_MASK ,ECC buffer information"
|
|
line.long 0x04 "GPMI_ECCCTRL_SET,GPMI Integrated ECC Control Set Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress"
|
|
bitfld.long 0x04 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,?..."
|
|
bitfld.long 0x04 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Set"
|
|
hexmask.long.word 0x04 0.--8. 1. " BUFFER_MASK ,ECC buffer information"
|
|
line.long 0x08 "GPMI_ECCCTRL_CLR,GPMI Integrated ECC Control Clear Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress"
|
|
bitfld.long 0x08 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,?..."
|
|
bitfld.long 0x08 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Clear"
|
|
hexmask.long.word 0x08 0.--8. 1. " BUFFER_MASK ,ECC buffer information"
|
|
line.long 0x0c "GPMI_ECCCTRL_TOG,GPMI Integrated ECC Control Toggle Register"
|
|
hexmask.long.word 0x0c 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress"
|
|
bitfld.long 0x0c 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,?..."
|
|
bitfld.long 0x0c 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "Not toggled,Toggled"
|
|
hexmask.long.word 0x0c 0.--8. 1. " BUFFER_MASK ,ECC buffer information"
|
|
line.long 0x10 "GPMI_ECCCOUNT,GPMI Integrated ECC Transfer Count Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of bytes to pass through ECC"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPMI_PAYLOAD,GPMI Payload Address"
|
|
hexmask.long 0x00 2.--31. 0x04 " ADDRESS ,Pointer to an array of one or more 512 byte payload buffers"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GPMI_AUXILIARY,GPMI Auxiliary Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " ADDRESS ,Pointer to ECC control structure and meta-data storage"
|
|
textline " "
|
|
group.long 0x60++0x13
|
|
line.long 0x00 "GPMI_CTRL1,GPMI Control Register 1"
|
|
bitfld.long 0x00 31. " DEV_CLK_STOP ,Device clock stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 29. " WRITE_CLK_STOP ,Stop clock durning data write" "Not stopped,Stopped"
|
|
bitfld.long 0x00 28. " TOGGLE_MODE ,Samsung toggle mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " GPMI_CLK_DIV2_EN ,GPMI clk divider enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " UPDATE_CS ,Force CS value update" "Not updated,Updated"
|
|
bitfld.long 0x00 25. " SSYNCMODE ,Asynchronous/synchronous mode" "Async,Sync"
|
|
bitfld.long 0x00 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "4-8 ns,6-10 ns,7-12 ns,No delay"
|
|
bitfld.long 0x00 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "Not forced,Forced"
|
|
bitfld.long 0x00 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" ",BCH"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DLL_ENABLE ,GPMI DLL enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " DMA2ECC_MODE ,DMA ECC mode" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DEV_IRQ ,ATA device interrupt received" "Not received,Received"
|
|
bitfld.long 0x00 9. " TIMEOUT_IRQ ,Interrupt timeout" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " BURST_EN ,4-transfer burst on APB bus enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DEV_RESET ,Device reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "Low,High"
|
|
bitfld.long 0x00 1. " CAMERA_MODE ,CAMERA Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPMI_MODE ,GPMI Mode" "NAND,ATA"
|
|
line.long 0x04 "GPMI_CTRL1_SET,GPMI Control Set Register 1"
|
|
bitfld.long 0x04 31. " DEV_CLK_STOP ,Device clock stop" "No effect,Set"
|
|
bitfld.long 0x04 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "No effect,Set"
|
|
bitfld.long 0x04 29. " WRITE_CLK_STOP ,Stop clock durning data write" "No effect,Set"
|
|
bitfld.long 0x04 28. " TOGGLE_MODE ,Samsung toggle mode enable" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 27. " GPMI_CLK_DIV2_EN ,gpmi clk divider enable" "No effect,Set"
|
|
bitfld.long 0x04 26. " UPDATE_CS ,Force CS value update" "No effect,Set"
|
|
bitfld.long 0x04 25. " SSYNCMODE ,Asynchronous/synchronous mode" "Async,Sync"
|
|
bitfld.long 0x04 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "4-8 ns,6-10 ns,7-12 ns,No delay"
|
|
bitfld.long 0x04 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "No effect,Set"
|
|
bitfld.long 0x04 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Set"
|
|
bitfld.long 0x04 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Set"
|
|
bitfld.long 0x04 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Set"
|
|
bitfld.long 0x04 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 11. " DMA2ECC_MODE ,DMA ECC mode" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DEV_IRQ ,ATA device interrupt received" "No effect,Set"
|
|
bitfld.long 0x04 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Set"
|
|
bitfld.long 0x04 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Set"
|
|
bitfld.long 0x04 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 3. " DEV_RESET ,Device reset" "No effect,Set"
|
|
bitfld.long 0x04 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Set"
|
|
bitfld.long 0x04 1. " CAMERA_MODE ,CAMERA Mode" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 0. " GPMI_MODE ,GPMI Mode" "No effect,Set"
|
|
line.long 0x08 "GPMI_CTRL1_CLR,GPMI Control Clear Register 1"
|
|
bitfld.long 0x08 31. " DEV_CLK_STOP ,Device clock stop" "No effect,Clear"
|
|
bitfld.long 0x08 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "No effect,Clear"
|
|
bitfld.long 0x08 29. " WRITE_CLK_STOP ,Stop clock durning data write" "No effect,Clear"
|
|
bitfld.long 0x08 28. " TOGGLE_MODE ,Samsung toggle mode enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 27. " GPMI_CLK_DIV2_EN ,gpmi clk divider enable" "No effect,Clear"
|
|
bitfld.long 0x08 26. " UPDATE_CS ,Force CS value update" "No effect,Clear"
|
|
bitfld.long 0x08 25. " SSYNCMODE ,Asynchronous/synchronous mode" "Async,Sync"
|
|
bitfld.long 0x08 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "4-8 ns,6-10 ns,7-12 ns,No delay"
|
|
bitfld.long 0x08 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "No effect,Clear"
|
|
bitfld.long 0x08 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Clear"
|
|
bitfld.long 0x08 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Clear"
|
|
bitfld.long 0x08 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Clear"
|
|
bitfld.long 0x08 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 11. " DMA2ECC_MODE ,DMA ECC mode" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DEV_IRQ ,ATA device interrupt received" "No effect,Clear"
|
|
bitfld.long 0x08 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Clear"
|
|
bitfld.long 0x08 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Clear"
|
|
bitfld.long 0x08 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 3. " DEV_RESET ,Device reset" "No effect,Clear"
|
|
bitfld.long 0x08 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Clear"
|
|
bitfld.long 0x08 1. " CAMERA_MODE ,CAMERA Mode" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 0. " GPMI_MODE ,GPMI Mode" "No effect,Clear"
|
|
line.long 0x0c "GPMI_CTRL1_TOG,GPMI Control Toggle Register 1"
|
|
bitfld.long 0x0c 31. " DEV_CLK_STOP ,Device clock stop" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 30. " SSYNC_CLK_STOP ,Source synchronous mode clock stop" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 29. " WRITE_CLK_STOP ,Stop clock durning data write" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 28. " TOGGLE_MODE ,Samsung toggle mode enable" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " GPMI_CLK_DIV2_EN ,gpmi clk divider enable" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 26. " UPDATE_CS ,Force CS value update" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 25. " SSYNCMODE ,Asynchronous/synchronous mode" "Async,Sync"
|
|
bitfld.long 0x0c 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0c 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "4-8 ns,6-10 ns,7-12 ns,No delay"
|
|
bitfld.long 0x0c 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " DLL_ENABLE ,GPMI DLL enable bit" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 11. " DMA2ECC_MODE ,DMA ECC mode" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " DEV_IRQ ,ATA device interrupt received" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 9. " TIMEOUT_IRQ ,Interrupt timeout" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 8. " BURST_EN ,4-transfer burst on APB bus enable" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 3. " DEV_RESET ,Device reset" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "Not toggled,Toggled"
|
|
bitfld.long 0x0c 1. " CAMERA_MODE ,CAMERA Mode" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " GPMI_MODE ,GPMI Mode" "Not toggled,Toggled"
|
|
textline " "
|
|
line.long 0x10 "GPMI_TIMING0,GPMI Timing Register 0"
|
|
hexmask.long.byte 0x10 16.--23. 1. " ADDRESS_SETUP ,Number of GPMICLK cycles that the CE signals are active before a strobe is asserted"
|
|
hexmask.long.byte 0x10 8.--15. 1. " DATA_HOLD ,Data bus hold time in GPMICLK cycles"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DATA_SETUP ,Data bus setup time in GPMICLK cycles"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GPMI_TIMING1,GPMI Timing Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " DEVICE_BUSY_TIMEOUT ,Timeout waiting for NAND Ready/Busy"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "GPMI_TIMING2,GPMI Timing Register 2"
|
|
bitfld.long 0x00 24.--26. " READ_LATENCY ,Read latency" "0,1,2,3,4,5,3,3"
|
|
bitfld.long 0x00 16.--20. " CE_DELAY ,CE delay" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--15. " PREAMBLE_DELAY ,Pre-amble delay" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " POSTAMBLE_DELAY ,Post-amble delay" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CMDADD_PAUSE ,Delay time from cmd/addr pause to cmd/addr resume in GPMICLK cycles" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DATA_PAUSE ,Delay time from data pause to data resume in GPMICLK cycles" "16,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xa0++0x03
|
|
line.long 0x00 "GPMI_DATA,GPMI DMA Data Transfer Register"
|
|
rgroup.long 0xb0++0x03
|
|
line.long 0x00 "GPMI_STAT,GPMI Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " READY_BUSY ,NAND Ready_Busy Input pins"
|
|
bitfld.long 0x00 23. " RDY_TIMEOUT[7] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout"
|
|
bitfld.long 0x00 22. " RDY_TIMEOUT[6] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RDY_TIMEOUT[5] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout"
|
|
bitfld.long 0x00 20. " RDY_TIMEOUT[4] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout"
|
|
bitfld.long 0x00 19. " RDY_TIMEOUT[3] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RDY_TIMEOUT[2] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout"
|
|
bitfld.long 0x00 17. " RDY_TIMEOUT[1] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout"
|
|
bitfld.long 0x00 16. " RDY_TIMEOUT[0] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DEV7_ERROR ,Error condition on NAND Device accessed by DMA channel 7" "No error,Error"
|
|
bitfld.long 0x00 14. " DEV6_ERROR ,Error condition on NAND Device accessed by DMA channel 6" "No error,Error"
|
|
bitfld.long 0x00 13. " DEV5_ERROR ,Error condition on NAND Device accessed by DMA channel 5" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DEV4_ERROR ,Error condition on NAND Device accessed by DMA channel 4" "No error,Error"
|
|
bitfld.long 0x00 11. " DEV3_ERROR ,Error condition on NAND Device accessed by DMA channel 3" "No error,Error"
|
|
bitfld.long 0x00 10. " DEV2_ERROR ,Error condition on NAND Device accessed by DMA channel 2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DEV1_ERROR ,Error condition on NAND Device accessed by DMA channel 1" "No error,Error"
|
|
bitfld.long 0x00 8. " DEV0_ERROR ,Error condition on NAND Device accessed by DMA channel 0" "No error,Error"
|
|
bitfld.long 0x00 4. " ATA_IRQ ,Status of ATA_IRQ input pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INVALID_BUFFER_MASK ,ECC Buffer Mask" "Not invalid,Invalid"
|
|
bitfld.long 0x00 2. " FIFO_EMPTY ,Fifo empty" "Not empty,Empty"
|
|
bitfld.long 0x00 1. " FIFO_FULL ,Fifo full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PRESENT ,GPMI present" "Not present,Present"
|
|
rgroup.long 0xc0++0x03
|
|
line.long 0x00 "GPMI_DEBUG,GPMI Debug Information Register"
|
|
bitfld.long 0x00 31. " WAIT_FOR_READY_END[7] ,WAIT_FOR_READY command end of channel 7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " WAIT_FOR_READY_END[6] ,WAIT_FOR_READY command end of channel 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " WAIT_FOR_READY_END[5] ,WAIT_FOR_READY command end of channel 5" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WAIT_FOR_READY_END[4] ,WAIT_FOR_READY command end of channel 4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " WAIT_FOR_READY_END[3] ,WAIT_FOR_READY command end of channel 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " WAIT_FOR_READY_END[2] ,WAIT_FOR_READY command end of channel 2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WAIT_FOR_READY_END[1] ,WAIT_FOR_READY command end of channel 1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " WAIT_FOR_READY_END[0] ,WAIT_FOR_READY command end of channel 0" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " DMA_SENSE[7] ,Sense state of channel 7" "No effect,Failed/Timeouted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DMA_SENSE[6] ,Sense state of channel 6" "No effect,Failed/Timeouted"
|
|
bitfld.long 0x00 21. " DMA_SENSE[5] ,Sense state of channel 5" "No effect,Failed/Timeouted"
|
|
bitfld.long 0x00 20. " DMA_SENSE[4] ,Sense state of channel 4" "No effect,Failed/Timeouted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DMA_SENSE[3] ,Sense state of channel 3" "No effect,Failed/Timeouted"
|
|
bitfld.long 0x00 18. " DMA_SENSE[2] ,Sense state of channel 2" "No effect,Failed/Timeouted"
|
|
bitfld.long 0x00 17. " DMA_SENSE[1] ,Sense state of channel 1" "No effect,Failed/Timeouted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DMA_SENSE[0] ,Sense state of channel 0" "No effect,Failed/Timeouted"
|
|
bitfld.long 0x00 15. " DMAREQ[7] ,DMA request line for channel 7" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " DMAREQ[6] ,DMA request line for channel 6" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAREQ[5] ,DMA request line for channel 5" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " DMAREQ[4] ,DMA request line for channel 4" "Not requested,Requested"
|
|
bitfld.long 0x00 11. " DMAREQ[3] ,DMA request line for channel 3" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DMAREQ[2] ,DMA request line for channel 2" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " DMAREQ[1] ,DMA request line for channel 1" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " DMAREQ[0] ,DMA request line for channel 0" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CMD_END[7] ,Command End toggle to DMA Channel 7" "Not finished,Finished"
|
|
bitfld.long 0x00 6. " CMD_END[6] ,Command End toggle to DMA Channel 6" "Not finished,Finished"
|
|
bitfld.long 0x00 5. " CMD_END[5] ,Command End toggle to DMA Channel 5" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CMD_END[4] ,Command End toggle to DMA Channel 4" "Not finished,Finished"
|
|
bitfld.long 0x00 3. " CMD_END[3] ,Command End toggle to DMA Channel 3" "Not finished,Finished"
|
|
bitfld.long 0x00 2. " CMD_END[2] ,Command End toggle to DMA Channel 2" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMD_END[1] ,Command End toggle to DMA Channel 1" "Not finished,Finished"
|
|
bitfld.long 0x00 0. " CMD_END[0] ,Command End toggle to DMA Channel 0" "Not finished,Finished"
|
|
rgroup.long 0xd0++0x03
|
|
line.long 0x00 "GPMI_VERSION,GPMI Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version"
|
|
hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version"
|
|
group.long 0x0E0++0x03
|
|
line.long 0x00 "GPMI_DEBUG2,GPMI Debug2 Information Register"
|
|
rbitfld.long 0x00 24.--27. " UDMA_STATE ,UDMA state" "USM_IDLE,USM_DMARQ,USM_ACK,USM_FIFO_E,USM_WPAUSE,USM_TSTRB,USM_CAPTUR,USM_DATOUT,USM_CRC,USM_WAIT_R,USM_END,USM_WAIT_S,USM_RPAUSE,USM_RSTOP,USM_WTERM,USM_RTERM"
|
|
rbitfld.long 0x00 23. " BUSY ,When asserted the GPMI is busy" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--22. " PIN_STATE ,Pin state" "PSM_IDLE,PSM_BYTCNT,PSM_ADDR,PSM_STALL,PSM_STROBE,PSM_ATARDY,PSM_DHOLD,PSM_DONE"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--19. " MAIN_STATE ,Main state" "MSM_IDLE,MSM_BYTCNT,MSM_WAITFE,MSM_WAITFR,MSM_DMAREQ,MSM_DMAACK,MSM_WAITFF,MSM_LDFIFO,MSM_LDDMAR,MSM_RDCMP,MSM_DONE,?..."
|
|
rbitfld.long 0x00 12.--15. " SYND2GPMI_BE ,Data byte enable Input from BCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 11. " GPMI2SYND_VALID ,Data handshake output to BCH" "Not valid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " GPMI2SYND_READY ,Data handshake output to BCH" "Not ready,Ready"
|
|
rbitfld.long 0x00 9. " SYND2GPMI_VALID ,Data handshake Input from BCH" "Not valid,Valid"
|
|
rbitfld.long 0x00 8. " SYND2GPMI_READY ,Data handshake Input from BCH" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VIEW_DELAYED_RDN ,feedback RDN to drive the GPMI_ADDR[0]" "No delay,Delay"
|
|
rbitfld.long 0x00 6. " UPDATE_WINDOW ,DLL is busy generating the required delay" "No,Yes"
|
|
rbitfld.long 0x00 0.--5. " RDN_TAP ,This is the DLL tap calculated by the DLL controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x0F0++0x03
|
|
line.long 0x00 "GPMI_DEBUG3,GPMI Debug3 Information Register Description"
|
|
hexmask.long.word 0x00 16.--31. 1. " APB_WORD_CNTR ,Reflects the number of words remains to be transferred on the APB bus"
|
|
hexmask.long.word 0x00 0.--15. 1. " DEV_WORD_CNTR ,Reflects the number of words remains to be transferred on the ATA/Nand bus"
|
|
textline " "
|
|
width 25.
|
|
group.long 0x0100++0x03
|
|
line.long 0x00 "GPMI_READ_DDR_DLL_CTRL,GPMI Double Rate Read DLL Control Register"
|
|
bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Update interval of 256 GPMICLK cycles"
|
|
hexmask.long.byte 0x00 10.--17. 1. " SLV_OVERRIDE_VAL ,Select 1 of 256 physical taps manually"
|
|
bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " REFCLK_ON ,Reference clock" "Off,On"
|
|
bitfld.long 0x00 7. " GATE_UPDATE ,Slave delay line" "No effect,Not updated"
|
|
bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the read clock" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,16/16"
|
|
bitfld.long 0x00 2. " SLV_FORCE_UPD ,Slave delay line" "No effect,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset on DLL" "No effect,Reset"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled"
|
|
group.long 0x0110++0x03
|
|
line.long 0x00 "GPMI_WRITE_DDR_DLL_CTRL,GPMI Double Rate Write DLL Control Register"
|
|
bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,Update interval of 256 GPMICLK cycles"
|
|
hexmask.long.byte 0x00 10.--17. 1. " SLV_OVERRIDE_VAL ,Select 1 of 256 physical taps manually"
|
|
bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay chain" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " REFCLK_ON ,Reference clock" "Off,On"
|
|
bitfld.long 0x00 7. " GATE_UPDATE ,Slave delay line" "No effect,Not updated"
|
|
bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the read clock" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,16/16"
|
|
bitfld.long 0x00 2. " SLV_FORCE_UPD ,Slave delay line" "No effect,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET ,Reset on DLL" "No effect,Reset"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled"
|
|
rgroup.long 0x0120++0x03
|
|
line.long 0x00 "GPMI_READ_DDR_DLL_STS,GPMI Double Rate Read DLL Status Register"
|
|
hexmask.long.byte 0x00 17.--24. 1. " REF_SEL ,Reference delay line select status"
|
|
bitfld.long 0x00 16. " REF_LOCK ,Reference DLL lock status" "Not locked,Locked"
|
|
hexmask.long.byte 0x00 1.--8. 1. " SLV_SEL ,Slave delay line select status"
|
|
bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Low,High"
|
|
rgroup.long 0x0130++0x03
|
|
line.long 0x00 "GPMI_WRITE_DDR_DLL_STS,GPMI Double Rate Write DLL Status Register"
|
|
hexmask.long.byte 0x00 17.--24. 1. " REF_SEL ,Reference delay line select status"
|
|
bitfld.long 0x00 16. " REF_LOCK ,Reference DLL lock status" "Not locked,Locked"
|
|
hexmask.long.byte 0x00 1.--8. 1. " SLV_SEL ,Slave delay line select status"
|
|
bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPT (General Purpose Timer)"
|
|
base ad:0x53FA0000
|
|
width 9.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "GPTCR,GPT Control Register"
|
|
bitfld.long 0x00 31. " FO3 ,Force Output Compare Channel 3" "No effect,Compare"
|
|
bitfld.long 0x00 30. " FO2 ,Force Output Compare Channel 2" "No effect,Compare"
|
|
bitfld.long 0x00 29. " FO1 ,Force Output Compare Channel 1" "No effect,Compare"
|
|
textline " "
|
|
bitfld.long 0x00 26.--28. " OM3 ,Output Compare Channel 3 Operating Mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse"
|
|
bitfld.long 0x00 23.--25. " OM2 ,Output Compare Channel 2 Operating Mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse"
|
|
bitfld.long 0x00 20.--22. " OM1 ,Output Compare Channel 1 Operating Mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IM2 ,Input Capture Channel 2 Operating Mode" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 16.--17. " IM1 ,Input Capture Channel 1 Operating Mode" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 15. " SWR ,Software Reset" "No reset,Reset"
|
|
textline " "
|
|
sif (cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6DUALLITE")
|
|
bitfld.long 0x00 10. " 24MEN ,Enable 24MHz clock input from crystal" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " FRR ,Freerun Or Restart Mode" "Restart,Freerun"
|
|
textline " "
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 6.--8. " CLKSRC ,Clock Source Select" "No clock,Peripheral Clock,High Frequency,External Clock,Low Frequency,Low Frequency,Low Frequency,Low Frequency"
|
|
elif (cpu()=="IMX6DUAL"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6QUAD")
|
|
bitfld.long 0x00 6.--8. " CLKSRC ,Clock Source Select" "No clock,Peripheral Clock,High Frequency,External Clock,Low Frequency,Crystal oscillator/8,,Crystal oscillator"
|
|
elif (cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6DUALLITE"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 6.--8. " CLKSRC ,Clock Source Select" "No clock,Peripheral Clock,High Frequency,External Clock,Low Frequency,Crystal oscillator,?..."
|
|
else
|
|
bitfld.long 0x00 6.--8. " CLKSRC ,Clock Source Select" "No clock,ipg_clk,ipg_clk_highfreq,ipp_ind_clkin,ipg_clk_32k,ipg_clk_32k,ipg_clk_32k,ipg_clk_32k"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPEN ,GPT Stop Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpuis("IMX50*"))
|
|
bitfld.long 0x00 4. " DOZEEN ,GPT Doze Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " WAITEN ,GPT Wait Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DBGEN ,GPT Debug Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENMODE ,GPT Enable Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,GPT Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPTPR,GPT Prescaler Register"
|
|
sif (cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6DUALLITE")
|
|
bitfld.long 0x04 12.--15. " PRESCALER24M ,Prescaler bits" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Prescaler"
|
|
line.long 0x08 "GPTSR,GPT Status Register"
|
|
eventfld.long 0x08 5. " ROV ,Rollover Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " IF2 ,Input Capture 2 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 3. " IF1 ,Input Capture 1 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x08 2. " OF3 ,Output Compare 3 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 1. " OF2 ,Output Compare 2 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 0. " OF1 ,Output Compare 1Flag" "Not occurred,Occurred"
|
|
line.long 0x0c "GPTIR,GPT Interrupt Register"
|
|
bitfld.long 0x0C 5. " ROVIE ,Rollover Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " IF2IE ,Input Capture 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " IF1IE ,Input Capture 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " OF3IE ,Output Compare 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " OF2IE ,Output Compare 2Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " OF1IE ,Output Compare 1Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GPTOCR1,GPT Output Compare Register 1"
|
|
line.long 0x14 "GPTOCR2,GPT Output Compare Register 2"
|
|
line.long 0x18 "GPTOCR3,GPT Output Compare Register 3"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "GPTICR1,GPT Input Capture Register 1"
|
|
line.long 0x04 "GPTICR2,GPT Input Capture Register 2"
|
|
line.long 0x08 "GPTCNT,GPT Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "I2C (Inter IC)"
|
|
tree "I2C1"
|
|
base ad:0x63FC8000
|
|
width 6.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "IADR,I2C Address Register"
|
|
hexmask.word.byte 0x00 1.--7. 0x2 " ADR ,Slave Address"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IFDR,I2C Frequency Divider Register"
|
|
bitfld.word 0x00 0.--5. " IC ,I2C Clock Rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2CR,I2C Control Register"
|
|
bitfld.word 0x00 7. " IEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " IIEN ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MSTA ,Master/Slave Mode Select" "Slave,Master"
|
|
bitfld.word 0x00 4. " MTX ,Transmit/Receive Mode Select bit" "Receive,Transmit"
|
|
bitfld.word 0x00 3. " TXAK ,Transmit Acknowledge Enable" "ACK,NACK"
|
|
bitfld.word 0x00 2. " RSTA ,Repeat Start" "No effect,Repeat"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2SR,I2C Status Register"
|
|
rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed"
|
|
rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed"
|
|
rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy"
|
|
bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost"
|
|
rbitfld.word 0x00 2. " SRW ,Slave read/write" "Read,Write"
|
|
bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,NACK"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "I2DR,I2C Data I/O Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data Byte"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x63FC4000
|
|
width 6.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "IADR,I2C Address Register"
|
|
hexmask.word.byte 0x00 1.--7. 0x2 " ADR ,Slave Address"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IFDR,I2C Frequency Divider Register"
|
|
bitfld.word 0x00 0.--5. " IC ,I2C Clock Rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2CR,I2C Control Register"
|
|
bitfld.word 0x00 7. " IEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " IIEN ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MSTA ,Master/Slave Mode Select" "Slave,Master"
|
|
bitfld.word 0x00 4. " MTX ,Transmit/Receive Mode Select bit" "Receive,Transmit"
|
|
bitfld.word 0x00 3. " TXAK ,Transmit Acknowledge Enable" "ACK,NACK"
|
|
bitfld.word 0x00 2. " RSTA ,Repeat Start" "No effect,Repeat"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2SR,I2C Status Register"
|
|
rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed"
|
|
rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed"
|
|
rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy"
|
|
bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost"
|
|
rbitfld.word 0x00 2. " SRW ,Slave read/write" "Read,Write"
|
|
bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,NACK"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "I2DR,I2C Data I/O Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data Byte"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C3"
|
|
base ad:0x53FEC000
|
|
width 6.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "IADR,I2C Address Register"
|
|
hexmask.word.byte 0x00 1.--7. 0x2 " ADR ,Slave Address"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IFDR,I2C Frequency Divider Register"
|
|
bitfld.word 0x00 0.--5. " IC ,I2C Clock Rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2CR,I2C Control Register"
|
|
bitfld.word 0x00 7. " IEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " IIEN ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MSTA ,Master/Slave Mode Select" "Slave,Master"
|
|
bitfld.word 0x00 4. " MTX ,Transmit/Receive Mode Select bit" "Receive,Transmit"
|
|
bitfld.word 0x00 3. " TXAK ,Transmit Acknowledge Enable" "ACK,NACK"
|
|
bitfld.word 0x00 2. " RSTA ,Repeat Start" "No effect,Repeat"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2SR,I2C Status Register"
|
|
rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed"
|
|
rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed"
|
|
rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy"
|
|
bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost"
|
|
rbitfld.word 0x00 2. " SRW ,Slave read/write" "Read,Write"
|
|
bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,NACK"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "I2DR,I2C Data I/O Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data Byte"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "IOMUXC (IOMUX Controller)"
|
|
base ad:0x53FA8000
|
|
width 6.
|
|
tree "General Purpose Registers"
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "GPR0,General Purpose Register 0"
|
|
bitfld.long 0x00 3. " DMAREQ_MUX_SEL3 ,Sources for SDMA_EVENT[11]" "Esdhc4.ipd_esdhcv2_dreq_b,Cti2.CTITRIGOUT[0]"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAREQ_MUX_SEL2 ,Sources for SDMA_EVENT[10]" "I2c3.ipi_int_b,Esdhc3.ipd_esdhcv3_dreq_b"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DMAREQ_MUX_SEL1 ,Sources for SDMA_EVENT[21]" "I2c2.ipi_int_b,Esdhc2.ipd_esdhcv2_dreq_b"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAREQ_MUX_SEL0 ,Sources for SDMA_EVENT[20]" "I2c1.ipi_int_b,Esdhc1.ipd_esdhcv2_dreq_b"
|
|
line.long 0x04 "GPR1,General Purpose Register 1"
|
|
bitfld.long 0x04 10.--11. " ADDRS3[10] ,Address Space 3" "32 MByte,64 MByte,128 MByte,256 MByte"
|
|
textline " "
|
|
bitfld.long 0x04 9. " ACT_CS3 ,Active Chip Select 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 7.--8. " ADDRS2[10] ,Address Space 2" "32 MByte,64 MByte,128 MByte,256 MByte"
|
|
bitfld.long 0x04 6. " ACT_CS2 ,Active Chip Select 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " ADDRS1[10] ,Address Space 1" "32 MByte,64 MByte,128 MByte,256 MByte"
|
|
bitfld.long 0x04 3. " ACT_CS1 ,Active Chip Select 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 1.--2. " ADDRS0[10] ,Address Space 0" "32 MByte,64 MByte,128 MByte,256 MByte"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ACT_CS0 ,Active Chip Select 0" "Disabled,Enabled"
|
|
line.long 0x08 "GPR2,General Purpose Register 2"
|
|
bitfld.long 0x08 3. " DRAM_DQ_INPUTON[3] ,dram_dq[31:24] dqm[3] sdqs[3] input path override for loopback test" "No override,Override"
|
|
bitfld.long 0x08 2. " DRAM_DQ_INPUTON[2] ,dram_dq[23:16] dqm[2] sdqs[2] input path override for loopback test" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DRAM_DQ_INPUTON[1] ,dram_dq[15:8] dqm[1] sdqs[1] input path override for loopback test" "No override,Override"
|
|
bitfld.long 0x08 0. " DRAM_DQ_INPUTON[0] ,dram_dq[7:0] dqm[0] sdqs[0] input path override for loopback test" "No override,Override"
|
|
tree.end
|
|
width 15.
|
|
tree "IOMUXC_OBSERVE_MUX Registers"
|
|
group.long 0x0C++0x13
|
|
line.long 0x00 "OBSERVE_MUX_0,OBSERVE_MUX_0 Register"
|
|
bitfld.long 0x00 0.--5. " OBSRV ,Instance Pin for Observability IOMUXC_OBSERVE_MUX_0" "ahbmax;Pin max_halted,ccm;Pin ccm_clk_switch_ack,ccm;Pin ccm_ipg_stop,ccm;Pin ccm_ipg_wait,ccm;Pin ccm_pdn_4all_req,ccm;Pin hndsk_current_state[0],ccm;Pin ipi_int_1,ccm;Pin ipi_int_2,ccm;Pin lpm_current_state[0],ccm;Pin shd_current_state[0],cspi;Pin ~ipi_int_cspi_b,dpllip1;Pin dpllip_cpen,ecspi1;Pin ipd_req_cspi_rdma_b,ecspi1;Pin ipd_req_cspi_tdma_b,ecspi1;Pin ~ipi_int_cspi_b,ecspi2;Pin ipd_req_cspi_rdma_b,ecspi2;Pin ~ipi_int_cspi_b,epit1;Pin ipi_int_epit_oc,esdhc1;Pin ~ipi_esdhcv2_irq_b,esdhc2;Pin ~ipi_esdhcv2_irq_b,esdhc3;Pin ~ipi_esdhcv3_irq_b,esdhc4;Pin ~ipi_esdhcv2_irq_b,fec;Pin fec_ipi_int,gpc;Pin gpc_cta8_pg[0],gpc;Pin gpc_cta8_pg[1],gpc;Pin gpc_cta8_pg[2],gpc;Pin gpc_cta8_pg[3],gpc;Pin gpc_cta8_pg[4],gpc;Pin gpc_emi_pg[0],gpc;Pin gpc_emi_short_b,gpc;Pin gpc_event,gpc;Pin gpc_int,gpc;Pin gpc_int2,gpc;Pin gpc_neon_pg[0],src;Pin arm_por_rst,src;Pin warm_reset,tigerp_platform_ne_32k_256k;Pin dsm_request,tigerp_platform_ne_32k_256k;Pin ~nm_irq_b,tzic;Pin tzic_fiq_b,tzic;Pin tzic_irq_b,?..."
|
|
line.long 0x04 "OBSERVE_MUX_1,OBSERVE_MUX_1 Register"
|
|
bitfld.long 0x04 0.--5. " OBSRV ,Instance Pin for Observability IOMUXC_OBSERVE_MUX_1" "ccm;Pin ahbmax_halt_req,ccm;Pin ccm_pdn_4arm_req,ccm;Pin ccm_pup_req,ccm;Pin ccm_system_in_stop_mode,ccm;Pin ccm_system_in_wait_mode,ccm;Pin dpll_en_dpllip,ccm;Pin weim_lpmd,ccm;Pin hndsk_current_state[1],ccm;Pin lpm_current_state[1],ccm;Pin shd_current_state[1],dpllip2;Pin dpllip_cpen,ecspi2;Pin ipd_req_cspi_tdma_b,gpc;Pin gpc_cta8_clk_upd_req,gpc;Pin gpc_cta8_pg[5],gpc;Pin gpc_cta8_pg[6],gpc;Pin gpc_cta8_pg[7],gpc;Pin gpc_cta8_pg[8],gpc;Pin gpc_cta8_pg[9],gpc;Pin gpc_emi_pg[1],gpc;Pin gpc_ipu_switch_b,gpc;Pin gpc_l1bits_pwrdwn,gpc;Pin gpc_l2bits_pwrdwn,gpc;Pin gpc_neon_pg[1],gpio1;Pin ipi_gpio_int15_0,gpio1;Pin ipi_gpio_int31_16,gpio1;Pin ipi_gpio_int32[0],gpio1;Pin ipi_gpio_int32[1],gpio1;Pin ipi_gpio_int32[2],gpio1;Pin ipi_gpio_int32[3],gpio1;Pin ipi_gpio_int32[4],gpio1;Pin ipi_gpio_int32[5],gpio1;Pin ipi_gpio_int32[6],gpio1;Pin ipi_gpio_int32[7],gpio2;Pin ipi_gpio_int15_0,gpio2;Pin ipi_gpio_int31_16,gpio3;Pin ipi_gpio_int15_0,gpio3;Pin ipi_gpio_int31_16,gpio4;Pin ipi_gpio_int15_0,gpio4;Pin ipi_gpio_int31_16,gpt;Pin ipi_int_gpt,src;Pin arm_soc_rst_b,tigerp_platform_ne_32k_256k;Pin dsm_request,uart1;Pin ipd_uart_rx_dmareq_b,uart1;Pin ipd_uart_tx_dmareq_b,uart2;Pin ipd_uart_rx_dmareq_b,uart2;Pin ipd_uart_tx_dmareq_b,wdog1;Pin wdog_rst_b,?..."
|
|
line.long 0x08 "OBSERVE_MUX_2,OBSERVE_MUX_2 Register"
|
|
bitfld.long 0x08 0.--5. " OBSRV ,Instance Pin for Observability IOMUXC_OBSERVE_MUX_2" "ccm;Pin hndsk_current_state[2],ccm;Pin lpm_current_state[2],dpllip3;Pin dpllip_cpen,gpc;Pin gpc_core_pwrdwn,gpc;Pin gpc_cta8_clk_dvfs_operation,gpc;Pin gpc_cta8_pg[10],gpc;Pin gpc_cta8_pg[11],gpc;Pin gpc_cta8_pg[12],gpc;Pin gpc_cta8_pg[13],gpc;Pin gpc_cta8_pg[14],gpc;Pin gpc_emi_pg[2],gpc;Pin gpc_neon_pg[2],gpc;Pin gpc_neon_pwrdwn,gpc;Pin gpc_pdn_ack,gpc;Pin gpc_pup_ack,i2c1;Pin ~ipi_int_b,i2c2;Pin ~ipi_int_b,kpp;Pin ~ipi_int_kpp_b,owire;Pin ipi_owire_int,pwm1;Pin ipi_int_pwm,pwm2;Pin ipi_int_pwm,src;Pin sjc_por_rst_b,src;Pin system_rst_b,ssi1;Pin ipd_ssi_rx0_dmareq_b,ssi1;Pin ipd_ssi_rx1_dmareq_b,ssi1;Pin ipd_ssi_tx1_dmareq_b,ssi2;Pin ipd_ssi_rx1_dmareq_b,?..."
|
|
line.long 0x0c "OBSERVE_MUX_3,OBSERVE_MUX_3 Register"
|
|
bitfld.long 0x0C 0.--4. " OBSRV ,Instance Pin for Observability IOMUXC_OBSERVE_MUX_3" "cspi;Pin ipd_req_cspi_rdma_b,cspi;Pin ipd_req_cspi_tdma_b,dpllip1;Pin dpllip_lrf_sticky,dpllip2;Pin dpllip_lrf_sticky,dpllip3;Pin dpllip_lrf_sticky,gpc;Pin gpc_cta8_pg[15],gpc;Pin gpc_cta8_pg[16],gpc;Pin gpc_cta8_pg[17],gpc;Pin gpc_cta8_pg[18],gpc;Pin gpc_cta8_pg[19],gpc;Pin gpc_emi_pg[3],gpc;Pin gpc_freq_change_mode,gpc;Pin gpc_neon_pg[3],gpc;Pin gpc_neon_short_b,sdma;Pin ipg_stop_ack,sdma;Pin ~ipi_host_intr_b,src;Pin any_pu_rst_b,src;Pin emi_rst_b,src;Pin ipi_int_1,src;Pin system_early_rst_b,srtc;Pin ~ipi_srtc_int_b,srtc;Pin ~ipi_srtc_sec_int_b,ssi1;Pin ipd_ssi_tx0_dmareq_b,ssi1;Pin ~ipi_int_b,ssi2;Pin ~ipi_int_b,tigerp_platform_ne_32k_256k;Pin nm_irq_b,?..."
|
|
line.long 0x10 "OBSERVE_MUX_4,OBSERVE_MUX_4 Register"
|
|
bitfld.long 0x10 0.--4. " OBSRV ,Instance Pin for Observability IOMUXC_OBSERVE_MUX_4" "ccm;Pin pll_lvs,ccm;Pin sdma_ipg_stop_req,ccm;Pin src_clock_ready,esdhc3;Pin ipd_esdhcv3_dreq_b,esdhc4;Pin ipd_esdhcv2_dreq_b,gpc;Pin gpc_cta8_iso,gpc;Pin gpc_cta8_pg[20],gpc;Pin gpc_emi_pg[4],gpc;Pin gpc_ipu_pg_event,gpc;Pin gpc_ipu_stat_pg,gpc;Pin volt_chng,sfp;Pin sfp_ready,src;Pin emi_dvfs_req,src;Pin en_system_clk,src;Pin memory_repair_mode,src;Pin power_gating_reset_done,tigerp_platform_ne_32k_256k;Pin cti1_trigout0,tigerp_platform_ne_32k_256k;Pin cti1_trigout1,tigerp_platform_ne_32k_256k;Pin cti1_trigout2,tigerp_platform_ne_32k_256k;Pin cti1_trigout3,tigerp_platform_ne_32k_256k;Pin ~cti_irq_b,tigerp_platform_ne_32k_256k;Pin dbgack,tigerp_platform_ne_32k_256k;Pin ~pmu_irq_b,tzic;Pin tzic_wakeup_request,uart1;Pin ~ipi_uart_anded_b,uart2;Pin ~ipi_uart_anded_b,uart3;Pin ipd_uart_rx_dmareq_b,uart3;Pin ipd_uart_tx_dmareq_b,uart3;Pin ~ipi_uart_anded_b,usboh1;Pin ipi_int_uh1,usboh1;Pin ipi_int_uotg,wdog1;Pin ~ipi_wdog_int_b"
|
|
tree.end
|
|
width 30.
|
|
tree "SW_MUX_CTL_PAD Registers"
|
|
group.long 0x20++0x2AB
|
|
line.long 0x00 "SW_MUX_CTL_PAD_KEY_COL0,SW_MUX_CTL_PAD_KEY_COL0 Register"
|
|
bitfld.long 0x00 4. " SION ,Software Input On Field" "Regular,Force input path KEY_COL0"
|
|
bitfld.long 0x00 0.--2. " MUX_MODE ,MUX Mode Select Field" "COL[0]:kpp,GPIO[0]:gpio4,CLE:rawnand,Reserved,Reserved,Reserved,CTI_TRIGIN7:tigerp_platform_ne_32k_256k,TXREADY:usbphy1"
|
|
line.long 0x04 "SW_MUX_CTL_PAD_KEY_ROW0,SW_MUX_CTL_PAD_KEY_ROW0 Register"
|
|
bitfld.long 0x04 4. " SION ,Software Input On Field" "Regular,Force input path KEY_ROW0"
|
|
bitfld.long 0x04 0.--2. " MUX_MODE ,MUX Mode Select Field" "ROW[0]:kpp,GPIO[1]:gpio4,ALE:rawnand,Reserved,Reserved,Reserved,CTI_TRIGIN_ACK7:tigerp_platform_ne_32k_256k,RXVALID:usbphy1"
|
|
line.long 0x08 "SW_MUX_CTL_PAD_KEY_COL1,SW_MUX_CTL_PAD_KEY_COL1 Register"
|
|
bitfld.long 0x08 4. " SION ,Software Input On Field" "Regular,Force input path KEY_COL1"
|
|
bitfld.long 0x08 0.--2. " MUX_MODE ,MUX Mode Select Field" "COL[1]:kpp,GPIO[2]:gpio4,CEN[0]:rawnand,Reserved,Reserved,Reserved,CTI_TRIGOUT_ACK6:tigerp_platform_ne_32k_256k,RXACTIVE:usbphy1"
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line.long 0x0C "SW_MUX_CTL_PAD_KEY_ROW1,SW_MUX_CTL_PAD_KEY_ROW1 Register"
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bitfld.long 0x0C 4. " SION ,Software Input On Field" "Regular,Force input path KEY_ROW1"
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bitfld.long 0x0C 0.--2. " MUX_MODE ,MUX Mode Select Field" "ROW[1]:kpp,GPIO[3]:gpio4,CEN[1]:rawnand,Reserved,Reserved,Reserved,CTI_TRIGOUT_ACK7:tigerp_platform_ne_32k_256k,RXERROR:usbphy1"
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line.long 0x10 "SW_MUX_CTL_PAD_KEY_COL2,SW_MUX_CTL_PAD_KEY_COL2 Register"
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bitfld.long 0x10 4. " SION ,Software Input On Field" "Regular,Force input path KEY_COL2"
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bitfld.long 0x10 0.--2. " MUX_MODE ,SW_MUX_CTL_PAD_MUX Mode Select Field" "COL[2]:kpp,GPIO[4]:gpio4,CEN[2]:rawnand,Reserved,Reserved,Reserved,CTI_TRIGOUT6:tigerp_platform_ne_32k_256k,SIECLOCK:usbphy1"
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line.long 0x14 "SW_MUX_CTL_PAD_KEY_ROW2,KEY_ROW2 Register"
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bitfld.long 0x14 4. " SION ,Software Input On Field" "Regular,Force input path KEY_ROW2"
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bitfld.long 0x14 0.--2. " MUX_MODE ,MUX Mode Select Field" "ROW[2]:kpp,GPIO[5]:gpio4,CEN[3]:rawnand,Reserved,Reserved,Reserved,CTI_TRIGOUT7:tigerp_platform_ne_32k_256k,lineSTATE[0]:usbphy1"
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line.long 0x18 "SW_MUX_CTL_PAD_KEY_COL3,SW_MUX_CTL_PAD_KEY_COL3 Register"
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bitfld.long 0x18 4. " SION ,Software Input On Field" "Regular,Force input path KEY_COL3"
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bitfld.long 0x18 0.--2. " MUX_MODE ,MUX Mode Select Field" "COL[3]:kpp,GPIO[6]:gpio4,READY0:rawnand,Reserved,Reserved,Reserved,SDMA_EXT_EVENT:sdma,lineSTATE[1]:usbphy1"
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line.long 0x1C "SW_MUX_CTL_PAD_KEY_ROW3,SW_MUX_CTL_PAD_KEY_ROW3 Register"
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|
bitfld.long 0x1C 4. " SION ,Software Input On Field" "Regular,Force input path KEY_ROW3"
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bitfld.long 0x1C 0.--2. " MUX_MODE ,MUX Mode Select Field" "ROW[3]:kpp,GPIO[7]:gpio4,DQS:rawnand,Reserved,Reserved,Reserved,SDMA_EXT_EVENT[1]:sdma,VBUSVALID:usbphy1"
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line.long 0x20 "SW_MUX_CTL_PAD_I2C1_SCL,SW_MUX_CTL_PAD_I2C1_SCL Register"
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bitfld.long 0x20 4. " SION ,Software Input On Field" "Regular,Force input path I2C1_SCL"
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bitfld.long 0x20 0.--1. " MUX_MODE ,MUX Mode Select Field" "SCL:i2c1,GPIO[18]:gpio6,TXD_MUX:uart2,?..."
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line.long 0x24 "SW_MUX_CTL_PAD_I2C1_SDA,SW_MUX_CTL_PAD_I2C1_SDA Register"
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bitfld.long 0x24 4. " SION ,Software Input On Field" "Regular,Force input path I2C1_SDA"
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bitfld.long 0x24 0.--1. " MUX_MODE ,MUX Mode Select Field" "SDA:i2c1,GPIO[19]:gpio6,RXD_MUX:uart2,?..."
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line.long 0x28 "SW_MUX_CTL_PAD_I2C2_SCL,SW_MUX_CTL_PAD_I2C2_SCL Register"
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bitfld.long 0x28 4. " SION ,Software Input On Field" "Regular,Force input path I2C2_SCL"
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bitfld.long 0x28 0.--2. " MUX_MODE ,MUX Mode Select Field" "SCL:i2c2,GPIO[20]:gpio6,CTS:uart2,?..."
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line.long 0x2C "SW_MUX_CTL_PAD_I2C2_SDA,SW_MUX_CTL_PAD_I2C2_SDA Register"
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bitfld.long 0x2C 4. " SION ,Software Input On Field" "Regular,Force input path I2C2_SDA"
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bitfld.long 0x2C 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDA:i2c2,GPIO[21]:gpio6,RTS:uart2,?..."
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line.long 0x30 "SW_MUX_CTL_PAD_I2C3_SCL,SW_MUX_CTL_PAD_I2C3_SCL Register"
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bitfld.long 0x30 4. " SION ,Software Input On Field" "Regular,Force input path I2C3_SCL"
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bitfld.long 0x30 0.--2. " MUX_MODE ,MUX Mode Select Field" "SCL:i2c3,GPIO[22]:gpio6,MDC:fec,PMIC_RDY:gpc,Reserved,CAPIN1:gpt,OBSRV_INT_OUT0:observe_mux,USBOTG_OC:usboh1"
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line.long 0x34 "SW_MUX_CTL_PAD_I2C3_SDA,SW_MUX_CTL_PAD_I2C3_SDA Register"
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bitfld.long 0x34 4. " SION ,Software Input On Field" "Regular,Force input path I2C3_SDA"
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bitfld.long 0x34 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDA:i2c3,GPIO[23]:gpio6,MDIO:fec,PWRFAIL_INT:gpc,ALARM_DEB:srtc,CAPIN2:gpt,OBSRV_INT_OUT1:observe_mux,USBOTG_PWR:usboh1"
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line.long 0x38 "SW_MUX_CTL_PAD_PWM1,SW_MUX_CTL_PAD_PWM1 Register"
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bitfld.long 0x38 4. " SION ,Software Input On Field" "Regular,Force input path PWM1"
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bitfld.long 0x38 0.--2. " MUX_MODE ,MUX Mode Select Field" "PWMO:pwm1,GPIO[24]:gpio6,USBOTG_OC:usboh1,Reserved,Reserved,CMPOUT1:gpt,OBSRV_INT_OUT2:observe_mux,FAIL:sjc"
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line.long 0x3C "SW_MUX_CTL_PAD_PWM2,SW_MUX_CTL_PAD_PWM2 Register"
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bitfld.long 0x3C 4. " SION ,Software Input On Field" "Regular,Force input path PWM2"
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bitfld.long 0x3C 0.--2. " MUX_MODE ,MUX Mode Select Field" "PWMO:pwm2,GPIO[25]:gpio6,USBOTG_PWR:usboh1,Reserved,Reserved,CMPOUT2:gpt,OBSRV_INT_OUT3:observe_mux,ANY_PU_RST:src"
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line.long 0x40 "SW_MUX_CTL_PAD_OWIRE,SW_MUX_CTL_PAD_OWIRE Register"
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bitfld.long 0x40 4. " SION ,Software Input On Field" "Regular,Force input path OWIRE"
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bitfld.long 0x40 0.--2. " MUX_MODE ,MUX Mode Select Field" "line:owire,GPIO[26]:gpio6,USBH1_OC:usboh1,SSI_EXT1_CLK:ccm,PWRIRQ:epdc,CMPOUT3:gpt,OBSRV_INT_OUT4:observe_mux,JTAG_ACT:sjc"
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line.long 0x44 "SW_MUX_CTL_PAD_EPITO,SW_MUX_CTL_PAD_EPITO Register"
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bitfld.long 0x44 4. " SION ,Software Input On Field" "Regular,Force input path EPITO"
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bitfld.long 0x44 0.--2. " MUX_MODE ,MUX Mode Select Field" "EPITO:epit1,GPIO[27]:gpio6,USBH1_PWR:usboh1,SSI_EXT2_CLK:ccm,TOG_EN:dplip1,CLKIN:gpt,PMU_IRQ_B:tigerp_platform_ne_32k_256k,DE_B:sjc"
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line.long 0x48 "SW_MUX_CTL_PAD_WDOG,SW_MUX_CTL_PAD_WDOG Register"
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bitfld.long 0x48 4. " SION ,Software Input On Field" "Regular,Force input path WDOG"
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bitfld.long 0x48 0.--2. " MUX_MODE ,MUX Mode Select Field" "WDOG_B:wdog1,GPIO[28]:gpio6,WDOG_RST_B_DEB:wdog1,Reserved,Reserved,Reserved,XTAL32K:ccm,DONE:sjc"
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line.long 0x4C "SW_MUX_CTL_PAD_SSI_TXFS,SW_MUX_CTL_PAD_SSI_TXFS Register"
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bitfld.long 0x4C 4. " SION ,Software Input On Field" "Regular,Force input path SSI_TXFS"
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bitfld.long 0x4C 0.--2. " MUX_MODE ,MUX Mode Select Field" "AUD3_TXFS:audmux,GPIO[0]:gpio6,Reserved,Reserved,Reserved,Reserved,BT_FUSE_RSV[1]:src,DATAOUT[8]:usbphy1"
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line.long 0x50 "SW_MUX_CTL_PAD_SSI_TXC,SW_MUX_CTL_PAD_SSI_TXC Register"
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bitfld.long 0x50 4. " SION ,Software Input On Field" "Regular,Force input path SSI_TXC"
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bitfld.long 0x50 0.--2. " MUX_MODE ,MUX Mode Select Field" "AUD3_TXC:audmux,GPIO[1]:gpio6,Reserved,Reserved,Reserved,Reserved,BT_FUSE_RSV[0]:src,DATAOUT[9]:usbphy1"
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line.long 0x54 "SW_MUX_CTL_PAD_SSI_TXD,SW_MUX_CTL_PAD_SSI_TXD Register"
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bitfld.long 0x54 4. " SION ,Software Input On Field" "Regular,Force input path SSI_TXD"
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bitfld.long 0x54 0.--2. " MUX_MODE ,MUX Mode Select Field" "AUD3_TXD:audmux,GPIO[2]:gpio6,Reserved,Reserved,Reserved,Reserved,RDY:cspi,DATAOUT[10]:usbphy1"
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line.long 0x58 "SW_MUX_CTL_PAD_SSI_RXD,SW_MUX_CTL_PAD_SSI_RXD Register"
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bitfld.long 0x58 4. " SION ,Software Input On Field" "Regular,Force input path SSI_RXD"
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bitfld.long 0x58 0.--2. " MUX_MODE ,MUX Mode Select Field" "AUD3_RXD:audmux,GPIO[3]:gpio6,Reserved,Reserved,Reserved,Reserved,SS3:cspi,DATAOUT[11]:usbphy1"
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line.long 0x5C "SW_MUX_CTL_PAD_SSI_RXF,SW_MUX_CTL_PAD_SSI_RXF Register"
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bitfld.long 0x5C 4. " SION ,Software Input On Field" "Regular,Force input path SSI_RXF"
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bitfld.long 0x5C 0.--2. " MUX_MODE ,MUX Mode Select Field" "AUD3_RXFS:audmux,GPIO[4]:gpio6,TXD_MUX:uart5,D[6]:weimv2,SS2:cspi,COL:fec,MDC:fec,DATAOUT[12]:usbphy1"
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line.long 0x60 "SW_MUX_CTL_PAD_SSI_RXC,SW_MUX_CTL_PAD_SSI_RXC Register"
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bitfld.long 0x60 4. " SION ,Software Input On Field" "Regular,Force input path SSI_RXC"
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bitfld.long 0x60 0.--2. " MUX_MODE ,MUX Mode Select Field" "AUD3_RXC:audmux,GPIO[5]:gpio6,RXD_MUX:uart5,D[7]:weimv2,SS1:cspi,RX_CLK:fec,MDIO:fec,DATAOUT[13]:usbphy1"
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line.long 0x64 "SW_MUX_CTL_PAD_UART1_TXD,SW_MUX_CTL_PAD_UART1_TXD Register"
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bitfld.long 0x64 4. " SION ,Software Input On Field" "Regular,Force input path UART1_TXD"
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bitfld.long 0x64 0.--2. " MUX_MODE ,MUX Mode Select Field" "TXD_MUX:uart1,GPIO[6]:gpio6,Reserved,Reserved,Reserved,Reserved,Reserved,DATAOUT[14]:usbphy1"
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line.long 0x68 "SW_MUX_CTL_PAD_UART1_RXD,SW_MUX_CTL_PAD_UART1_RXD Register"
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bitfld.long 0x68 4. " SION ,Software Input On Field" "Regular,Force input path UART1_RXD"
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bitfld.long 0x68 0.--2. " MUX_MODE ,MUX Mode Select Field" "RXD_MUX:uart1,GPIO[7]:gpio6,Reserved,Reserved,Reserved,Reserved,Reserved,DATAOUT[15]:usbphy1"
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line.long 0x6C "SW_MUX_CTL_PAD_UART1_CTS,SW_MUX_CTL_PAD_UART1_CTS Register"
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bitfld.long 0x6C 4. " SION ,Software Input On Field" "Regular,Force input path UART1_CTS"
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bitfld.long 0x6C 0.--2. " MUX_MODE ,MUX Mode Select Field" "CTS:uart1,GPIO[8]:gpio6,TXD_MUX:uart5,DAT4:esdhc4,CMD:esdhc4,Reserved,Reserved,DATAOUT[8]:usbphy2"
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line.long 0x70 "SW_MUX_CTL_PAD_UART1_RTS,SW_MUX_CTL_PAD_UART1_RTS Register"
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bitfld.long 0x70 4. " SION ,Software Input On Field" "Regular,Force input path UART1_RTS"
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bitfld.long 0x70 0.--2. " MUX_MODE ,MUX Mode Select Field" "RTS:uart1,GPIO[9]:gpio6,RXD_MUX:uart5,DAT5:esdhc4,CLK:esdhc4,Reserved,Reserved,DATAOUT[9]:usbphy2"
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line.long 0x74 "SW_MUX_CTL_PAD_UART2_TXD,SW_MUX_CTL_PAD_UART2_TXD Register"
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bitfld.long 0x74 4. " SION ,Software Input On Field" "Regular,Force input path UART2_TXD"
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bitfld.long 0x74 0.--2. " MUX_MODE ,MUX Mode Select Field" "TXD_MUX:uart2,GPIO[10]:gpio6,Reserved,Reserved,DAT6:esdhc4,DAT4:esdhc4,Reserved,DATAOUT[10]:usbphy2"
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line.long 0x78 "SW_MUX_CTL_PAD_UART2_RXD,SW_MUX_CTL_PAD_UART2_RXD Register"
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bitfld.long 0x78 4. " SION ,Software Input On Field" "Regular,Force input path UART2_RXD"
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bitfld.long 0x78 0.--2. " MUX_MODE ,MUX Mode Select Field" "RXD_MUX:uart2,GPIO[11]:gpio6,Reserved,Reserved,DAT7:esdhc4,DAT5:esdhc4,Reserved,DATAOUT[11]:usbphy2"
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line.long 0x7C "SW_MUX_CTL_PAD_UART2_CTS,SW_MUX_CTL_PAD_UART2_CTS Register"
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bitfld.long 0x7C 4. " SION ,Software Input On Field" "Regular,Force input path UART2_CTS"
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bitfld.long 0x7C 0.--2. " MUX_MODE ,MUX Mode Select Field" "CTS:uart2,GPIO[12]:gpio6,Reserved,Reserved,CMD:esdhc4,DAT6:esdhc4,Reserved,DATAOUT[12]:usbphy2"
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line.long 0x80 "SW_MUX_CTL_PAD_UART2_RTS,SW_MUX_CTL_PAD_UART2_RTS Register"
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bitfld.long 0x80 4. " SION ,Software Input On Field" "Regular,Force input path UART2_RTS"
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bitfld.long 0x80 0.--2. " MUX_MODE ,MUX Mode Select Field" "RTS:uart2,GPIO[13]:gpio6,Reserved,Reserved,CLK:esdhc4,DAT7:esdhc4,Reserved,DATAOUT[13]:usbphy2"
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line.long 0x84 "SW_MUX_CTL_PAD_UART3_TXD,SW_MUX_CTL_PAD_UART3_TXD Register"
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bitfld.long 0x84 4. " SION ,Software Input On Field" "Regular,Force input path UART3_TXD"
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bitfld.long 0x84 0.--2. " MUX_MODE ,MUX Mode Select Field" "TXD_MUX:uart3,GPIO[14]:gpio6,Reserved,DAT4:esdhc1,DAT0:esdhc4,WP:esdhc2,D[12]:weimv2,DATAOUT[14]:usbphy2"
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line.long 0x88 "SW_MUX_CTL_PAD_UART3_RXD,SW_MUX_CTL_PAD_UART3_RXD Register"
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bitfld.long 0x88 4. " SION ,Software Input On Field" "Regular,Force input path UART3_RXD"
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bitfld.long 0x88 0.--2. " MUX_MODE ,MUX Mode Select Field" "RXD_MUX:uart3,GPIO[15]:gpio6,Reserved,DAT5:esdhc1,DAT1:esdhc4,CD:esdhc2,D[13]:weimv2,DATAOUT[15]:usbphy2"
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line.long 0x8C "SW_MUX_CTL_PAD_UART4_TXD,SW_MUX_CTL_PAD_UART4_TXD Register"
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bitfld.long 0x8C 4. " SION ,Software Input On Field" "Regular,Force input path UART4_TXD"
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bitfld.long 0x8C 0.--2. " MUX_MODE ,MUX Mode Select Field" "TXD_MUX:uart4,GPIO[16]:gpio6,CTS:uart3,DAT6:esdhc1,DAT2:esdhc4,LCTL:esdhc2,D[14]:weimv2,?..."
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line.long 0x90 "SW_MUX_CTL_PAD_UART4_RXD,SW_MUX_CTL_PAD_UART4_RXD Register"
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bitfld.long 0x90 4. " SION ,Software Input On Field" "Regular,Force input path UART4_RXD"
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bitfld.long 0x90 0.--2. " MUX_MODE ,MUX Mode Select Field" "RXD_MUX:uart4,GPIO[17]:gpio6,RTS:uart3,DAT7:esdhc1,DAT3:esdhc4,LCTL:esdhc1,D[15]:weimv2,?..."
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line.long 0x94 "SW_MUX_CTL_PAD_CSPI_SCLK,SW_MUX_CTL_PAD_CSPI_SCLK Register"
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bitfld.long 0x94 4. " SION ,Software Input On Field" "Regular,Force input path CSPI_SCLK"
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bitfld.long 0x94 0. " MUX_MODE ,MUX Mode Select Field" "SCLK:cspi,GPIO[8]:gpio4"
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line.long 0x98 "SW_MUX_CTL_PAD_CSPI_MOSI,SW_MUX_CTL_PAD_CSPI_MOSI Register"
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bitfld.long 0x98 4. " SION ,Software Input On Field" "Regular,Force input path CSPI_MOSI"
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bitfld.long 0x98 0. " MUX_MODE ,MUX Mode Select Field" "MOSI:cspi,GPIO[9]:gpio4"
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line.long 0x9C "SW_MUX_CTL_PAD_CSPI_MISO,SW_MUX_CTL_PAD_CSPI_MISO Register"
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bitfld.long 0x9C 4. " SION ,Software Input On Field" "Regular,Force input path CSPI_MISO"
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bitfld.long 0x9C 0. " MUX_MODE ,MUX Mode Select Field" "MISO:cspi,GPIO[10]:gpio4"
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line.long 0xA0 "SW_MUX_CTL_PAD_CSPI_SS0,SW_MUX_CTL_PAD_CSPI_SS0 Register"
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bitfld.long 0xA0 4. " SION ,Software Input On Field" "Regular,Force input path CSPI_SS0"
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bitfld.long 0xA0 0. " MUX_MODE ,MUX Mode Select Field" "SS0:cspi,GPIO[11]:gpio4"
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line.long 0xA4 "SW_MUX_CTL_PAD_ECSPI1_SCLK,SW_MUX_CTL_PAD_ECSPI1_SCLK Register"
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bitfld.long 0xA4 4. " SION ,Software Input On Field" "Regular,Force input path ECSPI1_SCLK"
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bitfld.long 0xA4 0.--2. " MUX_MODE ,MUX Mode Select Field" "SCLK:ecspi1,GPIO[12]:gpio4,RDY:cspi,RDY:ecspi2,RTS:uart3,SDCE[6]:epdc,Reserved,D[8]:weimv2"
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line.long 0xA8 "SW_MUX_CTL_PAD_ECSPI1_MOSI,SW_MUX_CTL_PAD_ECSPI1_MOSI Register"
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bitfld.long 0xA8 4. " SION ,Software Input On Field" "Regular,Force input path ECSPI1_MOSI"
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bitfld.long 0xA8 0.--2. " MUX_MODE ,MUX Mode Select Field" "MOSI:ecspi1,GPIO[13]:gpio4,SS1:cspi,SS1:ecspi2,CTS:uart3,SDCE[7]:epdc,Reserved,D[9]:weimv2"
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line.long 0xAC "SW_MUX_CTL_PAD_ECSPI1_MISO,SW_MUX_CTL_PAD_ECSPI1_MISO Register"
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bitfld.long 0xAC 4. " SION ,Software Input On Field" "Regular,Force input path ECSPI1_MISO"
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bitfld.long 0xAC 0.--2. " MUX_MODE ,MUX Mode Select Field" "MISO:ecspi1,GPIO[14]:gpio4,SS2:cspi,SS2:ecspi2,RTS:uart4,SDCE[8]:epdc,Reserved,D[10]:weimv2"
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line.long 0xB0 "SW_MUX_CTL_PAD_ECSPI1_SS0,SW_MUX_CTL_PAD_ECSPI1_SS0 Register"
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bitfld.long 0xB0 4. " SION ,Software Input On Field" "Regular,Force input path ECSPI1_SS0"
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bitfld.long 0xB0 0.--2. " MUX_MODE ,MUX Mode Select Field" "SS0:ecspi1,GPIO[15]:gpio4,SS3:cspi,SS3:ecspi2,CTS:uart4,SDCE[9]:epdc,Reserved,D[11]:weimv2"
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line.long 0xB4 "SW_MUX_CTL_PAD_ECSPI2_SCLK,SW_MUX_CTL_PAD_ECSPI2_SCLK Register"
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bitfld.long 0xB4 4. " SION ,Software Input On Field" "Regular,Force input path ECSPI2_SCLK"
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bitfld.long 0xB4 0.--2. " MUX_MODE ,MUX Mode Select Field" "SCLK:ecspi2,GPIO[16]:gpio4,WR_RWN:elcdif,RDY:ecspi1,RTS:uart5,DOTCLK:elcdif,CEN[4]:rawnand,D[8]:weimv2"
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line.long 0xB8 "SW_MUX_CTL_PAD_ECSPI2_MOSI,SW_MUX_CTL_PAD_ECSPI2_MOSI Register"
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bitfld.long 0xB8 4. " SION ,Software Input On Field" "Regular,Force input path ECSPI2_MOSI"
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bitfld.long 0xB8 0.--2. " MUX_MODE ,MUX Mode Select Field" "MOSI:ecspi2,GPIO[17]:gpio4,RD_E:elcdif,SS1:ecspi1,CTS:uart5,ENABLE:elcdif,CEN[5]:rawnand,D[9]:weimv2"
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line.long 0xBC "SW_MUX_CTL_PAD_ECSPI2_MISO,SW_MUX_CTL_PAD_ECSPI2_MISO Register"
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bitfld.long 0xBC 4. " SION ,Software Input On Field" "Regular,Force input path ECSPI2_MISO"
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bitfld.long 0xBC 0.--2. " MUX_MODE ,MUX Mode Select Field" "MISO:ecspi2,GPIO[18]:gpio4,RS:elcdif,SS1:ecspi1,TXD_MUX:uart5,VSYNC:elcdif,CEN[6]:rawnand,D[10]:weimv2"
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line.long 0xC0 "SW_MUX_CTL_PAD_ECSPI2_SS0,SW_MUX_CTL_PAD_ECSPI2_SS0 Register"
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bitfld.long 0xC0 4. " SION ,Software Input On Field" "Regular,Force input path ECSPI2_SS0"
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bitfld.long 0xC0 0.--2. " MUX_MODE ,MUX Mode Select Field" "SS0:ecspi2,GPIO[19]:gpio4,CS:elcdif,SS3:ecspi1,RXD_MUX:uart5,HSYNC:elcdif,CEN[7]:rawnand,D[11]:weimv2"
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line.long 0xC4 "SW_MUX_CTL_PAD_SD1_CLK,SW_MUX_CTL_PAD_SD1_CLK Register"
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bitfld.long 0xC4 4. " SION ,Software Input On Field" "Regular,Force input path SD1_CLK"
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bitfld.long 0xC4 0.--2. " MUX_MODE ,MUX Mode Select Field" "CLK:esdhc1,GPIO[0]:gpio5,Reserved,Reserved,Reserved,Reserved,Reserved,CLKO:ccm"
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line.long 0xC8 "SW_MUX_CTL_PAD_SD1_CMD,SW_MUX_CTL_PAD_SD1_CMD Register"
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bitfld.long 0xC8 4. " SION ,Software Input On Field" "Regular,Force input path SD1_CMD"
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bitfld.long 0xC8 0.--2. " MUX_MODE ,MUX Mode Select Field" "CMD:esdhc1,GPIO[1]:gpio5,Reserved,Reserved,Reserved,Reserved,Reserved,CLKO2:ccm"
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line.long 0xCC "SW_MUX_CTL_PAD_SD1_D0,SW_MUX_CTL_PAD_SD1_D0 Register"
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bitfld.long 0xCC 4. " SION ,Software Input On Field" "Regular,Force input path SD1_D0"
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bitfld.long 0xCC 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT0:esdhc1,GPIO[2]:gpio5,Reserved,Reserved,Reserved,Reserved,Reserved,PLL1_BYP:ccm"
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line.long 0xD0 "SW_MUX_CTL_PAD_SD1_D1,SW_MUX_CTL_PAD_SD1_D1 Register"
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|
bitfld.long 0xD0 4. " SION ,Software Input On Field" "Regular,Force input path SD1_D1"
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|
bitfld.long 0xD0 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT1:esdhc1,GPIO[3]:gpio5,Reserved,Reserved,Reserved,Reserved,Reserved,PLL2_BYP:ccm"
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line.long 0xD4 "SW_MUX_CTL_PAD_SD1_D2,SW_MUX_CTL_PAD_SD1_D2 Register"
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|
bitfld.long 0xD4 4. " SION ,Software Input On Field" "Regular,Force input path SD1_D2"
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|
bitfld.long 0xD4 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT2:esdhc1,GPIO[4]:gpio5,Reserved,Reserved,Reserved,Reserved,Reserved,PLL3_BYP:ccm"
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line.long 0xD8 "SW_MUX_CTL_PAD_SD1_D3,SW_MUX_CTL_PAD_SD1_D3 Register"
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|
bitfld.long 0xD8 4. " SION ,Software Input On Field" "Regular,Force input path SD1_D3"
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bitfld.long 0xD8 0. " MUX_MODE ,MUX Mode Select Field" "DAT3:esdhc1,GPIO[5]:gpio5"
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line.long 0xDC "SW_MUX_CTL_PAD_SD2_CLK,SW_MUX_CTL_PAD_SD2_CLK Register"
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bitfld.long 0xDC 4. " SION ,Software Input On Field" "Regular,Force input path SD2_CLK"
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bitfld.long 0xDC 0.--1. " MUX_MODE ,MUX Mode Select Field" "CLK:esdhc2,GPIO[6]:gpio5,SCLK:mshc,?..."
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line.long 0xE0 "SW_MUX_CTL_PAD_SD2_CMD,SW_MUX_CTL_PAD_SD2_CMD Register"
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bitfld.long 0xE0 4. " SION ,Software Input On Field" "Regular,Force input path SD2_CMD"
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bitfld.long 0xE0 0.--1. " MUX_MODE ,MUX Mode Select Field" "CMD:esdhc2,GPIO[7]:gpio5,BS:mshc,?..."
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line.long 0xE4 "SW_MUX_CTL_PAD_SD2_D0,SW_MUX_CTL_PAD_SD2_D0 Register"
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bitfld.long 0xE4 4. " SION ,Software Input On Field" "Regular,Force input path SD2_D0"
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bitfld.long 0xE4 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT0:esdhc2,GPIO[8]:gpio5,DATA[0]:mshc,COL[4]:kpp"
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line.long 0xE8 "SW_MUX_CTL_PAD_SD2_D1,SW_MUX_CTL_PAD_SD2_D1 Register"
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bitfld.long 0xE8 4. " SION ,Software Input On Field" "Regular,Force input path SD2_D1"
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bitfld.long 0xE8 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT1:esdhc2,GPIO[9]:gpio5,DATA[1]:mshc,ROW[4]:kpp"
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line.long 0xEC "SW_MUX_CTL_PAD_SD2_D2,SW_MUX_CTL_PAD_SD2_D2 Register"
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bitfld.long 0xEC 4. " SION ,Software Input On Field" "Regular,Force input path SD2_D2"
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bitfld.long 0xEC 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT2:esdhc2,GPIO[10]:gpio5,DATA[2]:mshc,COL[5]:kpp"
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line.long 0xF0 "SW_MUX_CTL_PAD_SD2_D3,SW_MUX_CTL_PAD_SD2_D3 Register"
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bitfld.long 0xF0 4. " SION ,Software Input On Field" "Regular,Force input path SD2_D3"
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bitfld.long 0xF0 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT3:esdhc2,GPIO[11]:gpio5,DATA[3]:mshc,ROW[5]:kpp"
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line.long 0xF4 "SW_MUX_CTL_PAD_SD2_D4,SW_MUX_CTL_PAD_SD2_D4 Register"
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bitfld.long 0xF4 4. " SION ,Software Input On Field" "Regular,Force input path SD2_D4"
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bitfld.long 0xF4 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT4:esdhc2,GPIO[12]:gpio5,AUD4_RXFS:audmux,COL[6]:kpp,D[0]:weimv2,Reserved,Reserved,CCM_OUT_0:ccm"
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line.long 0xF8 "SW_MUX_CTL_PAD_SD2_D5,SW_MUX_CTL_PAD_SD2_D5 Register"
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bitfld.long 0xF8 4. " SION ,Software Input On Field" "Regular,Force input path SD2_D5"
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bitfld.long 0xF8 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT5:esdhc2,GPIO[13]:gpio5,AUD4_RXC:audmux,ROW[6]:kpp,D[1]:weimv2,Reserved,Reserved,CCM_OUT_1:ccm"
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line.long 0xFC "SW_MUX_CTL_PAD_SD2_D6,SW_MUX_CTL_PAD_SD2_D6 Register"
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bitfld.long 0xFC 4. " SION ,Software Input On Field" "Regular,Force input path SD2_D6"
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bitfld.long 0xFC 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT6:esdhc2,GPIO[14]:gpio5,AUD4_RXD:audmux,COL[7]:kpp,D[2]:weimv2,Reserved,Reserved,CCM_OUT_2:ccm"
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line.long 0x100 "SW_MUX_CTL_PAD_SD2_D7,SW_MUX_CTL_PAD_SD2_D7 Register"
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bitfld.long 0x100 4. " SION ,Software Input On Field" "Regular,Force input path SD2_D7"
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bitfld.long 0x100 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT7:esdhc2,GPIO[15]:gpio5,AUD4_TXFS:audmux,ROW[7]:kpp,D[3]:weimv2,Reserved,Reserved,STOP:ccm"
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line.long 0x104 "SW_MUX_CTL_PAD_SD2_WP,SW_MUX_CTL_PAD_SD2_WP Register"
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bitfld.long 0x104 4. " SION ,Software Input On Field" "Regular,Force input path SD2_WP"
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bitfld.long 0x104 0.--2. " MUX_MODE ,MUX Mode Select Field" "WP:esdhc2,GPIO[16]:gpio5,AUD4_TXD:audmux,Reserved,D[4]:weimv2,Reserved,Reserved,WAIT:ccm"
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line.long 0x108 "SW_MUX_CTL_PAD_SD2_CD,SW_MUX_CTL_PAD_SD2_CD Register"
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bitfld.long 0x108 4. " SION ,Software Input On Field" "Regular,Force input path SD2_CD"
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bitfld.long 0x108 0.--2. " MUX_MODE ,MUX Mode Select Field" "CD:esdhc2,GPIO[17]:gpio5,AUD4_TXC:audmux,Reserved,D[5]:weimv2,Reserved,Reserved,REF_EN_B:ccm"
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line.long 0x10C "SW_MUX_CTL_PAD_DISP_D0,SW_MUX_CTL_PAD_DISP_D0 Register"
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bitfld.long 0x10C 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D0"
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bitfld.long 0x10C 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[0]:elcdif,GPIO[0]:gpio2,TX_CLK:fec,A[16]:weimv2,Reserved,Reserved,DEBUG_PC[0]:sdma,VSTATUS[0]:usbphy1"
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line.long 0x110 "SW_MUX_CTL_PAD_DISP_D1,SW_MUX_CTL_PAD_DISP_D1 Register"
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bitfld.long 0x110 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D1"
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bitfld.long 0x110 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[1]:elcdif,GPIO[1]:gpio2,RX_ER:fec,A[17]:weimv2,Reserved,Reserved,DEBUG_PC[2]:sdma,VSTATUS[1]:usbphy1"
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line.long 0x114 "SW_MUX_CTL_PAD_DISP_D2,SW_MUX_CTL_PAD_DISP_D2 Register"
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bitfld.long 0x114 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D2"
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bitfld.long 0x114 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[2]:elcdif,GPIO[2]:gpio2,RX_DV:fec,A[18]:weimv2,Reserved,Reserved,DEBUG_PC[2]:sdma,VSTATUS[2]:usbphy1"
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line.long 0x118 "SW_MUX_CTL_PAD_DISP_D3,SW_MUX_CTL_PAD_DISP_D3 Register"
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bitfld.long 0x118 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D3"
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bitfld.long 0x118 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[3]:elcdif,GPIO[3]:gpio2,RDATA[1]:fec,A[19]:weimv2,COL:fec,Reserved,DEBUG_PC[3]:sdma,VSTATUS[3]:usbphy1"
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line.long 0x11C "SW_MUX_CTL_PAD_DISP_D4,SW_MUX_CTL_PAD_DISP_D4 Register"
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bitfld.long 0x11C 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D4"
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bitfld.long 0x11C 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[4]:elcdif,GPIO[4]:gpio2,RDATA[0]:fec,A[20]:weimv2,Reserved,Reserved,DEBUG_PC[4]:sdma,VSTATUS[4]:usbphy1"
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line.long 0x120 "SW_MUX_CTL_PAD_DISP_D5,SW_MUX_CTL_PAD_DISP_D5 Register"
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bitfld.long 0x120 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D5"
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bitfld.long 0x120 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[5]:elcdif,GPIO[5]:gpio2,TX_EN:fec,A[21]:weimv2,Reserved,Reserved,DEBUG_PC[5]:sdma,VSTATUS[5]:usbphy1"
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line.long 0x124 "SW_MUX_CTL_PAD_DISP_D6,SW_MUX_CTL_PAD_DISP_D6 Register"
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bitfld.long 0x124 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D6"
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bitfld.long 0x124 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[6]:elcdif,GPIO[6]:gpio2,TZDATA[1]:fec,A[22]:weimv2,RX_CLK:fec,Reserved,DEBUG_PC[6]:sdma,VSTATUS[6]:usbphy1"
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line.long 0x128 "SW_MUX_CTL_PAD_DISP_D7,SW_MUX_CTL_PAD_DISP_D7 Register"
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bitfld.long 0x128 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D7"
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bitfld.long 0x128 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[7]:elcdif,GPIO[7]:gpio2,TZDATA[0]:fec,A[23]:weimv2,Reserved,Reserved,DEBUG_PC[7]:sdma,VSTATUS[7]:usbphy"
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line.long 0x12C "SW_MUX_CTL_PAD_DISP_WR,SW_MUX_CTL_PAD_DISP_WR Register"
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bitfld.long 0x12C 4. " SION ,Software Input On Field" "Regular,Force input path DISP_WR"
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bitfld.long 0x12C 0.--2. " MUX_MODE ,MUX Mode Select Field" "WR_RWN:elcdif,GPIO[16]:gpio2,DOTCLK:elcdif,A[24]:weimv2,Reserved,Reserved,DEBUG_PC[8]:sdma,VSTATUS[8]:usbphy1"
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line.long 0x130 "SW_MUX_CTL_PAD_DISP_RD,SW_MUX_CTL_PAD_DISP_RD Register"
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bitfld.long 0x130 4. " SION ,Software Input On Field" "Regular,Force input path DISP_RD"
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bitfld.long 0x130 0.--2. " MUX_MODE ,MUX Mode Select Field" "RD_E:elcdif,GPIO[19]:gpio2,ENABLE:elcdif,A[25]:weimv2,Reserved,Reserved,DEBUG_PC[9]:sdma,BVALID:usbphy1"
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line.long 0x134 "SW_MUX_CTL_PAD_DISP_RS,SW_MUX_CTL_PAD_DISP_RS Register"
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bitfld.long 0x134 4. " SION ,Software Input On Field" "Regular,Force input path DISP_RS"
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bitfld.long 0x134 0.--2. " MUX_MODE ,MUX Mode Select Field" "RS:elcdif,GPIO[17]:gpio2,VSYNC:elcdif,A[26]:weimv2,Reserved,Reserved,DEBUG_PC[10]:sdma,ENDSESSION:usbphy1"
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line.long 0x138 "SW_MUX_CTL_PAD_DISP_CS,SW_MUX_CTL_PAD_DISP_CS Register"
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bitfld.long 0x138 4. " SION ,Software Input On Field" "Regular,Force input path DISP_CS"
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bitfld.long 0x138 0.--2. " MUX_MODE ,MUX Mode Select Field" "CS:elcdif,GPIO[21]:gpio2,HSYNC:elcdif,A[27]:weimv2,CS[3]:weimv2,Reserved,DEBUG_PC[11]:sdma,IDDIG:usbphy1"
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line.long 0x13C "SW_MUX_CTL_PAD_DISP_BUSY,SW_MUX_CTL_PAD_DISP_BUSY Register"
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bitfld.long 0x13C 4. " SION ,Software Input On Field" "Regular,Force input path DISP_BUSY"
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bitfld.long 0x13C 0.--2. " MUX_MODE ,MUX Mode Select Field" "HSYNC:elcdif,GPIO[18]:gpio2,Reserved,Reserved,CS[3]:weimv2,Reserved,DEBUG_PC[12]:sdma,HOSTDISCONNECT:usbphy1"
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line.long 0x140 "SW_MUX_CTL_PAD_DISP_RESET,SW_MUX_CTL_PAD_DISP_RESET Register"
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bitfld.long 0x140 4. " SION ,Software Input On Field" "Regular,Force input path DISP_RESET"
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bitfld.long 0x140 0.--2. " MUX_MODE ,MUX Mode Select Field" "RESET:elcdif,GPIO[20]:gpio2,Reserved,Reserved,CS[3]:weimv2,Reserved,DEBUG_PC[13]:sdma,BISTOK:usbphy1"
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line.long 0x144 "SW_MUX_CTL_PAD_SD3_CMD,SW_MUX_CTL_PAD_SD3_CMD Register"
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bitfld.long 0x144 4. " SION ,Software Input On Field" "Regular,Force input path SD3_CMD"
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bitfld.long 0x144 0.--1. " MUX_MODE ,MUX Mode Select Field" "CMD:esdhc3,GPIO[18]:gpio5,WRN:rawnand,CMD:ssp"
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line.long 0x148 "SW_MUX_CTL_PAD_SD3_CLK,SW_MUX_CTL_PAD_SD3_CLK Register"
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bitfld.long 0x148 4. " SION ,Software Input On Field" "Regular,Force input path SD3_CLK"
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bitfld.long 0x148 0.--1. " MUX_MODE ,MUX Mode Select Field" "CLK:esdhc3,GPIO[19]:gpio5,RDN:rawnand,CLK:ssp"
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line.long 0x14C "SW_MUX_CTL_PAD_SD3_D0,SW_MUX_CTL_PAD_SD3_D0 Register"
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bitfld.long 0x14C 4. " SION ,Software Input On Field" "Regular,Force input path SD3_D0"
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bitfld.long 0x14C 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT0:esdhc3,GPIO[20]:gpio5,D[4]:rawnand,D0:ssp,Reserved,Reserved,Reserved,PLL1_BYP:ccm"
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line.long 0x150 "SW_MUX_CTL_PAD_SD3_D1,SW_MUX_CTL_PAD_SD3_D1 Register"
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bitfld.long 0x150 4. " SION ,Software Input On Field" "Regular,Force input path SD3_D1"
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bitfld.long 0x150 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT1:esdhc3,GPIO[21]:gpio5,D[5]:rawnand,D1:ssp,Reserved,Reserved,Reserved,PLL2_BYP:ccm"
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line.long 0x154 "SW_MUX_CTL_PAD_SD3_D2,SW_MUX_CTL_PAD_SD3_D2 Register"
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bitfld.long 0x154 4. " SION ,Software Input On Field" "Regular,Force input path SD3_D2"
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bitfld.long 0x154 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT2:esdhc3,GPIO[22]:gpio5,D[6]:rawnand,D2:ssp,Reserved,Reserved,Reserved,PLL3_BYP:ccm"
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line.long 0x158 "SW_MUX_CTL_PAD_SD3_D3,SW_MUX_CTL_PAD_SD3_D3 Register"
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bitfld.long 0x158 4. " SION ,Software Input On Field" "Regular,Force input path SD3_D3"
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bitfld.long 0x158 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT3:esdhc3,GPIO[23]:gpio5,D[7]:rawnand,D3:ssp"
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line.long 0x15C "SW_MUX_CTL_PAD_SD3_D4,SW_MUX_CTL_PAD_SD3_D4 Register"
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bitfld.long 0x15C 4. " SION ,Software Input On Field" "Regular,Force input path SD3_D4"
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bitfld.long 0x15C 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT4:esdhc3,GPIO[24]:gpio5,D[0]:rawnand,D4:ssp"
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line.long 0x160 "SW_MUX_CTL_PAD_SD3_D5,SW_MUX_CTL_PAD_SD3_D5 Register"
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bitfld.long 0x160 4. " SION ,Software Input On Field" "Regular,Force input path SD3_D5"
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bitfld.long 0x160 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT5:esdhc3,GPIO[25]:gpio5,D[1]:rawnand,D5:ssp"
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line.long 0x164 "SW_MUX_CTL_PAD_SD3_D6,SW_MUX_CTL_PAD_SD3_D6 Register"
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bitfld.long 0x164 4. " SION ,Software Input On Field" "Regular,Force input path SD3_D6"
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bitfld.long 0x164 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT6:esdhc3,GPIO[26]:gpio5,D[2]:rawnand,D6:ssp"
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line.long 0x168 "SW_MUX_CTL_PAD_SD3_D7,SW_MUX_CTL_PAD_SD3_D7 Register"
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bitfld.long 0x168 4. " SION ,Software Input On Field" "Regular,Force input path SD3_D7"
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bitfld.long 0x168 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT7:esdhc3,GPIO[27]:gpio5,D[3]:rawnand,D7:ssp"
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line.long 0x16C "SW_MUX_CTL_PAD_SD3_WP,SW_MUX_CTL_PAD_SD3_WP Register"
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bitfld.long 0x16C 4. " SION ,Software Input On Field" "Regular,Force input path SD3_WP"
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bitfld.long 0x16C 0.--2. " MUX_MODE ,MUX Mode Select Field" "WP:esdhc3,GPIO[28]:gpio5,RESETN:rawnand,CD:ssp,LCTL:esdhc4,CS[3]:weimv2,?..."
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line.long 0x170 "SW_MUX_CTL_PAD_DISP_D8,SW_MUX_CTL_PAD_DISP_D8 Register"
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bitfld.long 0x170 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D8"
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bitfld.long 0x170 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[8]:elcdif,GPIO[8]:gpio2,CLE:rawnand,LCTL:esdhc1,CMD:esdhc4,COL[4]:kpp,TX_CLK:fec,DATAOUT[0]:usbphy1"
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line.long 0x174 "SW_MUX_CTL_PAD_DISP_D9,SW_MUX_CTL_PAD_DISP_D9 Register"
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bitfld.long 0x174 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D9"
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bitfld.long 0x174 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[9]:elcdif,GPIO[9]:gpio2,ALE:rawnand,LCTL:esdhc2,CLK:esdhc4,ROW[4]:kpp,RX_ER:fec,DATAOUT[1]:usbphy1"
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line.long 0x178 "SW_MUX_CTL_PAD_DISP_D10,SW_MUX_CTL_PAD_DISP_D10 Register"
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bitfld.long 0x178 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D10"
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bitfld.long 0x178 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[10]:elcdif,GPIO[10]:gpio2,CEN[0]:rawnand,LCTL:esdhc3,DAT0:esdhc4,COL[5]:kpp,RX_DV:fec,DATAOUT[2]:usbphy1"
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line.long 0x17C "SW_MUX_CTL_PAD_DISP_D11,SW_MUX_CTL_PAD_DISP_D11 Register"
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bitfld.long 0x17C 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D11"
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bitfld.long 0x17C 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[11]:elcdif,GPIO[11]:gpio2,CEN[1]:rawnand,Reserved,DAT1:esdhc4,ROW[5]:kpp,RDATA[1]:fec,DATAOUT[3]:usbphy1"
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line.long 0x180 "SW_MUX_CTL_PAD_DISP_D12,SW_MUX_CTL_PAD_DISP_D12 Register"
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bitfld.long 0x180 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D12"
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bitfld.long 0x180 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[12]:elcdif,GPIO[12]:gpio2,CEN[2]:rawnand,CD:esdhc1,DAT2:esdhc4,COL[6]:kpp,RDATA[0]:fec,DATAOUT[4]:usbphy1"
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line.long 0x184 "SW_MUX_CTL_PAD_DISP_D13,SW_MUX_CTL_PAD_DISP_D13 Register"
|
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bitfld.long 0x184 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D13"
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bitfld.long 0x184 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[13]:elcdif,GPIO[13]:gpio2,CEN[3]:rawnand,CD:esdhc3,DAT3:esdhc4,ROW[6]:kpp,TX_EN:fec,DATAOUT[5]:usbphy1"
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line.long 0x188 "SW_MUX_CTL_PAD_DISP_D14,SW_MUX_CTL_PAD_DISP_D14 Register"
|
|
bitfld.long 0x188 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D14"
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bitfld.long 0x188 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[14]:elcdif,GPIO[14]:gpio2,READY0:rawnand,WP:esdhc1,WP:esdhc4,COL[7]:kpp,TXDATA[1]:fec,DATAOUT[6]:usbphy1"
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line.long 0x18C "SW_MUX_CTL_PAD_DISP_D15,SW_MUX_CTL_PAD_DISP_D15 Register"
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bitfld.long 0x18C 4. " SION ,Software Input On Field" "Regular,Force input path DISP_D15"
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bitfld.long 0x18C 0.--2. " MUX_MODE ,MUX Mode Select Field" "DAT[15]:elcdif,GPIO[15]:gpio2,DQS:rawnand,RST:esdhc3,CD:esdhc4,ROW[7]:kpp,TDATA[0]:fec,DATAOUT[7]:usbphy1"
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line.long 0x190 "SW_MUX_CTL_PAD_EPDC_D0,SW_MUX_CTL_PAD_EPDC_D0 Register"
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bitfld.long 0x190 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D0"
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bitfld.long 0x190 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[0]:epdc,GPIO[0]:gpio3,D[0]:weimv2,RS:elcdif,DOTCLK:elcdif,Reserved,DEBUG_EVT_CHN_lineS[0]:sdma,DATAOUT[0]:usbphy2"
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line.long 0x194 "SW_MUX_CTL_PAD_EPDC_D1,SW_MUX_CTL_PAD_EPDC_D1 Register"
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bitfld.long 0x194 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D1"
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bitfld.long 0x194 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[1]:epdc,GPIO[1]:gpio3,D[1]:weimv2,CS:elcdif,ENABLE:elcdif,Reserved,DEBUG_EVT_CHN_lineS[1]:sdma,DATAOUT[1]:usbphy2"
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line.long 0x198 "SW_MUX_CTL_PAD_EPDC_D2,SW_MUX_CTL_PAD_EPDC_D2 Register"
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bitfld.long 0x198 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D2"
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bitfld.long 0x198 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[2]:epdc,GPIO[2]:gpio3,D[2]:weimv2,WR_RWN:elcdif,VSYNC:elcdif,Reserved,DEBUG_EVT_CHN_lineS[2]:sdma,DATAOUT[2]:usbphy2"
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line.long 0x19C "SW_MUX_CTL_PAD_EPDC_D3,SW_MUX_CTL_PAD_EPDC_D3 Register"
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bitfld.long 0x19C 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D3"
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bitfld.long 0x19C 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[3]:epdc,GPIO[3]:gpio3,D[3]:weimv2,RD_E:elcdif,HSYNC:elcdif,Reserved,DEBUG_EVT_CHN_lineS[3]:sdma,DATAOUT[3]:usbphy2"
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line.long 0x1A0 "SW_MUX_CTL_PAD_EPDC_D4,SW_MUX_CTL_PAD_EPDC_D4 Register"
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bitfld.long 0x1A0 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D4"
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bitfld.long 0x1A0 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[4]:epdc,GPIO[4]:gpio3,D[4]:weimv2,Reserved,Reserved,Reserved,DEBUG_EVT_CHN_lineS[4]:sdma,DATAOUT[4]:usbphy2"
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line.long 0x1A4 "SW_MUX_CTL_PAD_EPDC_D5,SW_MUX_CTL_PAD_EPDC_D5 Register"
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bitfld.long 0x1A4 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D5"
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bitfld.long 0x1A4 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[5]:epdc,GPIO[5]:gpio3,D[5]:weimv2,Reserved,Reserved,Reserved,DEBUG_EVT_CHN_lineS[5]:sdma,DATAOUT[5]:usbphy2"
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line.long 0x1A8 "SW_MUX_CTL_PAD_EPDC_D6,SW_MUX_CTL_PAD_EPDC_D6 Register"
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bitfld.long 0x1A8 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D6"
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bitfld.long 0x1A8 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[6]:epdc,GPIO[6]:gpio3,D[6]:weimv2,Reserved,Reserved,Reserved,DEBUG_EVT_CHN_lineS[6]:sdma,DATAOUT[6]:usbphy2"
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line.long 0x1AC "SW_MUX_CTL_PAD_EPDC_D7,SW_MUX_CTL_PAD_EPDC_D7 Register"
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bitfld.long 0x1AC 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D7"
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bitfld.long 0x1AC 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[7]:epdc,GPIO[7]:gpio3,D[7]:weimv2,Reserved,Reserved,Reserved,DEBUG_EVT_CHN_lineS[7]:sdma,DATAOUT[7]:usbphy2"
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line.long 0x1B0 "SW_MUX_CTL_PAD_EPDC_D8,SW_MUX_CTL_PAD_EPDC_D8 Register"
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bitfld.long 0x1B0 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D8"
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bitfld.long 0x1B0 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[8]:epdc,GPIO[8]:gpio3,D[8]:weimv2,DAT[24]:elcdif,Reserved,Reserved,DEBUG_MATCHED_DMBUS:sdma,VSTATUS[0]:usbphy2"
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line.long 0x1B4 "SW_MUX_CTL_PAD_EPDC_D9,SW_MUX_CTL_PAD_EPDC_D9 Register"
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bitfld.long 0x1B4 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D9"
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bitfld.long 0x1B4 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[9]:epdc,GPIO[9]:gpio3,D[9]:weimv2,DAT[25]:elcdif,Reserved,Reserved,DEBUG_EVENT_CHANNEL_SEL:sdma,VSTATUS[2]:usbphy2"
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line.long 0x1B8 "SW_MUX_CTL_PAD_EPDC_D10,SW_MUX_CTL_PAD_EPDC_D10 Register"
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bitfld.long 0x1B8 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D10"
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bitfld.long 0x1B8 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[10]:epdc,GPIO[10]:gpio3,D[10]:weimv2,DAT[26]:elcdif,Reserved,Reserved,DEBUG_EVENT_CHANNEL[0]:sdma,VSTATUS[2]:usbphy2"
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line.long 0x1BC "SW_MUX_CTL_PAD_EPDC_D11,SW_MUX_CTL_PAD_EPDC_D11 Register"
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bitfld.long 0x1BC 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D11"
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bitfld.long 0x1BC 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[11]:epdc,GPIO[11]:gpio3,D[11]:weimv2,DAT[27]:elcdif,Reserved,Reserved,DEBUG_EVENT_CHANNEL[1]:sdma,VSTATUS[3]:usbphy2"
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line.long 0x1C0 "SW_MUX_CTL_PAD_EPDC_D12,SW_MUX_CTL_PAD_EPDC_D12 Register"
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bitfld.long 0x1C0 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D12"
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bitfld.long 0x1C0 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[12]:epdc,GPIO[12]:gpio3,D[12]:weimv2,DAT[28]:elcdif,Reserved,Reserved,DEBUG_EVENT_CHANNEL[2]:sdma,VSTATUS[4]:usbphy2"
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line.long 0x1C4 "SW_MUX_CTL_PAD_EPDC_D13,SW_MUX_CTL_PAD_EPDC_D13 Register"
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bitfld.long 0x1C4 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D13"
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bitfld.long 0x1C4 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[13]:epdc,GPIO[13]:gpio3,D[13]:weimv2,DAT[29]:elcdif,Reserved,Reserved,DEBUG_EVENT_CHANNEL[3]:sdma,VSTATUS[5]:usbphy2"
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line.long 0x1C8 "SW_MUX_CTL_PAD_EPDC_D14,SW_MUX_CTL_PAD_EPDC_D14 Register"
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bitfld.long 0x1C8 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D14"
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bitfld.long 0x1C8 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[14]:epdc,GPIO[14]:gpio3,D[14]:weimv2,DAT[30]:elcdif,AUD6_TXD:audmux,Reserved,DEBUG_EVENT_CHANNEL[4]:sdma,VSTATUS[6]:usbphy2"
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line.long 0x1CC "SW_MUX_CTL_PAD_EPDC_D15,SW_MUX_CTL_PAD_EPDC_D15 Register"
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bitfld.long 0x1CC 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_D15"
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bitfld.long 0x1CC 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDDO[15]:epdc,GPIO[15]:gpio3,D[15]:weimv2,DAT[31]:elcdif,AUD6_TXC:audmux,Reserved,DEBUG_EVENT_CHANNEL[5]:sdma,VSTATUS[7]:usbphy2"
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line.long 0x1D0 "SW_MUX_CTL_PAD_EPDC_GDCLK,SW_MUX_CTL_PAD_EPDC_GDCLK Register"
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bitfld.long 0x1D0 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_GDCLK"
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bitfld.long 0x1D0 0.--2. " MUX_MODE ,MUX Mode Select Field" "GDCLK:epdc,GPIO[16]:gpio3,D[16]:weimv2,DAT[31]:elcdif,AUD6_TXFS:audmux,Reserved,DEBUG_CORE_STATE[0]:sdma,BISTOK:usbphy2"
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line.long 0x1D4 "SW_MUX_CTL_PAD_EPDC_GDSP,SW_MUX_CTL_PAD_EPDC_GDSP Register"
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bitfld.long 0x1D4 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_GDSP"
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bitfld.long 0x1D4 0.--2. " MUX_MODE ,MUX Mode Select Field" "GDSP:epdc,GPIO[17]:gpio3,D[17]:weimv2,DAT[17]:elcdif,AUD6_RXD:audmux,Reserved,DEBUG_CORE_STATE[1]:sdma,BVALID:usbphy2"
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line.long 0x1D8 "SW_MUX_CTL_PAD_EPDC_GDOE,SW_MUX_CTL_PAD_EPDC_GDOE Register"
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bitfld.long 0x1D8 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_GDOE"
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bitfld.long 0x1D8 0.--2. " MUX_MODE ,MUX Mode Select Field" "GDOE:epdc,GPIO[18]:gpio3,D[18]:weimv2,DAT[18]:elcdif,AUD6_RXC:audmux,Reserved,DEBUG_CORE_STATE[2]:sdma,ENDSESSION:usbphy2"
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line.long 0x1DC "SW_MUX_CTL_PAD_EPDC_GDRL,SW_MUX_CTL_PAD_EPDC_GDRL Register"
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bitfld.long 0x1DC 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_GDRL"
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bitfld.long 0x1DC 0.--2. " MUX_MODE ,MUX Mode Select Field" "GDRL:epdc,GPIO[19]:gpio3,D[19]:weimv2,DAT[19]:elcdif,AUD6_RXFS:audmux,Reserved,DEBUG_CORE_STATE[3]:sdma,IDDIG:usbphy2"
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line.long 0x1E0 "SW_MUX_CTL_PAD_EPDC_SDCLK,SW_MUX_CTL_PAD_EPDC_SDCLK Register"
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bitfld.long 0x1E0 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDCLK"
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bitfld.long 0x1E0 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDCLK:epdc,GPIO[20]:gpio3,D[20]:weimv2,DAT[20]:elcdif,AUD5_TXD:audmux,Reserved,DEBUG_BUS_DEVICE[0]:sdma,HOSTDISCONNECT:usbphy2"
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line.long 0x1E4 "SW_MUX_CTL_PAD_EPDC_SDOEZ,SW_MUX_CTL_PAD_EPDC_SDOEZ Register"
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bitfld.long 0x1E4 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDOEZ"
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bitfld.long 0x1E4 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDOEZ:epdc,GPIO[21]:gpio3,D[21]:weimv2,DAT[21]:elcdif,AUD5_TXC:audmux,Reserved,DEBUG_BUS_DEVICE[1]:sdma,TXREADY:usbphy2"
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line.long 0x1E8 "SW_MUX_CTL_PAD_EPDC_SDOED,SW_MUX_CTL_PAD_EPDC_SDOED Register"
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bitfld.long 0x1E8 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDOED"
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bitfld.long 0x1E8 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDOED:epdc,GPIO[22]:gpio3,D[22]:weimv2,DAT[22]:elcdif,AUD5_TXFS:audmux,Reserved,DEBUG_BUS_DEVICE[2]:sdma,RXVALID:usbphy2"
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line.long 0x1EC "SW_MUX_CTL_PAD_EPDC_SDOE,SW_MUX_CTL_PAD_EPDC_SDOE Register"
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bitfld.long 0x1EC 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDOE"
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bitfld.long 0x1EC 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDOE:epdc,GPIO[23]:gpio3,D[23]:weimv2,DAT[23]:elcdif,AUD5_RXD:audmux,Reserved,DEBUG_BUS_DEVICE[3]:sdma,RXACTIVE:usbphy2"
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line.long 0x1F0 "SW_MUX_CTL_PAD_EPDC_SDLE,SW_MUX_CTL_PAD_EPDC_SDLE Register"
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bitfld.long 0x1F0 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDLE"
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bitfld.long 0x1F0 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDLE:epdc,GPIO[24]:gpio3,D[24]:weimv2,DAT[24]:elcdif,AUD5_RXC:audmux,Reserved,DEBUG_BUS_DEVICE[4]:sdma,RXERROR:usbphy2"
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line.long 0x1F4 "SW_MUX_CTL_PAD_EPDC_SDCLKN,SW_MUX_CTL_PAD_EPDC_SDCLKN Register"
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bitfld.long 0x1F4 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDCLKN"
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bitfld.long 0x1F4 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDCLKN:epdc,GPIO[25]:gpio3,D[25]:weimv2,DAT[9]:elcdif,AUD5_RXFS:audmux,Reserved,DEBUG_BUS_ERROR:sdma,SIECLOCK:usbphy2"
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line.long 0x1F8 "SW_MUX_CTL_PAD_EPDC_SDSHR,SW_MUX_CTL_PAD_EPDC_SDSHR Register"
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bitfld.long 0x1F8 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDSHR"
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bitfld.long 0x1F8 0.--2. " MUX_MODE ,MUX Mode Select Field" "SDSHR:epdc,GPIO[26]:gpio3,D[26]:weimv2,DAT[10]:elcdif,AUD4_TXD:audmux,Reserved,DEBUG_BUS_RWB:sdma,lineSTATE[0]:usbphy2"
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line.long 0x1FC "SW_MUX_CTL_PAD_EPDC_PWRCOM,SW_MUX_CTL_PAD_EPDC_PWRCOM Register"
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bitfld.long 0x1FC 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_PWRCOM"
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bitfld.long 0x1FC 0.--2. " MUX_MODE ,MUX Mode Select Field" "PWRCOM:epdc,GPIO[27]:gpio3,D[27]:weimv2,DAT[11]:elcdif,AUD4_TXC:audmux,Reserved,DEBUG_CORE_RUN:sdma,lineSTATE[1]:usbphy2"
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line.long 0x200 "SW_MUX_CTL_PAD_EPDC_PWRSTAT,SW_MUX_CTL_PAD_EPDC_PWRSTAT Register"
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bitfld.long 0x200 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_PWRSTAT"
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bitfld.long 0x200 0.--2. " MUX_MODE ,MUX Mode Select Field" "PWRSTAT:epdc,GPIO[28]:gpio3,D[28]:weimv2,DAT[12]:elcdif,AUD4_TXFS:audmux,Reserved,DEBUG_MODE:sdma,VBUSVALID:usbphy2"
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line.long 0x204 "SW_MUX_CTL_PAD_EPDC_PWRCTRL0,SW_MUX_CTL_PAD_EPDC_PWRCTRL0 Register"
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bitfld.long 0x204 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_PWRCTRL0"
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bitfld.long 0x204 0.--2. " MUX_MODE ,MUX Mode Select Field" "PWRCTRL[0]:epdc,GPIO[29]:gpio3,D[29]:weimv2,DAT[13]:elcdif,AUD4_RXD:audmux,Reserved,DEBUG_RTBUFFER_WRITE:sdma,AVALID:usbphy2"
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line.long 0x208 "SW_MUX_CTL_PAD_EPDC_PWRCTRL1,SW_MUX_CTL_PAD_EPDC_PWRCTRL1 Register"
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bitfld.long 0x208 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_PWRCTRL1"
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bitfld.long 0x208 0.--2. " MUX_MODE ,MUX Mode Select Field" "PWRCTRL[1]:epdc,GPIO[30]:gpio3,D[30]:weimv2,DAT[14]:elcdif,AUD4_RXC:audmux,Reserved,DEBUG_YIELD:sdma,ONBIST:usbphy2"
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line.long 0x20C "SW_MUX_CTL_PAD_EPDC_PWRCTRL2,SW_MUX_CTL_PAD_EPDC_PWRCTRL2 Register"
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bitfld.long 0x20C 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_PWRCTRL2"
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bitfld.long 0x20C 0.--2. " MUX_MODE ,MUX Mode Select Field" "PWRCTRL[2]:epdc,GPIO[31]:gpio3,D[31]:weimv2,DAT[15]:elcdif,AUD4_RXFS:audmux,Reserved,SDMA_EXT_EVENT[0]:sdma,ONBIST:usbphy2"
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line.long 0x210 "SW_MUX_CTL_PAD_EPDC_PWRCTRL3,SW_MUX_CTL_PAD_EPDC_PWRCTRL3 Register"
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bitfld.long 0x210 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_PWRCTRL3"
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bitfld.long 0x210 0.--2. " MUX_MODE ,MUX Mode Select Field" "PWRCTRL[3]:epdc,GPIO[20]:gpio4,EB[2]:weimv2,Reserved,Reserved,Reserved,SDMA_EXT_EVENT[1]:sdma,BISTOK:usbphy1"
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line.long 0x214 "SW_MUX_CTL_PAD_EPDC_VCOM0,SW_MUX_CTL_PAD_EPDC_VCOM0 Register"
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bitfld.long 0x214 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_VCOM0"
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bitfld.long 0x214 0.--2. " MUX_MODE ,MUX Mode Select Field" "VCOM[0]:epdc,GPIO[21]:gpio4,EB[3]:weimv2,Reserved,Reserved,Reserved,Reserved,BISTOK:usbphy2"
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line.long 0x218 "SW_MUX_CTL_PAD_EPDC_VCOM1,SW_MUX_CTL_PAD_EPDC_VCOM1 Register"
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bitfld.long 0x218 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_VCOM1"
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bitfld.long 0x218 0.--1. " MUX_MODE ,MUX Mode Select Field" "VCOM[1]:epdc,GPIO[22]:gpio4,CS[3]:weimv2,?..."
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line.long 0x21C "SW_MUX_CTL_PAD_EPDC_BDR0,SW_MUX_CTL_PAD_EPDC_BDR0 Register"
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bitfld.long 0x21C 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_BDR0"
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bitfld.long 0x21C 0.--1. " MUX_MODE ,MUX Mode Select Field" "BDR[0]:epdc,GPIO[23]:gpio4,Reserved,DAT[7]:elcdif"
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line.long 0x220 "SW_MUX_CTL_PAD_EPDC_BDR1,SW_MUX_CTL_PAD_EPDC_BDR1 Register"
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bitfld.long 0x220 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_BDR1"
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bitfld.long 0x220 0.--1. " MUX_MODE ,MUX Mode Select Field" "BDR[1]:epdc,GPIO[24]:gpio4,Reserved,DAT[6]:elcdif"
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line.long 0x224 "SW_MUX_CTL_PAD_EPDC_SDCE0,SW_MUX_CTL_PAD_EPDC_SDCE0 Register"
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bitfld.long 0x224 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDCE0"
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bitfld.long 0x224 0.--1. " MUX_MODE ,MUX Mode Select Field" "SDCE[0]:epdc,GPIO[25]:gpio4,Reserved,DAT[5]:elcdif"
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line.long 0x228 "SW_MUX_CTL_PAD_EPDC_SDCE1,SW_MUX_CTL_PAD_EPDC_SDCE1 Register"
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bitfld.long 0x228 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDCE1"
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bitfld.long 0x228 0.--1. " MUX_MODE ,MUX Mode Select Field" "SDCE[1]:epdc,GPIO[26]:gpio4,Reserved,DAT[4]:elcdif"
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line.long 0x22C "SW_MUX_CTL_PAD_EPDC_SDCE2,SW_MUX_CTL_PAD_EPDC_SDCE2 Register"
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bitfld.long 0x22C 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDCE2"
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bitfld.long 0x22C 0.--1. " MUX_MODE ,MUX Mode Select Field" "SDCE[2]:epdc,GPIO[27]:gpio4,Reserved,DAT[3]:elcdif"
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line.long 0x230 "SW_MUX_CTL_PAD_EPDC_SDCE3,SW_MUX_CTL_PAD_EPDC_SDCE3 Register"
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bitfld.long 0x230 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDCE3"
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bitfld.long 0x230 0.--1. " MUX_MODE ,MUX Mode Select Field" "SDCE[3]:epdc,GPIO[28]:gpio4,Reserved,DAT[2]:elcdif"
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line.long 0x234 "SW_MUX_CTL_PAD_EPDC_SDCE4,SW_MUX_CTL_PAD_EPDC_SDCE4 Register"
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bitfld.long 0x234 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDCE4"
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bitfld.long 0x234 0.--1. " MUX_MODE ,MUX Mode Select Field" "SDCE[4]:epdc,GPIO[29]:gpio4,Reserved,DAT[1]:elcdif"
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line.long 0x238 "SW_MUX_CTL_PAD_EPDC_SDCE5,SW_MUX_CTL_PAD_EPDC_SDCE5 Register"
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bitfld.long 0x238 4. " SION ,Software Input On Field" "Regular,Force input path EPDC_SDCE5"
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bitfld.long 0x238 0.--1. " MUX_MODE ,MUX Mode Select Field" "SDCE[5]:epdc,GPIO[30]:gpio4,Reserved,DAT[0]:elcdif"
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line.long 0x23C "SW_MUX_CTL_PAD_EIM_DA0,SW_MUX_CTL_PAD_EIM_DA0 Register"
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bitfld.long 0x23C 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA0"
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bitfld.long 0x23C 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[0]:weimv2,GPIO[0]:gpio1,Reserved,COL[4]:kpp,Reserved,Reserved,TRACE[0]:tpiu,BT_CFG1[0]:src"
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line.long 0x240 "SW_MUX_CTL_PAD_EIM_DA1,SW_MUX_CTL_PAD_EIM_DA1 Register"
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bitfld.long 0x240 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA1"
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bitfld.long 0x240 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[1]:weimv2,GPIO[1]:gpio1,Reserved,ROW[4]:kpp,Reserved,Reserved,TRACE[1]:tpiu,BT_CFG1[1]:src"
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line.long 0x244 "SW_MUX_CTL_PAD_EIM_DA2,SW_MUX_CTL_PAD_EIM_DA2 Register"
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bitfld.long 0x244 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA2"
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bitfld.long 0x244 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[2]:weimv2,GPIO[2]:gpio1,Reserved,COL[5]:kpp,Reserved,Reserved,TRACE[2]:tpiu,BT_CFG1[2]:src"
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line.long 0x248 "SW_MUX_CTL_PAD_EIM_DA3,SW_MUX_CTL_PAD_EIM_DA3 Register"
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bitfld.long 0x248 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA3"
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bitfld.long 0x248 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[3]:weimv2,GPIO[3]:gpio1,Reserved,ROW[5]:kpp,Reserved,Reserved,TRACE[3]:tpiu,BT_CFG1[3]:src"
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|
line.long 0x24C "SW_MUX_CTL_PAD_EIM_DA4,SW_MUX_CTL_PAD_EIM_DA4 Register"
|
|
bitfld.long 0x24C 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA4"
|
|
bitfld.long 0x24C 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[4]:weimv2,GPIO[4]:gpio1,Reserved,COL[6]:kpp,Reserved,Reserved,TRACE[4]:tpiu,BT_CFG1[4]:src"
|
|
line.long 0x250 "SW_MUX_CTL_PAD_EIM_DA5,SW_MUX_CTL_PAD_EIM_DA5 Register"
|
|
bitfld.long 0x250 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA5"
|
|
bitfld.long 0x250 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[5]:weimv2,GPIO[5]:gpio1,Reserved,ROW[6]:kpp,Reserved,Reserved,TRACE[5]:tpiu,BT_CFG1[5]:src"
|
|
line.long 0x254 "SW_MUX_CTL_PAD_EIM_DA6,SW_MUX_CTL_PAD_EIM_DA6 Register"
|
|
bitfld.long 0x254 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA6"
|
|
bitfld.long 0x254 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[6]:weimv2,GPIO[6]:gpio1,Reserved,COL[7]:kpp,Reserved,Reserved,TRACE[6]:tpiu,BT_CFG1[6]:src"
|
|
line.long 0x258 "SW_MUX_CTL_PAD_EIM_DA7,SW_MUX_CTL_PAD_EIM_DA7 Register"
|
|
bitfld.long 0x258 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA7"
|
|
bitfld.long 0x258 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[7]:weimv2,GPIO[7]:gpio1,Reserved,ROW[7]:kpp,Reserved,Reserved,TRACE[7]:tpiu,BT_CFG1[7]:src"
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|
line.long 0x25C "SW_MUX_CTL_PAD_EIM_DA8,SW_MUX_CTL_PAD_EIM_DA8 Register"
|
|
bitfld.long 0x25C 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA8"
|
|
bitfld.long 0x25C 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[8]:weimv2,GPIO[8]:gpio1,CLE:rawnand,Reserved,Reserved,Reserved,TRACE[8]:tpiu,BT_CFG2[0]:src"
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|
line.long 0x260 "SW_MUX_CTL_PAD_EIM_DA9,SW_MUX_CTL_PAD_EIM_DA9 Register"
|
|
bitfld.long 0x260 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA9"
|
|
bitfld.long 0x260 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[9]:weimv2,GPIO[9]:gpio1,ALE:rawnand,Reserved,Reserved,Reserved,TRACE[9]:tpiu,BT_CFG2[1]:src"
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|
line.long 0x264 "SW_MUX_CTL_PAD_EIM_DA10,SW_MUX_CTL_PAD_EIM_DA10 Register"
|
|
bitfld.long 0x264 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA10"
|
|
bitfld.long 0x264 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[10]:weimv2,GPIO[10]:gpio1,CEN[0]:rawnand,Reserved,Reserved,Reserved,TRACE[10]:tpiu,BT_CFG2[2]:src"
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|
line.long 0x268 "SW_MUX_CTL_PAD_EIM_DA11,SW_MUX_CTL_PAD_EIM_DA11 Register"
|
|
bitfld.long 0x268 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA11"
|
|
bitfld.long 0x268 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[11]:weimv2,GPIO[11]:gpio1,CEN[1]:rawnand,Reserved,Reserved,Reserved,TRACE[11]:tpiu,BT_CFG2[3]:src"
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|
line.long 0x26C "SW_MUX_CTL_PAD_EIM_DA12,SW_MUX_CTL_PAD_EIM_DA12 Register"
|
|
bitfld.long 0x26C 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA12"
|
|
bitfld.long 0x26C 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[12]:weimv2,GPIO[12]:gpio1,CEN[2]:rawnand,Reserved,Reserved,Reserved,TRACE[12]:tpiu,BT_CFG2[4]:src"
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|
line.long 0x270 "SW_MUX_CTL_PAD_EIM_DA13,SW_MUX_CTL_PAD_EIM_DA13 Register"
|
|
bitfld.long 0x270 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA13"
|
|
bitfld.long 0x270 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[13]:weimv2,GPIO[13]:gpio1,CEN[3]:rawnand,SDCE[7]:epdc,Reserved,Reserved,TRACE[13]:tpiu,BT_CFG2[5]:src"
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|
line.long 0x274 "SW_MUX_CTL_PAD_EIM_DA14,SW_MUX_CTL_PAD_EIM_DA14 Register"
|
|
bitfld.long 0x274 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA14"
|
|
bitfld.long 0x274 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[14]:weimv2,GPIO[14]:gpio1,READY0:rawnand,SDCE[8]:epdc,Reserved,Reserved,TRACE[14]:tpiu,BT_CFG2[6]:src"
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|
line.long 0x278 "SW_MUX_CTL_PAD_EIM_DA15,SW_MUX_CTL_PAD_EIM_DA15 Register"
|
|
bitfld.long 0x278 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DA15"
|
|
bitfld.long 0x278 0.--2. " MUX_MODE ,MUX Mode Select Field" "A[15]:weimv2,GPIO[15]:gpio1,DQS:rawnand,SDCE[9]:epdc,Reserved,Reserved,TRACE[15]:tpiu,BT_CFG2[7]:src"
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|
line.long 0x27C "SW_MUX_CTL_PAD_EIM_CS2,SW_MUX_CTL_PAD_EIM_CS2 Register"
|
|
bitfld.long 0x27C 4. " SION ,Software Input On Field" "Regular,Force input path EIM_CS2"
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|
bitfld.long 0x27C 0.--2. " MUX_MODE ,MUX Mode Select Field" "CS[2]:weimv2,GPIO[16]:gpio1,A[27]:weimv2,Reserved,Reserved,Reserved,TRCLK:tpiu,BT_CFG3[0]:src"
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|
line.long 0x280 "SW_MUX_CTL_PAD_EIM_CS1,SW_MUX_CTL_PAD_EIM_CS1 Register"
|
|
bitfld.long 0x280 4. " SION ,Software Input On Field" "Regular,Force input path EIM_CS1"
|
|
bitfld.long 0x280 0.--2. " MUX_MODE ,MUX Mode Select Field" "CS[1]:weimv2,GPIO[17]:gpio1,Reserved,Reserved,Reserved,Reserved,TRCTL:tpiu,BT_CFG3[1]:src"
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|
line.long 0x284 "SW_MUX_CTL_PAD_EIM_CS0,SW_MUX_CTL_PAD_EIM_CS0 Register"
|
|
bitfld.long 0x284 4. " SION ,Software Input On Field" "Regular,Force input path EIM_CS0"
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|
bitfld.long 0x284 0.--2. " MUX_MODE ,MUX Mode Select Field" "CS[0]:weimv2,GPIO[18]:gpio1,Reserved,Reserved,Reserved,Reserved,Reserved,BT_CFG3[2]:src"
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|
line.long 0x288 "SW_MUX_CTL_PAD_EIM_EB0,SW_MUX_CTL_PAD_EIM_EB0 Register"
|
|
bitfld.long 0x288 4. " SION ,Software Input On Field" "Regular,Force input path EIM_EB0"
|
|
bitfld.long 0x288 0.--2. " MUX_MODE ,MUX Mode Select Field" "EB[0]:weimv2,GPIO[19]:gpio1,Reserved,Reserved,Reserved,Reserved,Reserved,BT_CFG3[3]:src"
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|
line.long 0x28C "SW_MUX_CTL_PAD_EIM_EB1,SW_MUX_CTL_PAD_EIM_EB1 Register"
|
|
bitfld.long 0x28C 4. " SION ,Software Input On Field" "Regular,Force input path EIM_EB1"
|
|
bitfld.long 0x28C 0.--2. " MUX_MODE ,MUX Mode Select Field" "EB[1]:weimv2,GPIO[20]:gpio1,Reserved,Reserved,Reserved,Reserved,Reserved,BT_CFG3[4]:src"
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|
line.long 0x290 "SW_MUX_CTL_PAD_EIM_WAIT,SW_MUX_CTL_PAD_EIM_WAIT Register"
|
|
bitfld.long 0x290 4. " SION ,Software Input On Field" "Regular,Force input path EIM_WAIT"
|
|
bitfld.long 0x290 0.--2. " MUX_MODE ,MUX Mode Select Field" "WAIT:weimv2,GPIO[21]:gpio1,DTACK_B:weimv2,Reserved,Reserved,Reserved,Reserved,BT_CFG3[5]:src"
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|
line.long 0x294 "SW_MUX_CTL_PAD_EIM_BCLK,SW_MUX_CTL_PAD_EIM_BCLK Register"
|
|
bitfld.long 0x294 4. " SION ,Software Input On Field" "Regular,Force input path EIM_BCLK"
|
|
bitfld.long 0x294 0.--2. " MUX_MODE ,MUX Mode Select Field" "BCLK:weimv2,GPIO[22]:gpio1,Reserved,Reserved,Reserved,Reserved,Reserved,BT_CFG3[6]:src"
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|
line.long 0x298 "SW_MUX_CTL_PAD_EIM_RDY,SW_MUX_CTL_PAD_EIM_RDY Register"
|
|
bitfld.long 0x298 4. " SION ,Software Input On Field" "Regular,Force input path EIM_RDY"
|
|
bitfld.long 0x298 0.--2. " MUX_MODE ,MUX Mode Select Field" "RDY:weimv2,GPIO[23]:gpio1,Reserved,Reserved,Reserved,Reserved,Reserved,BT_CFG3[7]:src"
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|
line.long 0x29C "SW_MUX_CTL_PAD_EIM_OE,SW_MUX_CTL_PAD_EIM_OE Register"
|
|
bitfld.long 0x29C 4. " SION ,Software Input On Field" "Regular,Force input path EIM_OE"
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|
bitfld.long 0x29C 0.--2. " MUX_MODE ,MUX Mode Select Field" "OE:weimv2,GPIO[24]:gpio1,Reserved,Reserved,Reserved,Reserved,Reserved,INT_BOOT:src"
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|
line.long 0x2A0 "SW_MUX_CTL_PAD_EIM_RW,SW_MUX_CTL_PAD_EIM_RW Register"
|
|
bitfld.long 0x2A0 4. " SION ,Software Input On Field" "Regular,Force input path EIM_RW"
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|
bitfld.long 0x2A0 0.--2. " MUX_MODE ,MUX Mode Select Field" "RW:weimv2,GPIO[25]:gpio1,Reserved,Reserved,Reserved,Reserved,Reserved,SYSTEM_RST:src"
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line.long 0x2A4 "SW_MUX_CTL_PAD_EIM_LBA,SW_MUX_CTL_PAD_EIM_LBA Register"
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|
bitfld.long 0x2A4 4. " SION ,Software Input On Field" "Regular,Force input path EIM_LBA"
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|
bitfld.long 0x2A4 0.--2. " MUX_MODE ,MUX Mode Select Field" "LBA:weimv2,GPIO[26]:gpio1,Reserved,Reserved,Reserved,Reserved,Reserved,TESTER_ACK:src"
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line.long 0x2A8 "SW_MUX_CTL_PAD_EIM_CRE,SW_MUX_CTL_PAD_EIM_CRE Register"
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bitfld.long 0x2A8 4. " SION ,Software Input On Field" "Regular,Force input path EIM_CRE"
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|
bitfld.long 0x2A8 0. " MUX_MODE ,MUX Mode Select Field" "CRE:weimv2,GPIO[27]:gpio1"
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tree.end
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width 32.
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tree "SW_PAD_CTL_PAD Registers"
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group.long 0x2CC++0x3F7
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line.long 0x0 "SW_PAD_CTL_PAD_KEY_COL0,SW_PAD_CTL_PAD_KEY_COL0 Register"
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bitfld.long 0x0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x4 "SW_PAD_CTL_PAD_KEY_ROW0,SW_PAD_CTL_PAD_KEY_ROW0 Register"
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bitfld.long 0x4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x8 "SW_PAD_CTL_PAD_KEY_COL1,SW_PAD_CTL_PAD_KEY_COL1 Register"
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bitfld.long 0x8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0xC "SW_PAD_CTL_PAD_KEY_ROW1,SW_PAD_CTL_PAD_KEY_ROW1 Register"
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bitfld.long 0xC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0xC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0xC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0xC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0xC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x10 "SW_PAD_CTL_PAD_KEY_COL2,SW_PAD_CTL_PAD_KEY_COL2 Register"
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bitfld.long 0x10 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x10 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x10 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x10 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x10 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x14 "SW_PAD_CTL_PAD_KEY_ROW2,SW_PAD_CTL_PAD_KEY_ROW2 Register"
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bitfld.long 0x14 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
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bitfld.long 0x14 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x14 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x14 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x14 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x18 "SW_PAD_CTL_PAD_KEY_COL3,SW_PAD_CTL_PAD_KEY_COL3 Register"
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bitfld.long 0x18 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
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bitfld.long 0x18 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
bitfld.long 0x18 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x18 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x18 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x1C "SW_PAD_CTL_PAD_KEY_ROW3,SW_PAD_CTL_PAD_KEY_ROW3 Register"
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bitfld.long 0x1C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
bitfld.long 0x1C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x1C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x1C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x20 "SW_PAD_CTL_PAD_I2C1_SCL,SW_PAD_CTL_PAD_I2C1_SCL Register"
|
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bitfld.long 0x20 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x20 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
bitfld.long 0x20 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x20 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x20 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x24 "SW_PAD_CTL_PAD_I2C1_SDA,SW_PAD_CTL_PAD_I2C1_SDA Register"
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bitfld.long 0x24 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
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bitfld.long 0x24 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x24 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x24 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0x24 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x28 "SW_PAD_CTL_PAD_I2C2_SCL,SW_PAD_CTL_PAD_I2C2_SCL Register"
|
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bitfld.long 0x28 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x28 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
bitfld.long 0x28 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
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|
bitfld.long 0x28 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x2C "SW_PAD_CTL_PAD_I2C2_SDA,SW_PAD_CTL_PAD_I2C2_SDA Register"
|
|
bitfld.long 0x2C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
|
|
bitfld.long 0x2C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x30 "SW_PAD_CTL_PAD_I2C3_SCL,SW_PAD_CTL_PAD_I2C3_SCL Register"
|
|
bitfld.long 0x30 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x30 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
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bitfld.long 0x30 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x34 "SW_PAD_CTL_PAD_I2C3_SDA,SW_PAD_CTL_PAD_I2C3_SDA Register"
|
|
bitfld.long 0x34 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x34 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x34 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
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line.long 0x38 "SW_PAD_CTL_PAD_PWM1,SW_PAD_CTL_PAD_PWM1 Register"
|
|
bitfld.long 0x38 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x38 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x38 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x3C "SW_PAD_CTL_PAD_PWM2,SW_PAD_CTL_PAD_PWM2 Register"
|
|
bitfld.long 0x3C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x3C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x3C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x3C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x40 "SW_PAD_CTL_PAD_OWIRE,SW_PAD_CTL_PAD_OWIRE Register"
|
|
bitfld.long 0x40 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x40 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x40 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x40 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x44 "SW_PAD_CTL_PAD_EPITO,SW_PAD_CTL_PAD_EPITO Register"
|
|
bitfld.long 0x44 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x44 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x44 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x44 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x48 "SW_PAD_CTL_PAD_WDOG,SW_PAD_CTL_PAD_WDOG Register"
|
|
bitfld.long 0x48 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x48 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x48 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x48 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x48 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x4C "SW_PAD_CTL_PAD_SSI_TXFS,SW_PAD_CTL_PAD_SSI_TXFS Register"
|
|
bitfld.long 0x4C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x4C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x4C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x50 "SW_PAD_CTL_PAD_SSI_TXC,SW_PAD_CTL_PAD_SSI_TXC Register"
|
|
bitfld.long 0x50 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x50 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x50 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x50 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x50 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x54 "SW_PAD_CTL_PAD_SSI_TXD,SW_PAD_CTL_PAD_SSI_TXD Register"
|
|
bitfld.long 0x54 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x54 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x54 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x54 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x54 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x58 "SW_PAD_CTL_PAD_SSI_RXD,SW_PAD_CTL_PAD_SSI_RXD Register"
|
|
bitfld.long 0x58 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x58 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x58 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x58 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x58 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x5C "SW_PAD_CTL_PAD_SSI_RXFS,SW_PAD_CTL_PAD_SSI_RXFS Register"
|
|
bitfld.long 0x5C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x5C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x5C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x5C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x5C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x60 "SW_PAD_CTL_PAD_SSI_RXC,SW_PAD_CTL_PAD_SSI_RXC Register"
|
|
bitfld.long 0x60 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x60 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x60 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x60 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x60 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x64 "SW_PAD_CTL_PAD_UART1_TXD,SW_PAD_CTL_PAD_UART1_TXD Register"
|
|
bitfld.long 0x64 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x64 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x64 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x64 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x64 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x68 "SW_PAD_CTL_PAD_UART1_RXD,SW_PAD_CTL_PAD_UART1_RXD Register"
|
|
bitfld.long 0x68 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x68 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x68 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x68 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x68 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x6C "SW_PAD_CTL_PAD_UART1_CTS,SW_PAD_CTL_PAD_UART1_CTS Register"
|
|
bitfld.long 0x6C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x6C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x6C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x6C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x6C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x70 "SW_PAD_CTL_PAD_UART1_RTS,SW_PAD_CTL_PAD_UART1_RTS Register"
|
|
bitfld.long 0x70 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x70 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x70 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x70 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x70 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x74 "SW_PAD_CTL_PAD_UART2_TXD,SW_PAD_CTL_PAD_UART1_TXD Register"
|
|
bitfld.long 0x74 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x74 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x74 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x74 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x74 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x78 "SW_PAD_CTL_PAD_UART2_RXD,SW_PAD_CTL_PAD_UART1_RXD Register"
|
|
bitfld.long 0x78 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x78 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x78 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x78 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x78 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x7C "SW_PAD_CTL_PAD_UART2_CTS,SW_PAD_CTL_PAD_UART1_CTS Register"
|
|
bitfld.long 0x7C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x7C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x7C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x7C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x7C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x80 "SW_PAD_CTL_PAD_UART2_RTS,SW_PAD_CTL_PAD_UART1_RTS Register"
|
|
bitfld.long 0x80 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x80 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x80 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x80 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x80 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x84 "SW_PAD_CTL_PAD_UART3_TXD,SW_PAD_CTL_PAD_UART3_TXD Register"
|
|
bitfld.long 0x84 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x84 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x84 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x84 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x84 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x88 "SW_PAD_CTL_PAD_UART3_RXD,SW_PAD_CTL_PAD_UART3_RXD Register"
|
|
bitfld.long 0x88 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x88 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x88 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x88 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x88 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x8C "SW_PAD_CTL_PAD_UART4_TXD,SW_PAD_CTL_PAD_UART4_TXD Register"
|
|
bitfld.long 0x8C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x8C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x8C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x90 "SW_PAD_CTL_PAD_UART4_RXD,SW_PAD_CTL_PAD_UART4_RXD Register"
|
|
bitfld.long 0x90 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x90 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x90 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x90 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x90 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x94 "SW_PAD_CTL_PAD_CSPI_SCLK,SW_PAD_CTL_PAD_CSPI_SCLK Register"
|
|
bitfld.long 0x94 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x94 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x94 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x94 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x94 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x98 "SW_PAD_CTL_PAD_CSPI_MOSI,SW_PAD_CTL_PAD_CSPI_MOSI Register"
|
|
bitfld.long 0x98 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x98 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x98 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x98 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x98 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x9C "SW_PAD_CTL_PAD_CSPI_MISO,SW_PAD_CTL_PAD_CSPI_MISO Register"
|
|
bitfld.long 0x9C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x9C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x9C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x9C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x9C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xA0 "SW_PAD_CTL_PAD_CSPI_SS0,SW_PAD_CTL_PAD_CSPI_SS0 Register"
|
|
bitfld.long 0xA0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xA0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xA0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xA0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xA0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xA4 "SW_PAD_CTL_PAD_ECSPI1_SCLK,SW_PAD_CTL_PAD_ECSPI1_SCLK Register"
|
|
bitfld.long 0xA4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xA4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xA4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xA4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xA4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xA8 "SW_PAD_CTL_PAD_ECSPI1_MOSI,SW_PAD_CTL_PAD_ECSPI1_MOSI Register"
|
|
bitfld.long 0xA8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xA8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xA8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xA8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xA8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xAC "SW_PAD_CTL_PAD_ECSPI1_MISO,SW_PAD_CTL_PAD_ECSPI1_MISO Register"
|
|
bitfld.long 0xAC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xAC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xAC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xAC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xAC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xB0 "SW_PAD_CTL_PAD_ECSPI1_SS0,SW_PAD_CTL_PAD_ECSPI1_SS0 Register"
|
|
bitfld.long 0xB0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xB0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xB0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xB0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xB0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xB4 "SW_PAD_CTL_PAD_ECSPI2_SCLK,SW_PAD_CTL_PAD_ECSPI2_SCLK Register"
|
|
bitfld.long 0xB4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xB4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xB4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xB4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xB4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xB8 "SW_PAD_CTL_PAD_ECSPI2_MOSI,SW_PAD_CTL_PAD_ECSPI2_MOSI Register"
|
|
bitfld.long 0xB8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xB8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xB8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xB8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xB8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xBC "SW_PAD_CTL_PAD_ECSPI2_MISO,SW_PAD_CTL_PAD_ECSPI2_MISO Register"
|
|
bitfld.long 0xBC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xBC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xBC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xBC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xBC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xC0 "SW_PAD_CTL_PAD_ECSPI2_SS0,SW_PAD_CTL_PAD_ECSPI2_SS0 Register"
|
|
bitfld.long 0xC0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xC0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xC0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xC4 "SW_PAD_CTL_PAD_SD1_CLK,SW_PAD_CTL_PAD_SD1_CLK Register"
|
|
bitfld.long 0xC4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xC4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xC4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xC8 "SW_PAD_CTL_PAD_SD1_CMD,SW_PAD_CTL_PAD_SD1_CMD Register"
|
|
bitfld.long 0xC8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xC8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xC8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0xC8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xCC "SW_PAD_CTL_PAD_SD1_D0,SW_PAD_CTL_PAD_SD1_D0 Register"
|
|
bitfld.long 0xCC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xCC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xCC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
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|
bitfld.long 0xCC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0xCC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xD0 "SW_PAD_CTL_PAD_SD1_D1,SW_PAD_CTL_PAD_SD1_D1 Register"
|
|
bitfld.long 0xD0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xD0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xD0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
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|
bitfld.long 0xD0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0xD0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xD4 "SW_PAD_CTL_PAD_SD1_D2,SW_PAD_CTL_PAD_SD1_D2 Register"
|
|
bitfld.long 0xD4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xD4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xD4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xD4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0xD4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xD8 "SW_PAD_CTL_PAD_SD1_D3,SW_PAD_CTL_PAD_SD1_D3 Register"
|
|
bitfld.long 0xD8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xD8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xD8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xD8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0xD8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xDC "SW_PAD_CTL_PAD_SD2_CLK,SW_PAD_CTL_PAD_SD1_CLK Register"
|
|
bitfld.long 0xDC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xDC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xDC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xDC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0xDC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xE0 "SW_PAD_CTL_PAD_SD2_CMD,SW_PAD_CTL_PAD_SD1_CMD Register"
|
|
bitfld.long 0xE0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xE0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xE0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xE0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0xE0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xE4 "SW_PAD_CTL_PAD_SD2_D0,SW_PAD_CTL_PAD_SD1_D0 Register"
|
|
bitfld.long 0xE4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xE4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xE4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xE4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xE4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xE8 "SW_PAD_CTL_PAD_SD2_D1,SW_PAD_CTL_PAD_SD1_D1 Register"
|
|
bitfld.long 0xE8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xE8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xE8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xE8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0xE8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xEC "SW_PAD_CTL_PAD_SD2_D2,SW_PAD_CTL_PAD_SD1_D2 Register"
|
|
bitfld.long 0xEC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xEC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xEC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xEC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0xEC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xF0 "SW_PAD_CTL_PAD_SD2_D3,SW_PAD_CTL_PAD_SD1_D3 Register"
|
|
bitfld.long 0xF0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xF0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xF0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xF0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xF0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xF4 "SW_PAD_CTL_PAD_SD2_D4,SW_PAD_CTL_PAD_SD1_D4 Register"
|
|
bitfld.long 0xF4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xF4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xF4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xF4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xF4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xF8 "SW_PAD_CTL_PAD_SD2_D5,SW_PAD_CTL_PAD_SD1_D5 Register"
|
|
bitfld.long 0xF8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xF8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xF8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xF8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xF8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0xFC "SW_PAD_CTL_PAD_SD2_D6,SW_PAD_CTL_PAD_SD1_D6 Register"
|
|
bitfld.long 0xFC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0xFC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0xFC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xFC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0xFC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x100 "SW_PAD_CTL_PAD_SD2_D7,SW_PAD_CTL_PAD_SD1_D7 Register"
|
|
bitfld.long 0x100 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x100 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x100 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x100 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x100 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x104 "SW_PAD_CTL_PAD_SD2_WP,SW_PAD_CTL_PAD_SD1_WP Register"
|
|
bitfld.long 0x104 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x104 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x104 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x104 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x104 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x108 "SW_PAD_CTL_PAD_SD2_CD,SW_PAD_CTL_PAD_SD1_CD Register"
|
|
bitfld.long 0x108 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x108 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x108 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x108 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x108 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x10C "SW_PAD_CTL_PAD_PMIC_ON_REQ,SW_PAD_CTL_PAD_PMIC_ON_REQ Register"
|
|
bitfld.long 0x10C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10C 0. " SRE ,Slew Rate" "Slow,Fast"
|
|
line.long 0x110 "SW_PAD_CTL_PAD_PMIC_STBY_REQ,SW_PAD_CTL_PAD_PMIC_STBY_REQ Register"
|
|
bitfld.long 0x110 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
bitfld.long 0x110 0. " SRE ,Slew Rate" "Slow,Fast"
|
|
line.long 0x114 "SW_PAD_CTL_PAD_POR_B,SW_PAD_CTL_PAD_POR_B Register"
|
|
bitfld.long 0x114 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x114 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
line.long 0x118 "SW_PAD_CTL_PAD_BOOT_MODE1,SW_PAD_CTL_PAD_BOOT_MODE1 Register"
|
|
bitfld.long 0x118 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x118 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
line.long 0x11C "SW_PAD_CTL_PAD_RESET_IN_B,SW_PAD_CTL_PAD_RESET_IN_B Register"
|
|
bitfld.long 0x11C 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
line.long 0x120 "SW_PAD_CTL_PAD_BOOT_MODE0,SW_PAD_CTL_PAD_BOOT_MODE0 Register"
|
|
bitfld.long 0x120 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x120 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
line.long 0x124 "SW_PAD_CTL_PAD_TEST_MODE,SW_PAD_CTL_PAD_TEST_MODE Register"
|
|
bitfld.long 0x124 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x124 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
line.long 0x128 "SW_PAD_CTL_PAD_JTAG_TMS,SW_PAD_CTL_PAD_JTAG_TMS Register"
|
|
bitfld.long 0x128 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x128 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
line.long 0x12C "SW_PAD_CTL_PAD_JTAG_MOD,SW_PAD_CTL_PAD_JTAG_MOD Register"
|
|
bitfld.long 0x12C 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x12C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
line.long 0x130 "SW_PAD_CTL_PAD_JTAG_TRSTB,SW_PAD_CTL_PAD_JTAG_TRSTB Register"
|
|
bitfld.long 0x130 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x130 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
line.long 0x134 "SW_PAD_CTL_PAD_JTAG_TDI,SW_PAD_CTL_PAD_JTAG_TDI Register"
|
|
bitfld.long 0x134 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x134 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
line.long 0x138 "SW_PAD_CTL_PAD_JTAG_TCK,SW_PAD_CTL_PAD_JTAG_TCK Register"
|
|
bitfld.long 0x138 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x138 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
line.long 0x13C "SW_PAD_CTL_PAD_JTAG_TDO,SW_PAD_CTL_PAD_JTAG_TDO Register"
|
|
bitfld.long 0x13C 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
bitfld.long 0x13C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x13C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
bitfld.long 0x13C 0. " SRE ,Slew Rate" "Slow,Fast"
|
|
line.long 0x140 "SW_PAD_CTL_PAD_DISP_D0,SW_PAD_CTL_PAD_DISP_D0 Register"
|
|
bitfld.long 0x140 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x140 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x140 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x140 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x140 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x144 "SW_PAD_CTL_PAD_DISP_D1,SW_PAD_CTL_PAD_DISP_D1 Register"
|
|
bitfld.long 0x144 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x144 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x144 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x144 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x144 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x148 "SW_PAD_CTL_PAD_DISP_D2,SW_PAD_CTL_PAD_DISP_D2 Register"
|
|
bitfld.long 0x148 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x148 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x148 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x148 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x148 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x14C "SW_PAD_CTL_PAD_DISP_D3,SW_PAD_CTL_PAD_DISP_D3 Register"
|
|
bitfld.long 0x14C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x14C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x14C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x150 "SW_PAD_CTL_PAD_DISP_D4,SW_PAD_CTL_PAD_DISP_D4 Register"
|
|
bitfld.long 0x150 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x150 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x150 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x150 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x150 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x154 "SW_PAD_CTL_PAD_DISP_D5,SW_PAD_CTL_PAD_DISP_D5 Register"
|
|
bitfld.long 0x154 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x154 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x154 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x154 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x154 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x158 "SW_PAD_CTL_PAD_DISP_D6,SW_PAD_CTL_PAD_DISP_D6 Register"
|
|
bitfld.long 0x158 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x158 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x158 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x158 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x158 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x15C "SW_PAD_CTL_PAD_DISP_D7,SW_PAD_CTL_PAD_DISP_D7 Register"
|
|
bitfld.long 0x15C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x15C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x15C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x15C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x15C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x160 "SW_PAD_CTL_PAD_DISP_WR,SW_PAD_CTL_PAD_DISP_WR Register"
|
|
bitfld.long 0x160 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x160 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x160 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x160 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x160 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
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line.long 0x164 "SW_PAD_CTL_PAD_DISP_RD,SW_PAD_CTL_PAD_DISP_RD Register"
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bitfld.long 0x164 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x164 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
bitfld.long 0x164 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x164 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0x164 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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|
line.long 0x168 "SW_PAD_CTL_PAD_DISP_RS,SW_PAD_CTL_PAD_DISP_RS Register"
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bitfld.long 0x168 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x168 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
bitfld.long 0x168 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x168 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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|
bitfld.long 0x168 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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|
line.long 0x16C "SW_PAD_CTL_PAD_DISP_CS,SW_PAD_CTL_PAD_DISP_CS Register"
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|
bitfld.long 0x16C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x16C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
bitfld.long 0x16C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x16C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x16C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x170 "SW_PAD_CTL_PAD_DISP_BUSY,SW_PAD_CTL_PAD_DISP_BUSY Register"
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bitfld.long 0x170 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x170 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
bitfld.long 0x170 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x170 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x170 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x174 "SW_PAD_CTL_PAD_DISP_RESET,SW_PAD_CTL_PAD_DISP_RESET Register"
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bitfld.long 0x174 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x174 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x174 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x174 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x174 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x178 "SW_PAD_CTL_PAD_SD3_CMD,SW_PAD_CTL_PAD_SD1_CMD Register"
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bitfld.long 0x178 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x178 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x178 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x178 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x178 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x17C "SW_PAD_CTL_PAD_SD3_CLK,SW_PAD_CTL_PAD_SD1_CLK Register"
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bitfld.long 0x17C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x17C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x17C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x17C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x17C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x180 "SW_PAD_CTL_PAD_SD3_D0,SW_PAD_CTL_PAD_SD1_D0 Register"
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bitfld.long 0x180 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x180 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x180 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x180 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x180 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x184 "SW_PAD_CTL_PAD_SD3_D1,SW_PAD_CTL_PAD_SD1_D1 Register"
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bitfld.long 0x184 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x184 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x184 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x184 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x184 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x188 "SW_PAD_CTL_PAD_SD3_D2,SW_PAD_CTL_PAD_SD1_D2 Register"
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bitfld.long 0x188 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x188 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x188 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x188 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x188 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x18C "SW_PAD_CTL_PAD_SD3_D3,SW_PAD_CTL_PAD_SD1_D3 Register"
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bitfld.long 0x18C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x18C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
bitfld.long 0x18C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x18C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x18C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x190 "SW_PAD_CTL_PAD_SD3_D4,SW_PAD_CTL_PAD_SD1_D4 Register"
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bitfld.long 0x190 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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|
bitfld.long 0x190 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
bitfld.long 0x190 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x190 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x190 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x194 "SW_PAD_CTL_PAD_SD3_D5,SW_PAD_CTL_PAD_SD1_D5 Register"
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bitfld.long 0x194 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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|
bitfld.long 0x194 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x194 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x194 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x194 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x198 "SW_PAD_CTL_PAD_SD3_D6,SW_PAD_CTL_PAD_SD1_D6 Register"
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bitfld.long 0x198 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x198 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x198 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x198 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x198 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x19C "SW_PAD_CTL_PAD_SD3_D7,SW_PAD_CTL_PAD_SD1_D7 Register"
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bitfld.long 0x19C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x19C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x19C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x19C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x19C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x1A0 "SW_PAD_CTL_PAD_SD3_WP,SW_PAD_CTL_PAD_SD1_WP Register"
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bitfld.long 0x1A0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x1A0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x1A0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x1A0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x1A0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x1A4 "SW_PAD_CTL_PAD_DISP_D8,SW_PAD_CTL_PAD_DISP_D8 Register"
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bitfld.long 0x1A4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x1A4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x1A4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x1A4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x1A4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x1A8 "SW_PAD_CTL_PAD_DISP_D9,SW_PAD_CTL_PAD_DISP_D9 Register"
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bitfld.long 0x1A8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x1A8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x1A8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x1A8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x1A8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x1AC "SW_PAD_CTL_PAD_DISP_D10,SW_PAD_CTL_PAD_DISP_D10 Register"
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bitfld.long 0x1AC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x1AC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x1AC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x1AC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x1AC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x1B0 "SW_PAD_CTL_PAD_DISP_D11,SW_PAD_CTL_PAD_DISP_D11 Register"
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bitfld.long 0x1B0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x1B0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x1B0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x1B0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x1B0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x1B4 "SW_PAD_CTL_PAD_DISP_D12,SW_PAD_CTL_PAD_DISP_D12 Register"
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bitfld.long 0x1B4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x1B4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x1B4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
|
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bitfld.long 0x1B4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x1B4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x1B8 "SW_PAD_CTL_PAD_DISP_D13,SW_PAD_CTL_PAD_DISP_D13 Register"
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bitfld.long 0x1B8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x1B8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x1B8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
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bitfld.long 0x1B8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x1B8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x1BC "SW_PAD_CTL_PAD_DISP_D14,SW_PAD_CTL_PAD_DISP_D14 Register"
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bitfld.long 0x1BC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x1BC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x1BC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
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bitfld.long 0x1BC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x1BC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x1C0 "SW_PAD_CTL_PAD_DISP_D15,SW_PAD_CTL_PAD_DISP_D15 Register"
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bitfld.long 0x1C0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x1C0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x1C0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
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bitfld.long 0x1C0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x1C0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x1C4 "SW_PAD_CTL_PAD_DRAM_OPEN,SW_PAD_CTL_PAD_DRAM_OPEN Register"
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bitfld.long 0x1C4 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
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line.long 0x1C8 "SW_PAD_CTL_PAD_DRAM_OPENFB,SW_PAD_CTL_PAD_DRAM_OPEN Register"
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bitfld.long 0x1C8 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
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line.long 0x1CC "SW_PAD_CTL_PAD_DRAM_SDCLK_1,SW_PAD_CTL_PAD_DRAM_SDCLK_1 Register"
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bitfld.long 0x1CC 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
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bitfld.long 0x1CC 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
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line.long 0x1D0 "SW_PAD_CTL_PAD_DRAM_SDCLK_0,SW_PAD_CTL_PAD_DRAM_SDCLK_0 Register"
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bitfld.long 0x1D0 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
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bitfld.long 0x1D0 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
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line.long 0x1D4 "SW_PAD_CTL_PAD_DRAM_SDCKE,SW_PAD_CTL_PAD_DRAM_SDCKE Register"
|
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bitfld.long 0x1D4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1D4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
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line.long 0x1D8 "SW_PAD_CTL_PAD_DRAM_SDODT0,SW_PAD_CTL_PAD_DRAM_SDODT0 Register"
|
|
bitfld.long 0x1D8 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
bitfld.long 0x1D8 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
|
|
textline " "
|
|
bitfld.long 0x1D8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1D8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
line.long 0x1DC "SW_PAD_CTL_PAD_DRAM_D16,SW_PAD_CTL_PAD_DRAM_D16 Register"
|
|
bitfld.long 0x1DC 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x1E0 "SW_PAD_CTL_PAD_DRAM_D17,SW_PAD_CTL_PAD_DRAM_D17 Register"
|
|
bitfld.long 0x1E0 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x1E4 "SW_PAD_CTL_PAD_DRAM_D18,SW_PAD_CTL_PAD_DRAM_D18 Register"
|
|
bitfld.long 0x1E4 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x1E8 "SW_PAD_CTL_PAD_DRAM_D19,SW_PAD_CTL_PAD_DRAM_D19 Register"
|
|
bitfld.long 0x1E8 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x1EC "SW_PAD_CTL_PAD_DRAM_D20,SW_PAD_CTL_PAD_DRAM_D20 Register"
|
|
bitfld.long 0x1EC 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x1F0 "SW_PAD_CTL_PAD_DRAM_D21,SW_PAD_CTL_PAD_DRAM_D21 Register"
|
|
bitfld.long 0x1F0 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x1F4 "SW_PAD_CTL_PAD_DRAM_D22,SW_PAD_CTL_PAD_DRAM_D22 Register"
|
|
bitfld.long 0x1F4 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x1F8 "SW_PAD_CTL_PAD_DRAM_D23,SW_PAD_CTL_PAD_DRAM_D23 Register"
|
|
bitfld.long 0x1F8 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x1FC "SW_PAD_CTL_PAD_DRAM_DQM2,SW_PAD_CTL_PAD_DRAM_DQM2 Register"
|
|
bitfld.long 0x1FC 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
bitfld.long 0x1FC 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
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|
line.long 0x200 "SW_PAD_CTL_PAD_DRAM_SDQS2,SW_PAD_CTL_PAD_DRAM_SDQS2 Register"
|
|
bitfld.long 0x200 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
|
|
textline " "
|
|
bitfld.long 0x200 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x200 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
line.long 0x204 "SW_PAD_CTL_PAD_DRAM_D0,SW_PAD_CTL_PAD_DRAM_D0 Register"
|
|
bitfld.long 0x204 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x208 "SW_PAD_CTL_PAD_DRAM_D1,SW_PAD_CTL_PAD_DRAM_D1 Register"
|
|
bitfld.long 0x208 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x20C "SW_PAD_CTL_PAD_DRAM_D2,SW_PAD_CTL_PAD_DRAM_D2 Register"
|
|
bitfld.long 0x20C 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x210 "SW_PAD_CTL_PAD_DRAM_D3,SW_PAD_CTL_PAD_DRAM_D3 Register"
|
|
bitfld.long 0x210 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x214 "SW_PAD_CTL_PAD_DRAM_D4,SW_PAD_CTL_PAD_DRAM_D4 Register"
|
|
bitfld.long 0x214 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x218 "SW_PAD_CTL_PAD_DRAM_D5,SW_PAD_CTL_PAD_DRAM_D5 Register"
|
|
bitfld.long 0x218 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x21C "SW_PAD_CTL_PAD_DRAM_D6,SW_PAD_CTL_PAD_DRAM_D6 Register"
|
|
bitfld.long 0x21C 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x220 "SW_PAD_CTL_PAD_DRAM_D7,SW_PAD_CTL_PAD_DRAM_D7 Register"
|
|
bitfld.long 0x220 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x224 "SW_PAD_CTL_PAD_DRAM_DQM0,SW_PAD_CTL_PAD_DRAM_DQM0 Register"
|
|
bitfld.long 0x224 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
bitfld.long 0x224 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
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|
line.long 0x228 "SW_PAD_CTL_PAD_DRAM_SDQS0,SW_PAD_CTL_PAD_DRAM_SDQS0 Register"
|
|
bitfld.long 0x228 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
|
|
textline " "
|
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bitfld.long 0x228 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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|
bitfld.long 0x228 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
line.long 0x22C "SW_PAD_CTL_PAD_DRAM_SDODT1,SW_PAD_CTL_PAD_DRAM_SDODT1 Register"
|
|
bitfld.long 0x22C 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
bitfld.long 0x22C 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
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|
textline " "
|
|
bitfld.long 0x22C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x22C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
line.long 0x230 "SW_PAD_CTL_PAD_DRAM_SDQS1,SW_PAD_CTL_PAD_DRAM_SDQS1 Register"
|
|
bitfld.long 0x230 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
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|
textline " "
|
|
bitfld.long 0x230 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x230 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
line.long 0x234 "SW_PAD_CTL_PAD_DRAM_DQM1,SW_PAD_CTL_PAD_DRAM_DQM1 Register"
|
|
bitfld.long 0x234 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
bitfld.long 0x234 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
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|
line.long 0x238 "SW_PAD_CTL_PAD_DRAM_D8,SW_PAD_CTL_PAD_DRAM_D8 Register"
|
|
bitfld.long 0x238 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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|
line.long 0x23C "SW_PAD_CTL_PAD_DRAM_D9,SW_PAD_CTL_PAD_DRAM_D9 Register"
|
|
bitfld.long 0x23C 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x240 "SW_PAD_CTL_PAD_DRAM_D10,SW_PAD_CTL_PAD_DRAM_D10 Register"
|
|
bitfld.long 0x240 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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|
line.long 0x244 "SW_PAD_CTL_PAD_DRAM_D11,SW_PAD_CTL_PAD_DRAM_D11 Register"
|
|
bitfld.long 0x244 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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|
line.long 0x248 "SW_PAD_CTL_PAD_DRAM_D12,SW_PAD_CTL_PAD_DRAM_D12 Register"
|
|
bitfld.long 0x248 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
|
|
line.long 0x24C "SW_PAD_CTL_PAD_DRAM_D13,SW_PAD_CTL_PAD_DRAM_D13 Register"
|
|
bitfld.long 0x24C 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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|
line.long 0x250 "SW_PAD_CTL_PAD_DRAM_D14,SW_PAD_CTL_PAD_DRAM_D14 Register"
|
|
bitfld.long 0x250 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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|
line.long 0x254 "SW_PAD_CTL_PAD_DRAM_D15,SW_PAD_CTL_PAD_DRAM_D15 Register"
|
|
bitfld.long 0x254 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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|
line.long 0x258 "SW_PAD_CTL_PAD_DRAM_SDQS3,SW_PAD_CTL_PAD_DRAM_SDQS3 Register"
|
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bitfld.long 0x258 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
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|
textline " "
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|
bitfld.long 0x258 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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|
bitfld.long 0x258 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
line.long 0x25C "SW_PAD_CTL_PAD_DRAM_DQM3,SW_PAD_CTL_PAD_DRAM_DQM3 Register"
|
|
bitfld.long 0x25C 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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|
bitfld.long 0x25C 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
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line.long 0x260 "SW_PAD_CTL_PAD_DRAM_D24,SW_PAD_CTL_PAD_DRAM_D24 Register"
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bitfld.long 0x260 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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line.long 0x264 "SW_PAD_CTL_PAD_DRAM_D25,SW_PAD_CTL_PAD_DRAM_D25 Register"
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|
bitfld.long 0x264 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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line.long 0x268 "SW_PAD_CTL_PAD_DRAM_D26,SW_PAD_CTL_PAD_DRAM_D26 Register"
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|
bitfld.long 0x268 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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|
line.long 0x26C "SW_PAD_CTL_PAD_DRAM_D27,SW_PAD_CTL_PAD_DRAM_D27 Register"
|
|
bitfld.long 0x26C 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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|
line.long 0x270 "SW_PAD_CTL_PAD_DRAM_D28,SW_PAD_CTL_PAD_DRAM_D28 Register"
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|
bitfld.long 0x270 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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line.long 0x274 "SW_PAD_CTL_PAD_DRAM_D29,SW_PAD_CTL_PAD_DRAM_D29 Register"
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bitfld.long 0x274 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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line.long 0x278 "SW_PAD_CTL_PAD_DRAM_D30,SW_PAD_CTL_PAD_DRAM_D30 Register"
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bitfld.long 0x278 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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line.long 0x27C "SW_PAD_CTL_PAD_DRAM_D31,SW_PAD_CTL_PAD_DRAM_D31 Register"
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bitfld.long 0x27C 27.--28. " DO_TRIM ,DO_TRIM field" "min,+50 ps,+100 ps,+150 ps"
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line.long 0x280 "SW_PAD_CTL_PAD_EPDC_D0,SW_PAD_CTL_PAD_EPDC_D0 Register"
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bitfld.long 0x280 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x280 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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|
bitfld.long 0x280 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x280 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x280 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x284 "SW_PAD_CTL_PAD_EPDC_D1,SW_PAD_CTL_PAD_EPDC_D1 Register"
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bitfld.long 0x284 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x284 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x284 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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textline " "
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bitfld.long 0x284 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x284 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x288 "SW_PAD_CTL_PAD_EPDC_D2,SW_PAD_CTL_PAD_EPDC_D2 Register"
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bitfld.long 0x288 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x288 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
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bitfld.long 0x288 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x288 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x288 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x28C "SW_PAD_CTL_PAD_EPDC_D3,SW_PAD_CTL_PAD_EPDC_D3 Register"
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bitfld.long 0x28C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x28C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
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bitfld.long 0x28C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
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bitfld.long 0x28C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
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bitfld.long 0x28C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x290 "SW_PAD_CTL_PAD_EPDC_D4,SW_PAD_CTL_PAD_EPDC_D4 Register"
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bitfld.long 0x290 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
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bitfld.long 0x290 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x290 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
|
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bitfld.long 0x290 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x290 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
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line.long 0x294 "SW_PAD_CTL_PAD_EPDC_D5,SW_PAD_CTL_PAD_EPDC_D5 Register"
|
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bitfld.long 0x294 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x294 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x294 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
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|
textline " "
|
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bitfld.long 0x294 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x294 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
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line.long 0x298 "SW_PAD_CTL_PAD_EPDC_D6,SW_PAD_CTL_PAD_EPDC_D6 Register"
|
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bitfld.long 0x298 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x298 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x298 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
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bitfld.long 0x298 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x298 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x29C "SW_PAD_CTL_PAD_EPDC_D7,SW_PAD_CTL_PAD_EPDC_D7 Register"
|
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bitfld.long 0x29C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x29C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x29C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x29C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x29C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
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line.long 0x2A0 "SW_PAD_CTL_PAD_EPDC_D8,SW_PAD_CTL_PAD_EPDC_D8 Register"
|
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bitfld.long 0x2A0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2A0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2A0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2A0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2A0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2A4 "SW_PAD_CTL_PAD_EPDC_D9,SW_PAD_CTL_PAD_EPDC_D9 Register"
|
|
bitfld.long 0x2A4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2A4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2A4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2A4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2A4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2A8 "SW_PAD_CTL_PAD_EPDC_D10,SW_PAD_CTL_PAD_EPDC_D10 Register"
|
|
bitfld.long 0x2A8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2A8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2A8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2A8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2A8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2AC "SW_PAD_CTL_PAD_EPDC_D11,SW_PAD_CTL_PAD_EPDC_D11 Register"
|
|
bitfld.long 0x2AC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2AC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2AC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2AC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2AC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2B0 "SW_PAD_CTL_PAD_EPDC_D12,SW_PAD_CTL_PAD_EPDC_D12 Register"
|
|
bitfld.long 0x2B0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2B0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2B0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2B0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2B0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2B4 "SW_PAD_CTL_PAD_EPDC_D13,SW_PAD_CTL_PAD_EPDC_D13 Register"
|
|
bitfld.long 0x2B4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2B4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2B4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2B4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2B4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2B8 "SW_PAD_CTL_PAD_EPDC_D14,SW_PAD_CTL_PAD_EPDC_D14 Register"
|
|
bitfld.long 0x2B8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2B8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2B8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2B8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2B8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2BC "SW_PAD_CTL_PAD_EPDC_D15,SW_PAD_CTL_PAD_EPDC_D15 Register"
|
|
bitfld.long 0x2BC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2BC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2BC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2BC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2BC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2C0 "SW_PAD_CTL_PAD_EPDC_GDCLK,SW_PAD_CTL_PAD_EPDC_GDCLK Register"
|
|
bitfld.long 0x2C0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2C0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2C0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2C4 "SW_PAD_CTL_PAD_EPDC_GDSP,SW_PAD_CTL_PAD_EPDC_GDSP Register"
|
|
bitfld.long 0x2C4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2C4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2C4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2C8 "SW_PAD_CTL_PAD_EPDC_GDOE,SW_PAD_CTL_PAD_EPDC_GDOE Register"
|
|
bitfld.long 0x2C8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2C8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2C8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2CC "SW_PAD_CTL_PAD_EPDC_GDRL,SW_PAD_CTL_PAD_EPDC_GDRL Register"
|
|
bitfld.long 0x2CC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2CC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2CC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2CC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2CC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2D0 "SW_PAD_CTL_PAD_EPDC_SDCLK,SW_PAD_CTL_PAD_EPDC_SDCLK Register"
|
|
bitfld.long 0x2D0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2D0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2D0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2D0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2D0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2D4 "SW_PAD_CTL_PAD_EPDC_SDOEZ,SW_PAD_CTL_PAD_EPDC_SDOEZ Register"
|
|
bitfld.long 0x2D4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2D4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2D4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2D4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2D4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2D8 "SW_PAD_CTL_PAD_EPDC_SDOED,SW_PAD_CTL_PAD_EPDC_SDOED Register"
|
|
bitfld.long 0x2D8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2D8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2D8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2D8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2D8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2DC "SW_PAD_CTL_PAD_EPDC_SDOE,SW_PAD_CTL_PAD_EPDC_SDOE Register"
|
|
bitfld.long 0x2DC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2DC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2DC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2DC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2DC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2E0 "SW_PAD_CTL_PAD_EPDC_SDLE,SW_PAD_CTL_PAD_EPDC_SDLE Register"
|
|
bitfld.long 0x2E0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2E0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2E0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2E0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2E0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2E4 "SW_PAD_CTL_PAD_EPDC_SDCLKN,SW_PAD_CTL_PAD_EPDC_SDCLKN Register"
|
|
bitfld.long 0x2E4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2E4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2E4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2E4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2E4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2E8 "SW_PAD_CTL_PAD_EPDC_SDSHR,SW_PAD_CTL_PAD_EPDC_SDSHR Register"
|
|
bitfld.long 0x2E8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2E8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2E8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2E8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2E8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2EC "SW_PAD_CTL_PAD_EPDC_PWRCOM,SW_PAD_CTL_PAD_EPDC_PWRCOM Register"
|
|
bitfld.long 0x2EC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2EC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2EC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2EC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2EC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2F0 "SW_PAD_CTL_PAD_EPDC_PWRSTAT,SW_PAD_CTL_PAD_EPDC_PWRSTAT Register"
|
|
bitfld.long 0x2F0 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2F0 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2F0 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2F0 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2F0 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2F4 "SW_PAD_CTL_PAD_EPDC_PWRCTRL0,SW_PAD_CTL_PAD_EPDC_PWRCTRL0 Register"
|
|
bitfld.long 0x2F4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2F4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2F4 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2F4 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2F4 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2F8 "SW_PAD_CTL_PAD_EPDC_PWRCTRL1,SW_PAD_CTL_PAD_EPDC_PWRCTRL1 Register"
|
|
bitfld.long 0x2F8 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2F8 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2F8 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2F8 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2F8 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x2FC "SW_PAD_CTL_PAD_EPDC_PWRCTRL2,SW_PAD_CTL_PAD_EPDC_PWRCTRL2 Register"
|
|
bitfld.long 0x2FC 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2FC 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x2FC 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2FC 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2FC 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x300 "SW_PAD_CTL_PAD_EPDC_PWRCTRL3,SW_PAD_CTL_PAD_EPDC_PWRCTRL3 Register"
|
|
bitfld.long 0x300 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x300 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x300 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x300 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x300 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x304 "SW_PAD_CTL_PAD_EPDC_VCOM0,SW_PAD_CTL_PAD_EPDC_VCOM0 Register"
|
|
bitfld.long 0x304 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x304 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x304 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x304 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x304 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x308 "SW_PAD_CTL_PAD_EPDC_VCOM1,SW_PAD_CTL_PAD_EPDC_VCOM1 Register"
|
|
bitfld.long 0x308 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x308 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x308 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x308 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x308 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x30C "SW_PAD_CTL_PAD_EPDC_BDR0,SW_PAD_CTL_PAD_EPDC_BDR0 Register"
|
|
bitfld.long 0x30C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x30C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x30C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x30C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x30C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x310 "SW_PAD_CTL_PAD_EPDC_BDR1,SW_PAD_CTL_PAD_EPDC_BDR1 Register"
|
|
bitfld.long 0x310 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x310 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x310 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x310 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x310 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x314 "SW_PAD_CTL_PAD_EPDC_SDCE0,SW_PAD_CTL_PAD_EPDC_SDCE0 Register"
|
|
bitfld.long 0x314 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x314 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x314 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x314 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x314 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x318 "SW_PAD_CTL_PAD_EPDC_SDCE1,SW_PAD_CTL_PAD_EPDC_SDCE1 Register"
|
|
bitfld.long 0x318 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x318 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x318 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x318 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x318 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x31C "SW_PAD_CTL_PAD_EPDC_SDCE2,SW_PAD_CTL_PAD_EPDC_SDCE2 Register"
|
|
bitfld.long 0x31C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x31C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x31C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x31C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x31C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x320 "SW_PAD_CTL_PAD_EPDC_SDCE3,SW_PAD_CTL_PAD_EPDC_SDCE3 Register"
|
|
bitfld.long 0x320 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x320 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x320 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x320 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x320 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x324 "SW_PAD_CTL_PAD_EPDC_SDCE4,SW_PAD_CTL_PAD_EPDC_SDCE4 Register"
|
|
bitfld.long 0x324 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x324 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x324 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x324 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x324 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x328 "SW_PAD_CTL_PAD_EPDC_SDCE5,SW_PAD_CTL_PAD_EPDC_SDCE5 Register"
|
|
bitfld.long 0x328 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x328 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x328 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x328 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x328 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x32C "SW_PAD_CTL_PAD_EIM_DA0,SW_PAD_CTL_PAD_EIM_DA0 Register"
|
|
bitfld.long 0x32C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x32C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x32C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x32C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x32C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x330 "SW_PAD_CTL_PAD_EIM_DA1,SW_PAD_CTL_PAD_EIM_DA1 Register"
|
|
bitfld.long 0x330 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x330 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x330 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x330 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x330 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x334 "SW_PAD_CTL_PAD_EIM_DA2,SW_PAD_CTL_PAD_EIM_DA2 Register"
|
|
bitfld.long 0x334 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x334 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x334 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x334 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x334 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x338 "SW_PAD_CTL_PAD_EIM_DA3,SW_PAD_CTL_PAD_EIM_DA3 Register"
|
|
bitfld.long 0x338 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x338 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x338 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x338 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x338 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x33C "SW_PAD_CTL_PAD_EIM_DA4,SW_PAD_CTL_PAD_EIM_DA4 Register"
|
|
bitfld.long 0x33C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x33C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x33C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x33C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x33C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x340 "SW_PAD_CTL_PAD_EIM_DA5,SW_PAD_CTL_PAD_EIM_DA5 Register"
|
|
bitfld.long 0x340 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x340 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x340 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x340 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x340 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x344 "SW_PAD_CTL_PAD_EIM_DA6,SW_PAD_CTL_PAD_EIM_DA6 Register"
|
|
bitfld.long 0x344 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x344 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x344 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x344 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x344 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x348 "SW_PAD_CTL_PAD_EIM_DA7,SW_PAD_CTL_PAD_EIM_DA7 Register"
|
|
bitfld.long 0x348 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x348 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x348 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x348 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x348 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x34C "SW_PAD_CTL_PAD_EIM_DA8,SW_PAD_CTL_PAD_EIM_DA8 Register"
|
|
bitfld.long 0x34C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x34C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x34C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x34C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x34C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x350 "SW_PAD_CTL_PAD_EIM_DA9,SW_PAD_CTL_PAD_EIM_DA9 Register"
|
|
bitfld.long 0x350 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x350 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x350 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x350 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x350 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x354 "SW_PAD_CTL_PAD_EIM_DA10,SW_PAD_CTL_PAD_EIM_DA10 Register"
|
|
bitfld.long 0x354 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x354 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x354 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x354 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x354 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x358 "SW_PAD_CTL_PAD_EIM_DA11,SW_PAD_CTL_PAD_EIM_DA11 Register"
|
|
bitfld.long 0x358 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x358 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x358 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x358 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x358 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x35C "SW_PAD_CTL_PAD_EIM_DA12,SW_PAD_CTL_PAD_EIM_DA12 Register"
|
|
bitfld.long 0x35C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x35C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x35C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x35C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x35C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x360 "SW_PAD_CTL_PAD_EIM_DA13,SW_PAD_CTL_PAD_EIM_DA13 Register"
|
|
bitfld.long 0x360 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x360 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x360 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x360 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x360 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x364 "SW_PAD_CTL_PAD_EIM_DA14,SW_PAD_CTL_PAD_EIM_DA14 Register"
|
|
bitfld.long 0x364 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x364 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x364 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x364 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x364 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x368 "SW_PAD_CTL_PAD_EIM_DA15,SW_PAD_CTL_PAD_EIM_DA15 Register"
|
|
bitfld.long 0x368 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x368 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x368 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x368 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x368 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x36C "SW_PAD_CTL_PAD_EIM_CS2,SW_PAD_CTL_PAD_EIM_CS2 Register"
|
|
bitfld.long 0x36C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x36C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x36C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x36C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x36C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x370 "SW_PAD_CTL_PAD_EIM_CS1,SW_PAD_CTL_PAD_EIM_CS1 Register"
|
|
bitfld.long 0x370 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x370 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x370 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x370 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x370 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x374 "SW_PAD_CTL_PAD_EIM_CS0,SW_PAD_CTL_PAD_EIM_CS0 Register"
|
|
bitfld.long 0x374 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x374 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x374 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x374 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x374 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x378 "SW_PAD_CTL_PAD_EIM_EB0,SW_PAD_CTL_PAD_EIM_EB0 Register"
|
|
bitfld.long 0x378 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x378 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x378 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x378 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x378 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x37C "SW_PAD_CTL_PAD_EIM_EB1,SW_PAD_CTL_PAD_EIM_EB1 Register"
|
|
bitfld.long 0x37C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x37C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x37C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x37C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x37C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x380 "SW_PAD_CTL_PAD_EIM_WAIT,SW_PAD_CTL_PAD_EIM_WAIT Register"
|
|
bitfld.long 0x380 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x380 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x380 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x380 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x380 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x384 "SW_PAD_CTL_PAD_EIM_BCLK,SW_PAD_CTL_PAD_EIM_BCLK Register"
|
|
bitfld.long 0x384 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x384 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x384 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x384 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x384 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x388 "SW_PAD_CTL_PAD_EIM_RDY,SW_PAD_CTL_PAD_EIM_RDY Register"
|
|
bitfld.long 0x388 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x388 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x388 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x388 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x388 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x38C "SW_PAD_CTL_PAD_EIM_OE,SW_PAD_CTL_PAD_EIM_OE Register"
|
|
bitfld.long 0x38C 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x38C 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x38C 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x38C 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x38C 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x390 "SW_PAD_CTL_PAD_EIM_RW,SW_PAD_CTL_PAD_EIM_RW Register"
|
|
bitfld.long 0x390 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x390 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x390 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x390 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x390 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x394 "SW_PAD_CTL_PAD_EIM_LBA,SW_PAD_CTL_PAD_EIM_LBA Register"
|
|
bitfld.long 0x394 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x394 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x394 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x394 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x394 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x398 "SW_PAD_CTL_PAD_EIM_CRE,SW_PAD_CTL_PAD_EIM_CRE Register"
|
|
bitfld.long 0x398 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x398 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
bitfld.long 0x398 4.--5. " PUS ,Pull Up/Pull Down Configuration" "100 kOhm Pull Down,47 kOhm Pull Up,100 kOhm Pull Up,22 kOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x398 3. " ODE ,Open Drain Enable" "Disabled,Enabled"
|
|
bitfld.long 0x398 1.--2. " DSE ,Drive Strength" "Low,Medium,High,Max"
|
|
line.long 0x39C "SW_PAD_CTL_GRP_ADDDS,SW_PAD_CTL_GRP_ADDDS Register"
|
|
bitfld.long 0x39C 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
|
|
line.long 0x3A0 "SW_PAD_CTL_GRP_DDRMODE_CTL,SW_PAD_CTL_GRP_DDRMODE_CTL Register"
|
|
bitfld.long 0x3A0 9. " DDR_INPUT ,DDR / CMOS Input Mode" "CMOS,Differential"
|
|
line.long 0x3A4 "SW_PAD_CTL_GRP_DDRPKE,SW_PAD_CTL_GRP_DDRPKE Register"
|
|
bitfld.long 0x3A4 7. " PKE ,Pull/Keep Enable" "Disabled,Enabled"
|
|
line.long 0x3A8 "SW_PAD_CTL_GRP_EIM,SW_PAD_CTL_GRP_EIM Register"
|
|
bitfld.long 0x3A8 13. " HVE ,Low/High Output Voltage" "High (2.7-3.3 V),Low (1.65-1.95 V)"
|
|
line.long 0x3AC "SW_PAD_CTL_GRP_EPDC,SW_PAD_CTL_GRP_EPDC Register"
|
|
bitfld.long 0x3AC 13. " HVE ,Low/High Output Voltage" "High (2.7-3.3 V),Low (1.65-1.95 V)"
|
|
line.long 0x3B0 "SW_PAD_CTL_GRP_UART,SW_PAD_CTL_GRP_UART Register"
|
|
bitfld.long 0x3B0 13. " HVE ,Low/High Output Voltage" "High (2.7-3.3 V),Low (1.65-1.95 V)"
|
|
line.long 0x3B4 "SW_PAD_CTL_GRP_DDRPK,SW_PAD_CTL_GRP_DDRPK Register"
|
|
bitfld.long 0x3B4 6. " PUE ,Pull/Keep Select" "Keeper,Pull"
|
|
line.long 0x3B8 "SW_PAD_CTL_GRP_DDRHYS,SW_PAD_CTL_GRP_DDRHYS Register"
|
|
bitfld.long 0x3B8 8. " HYS ,Hysteresis Enable" "Disabled,Enabled"
|
|
line.long 0x3BC "SW_PAD_CTL_GRP_KEYPAD,SW_PAD_CTL_GRP_KEYPAD Register"
|
|
bitfld.long 0x3BC 13. " HVE ,Low/High Output Voltage" "High (2.7-3.3 V),Low (1.65-1.95 V)"
|
|
line.long 0x3C0 "SW_PAD_CTL_GRP_DDRMODE_CTL,SW_PAD_CTL_GRP_DDRMODE_CTL Register"
|
|
bitfld.long 0x3C0 9. " DDR_INPUT ,DDR / CMOS Input Mode" "CMOS,Differential"
|
|
line.long 0x3C4 "SW_PAD_CTL_GRP_SSI,SW_PAD_CTL_GRP_SSI Register"
|
|
bitfld.long 0x3C4 13. " HVE ,Low/High Output Voltage" "High (2.7-3.3 V),Low (1.65-1.95 V)"
|
|
line.long 0x3C8 "SW_PAD_CTL_GRP_SD1,SW_PAD_CTL_GRP_SD1 Register"
|
|
bitfld.long 0x3C8 13. " HVE ,Low/High Output Voltage" "High (2.7-3.3 V),Low (1.65-1.95 V)"
|
|
line.long 0x3CC "SW_PAD_CTL_GRP_B0DS,SW_PAD_CTL_GRP_B0DS Register"
|
|
bitfld.long 0x3CC 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
|
|
line.long 0x3D0 "SW_PAD_CTL_GRP_SD2,SW_PAD_CTL_GRP_SD2 Register"
|
|
bitfld.long 0x3D0 13. " HVE ,Low/High Output Voltage" "High (2.7-3.3 V),Low (1.65-1.95 V)"
|
|
line.long 0x3D4 "SW_PAD_CTL_GRP_B1DS,SW_PAD_CTL_GRP_B1DS Register"
|
|
bitfld.long 0x3D4 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
|
|
line.long 0x3D8 "SW_PAD_CTL_GRP_CTLDS,SW_PAD_CTL_GRP_CTLDS Register"
|
|
bitfld.long 0x3D8 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
|
|
line.long 0x3DC "SW_PAD_CTL_GRP_B2DS,SW_PAD_CTL_GRP_B2DS Register"
|
|
bitfld.long 0x3DC 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
|
|
line.long 0x3E0 "SW_PAD_CTL_GRP_DDR_TYPE,SW_PAD_CTL_GRP_DDR_TYPE Register"
|
|
bitfld.long 0x3E0 25.--26. " DDR_SEL ,DDR_SEL Field" "LPDDR1/ DDR2 ODT @ 1.8V,DDR2 drive @ 1.8V,LPDDR2 @ 1.2V,?..."
|
|
line.long 0x3E4 "SW_PAD_CTL_GRP_LCD,SW_PAD_CTL_GRP_LCD Register"
|
|
bitfld.long 0x3E4 13. " HVE ,Low/High Output Voltage" "High (2.7-3.3 V),Low (1.65-1.95 V)"
|
|
line.long 0x3E8 "SW_PAD_CTL_GRP_B3DS,SW_PAD_CTL_GRP_B3DS Register"
|
|
bitfld.long 0x3E8 19.--21. " DSE ,Drive Strength (LPDDR2/LPDDR1/DDR2)" "Output Driver Disabled,240 Ohm/-/-,120 Ohm/-/-,80 Ohm/-/-,60 Ohm/75 Ohm/45 Ohm,48 Ohm/-/-,40 Ohm/50 Ohm/-,34 Ohm/-/-"
|
|
line.long 0x3EC "SW_PAD_CTL_GRP_MISC,SW_PAD_CTL_GRP_MISC Register"
|
|
bitfld.long 0x3EC 13. " HVE ,Low/High Output Voltage" "High (2.7-3.3 V),Low (1.65-1.95 V)"
|
|
line.long 0x3F0 "SW_PAD_CTL_GRP_SPI,SW_PAD_CTL_GRP_SPI Register"
|
|
bitfld.long 0x3F0 13. " HVE ,Low/High Output Voltage" "High (2.7-3.3 V),Low (1.65-1.95 V)"
|
|
line.long 0x3F4 "SW_PAD_CTL_GRP_NANDF,SW_PAD_CTL_GRP_NANDF Register"
|
|
bitfld.long 0x3F4 13. " HVE ,Low/High Output Voltage" "High (2.7-3.3 V),Low (1.65-1.95 V)"
|
|
tree.end
|
|
width 47.
|
|
tree "SELECT_INPUT Registers"
|
|
group.long 0x6C4++0x167
|
|
line.long 0x00 "AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT,AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x00 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D6: ALT2,EPDC_PWRCTRL0: ALT4"
|
|
line.long 0x04 "AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT,AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT Register"
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bitfld.long 0x04 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_WP: ALT2,EPDC_SDSHR: ALT4"
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line.long 0x08 "AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT Register"
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bitfld.long 0x08 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D5: ALT2,EPDC_PWRCTRL1: ALT4"
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line.long 0x0C "AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT Register"
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bitfld.long 0x0C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D4: ALT2,EPDC_PWRCTRL2: ALT4"
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line.long 0x10 "AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT Register"
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bitfld.long 0x10 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_CD: ALT2,EPDC_PWRCOM: ALT4"
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line.long 0x14 "AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT Register"
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bitfld.long 0x14 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D7: ALT2,EPDC_PWRSTAT: ALT4"
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line.long 0x18 "CCM_PLL1_BYPASS_CLK_SELECT_INPUT,CCM_PLL1_BYPASS_CLK_SELECT_INPUT Register"
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bitfld.long 0x18 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD1_D0: ALT7,SD3_D0: ALT7"
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line.long 0x1C "CCM_PLL2_BYPASS_CLK_SELECT_INPUT,CCM_PLL2_BYPASS_CLK_SELECT_INPUT Register"
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bitfld.long 0x1C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD1_D1: ALT7,SD3_D1: ALT7"
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line.long 0x20 "CCM_PLL3_BYPASS_CLK_SELECT_INPUT,CCM_PLL3_BYPASS_CLK_SELECT_INPUT Register"
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bitfld.long 0x20 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD1_D2: ALT7,SD3_D2: ALT7"
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line.long 0x24 "CSPI_IPP_IND_DATAREADY_B_SELECT_INPUT,CSPI_IPP_IND_DATAREADY_B_SELECT_INPUT Register"
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bitfld.long 0x24 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SSI_TXD: ALT4,ECSPI1_SCLK: ALT2"
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line.long 0x28 "CSPI_IPP_IND_SS1_B_SELECT_INPUT,CSPI_IPP_IND_SS1_B_SELECT_INPUT Register"
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bitfld.long 0x28 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SSI_RXC: ALT4,ECSPI1_MOSI: ALT2"
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line.long 0x2C "CSPI_IPP_IND_SS2_B_SELECT_INPUT,CSPI_IPP_IND_SS2_B_SELECT_INPUT Register"
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bitfld.long 0x2C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SSI_RXFS: ALT4,ECSPI1_MISO: ALT2"
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line.long 0x30 "CSPI_IPP_IND_SS3_B_SELECT_INPUT,CSPI_IPP_IND_SS3_B_SELECT_INPUT Register"
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bitfld.long 0x30 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SSI_RXD: ALT4,ECSPI1_SS0: ALT2"
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line.long 0x34 "ELCDIF_LCDIF_BUSY_SELECT_INPUT,ELCDIF_LCDIF_BUSY_SELECT_INPUT Register"
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bitfld.long 0x34 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "ECSPI2_SS0: ALT5,DISP_CS: ALT2,DISP_BUSY: ALT0,EPDC: ALT4"
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line.long 0x38 "ELCDIF_LCDIF_RXDATA_0_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_0_SELECT_INPUT Register"
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bitfld.long 0x38 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D0: ALT0,EPDC_SDCE5: ALT3"
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line.long 0x3C "ELCDIF_LCDIF_RXDATA_1_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_1_SELECT_INPUT Register"
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bitfld.long 0x3C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D1: ALT0,EPDC_SCDE4: ALT3"
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line.long 0x40 "ELCDIF_LCDIF_RXDATA_2_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_2_SELECT_INPUT Register"
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bitfld.long 0x40 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D1: ALT0,EPDC_SDCE3: ALT3"
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line.long 0x44 "ELCDIF_LCDIF_RXDATA_3_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_3_SELECT_INPUT Register"
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bitfld.long 0x44 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D3: ALT0,EPDC_SDCE2: ALT3"
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line.long 0x48 "ELCDIF_LCDIF_RXDATA_4_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_4_SELECT_INPUT Register"
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bitfld.long 0x48 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D4: ALT0,EPDC_SDCE1: ALT3"
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line.long 0x4C "ELCDIF_LCDIF_RXDATA_5_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_5_SELECT_INPUT Register"
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bitfld.long 0x4C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D5: ALT0,EPDC_SDCE0: ALT3"
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line.long 0x50 "ELCDIF_LCDIF_RXDATA_6_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_6_SELECT_INPUT Register"
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bitfld.long 0x50 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D6: ALT0,EPDC_BDR1: ALT3"
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line.long 0x54 "ELCDIF_LCDIF_RXDATA_7_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_7_SELECT_INPUT Register"
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bitfld.long 0x54 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D7: ALT0,EPDC_BDR0: ALR3"
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line.long 0x58 "ELCDIF_LCDIF_RXDATA_8_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_8_SELECT_INPUT Register"
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bitfld.long 0x58 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D8: ALT0,EPDC_SDLE: ALT3"
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line.long 0x5C "C_ELCDIF_LCDIF_RXDATA_9_SELECT_INPUT,C_ELCDIF_LCDIF_RXDATA_9_SELECT_INPUT Register"
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bitfld.long 0x5C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D9: ALT0,EPDC_SDCLKN: ALT3"
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line.long 0x60 "ELCDIF_LCDIF_RXDATA_10_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_10_SELECT_INPUT Register"
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bitfld.long 0x60 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D10: ALT0,EPDC_SDSHR: ALT3"
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line.long 0x64 "ELCDIF_LCDIF_RXDATA_11_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_11_SELECT_INPUT Register"
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bitfld.long 0x64 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D11: ALT0,EPDC_PWRCOM: ALT3"
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line.long 0x68 "ELCDIF_LCDIF_RXDATA_12_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_12_SELECT_INPUT Register"
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bitfld.long 0x68 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D12: ALT0,EPDC_PWRSTAT: ALT3"
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line.long 0x6C "ELCDIF_LCDIF_RXDATA_13_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_13_SELECT_INPUT Register"
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bitfld.long 0x6C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D13: ALT0,EPDC_PWRCTRL0: ALT3"
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line.long 0x70 "ELCDIF_LCDIF_RXDATA_14_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_14_SELECT_INPUT Register"
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bitfld.long 0x70 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D14: ALT0,EPDC_PWRCTRL1: ALT3"
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line.long 0x74 "ELCDIF_LCDIF_RXDATA_15_SELECT_INPUT,ELCDIF_LCDIF_RXDATA_15_SELECT_INPUT Register"
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bitfld.long 0x74 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D15: ALT0,EPDC_PWRCTRL2"
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line.long 0x78 "ELCDIF_VSYNC_I_SELECT_INPUT,ELCDIF_VSYNC_I_SELECT_INPUT Register"
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bitfld.long 0x78 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "ECSPI2_MISO: ALT5,DISP_RS: ALT2,EPDC_D2: ALT4,?..."
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line.long 0x7C "ESDHC2_IPP_CARD_DET_SELECT_INPUT,ESDHC2_IPP_CARD_DET_SELECT_INPUT Register"
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bitfld.long 0x7C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART3_RXD: ALT5,SD2_CD: ALT0"
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line.long 0x80 "ESDHC2_IPP_WP_ON_SELECT_INPUT,ESDHC2_IPP_WP_ON_SELECT_INPUT Register"
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bitfld.long 0x80 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART3_TDX: ALT5,SD2_WP:ALT0"
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line.long 0x84 "ESDHC4_IPP_CARD_CLK_IN_SELECT_INPUT,ESDHC4_IPP_CARD_CLK_IN_SELECT_INPUT Register"
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bitfld.long 0x84 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART1_RTS: ALT5,UART2_RTS: ALT4,DISP_D9: ALT4,?..."
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line.long 0x88 "ESDHC4_IPP_CMD_IN_SELECT_INPUT,ESDHC4_IPP_CMD_IN_SELECT_INPUT Register"
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bitfld.long 0x88 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART1_CTS: ALT5,UART2_CTS: ALT4,DISP_D8: ALT4,?..."
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line.long 0x8C "ESDHC4_IPP_DAT0_IN_SELECT_INPUT,ESDHC4_IPP_DAT0_IN_SELECT_INPUT Register"
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bitfld.long 0x8C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART3_TXD: ALT4,DISP_D10: ALT4"
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line.long 0x90 "XC_ESDHC4_IPP_DAT1_IN_SELECT_INPUT,XC_ESDHC4_IPP_DAT1_IN_SELECT_INPUT Register"
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bitfld.long 0x90 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART3_RXD: ALT4,DISP_D11: ALT4"
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line.long 0x94 "ESDHC4_IPP_DAT2_IN_SELECT_INPUT,ESDHC4_IPP_DAT2_IN_SELECT_INPUT Register"
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bitfld.long 0x94 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART4_TXD: ALT4,DISP_D12: ALT4"
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line.long 0x98 "ESDHC4_IPP_DAT3_IN_SELECT_INPUT,ESDHC4_IPP_DAT3_IN_SELECT_INPUT Register"
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bitfld.long 0x98 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART4_RXD: ALT4,DISP_D13: ALT"
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line.long 0x9C "ESDHC4_IPP_DAT4_IN_SELECT_INPUT,ESDHC4_IPP_DAT4_IN_SELECT_INPUT Register"
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bitfld.long 0x9C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART1_CTS: ALT4,UART2_TXD: ALT5"
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line.long 0xA0 "ESDHC4_IPP_DAT5_IN_SELECT_INPUT,ESDHC4_IPP_DAT5_IN_SELECT_INPUT Register"
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bitfld.long 0xA0 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART1_RTS: ALT4,UART2_RXD: ALT5"
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line.long 0xA4 "ESDHC4_IPP_DAT6_IN_SELECT_INPUT,ESDHC4_IPP_DAT6_IN_SELECT_INPUT Register"
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bitfld.long 0xA4 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART1_TXD: ALT4,UART2_CTS: ALT5"
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line.long 0xA8 "ESDHC4_IPP_DAT7_IN_SELECT_INPUT,ESDHC4_IPP_DAT7_IN_SELECT_INPUT Register"
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bitfld.long 0xA8 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART2_RXD: ALT4,UART2_RTS: ALT5"
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line.long 0xAC "FEC_FEC_COL_SELECT_INPUT,FEC_FEC_COL_SELECT_INPUT Register"
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bitfld.long 0xAC 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SSI_RXFS: ALT5,DISP_D3: ALT4"
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line.long 0xB0 "FEC_FEC_MDI_SELECT_INPUT,FEC_FEC_MDI_SELECT_INPUT Register"
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bitfld.long 0xB0 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "I2C3_SDA: ALT2,SSI_RXC: ALT6"
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line.long 0xB4 "FEC_FEC_RDATA_0_SELECT_INPUT,FEC_FEC_RDATA_0_SELECT_INPUT Register"
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bitfld.long 0xB4 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D4: ALT2,DISP_D12: ALT6"
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line.long 0xB8 "FEC_FEC_RDATA_1_SELECT_INPUT,FEC_FEC_RDATA_1_SELECT_INPUT Register"
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bitfld.long 0xB8 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D3: ALT2,DISP_D11: ALT6"
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line.long 0xBC "FEC_FEC_RX_CLK_SELECT_INPUT,FEC_FEC_RX_CLK_SELECT_INPUT Register"
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bitfld.long 0xBC 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SSI_RXC: ALT5,DISP_D6: ALT4"
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line.long 0xC0 "FEC_FEC_RX_DV_SELECT_INPUT,FEC_FEC_RX_DV_SELECT_INPUT Register"
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bitfld.long 0xC0 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D2: ALT2,DISP_D10: ALT6"
|
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line.long 0xC4 "FEC_FEC_RX_ER_SELECT_INPUT,FEC_FEC_RX_ER_SELECT_INPUT Register"
|
|
bitfld.long 0xC4 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D1: ALT2,DISP_D9: ALT6"
|
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line.long 0xC8 "FEC_FEC_TX_CLK_SELECT_INPUT,FEC_FEC_TX_CLK_SELECT_INPUT Register"
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bitfld.long 0xC8 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISP_D0: ALT2,DISP_D8: ALT6"
|
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line.long 0xCC "KPP_IPP_IND_COL_4_SELECT_INPUT,KPP_IPP_IND_COL_4_SELECT_INPUT Register"
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bitfld.long 0xCC 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D0: ALT3,DISP_D8: ALT5,EIM_DA0: ALT3,?..."
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|
line.long 0xD0 "KPP_IPP_IND_COL_5_SELECT_INPUT,KPP_IPP_IND_COL_5_SELECT_INPUT Register"
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bitfld.long 0xD0 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D2: ALT3,DISP_D10: ALT5,EIM_DA2: ALT3,?..."
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|
line.long 0xD4 "KPP_IPP_IND_COL_6_SELECT_INPUT,KPP_IPP_IND_COL_6_SELECT_INPUT Register"
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bitfld.long 0xD4 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D4: ALT3,DISP_D12: ALT5,EIM_DA4: ALT3,?..."
|
|
line.long 0xD8 "KPP_IPP_IND_COL_7_SELECT_INPUT,KPP_IPP_IND_COL_7_SELECT_INPUT Register"
|
|
bitfld.long 0xD8 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D6: ALT3,DISP_D14: ALT5,EIM_DA6: ALT3,?..."
|
|
line.long 0xDC "KPP_IPP_IND_ROW_4_SELECT_INPUT,KPP_IPP_IND_ROW_4_SELECT_INPUT Register"
|
|
bitfld.long 0xDC 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D1: ALT3,DISP_D9: ALT5,EIM_DA1: ALT3,?..."
|
|
line.long 0xE0 "KPP_IPP_IND_ROW_5_SELECT_INPUT,KPP_IPP_IND_ROW_5_SELECT_INPUT Register"
|
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bitfld.long 0xE0 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D3: ALT3,DISP_D11: ALT5,EIM_DA3: ALT3,?..."
|
|
line.long 0xE4 "KPP_IPP_IND_ROW_6_SELECT_INPUT,KPP_IPP_IND_ROW_6_SELECT_INPUT Register"
|
|
bitfld.long 0xE4 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D5: ALT3,DISP_D13: ALT5,EIM_DA5: ALT3,?..."
|
|
line.long 0xE8 "KPP_IPP_IND_ROW_7_SELECT_INPUT,KPP_IPP_IND_ROW_7_SELECT_INPUT Register"
|
|
bitfld.long 0xE8 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D7: ALT3,DISP_D15: ALT5,EIM_DA7: ALT3,?..."
|
|
line.long 0xEC "RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT,RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT Register"
|
|
bitfld.long 0xEC 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "KEY_ROW3: ALT2,DISP_D15: ALT2,EIM_DA15: ALT2,?..."
|
|
line.long 0xF0 "RAWNAND_U_GPMI_INPUT_GPMI_RDY0_SELECT_INPUT,RAWNAND_U_GPMI_INPUT_GPMI_RDY0_SELECT_INPUT Register"
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bitfld.long 0xF0 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "KEY_COL3: ALT2,DISP_D14: ALT2,EIM_DA14: ALT2,?..."
|
|
line.long 0xF4 "SDMA_EVENTS_14_SELECT_INPUT,SDMA_EVENTS_14_SELECT_INPUT Register"
|
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bitfld.long 0xF4 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "KEY_COL3: ALT6,EPDC_PWRCTRL2: ALT6"
|
|
line.long 0xF8 "SDMA_EVENTS_15_SELECT_INPUT,SDMA_EVENTS_15_SELECT_INPUT Register"
|
|
bitfld.long 0xF8 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "KEY_ROW3: ALT6,EPDC_PWRCTRL3: ALT6"
|
|
line.long 0xFC "UART1_IPP_UART_RTS_B_SELECT_INPUT,UART1_IPP_UART_RTS_B_SELECT_INPUT Register"
|
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bitfld.long 0xFC 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART1_CTS: ALT0,UART1_RTS: ALT0"
|
|
line.long 0x100 "UART1_IPP_UART_RXD_MUX_SELECT_INPUT,UART1_IPP_UART_RXD_MUX_SELECT_INPUT Register"
|
|
bitfld.long 0x100 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART1_TXD: ALT0,UART1_RXD: ALT0"
|
|
line.long 0x104 "UART2_IPP_UART_RTS_B_SELECT_INPUT,UART2_IPP_UART_RTS_B_SELECT_INPUT Register"
|
|
bitfld.long 0x104 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "I2C2_SCL: ALT2,I2C2_SDA: ALT2,UART2_CTS: ALT0,UART2_RTS: ALT0"
|
|
line.long 0x108 "UART2_IPP_UART_RXD_MUX_SELECT_INPUT,UART2_IPP_UART_RXD_MUX_SELECT_INPUT Register"
|
|
bitfld.long 0x108 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "I2C1_SCL: ALT2,I2C1_SDA: ALT2,UART2_TXD: ALT0,UART2_RXD: ALT0"
|
|
line.long 0x10C "UART3_IPP_UART_RTS_B_SELECT_INPUT,UART3_IPP_UART_RTS_B_SELECT_INPUT Register"
|
|
bitfld.long 0x10C 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART4_TXD: ALT2,UART4_RXD: ALT2,ECSPI1_SCLK: ALT4,ECSPI1_MOSI: ALT4"
|
|
line.long 0x110 "UART3_IPP_UART_RXD_MUX_SELECT_INPUT,UART3_IPP_UART_RXD_MUX_SELECT_INPUT Register"
|
|
bitfld.long 0x110 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART3_TXD: ALT0,UART3_RXD: ALT0"
|
|
line.long 0x114 "UART4_IPP_UART_RTS_B_SELECT_INPUT,UART4_IPP_UART_RTS_B_SELECT_INPUT Register"
|
|
bitfld.long 0x114 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "ECSPI1_MISO: ALT4,ECSPI1_SS0: ALT4"
|
|
line.long 0x118 "UART4_IPP_UART_RXD_MUX_SELECT_INPUT,UART4_IPP_UART_RXD_MUX_SELECT_INPUT Register"
|
|
bitfld.long 0x118 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART4_TXD: ALT0,UART4_RXD: ALT0"
|
|
line.long 0x11C "UART5_IPP_UART_RTS_B_SELECT_INPUT,UART5_IPP_UART_RTS_B_SELECT_INPUT Register"
|
|
bitfld.long 0x11C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "ECSPI2_SCLK: ALT4,ECSPI2_MOSI: ALT4"
|
|
line.long 0x120 "UART5_IPP_UART_RXD_MUX_SELECT_INPUT,UART5_IPP_UART_RXD_MUX_SELECT_INPUT Register"
|
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bitfld.long 0x120 0.--2. " DAISY ,Selecting Pads Involved in Daisy Chain" "SSI_RXFS: ALT2,SSI_RXC: ALT2,UART1_CTS: ALT2,UART1_RTS: ALT2,ECSPI2_MISO: ALT4,ECSPI2_SS0: ALT4,?..."
|
|
line.long 0x124 "USBOH1_IPP_IND_OTG_OC_SELECT_INPUT,USBOH1_IPP_IND_OTG_OC_SELECT_INPUT Register"
|
|
bitfld.long 0x124 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "I2C3_SCL: ALT7,PWM1: ALT2"
|
|
line.long 0x128 "WEIMV2_IPP_IND_READ_DATA_0_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_0_SELECT_INPUT Register"
|
|
bitfld.long 0x128 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D4: ALT4,EPDC_D0: ALT2"
|
|
line.long 0x12C "WEIMV2_IPP_IND_READ_DATA_1_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_1_SELECT_INPUT Register"
|
|
bitfld.long 0x12C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D5: ALT4,EPDC_D1: ALT2"
|
|
line.long 0x130 "WEIMV2_IPP_IND_READ_DATA_2_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_2_SELECT_INPUT Register"
|
|
bitfld.long 0x130 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D6: ALT4,EPDC_D2: ALT2"
|
|
line.long 0x134 "WEIMV2_IPP_IND_READ_DATA_3_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_3_SELECT_INPUT Register"
|
|
bitfld.long 0x134 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_D7: ALT4,EPDC_D3: ALT2"
|
|
line.long 0x138 "WEIMV2_IPP_IND_READ_DATA_4_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_4_SELECT_INPUT Register"
|
|
bitfld.long 0x138 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_WP: ALT4,EPDC_D4: ALT2"
|
|
line.long 0x13C "WEIMV2_IPP_IND_READ_DATA_5_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_5_SELECT_INPUT Register"
|
|
bitfld.long 0x13C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SD2_CD: ALT4,EPDC_D5: ALT2"
|
|
line.long 0x140 "WEIMV2_IPP_IND_READ_DATA_6_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_6_SELECT_INPUT Register"
|
|
bitfld.long 0x140 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SSI_RXFS: ALT3,EPDC_D6: ALT2"
|
|
line.long 0x144 "WEIMV2_IPP_IND_READ_DATA_7_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_7_SELECT_INPUT Register"
|
|
bitfld.long 0x144 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "SSI_RXC: ALT2,EPDC_D7: ALT2"
|
|
line.long 0x148 "WEIMV2_IPP_IND_READ_DATA_8_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_8_SELECT_INPUT Register"
|
|
bitfld.long 0x148 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "ECSPI1_SCLK: ALT7,ECSPI2_SCLK: ALT7,EPDC_D8: ALT2,?..."
|
|
line.long 0x14C "WEIMV2_IPP_IND_READ_DATA_9_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_9_SELECT_INPUT Register"
|
|
bitfld.long 0x14C 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "ECSPI1_MOSI: ALT7,ECSPI2_MOSI: ALT7,EPDC_D9: ALT2,?..."
|
|
line.long 0x150 "WEIMV2_IPP_IND_READ_DATA_10_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_10_SELECT_INPUT Register"
|
|
bitfld.long 0x150 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "ECSPI1_MISO: ALT7,ECSPI2_MISO: ALT7,EPDC_D10: ALT2,?..."
|
|
line.long 0x154 "WEIMV2_IPP_IND_READ_DATA_11_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_11_SELECT_INPUT Register"
|
|
bitfld.long 0x154 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "ECSPI1_SS0: ALT7,ECSPI2_SS0: ALT7,EPDC_D11: ALT2,?..."
|
|
line.long 0x158 "WEIMV2_IPP_IND_READ_DATA_12_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_12_SELECT_INPUT Register"
|
|
bitfld.long 0x158 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART3_TXD: ALT6,EPDC_D12: ALT2"
|
|
line.long 0x15C "WEIMV2_IPP_IND_READ_DATA_13_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_13_SELECT_INPUT Register"
|
|
bitfld.long 0x15C 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART3_RXD: ALT6,EPDC_D13: ALT2"
|
|
line.long 0x160 "WEIMV2_IPP_IND_READ_DATA_14_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_14_SELECT_INPUT Register"
|
|
bitfld.long 0x160 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART4_TXD: ALT6,EPDC_D14: ALT2"
|
|
line.long 0x164 "WEIMV2_IPP_IND_READ_DATA_15_SELECT_INPUT,WEIMV2_IPP_IND_READ_DATA_15_SELECT_INPUT Register"
|
|
bitfld.long 0x164 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART4_RXD: ALT6,EPDC_D15: ALT2"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "KPP (Keypad Port)"
|
|
base ad:0x53F94000
|
|
width 6.
|
|
group.word 0x00++0x7
|
|
line.word 0x00 "KPCR,Keypad Control Register"
|
|
bitfld.word 0x00 15. " KCO7 ,Keypad Column Strobe Open-Drain Enable 7" "Totem pole,Open drain"
|
|
bitfld.word 0x00 14. " KCO6 ,Keypad Column Strobe Open-Drain Enable 6" "Totem pole,Open drain"
|
|
bitfld.word 0x00 13. " KCO5 ,Keypad Column Strobe Open-Drain Enable 5" "Totem pole,Open drain"
|
|
bitfld.word 0x00 12. " KCO4 ,Keypad Column Strobe Open-Drain Enable 4" "Totem pole,Open drain"
|
|
bitfld.word 0x00 11. " KCO3 ,Keypad Column Strobe Open-Drain Enable 3" "Totem pole,Open drain"
|
|
bitfld.word 0x00 10. " KCO2 ,Keypad Column Strobe Open-Drain Enable 2" "Totem pole,Open drain"
|
|
bitfld.word 0x00 9. " KCO1 ,Keypad Column Strobe Open-Drain Enable 1" "Totem pole,Open drain"
|
|
bitfld.word 0x00 8. " KCO0 ,Keypad Column Strobe Open-Drain Enable 0" "Totem pole,Open drain"
|
|
textline " "
|
|
bitfld.word 0x00 7. " KRE7 ,Keypad Row Enable 7" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " KRE6 ,Keypad Row Enable 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " KRE5 ,Keypad Row Enable 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " KRE4 ,Keypad Row Enable 4" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " KRE3 ,Keypad Row Enable 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " KRE2 ,Keypad Row Enable 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " KRE1 ,Keypad Row Enable 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " KRE0 ,Keypad Row Enable 0" "Disabled,Enabled"
|
|
line.word 0x02 "KPSR,Keypad Status Register"
|
|
bitfld.word 0x02 9. " KRIE ,Keypad Release Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " KDIE ,Keypad Key Depress Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 3. " KRSS ,Key Release Synchronizer Set" "No effect,Set"
|
|
bitfld.word 0x02 2. " KDSC ,Key Depress Synchronizer Clear" "No effect,Clear"
|
|
eventfld.word 0x02 1. " KPKR ,Keypad Key Release" "Not released,Released"
|
|
eventfld.word 0x02 0. " KPKD ,Keypad Key Depress" "Not depressed,Depressed"
|
|
line.word 0x04 "KDDR,Keypad Data Direction Register"
|
|
bitfld.word 0x04 15. " KCDD7 ,Keypad Column Data Direction 7" "Input,Output"
|
|
bitfld.word 0x04 14. " KCDD6 ,Keypad Column Data Direction 6" "Input,Output"
|
|
bitfld.word 0x04 13. " KCDD5 ,Keypad Column Data Direction 5" "Input,Output"
|
|
bitfld.word 0x04 12. " KCDD4 ,Keypad Column Data Direction 4" "Input,Output"
|
|
bitfld.word 0x04 11. " KCDD3 ,Keypad Column Data Direction 3" "Input,Output"
|
|
bitfld.word 0x04 10. " KCDD2 ,Keypad Column Data Direction 2" "Input,Output"
|
|
bitfld.word 0x04 9. " KCDD1 ,Keypad Column Data Direction 1" "Input,Output"
|
|
bitfld.word 0x04 8. " KCDD0 ,Keypad Column Data Direction 0" "Input,Output"
|
|
textline " "
|
|
bitfld.word 0x04 7. " KRDD7 ,Keypad Row Data Direction 7" "Input,Output"
|
|
bitfld.word 0x04 6. " KRDD6 ,Keypad Row Data Direction 6" "Input,Output"
|
|
bitfld.word 0x04 5. " KRDD5 ,Keypad Row Data Direction 5" "Input,Output"
|
|
bitfld.word 0x04 4. " KRDD4 ,Keypad Row Data Direction 4" "Input,Output"
|
|
bitfld.word 0x04 3. " KRDD3 ,Keypad Row Data Direction 3" "Input,Output"
|
|
bitfld.word 0x04 2. " KRDD2 ,Keypad Row Data Direction 2" "Input,Output"
|
|
bitfld.word 0x04 1. " KRDD1 ,Keypad Row Data Direction 1" "Input,Output"
|
|
bitfld.word 0x04 0. " KRDD0 ,Keypad Row Data Direction 0" "Input,Output"
|
|
line.word 0x06 "KPDR,Keypad Data Register"
|
|
bitfld.word 0x06 15. " KCD7 ,Keypad Column Data 7" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 14. " KCD6 ,Keypad Column Data 6" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 13. " KCD5 ,Keypad Column Data 5" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 12. " KCD4 ,Keypad Column Data 4" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 11. " KCD3 ,Keypad Column Data 3" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 10. " KCD2 ,Keypad Column Data 2" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 9. " KCD1 ,Keypad Column Data 1" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 8. " KCD0 ,Keypad Column Data 0" "Pin=0,Pin=1"
|
|
textline " "
|
|
bitfld.word 0x06 7. " KRD7 ,Keypad Row Data 7" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 6. " KRD6 ,Keypad Row Data 6" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 5. " KRD5 ,Keypad Row Data 5" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 4. " KRD4 ,Keypad Row Data 4" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 3. " KRD3 ,Keypad Row Data 3" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 2. " KRD2 ,Keypad Row Data 2" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 1. " KRD1 ,Keypad Row Data 1" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 0. " KRD0 ,Keypad Row Data 0" "Pin=0,Pin=1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "eLCDIF (Enhanced LCD Interface)"
|
|
base ad:0x4100A000
|
|
width 16.
|
|
group.long 0x00++0x0f
|
|
line.long 0x00 "CTRL,LCDIF General Control Register"
|
|
bitfld.long 0x00 31. " SFTRST ,Block level reset" "No reset,Reset"
|
|
bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "0,1"
|
|
bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "Not wait,Wait"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "Left,Right"
|
|
bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass Count" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VSYNC_MODE ,Enable VSYNC mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DOTCLK_MODE ,Enable DOTCLK mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_SELECT ,Command Mode polarity bit" "Command mode,Data mode"
|
|
bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes"
|
|
bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit"
|
|
bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "Slave,Master"
|
|
bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,Data Format 18 bit" "RGB565,ARGB555"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "Lower 18 bits valid,Upper 18 bits valid"
|
|
bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "All 24 bits valid,Drop upper 2 bits per byte"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RUN ,Start LCDIF" "No effect,Start"
|
|
line.long 0x04 "CTRL_SET,LCDIF General Control Set Register"
|
|
bitfld.long 0x04 31. " SFTRST ,Block level reset" "No effect,Set"
|
|
bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "No effect,Set"
|
|
bitfld.long 0x04 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "No effect,Set"
|
|
bitfld.long 0x04 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "No effect,Set"
|
|
bitfld.long 0x04 19. " BYPASS_COUNT ,Bypass Count" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 18. " VSYNC_MODE ,Enable VSYNC mode" "No effect,Set"
|
|
bitfld.long 0x04 17. " DOTCLK_MODE ,Enable DOTCLK mode" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DATA_SELECT ,Command Mode polarity bit" "No effect,Set"
|
|
bitfld.long 0x04 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes"
|
|
bitfld.long 0x04 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit"
|
|
bitfld.long 0x04 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "No effect,Set"
|
|
bitfld.long 0x04 3. " DATA_FORMAT_16_BIT ,Data Format 18 bit" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "No effect,Set"
|
|
bitfld.long 0x04 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RUN ,Start LCDIF" "No effect,Set"
|
|
line.long 0x08 "CTRL_CLR,LCDIF General Control Clear Register"
|
|
bitfld.long 0x08 31. " SFTRST ,Block level reset" "No effect,Clear"
|
|
bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "No effect,Clear"
|
|
bitfld.long 0x08 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "No effect,Clear"
|
|
bitfld.long 0x08 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "No effect,Clear"
|
|
bitfld.long 0x08 19. " BYPASS_COUNT ,Bypass Count" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 18. " VSYNC_MODE ,Enable VSYNC mode" "No effect,Clear"
|
|
bitfld.long 0x08 17. " DOTCLK_MODE ,Enable DOTCLK mode" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DATA_SELECT ,Command Mode polarity bit" "No effect,Clear"
|
|
bitfld.long 0x08 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes"
|
|
bitfld.long 0x08 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit"
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit"
|
|
bitfld.long 0x08 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "No effect,Clear"
|
|
bitfld.long 0x08 3. " DATA_FORMAT_16_BIT ,Data Format 18 bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "No effect,Clear"
|
|
bitfld.long 0x08 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 0. " RUN ,Start LCDIF" "No effect,Clear"
|
|
line.long 0x0c "CTRL_TOG,LCDIF General Control Toggle Register"
|
|
bitfld.long 0x0c 31. " SFTRST ,Block level reset" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0c 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 19. " BYPASS_COUNT ,Bypass Count" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 18. " VSYNC_MODE ,Enable VSYNC mode" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 17. " DOTCLK_MODE ,Enable DOTCLK mode" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " DATA_SELECT ,Command Mode polarity bit" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes"
|
|
textline " "
|
|
bitfld.long 0x0c 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes"
|
|
bitfld.long 0x0c 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit"
|
|
bitfld.long 0x0c 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 3. " DATA_FORMAT_16_BIT ,Data Format 18 bit" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " RUN ,Start LCDIF" "Not toggle,Toggle"
|
|
if (((d.l((ad:0x4100A000)+0x00))&0x300)==0x100)
|
|
;8-bit
|
|
group.long 0x10++0x0f
|
|
line.long 0x00 "CTRL1,LCDIF General Control1 Register"
|
|
bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst"
|
|
bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field"
|
|
bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Toggle/High,Low"
|
|
bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode"
|
|
bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High"
|
|
line.long 0x04 "CTRL1_SET,LCDIF General Control1 Set Register"
|
|
bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set"
|
|
bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set"
|
|
bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set"
|
|
bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set"
|
|
bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set"
|
|
bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set"
|
|
bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Set"
|
|
bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set"
|
|
bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set"
|
|
line.long 0x08 "CTRL1_CLR,LCDIF General Control1 Clear Register"
|
|
bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear"
|
|
bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear"
|
|
bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear"
|
|
bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear"
|
|
bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear"
|
|
bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear"
|
|
bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Clear"
|
|
bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear"
|
|
bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear"
|
|
line.long 0x0c "CTRL1_TOG,LCDIF General Control1 Toggle Register"
|
|
bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle"
|
|
elif (((d.l((ad:0x4100A000)+0x00))&0x300)==0x00)
|
|
;16-bit
|
|
group.long 0x10++0x0f
|
|
line.long 0x00 "CTRL1,LCDIF General Control1 Register"
|
|
bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst"
|
|
bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field"
|
|
bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Toggle/High,Low"
|
|
bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode"
|
|
bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High"
|
|
line.long 0x04 "CTRL1_SET,LCDIF General Control1 Set Register"
|
|
bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set"
|
|
bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set"
|
|
bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set"
|
|
bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set"
|
|
bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set"
|
|
bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set"
|
|
bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Set"
|
|
bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set"
|
|
bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set"
|
|
line.long 0x08 "CTRL1_CLR,LCDIF General Control1 Clear Register"
|
|
bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear"
|
|
bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear"
|
|
bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear"
|
|
bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear"
|
|
bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear"
|
|
bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear"
|
|
bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Clear"
|
|
bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear"
|
|
bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear"
|
|
line.long 0x0c "CTRL1_TOG,LCDIF General Control1 Toggle Register"
|
|
bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle"
|
|
elif (((d.l((ad:0x4100A000)+0x00))&0x300)==0x200)
|
|
;18-bit
|
|
group.long 0x10++0x0f
|
|
line.long 0x00 "CTRL1,LCDIF General Control1 Register"
|
|
bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst"
|
|
bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field"
|
|
bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Toggle/High,Low"
|
|
bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode"
|
|
bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High"
|
|
line.long 0x04 "CTRL1_SET,LCDIF General Control1 Set Register"
|
|
bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set"
|
|
bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set"
|
|
bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set"
|
|
bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set"
|
|
bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set"
|
|
bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set"
|
|
bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Set"
|
|
bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set"
|
|
bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set"
|
|
line.long 0x08 "CTRL1_CLR,LCDIF General Control1 Clear Register"
|
|
bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear"
|
|
bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear"
|
|
bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear"
|
|
bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear"
|
|
bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear"
|
|
bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear"
|
|
bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Clear"
|
|
bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear"
|
|
bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear"
|
|
line.long 0x0c "CTRL1_TOG,LCDIF General Control1 Toggle Register"
|
|
bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle"
|
|
else
|
|
;24-bit
|
|
group.long 0x10++0x0f
|
|
line.long 0x00 "CTRL1,LCDIF General Control1 Register"
|
|
bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst"
|
|
bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field"
|
|
bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Toggle/High,Low"
|
|
bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode"
|
|
bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High"
|
|
line.long 0x04 "CTRL1_SET,LCDIF General Control1 Set Register"
|
|
bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set"
|
|
bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set"
|
|
bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set"
|
|
bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set"
|
|
bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set"
|
|
bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set"
|
|
bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Set"
|
|
bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set"
|
|
bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set"
|
|
line.long 0x08 "CTRL1_CLR,LCDIF General Control1 Clear Register"
|
|
bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear"
|
|
bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear"
|
|
bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear"
|
|
bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear"
|
|
bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear"
|
|
bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear"
|
|
bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Clear"
|
|
bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear"
|
|
bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear"
|
|
line.long 0x0c "CTRL1_TOG,LCDIF General Control1 Toggle Register"
|
|
bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle"
|
|
endif
|
|
; if CTRL->LCDIF_MASTER == "Master"
|
|
if (d.l(ad:0x4100A000)&0x20)==0x20
|
|
group.long 0x20++0x0f
|
|
line.long 0x00 "CTRL2,General Control2 Register"
|
|
bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions to be requested in bus master mode" "1,2,4,8,16,?..."
|
|
bitfld.long 0x00 20. " BURST_LEN_8 ,AXI Burst length (normal-packed 24bpp)" "16 bits-15 bits,8 bits-9 bits"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Odd lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Even lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " READ_PACK_DIR ,Data Packing Direction" "From LSB,From MSB"
|
|
bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data to RGB conversion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Input data length" "8-bit,6-bit"
|
|
bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid subwords to be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy subwords to be read back from LCD controller" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CTRL2_SET,General Control2 Register"
|
|
bitfld.long 0x4 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions to be requested in bus master mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 20. " BURST_LEN_8 ,AXI Burst length (normal-packed 24bpp)" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " ODD_LINE_PATTERN ,Odd lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
bitfld.long 0x4 12.--14. " EVEN_LINE_PATTERN ,Even lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
textline " "
|
|
bitfld.long 0x4 10. " READ_PACK_DIR ,Data Packing Direction" "No effect,Set"
|
|
bitfld.long 0x4 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data to RGB conversion" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x4 8. " READ_MODE_6_BIT_INPUT ,Input data length" "No effect,Set"
|
|
bitfld.long 0x4 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid subwords to be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 1.--3. " INITIAL_DUMMY_READ ,Number of dummy subwords to be read back from LCD controller" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CTRL2_CLR,General Control2 Register"
|
|
bitfld.long 0x8 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions to be requested in bus master mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 20. " BURST_LEN_8 ,AXI Burst length (normal-packed 24bpp)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " ODD_LINE_PATTERN ,Odd lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
bitfld.long 0x8 12.--14. " EVEN_LINE_PATTERN ,Even lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
textline " "
|
|
bitfld.long 0x8 10. " READ_PACK_DIR ,Data Packing Direction" "No effect,Clear"
|
|
bitfld.long 0x8 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data to RGB conversion" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x8 8. " READ_MODE_6_BIT_INPUT ,Input data length" "No effect,Clear"
|
|
bitfld.long 0x8 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid subwords to be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 1.--3. " INITIAL_DUMMY_READ ,Number of dummy subwords to be read back from LCD controller" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "CTRL2_TOG,General Control2 Register"
|
|
bitfld.long 0xC 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions to be requested in bus master mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 20. " BURST_LEN_8 ,AXI Burst length (normal-packed 24bpp)" "No toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " ODD_LINE_PATTERN ,Odd lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
bitfld.long 0xC 12.--14. " EVEN_LINE_PATTERN ,Even lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
textline " "
|
|
bitfld.long 0xC 10. " READ_PACK_DIR ,Data Packing Direction" "No toggle,Toggle"
|
|
bitfld.long 0xC 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data to RGB conversion" "No toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0xC 8. " READ_MODE_6_BIT_INPUT ,Input data length" "No toggle,Toggle"
|
|
bitfld.long 0xC 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid subwords to be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 1.--3. " INITIAL_DUMMY_READ ,Number of dummy subwords to be read back from LCD controller" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x20++0x0f
|
|
line.long 0x00 "CTRL2,General Control2 Register"
|
|
bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions to be requested in bus master mode" "1,2,4,8,16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,Odd lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,Even lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " READ_PACK_DIR ,Data Packing Direction" "From LSB,From MSB"
|
|
bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data to RGB conversion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Input data length" "8-bit,6-bit"
|
|
bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid subwords to be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy subwords to be read back from LCD controller" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CTRL2_SET,General Control2 Register"
|
|
bitfld.long 0x4 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions to be requested in bus master mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " ODD_LINE_PATTERN ,Odd lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
bitfld.long 0x4 12.--14. " EVEN_LINE_PATTERN ,Even lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
textline " "
|
|
bitfld.long 0x4 10. " READ_PACK_DIR ,Data Packing Direction" "No effect,Set"
|
|
bitfld.long 0x4 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data to RGB conversion" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x4 8. " READ_MODE_6_BIT_INPUT ,Input data length" "No effect,Set"
|
|
bitfld.long 0x4 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid subwords to be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 1.--3. " INITIAL_DUMMY_READ ,Number of dummy subwords to be read back from LCD controller" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CTRL2_CLR,General Control2 Register"
|
|
bitfld.long 0x8 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions to be requested in bus master mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " ODD_LINE_PATTERN ,Odd lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
bitfld.long 0x8 12.--14. " EVEN_LINE_PATTERN ,Even lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
textline " "
|
|
bitfld.long 0x8 10. " READ_PACK_DIR ,Data Packing Direction" "No effect,Clear"
|
|
bitfld.long 0x8 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data to RGB conversion" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x8 8. " READ_MODE_6_BIT_INPUT ,Input data length" "No effect,Clear"
|
|
bitfld.long 0x8 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid subwords to be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 1.--3. " INITIAL_DUMMY_READ ,Number of dummy subwords to be read back from LCD controller" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "CTRL2_TOG,General Control2 Register"
|
|
bitfld.long 0xC 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions to be requested in bus master mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " ODD_LINE_PATTERN ,Odd lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
bitfld.long 0xC 12.--14. " EVEN_LINE_PATTERN ,Even lines RGB components order" "RGB,RBG,GBR,GRB,BRG,BGR,?..."
|
|
textline " "
|
|
bitfld.long 0xC 10. " READ_PACK_DIR ,Data Packing Direction" "No toggle,Toggle"
|
|
bitfld.long 0xC 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Incoming data to RGB conversion" "No toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0xC 8. " READ_MODE_6_BIT_INPUT ,Input data length" "No toggle,Toggle"
|
|
bitfld.long 0xC 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Indicates the number of valid subwords to be packed into the 32-bit word in read mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 1.--3. " INITIAL_DUMMY_READ ,Number of dummy subwords to be read back from LCD controller" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TRANSFER_COUNT,LCDIF Horizontal and Vertical Valid Data Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " V_COUNT ,Number of horizontal lines per frame which contain valid data"
|
|
hexmask.long.word 0x00 0.--15. 1. " H_COUNT ,Total valid data (pixels) in each horizontal line"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CUR_BUF,LCD Interface Current Buffer Address Register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "NEXT_BUF,LCD Interface Next Buffer Address Register"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TIMING,LCD Interface Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CMD_HOLD ,Number of PIXCLK cycles that the DCn signal is active after CEn is deasserted"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CMD_SETUP ,Number of PIXCLK cycles that the the DCn signal is active before CEn is asserted"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_HOLD ,Data bus hold time in PIXCLK cycles"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA_SETUP ,Data bus setup time in PIXCLK cycles"
|
|
group.long 0x70++0x0f
|
|
line.long 0x00 "VDCTRL0,LCDIF VSYNC Mode and Dotclk Mode Control Register 0"
|
|
bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC pin mode" "Output,Input"
|
|
bitfld.long 0x00 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x00 24. " ENABLE_POL ,ENABLE polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "PIXCLKS,Complete horizontal lines"
|
|
textline " "
|
|
bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "PIXCLKS,Complete horizontal lines"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HALF_LINE ,Half line (VSYNC period equal to)" "VSYNC,VSYNC + 1/2 HORIZONTAL"
|
|
textline " "
|
|
bitfld.long 0x00 18. " HALF_LINE_MODE ,Half line mode " "First/Second,All/None"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active"
|
|
line.long 0x04 "VDCTRL0_SET,LCDIF VSYNC Mode and Dotclk Mode Control Set Register 0"
|
|
bitfld.long 0x04 29. " VSYNC_OEB ,VSYNC pin mode" "No effect,Set"
|
|
bitfld.long 0x04 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 27. " VSYNC_POL ,VSYNC polarity" "No effect,Set"
|
|
bitfld.long 0x04 26. " HSYNC_POL ,HSYNC polarity" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 25. " DOTCLK_POL ,DOTCLK polarity" "No effect,Set"
|
|
bitfld.long 0x04 24. " ENABLE_POL ,ENABLE polarity" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 19. " HALF_LINE ,Half line (VSYNC period equal to)" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 18. " HALF_LINE_MODE ,Half line mode " "No effect,Set"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active"
|
|
line.long 0x08 "VDCTRL0_CLR,LCDIF VSYNC Mode and Dotclk Mode Control Clear Register 0"
|
|
bitfld.long 0x08 29. " VSYNC_OEB ,VSYNC pin mode" "No effect,Clear"
|
|
bitfld.long 0x08 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 27. " VSYNC_POL ,VSYNC polarity" "No effect,Clear"
|
|
bitfld.long 0x08 26. " HSYNC_POL ,HSYNC polarity" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 25. " DOTCLK_POL ,DOTCLK polarity" "No effect,Clear"
|
|
bitfld.long 0x08 24. " ENABLE_POL ,ENABLE polarity" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HALF_LINE ,Half line (VSYNC period equal to)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x08 18. " HALF_LINE_MODE ,Half line mode " "No effect,Clear"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active"
|
|
line.long 0x0c "VDCTRL0_TOG,LCDIF VSYNC Mode and Dotclk Mode Control Toggle Register 0"
|
|
bitfld.long 0x0c 29. " VSYNC_OEB ,VSYNC pin mode" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " VSYNC_POL ,VSYNC polarity" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 26. " HSYNC_POL ,HSYNC polarity" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " DOTCLK_POL ,DOTCLK polarity" "Not toggle,Toggle"
|
|
bitfld.long 0x0c 24. " ENABLE_POL ,ENABLE polarity" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " HALF_LINE ,Half line (VSYNC period equal to)" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0c 18. " HALF_LINE_MODE ,Half line mode " "Not toggle,Toggle"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0c 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "VDCTRL1,LCDIF VSYNC Mode and Dotclk Mode Control Register 1"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "VDCTRL2,LCDIF VSYNC Mode and Dotclk Mode Control Register 2"
|
|
hexmask.long.word 0x00 18.--31. 1. " HSYNC_PULSE_WIDTH ,Number of PIXCLKs for which HSYNC signal is active"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " HSYNC_PERIOD ,Total number of PIXCLKs between two positive or two negative edges of the HSYNC signal"
|
|
group.long 0xa0++0x03
|
|
line.long 0x00 "VDCTRL3,LCDIF VSYNC Mode and Dotclk Mode Control Register 3"
|
|
bitfld.long 0x00 29. " MUX_SYNC_SIGNALS ,Mux sync signals (HSYNC with LCD_D14,DOTCLK with LCD_D13,ENABLE with LCD_D12)" "Not muxed,Muxed"
|
|
bitfld.long 0x00 28. " VSYNC_ONLY ,VSYNC only" "DOTCLK,VSYNC"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--27. 1. " HORIZONTAL_WAIT_CNT ,Horizontal wait count"
|
|
hexmask.long.word 0x00 0.--15. 1. " VERTICAL_WAIT_CNT ,Vertical wait count"
|
|
group.long 0xb0++0x03
|
|
line.long 0x00 "VDCTRL4,LCDIF VSYNC Mode and Dotclk Mode Control Register 4"
|
|
bitfld.long 0x00 29.--31. " DOTCLK_DLY_SEL ,DOTCLK signal output delay" "2 ns,4 ns,6 ns,8 ns,?..."
|
|
bitfld.long 0x00 18. " SYNC_SIGNALS_ON ,Sync signals active at least one frame before data" "Not active,Active"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " DOTCLK_H_VALID_DATA_CNT ,Total number of PIXCLKs on each horizontal line that carry valid data in DOTCLK mode"
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "DVICTRL0,Digital Video Interface Control 0 Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " H_ACTIVE_CNT ,Number of active video samples to be transmitted"
|
|
hexmask.long.word 0x00 0.--11. 1. " H_BLANKING_CNT ,Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval"
|
|
group.long 0xd0++0x03
|
|
line.long 0x00 "DVICTRL1,Digital Video Interface Control 1 Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " F1_START_LINE ,Vertical line number from which Field 1 begins"
|
|
hexmask.long.word 0x00 10.--19. 1. " F1_END_LINE ,Vertical line number at which Field1 ends"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " F2_START_LINE ,Vertical line number from which Field 2 begins"
|
|
group.long 0xe0++0x03
|
|
line.long 0x00 "DVICTRL2,Digital Video Interface Control 2 Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " F2_END_LINE ,Vertical line number at which Field 2 ends"
|
|
hexmask.long.word 0x00 10.--19. 1. " V1_BLANK_START_LINE ,Vertical line number towards the end of Field1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " V1_BLANK_END_LINE ,Vertical line number in the beginning part of Field2"
|
|
group.long 0xf0++0x03
|
|
line.long 0x00 "DVICTRL3,Digital Video Interface Control 3 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " V2_BLANK_START_LINE ,Vertical line number towards the end of Field2"
|
|
hexmask.long.word 0x00 10.--19. 1. " V2_BLANK_END_LINE ,Vertical line number in the beginning part of Field1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " V_LINES_CNT ,Vertical Lines Per Frame Total Count"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DVICTRL4,Digital Video Interface Control 4 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Y_FILL_VALUE ,Value of Y component of filler data"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CB_FILL_VALUE ,Value of CB component of filler data"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CR_FILL_VALUE ,Value of CR component of filler data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " H_FILL_CNT ,Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CSC_COEFF0,RGB to YCbCr 4:2:2 CSC Coefficient 0 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " C0 ,Two complement red multiplier coefficient for Y"
|
|
bitfld.long 0x00 0.--1. " CSC_SUBSAMPLE_FILTER ,Filtering and subsampling scheme to be performed on the chroma components" "Sample and hold,Reserved,Interstitial,Cosited"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CSC_COEFF1,RGB to YCbCr 4:2:2 CSC Coefficient 1 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " C2 ,Two complement blue multiplier coefficient for Y"
|
|
hexmask.long.word 0x00 0.--9. 1. " C1 ,Two complement green multiplier coefficient for Y"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CSC_COEFF2,RGB to YCbCr 4:2:2 CSC Coefficent 2 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " C4 ,Two complement green multiplier coefficient for Cb"
|
|
hexmask.long.word 0x00 0.--9. 1. " C3 ,Two complement red multiplier coefficient for Cb"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CSC_COEFF3,RGB to YCbCr 4:2:2 CSC Coefficient 3 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " C6 ,Two complement red multiplier coefficient for Cr"
|
|
hexmask.long.word 0x00 0.--9. 1. " C5 ,Two complement blue multiplier coefficient for Cb"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CSC_COEFF4,RGB to YCbCr 4:2:2 CSC Coefficient 4 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " C8 ,Two complement blue multiplier coefficient for Cr"
|
|
hexmask.long.word 0x00 0.--9. 1. " C7 ,Two complement green multiplier coefficient for Cr"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CSC_OFFSET,RGB to YCbCr 4:2:2 CSC Offset Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " CBCR_OFFSET ,Two complement offset for the Cb and Cr components"
|
|
hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Two complement offset for the Y component"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CSC_LIMIT,RGB to YCbCr 4:2:2 CSC Limit Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CBCR_MIN ,Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CBCR_MAX ,Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " Y_MIN ,Lower limit of Y after RGB to 4:2:2 YCbCr conversion"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Y_MAX ,Upper limit of Y after RGB to 4:2:2 YCbCr conversion"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DATA,LCD Interface Data Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA_THREE ,Byte 3 (most significant byte) of data written to LCDIF by the CPU"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA_TWO ,Byte 2 of data written to LCDIF by the CPU"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA_ONE ,Byte 1 of data written to LCDIF by the CPU"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA_ZERO ,Byte 0 (least significant byte) of data written to LCDIF by the CPU"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "BM_ERROR_STAT,Bus Master Error Status Register"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CRC_STAT,CRC Status Register"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "STAT,LCD Interface Status Register"
|
|
bitfld.long 0x00 31. " PRESENT ,LCDIF is present" "Not present,Present"
|
|
bitfld.long 0x00 30. " DMA_REQ ,Reflects the current state of the DMA Request line for the LCDIF" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 29. " LFIFO_FULL ,LCD read datapath FIFO is full" "Not full,Full"
|
|
bitfld.long 0x00 28. " LFIFO_EMPTY ,LCD read datapath FIFO is empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 27. " TXFIFO_FULL ,LCD write datapath FIFO is full" "Not full,Full"
|
|
bitfld.long 0x00 26. " TXFIFO_EMPTY ,LCD write datapath FIFO is empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUSY ,View of the input busy signal from the external LCD controller" "Not busy,Busy"
|
|
bitfld.long 0x00 24. " DVI_CURRENT_FIELD ,View of the current field being transmitted" "Field 1,Field 2"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " LFIFO_COUNT ,LFIFO Latency Buffer Current Count"
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "VERSION,LCD Interface Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of RTL version"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of RTL version"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of RTL version"
|
|
rgroup.long 0x1D0++0x03
|
|
line.long 0x00 "DEBUG0,LCD Interface Debug 0 Register"
|
|
bitfld.long 0x00 31. " STREAMING_END_DETECTED ,view of the DOTCLK_MODE or DVI_MODE bit going from 1 to 0" "0,1"
|
|
bitfld.long 0x00 30. " WAIT_FOR_VSYNC_EDGE_OUT ,view of WAIT_FOR_VSYNC_EDGE bit in the VSYNC mode after it comes out of the TXFIFO" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SYNC_SIGNALS_ON_REG ,View of internal sync_signals_on_reg signal" "0,1"
|
|
bitfld.long 0x00 28. " DMACMDKICK ,View of the DMA command kick signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ENABLE ,View of ENABLE signal" "0,1"
|
|
bitfld.long 0x00 26. " HSYNC ,View of HSYNC signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " VSYNC ,View of VSYNC signal" "0,1"
|
|
bitfld.long 0x00 24. " CUR_FRAME_TX ,Current Frame is being transmitted in the VSYNC mode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EMPTY_WORD ,Indicates that the current word is empty" "Not empty,Empty"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CUR_STATE ,View of the current state machine state in the current mode of operation"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PXP_LCDIF_B0_READY ,Buffer0 ready signal issued by ePXP" "Not ready,Ready"
|
|
bitfld.long 0x00 14. " PXP_B0_DONE ,Buffer0 done signal issued by eLCDIF" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PXP_LCDIF_B1_READY ,Buffer1 ready signal issued by ePXP" "Not ready,Ready"
|
|
bitfld.long 0x00 12. " PXP_B1_DONE ,Buffer1 done signal issued by eLCDIF" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CUR_REQ_STATE ,Read only view of the request state machine" "0,1,2,3"
|
|
bitfld.long 0x00 9. " MST_AVALID ,view of the mst_avalid signal issued by the AXI bus master" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--8. " MST_OUTSTANDING_REQS ,view of the current outstanding requests issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--3. " MST_WORDS ,view of the current bursts issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "DEBUG1,LCD Interface Debug 1 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " H_DATA_COUNT ,View of the current state of the horizontal data counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " V_DATA_COUNT ,view of the current state of the vertical data counter"
|
|
rgroup.long 0x1F0++0x03
|
|
line.long 0x00 "DEBUG2,LCD Interface Debug2 Register"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "THRES,Threshold Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " FASTCLOCK ,High limit of the pixel FIFO pixel count for raising the fast clock control output"
|
|
hexmask.long.word 0x00 0.--8. 1. " PANIC ,High limit of the pixel FIFO pixel count for raising the panic control output"
|
|
width 0xb
|
|
tree.end
|
|
tree "OCOTP (On-Chip OTP Controller)"
|
|
base ad:0x41002000
|
|
width 11.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CTRL,OTP Controller Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable [key: 0x3E77]"
|
|
bitfld.long 0x00 13. " RELOAD_SHADOWS ,Re-loading the shadow registers" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RD_BANK_OPEN ,Open all OTP banks for reading" "Not open,Open"
|
|
bitfld.long 0x00 9. " ERROR ,Accessing to locked region error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BUSY ,OTP controller status bit" "Not busy,Busy"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ADDR ,OTP write and read access address register"
|
|
line.long 0x04 "CTRL_SET,OTP Controller Control Set Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable"
|
|
bitfld.long 0x04 13. " RELOAD_SHADOWS ,Re-loading the shadow registers" "Not effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 12. " RD_BANK_OPEN ,Open all OTP banks for reading" "Not effect,Set"
|
|
bitfld.long 0x04 9. " ERROR ,Accessing to locked region error" "Not effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 8. " BUSY ,OTP controller status bit" "Not effect,Set"
|
|
hexmask.long.byte 0x04 0.--5. 1. " ADDR ,OTP write and read access address register"
|
|
line.long 0x08 "CTRL_CLR,OTP Controller Control Clear Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable"
|
|
bitfld.long 0x08 13. " RELOAD_SHADOWS ,Re-loading the shadow registers" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 12. " RD_BANK_OPEN ,Open all OTP banks for reading" "No effect,Cleared"
|
|
bitfld.long 0x08 9. " ERROR ,Accessing to locked region error" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 8. " BUSY ,OTP controller status bit" "No effect,Cleared"
|
|
hexmask.long.byte 0x08 0.--5. 1. " ADDR ,OTP write and read access address register"
|
|
line.long 0x0c "CTRL_TOG,OTP Controller Control Toggle Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " WR_UNLOCK ,OTP write accesses enable"
|
|
bitfld.long 0x0C 13. " RELOAD_SHADOWS ,Re-loading the shadow registers" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " RD_BANK_OPEN ,Open all OTP banks for reading" "Not toggle,Toggle"
|
|
bitfld.long 0x0C 9. " ERROR ,Accessing to locked region error" "Not toggle,Toggle"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " BUSY ,OTP controller status bit" "Not toggle,Toggle"
|
|
hexmask.long.byte 0x0C 0.--5. 1. " ADDR ,OTP write and read access address register"
|
|
line.long 0x10 "TIMING,OTP Controller Timing Register"
|
|
bitfld.long 0x10 16.--21. " RD_BUSY ,Time to wait while the banks are busy after requesting a read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " RELAX ,Time to add to all default timing parameters other than the Tpgm and Trd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x10 0.--11. 1. " SCLK_COUNT ,SCLK High Time"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DATA,OTP Controller Write Data Register"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "LOCK,Value of OTP Bank0 Word0"
|
|
bitfld.long 0x00 26.--31. " UNALLOCATED ,Value of un-used portion of LOCK word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 25. " PIN ,Status of Pin access lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " DCPKEY_ALT ,Status of read lock bit for DCP APB crypto key access" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SCC_ALT ,Status of alternate bit for SCC lock" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " DCPKEY ,Status of read lock bit for DCP APB crypto key access" "Not locked,Locked"
|
|
bitfld.long 0x00 21. " SWCAP_SHADOW ,Status of shadow register lock for the region contained in the SWCAP registers" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SWCAP ,Status of register lock for the fuse region contained in the SWCAP registers" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " HWCAP_SHADOW ,Status of shadow register lock for the region contained in the HWCAP registers" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " HWCAP ,Status of register lock for the fuse region contained in the CRYPTO registers" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MAC_SHADOW ,Status of shadow register lock for the region contained in the MAC registers" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " MAC ,Status of register lock for the fuse region contained in the MAC registers" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " SJC_SHADOW ,Status of shadow register lock for the fuse region contained in the SJC (sjc_response) registers" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SJC ,Status of register lock for the region contained in the SJC (sjc_response) registers" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " SRK_SHADOW ,Status of shadow register lock for the region contained in the SRK registers" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " SRK ,Status of register lock for the fuse region contained in the SRK registers" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SCC_SHADOW ,Status of shadow register lock for the region contained in the SCC registers" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " SCC ,Status of register lock for the fuse region contained in the SCC registers" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " GP_SHADOW ,Status of shadow register lock for the region contained in the GP (General Purpose) registers" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GP ,Status of register lock for the fuse region contained in the GP (General Purpose)" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " MEM_MISC_SHADOW ,Status of shadow register lock for the region contained in the MEM registers 5-6" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " MEM_TRIM_SHADOW ,Status of shadow register lock for the region contained in the MEM registers 0-4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MEM_TRIM ,Status of register lock for the fuse region contained in the MEM registers 0-4" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " CFG_MISC_SHADOW ,Status of shadow register lock for the region contained in the CFG registers 5-6" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " CFG_BOOT_SHADOW ,Status of shadow register lock for the region contained in the CFG registers 3-4" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CFG_BOOT ,Status of register lock for the fuse region contained in the CFG registers 3-4" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " CFG_TESTER_SHADOW ,Status of shadow register lock for the region contained in the CFG registers 0-2" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " CFG_TESTER ,Status of register lock for the fuse region contained in the CFG registers 0-2" "Not locked,Locked"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CFG0,Value of OTP Bank0 Word1"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CFG1,Value of OTP Bank0 Word2"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CFG2,Value of OTP Bank0 Word3"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CFG3,Value of OTP Bank0 Word4"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CFG4,Value of OTP Bank0 Word5"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CFG5,Value of OTP Bank0 Word6"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CFG6,Value of OTP Bank0 Word7"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "MEM0,Value of OTP Bank1 Word0"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "MEM1,Value of OTP Bank1 Word1"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "MEM2,Value of OTP Bank1 Word2"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "MEM3,Value of OTP Bank1 Word3"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "MEM4,Value of OTP Bank1 Word4"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MEM5,Value of OTP Bank1 Word5"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "GP0,Value of OTP Bank1 Word6"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "GP1,Value of OTP Bank1 Word7"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "SCC0,Shadow Register for OTP Bank2 Word0"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SCC1,Shadow Register for OTP Bank2 Word1"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "SCC2,Shadow Register for OTP Bank2 Word2"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "SCC3,Shadow Register for OTP Bank2 Word3"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "SCC4,Shadow Register for OTP Bank2 Word4"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SCC5,Shadow Register for OTP Bank2 Word5"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SCC6,Shadow Register for OTP Bank2 Word6"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "SCC7,Shadow Register for OTP Bank2 Word7"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "SRK0,Shadow Register for OTP Bank3 Word0"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "SRK1,Shadow Register for OTP Bank3 Word1"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "SRK2,Shadow Register for OTP Bank3 Word2"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SRK3,Shadow Register for OTP Bank3 Word3"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "SRK4,Shadow Register for OTP Bank3 Word4"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SRK5,Shadow Register for OTP Bank3 Word5"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "SRK6,Shadow Register for OTP Bank3 Word6"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "SRK7,Shadow Register for OTP Bank3 Word7"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "SJC_RESP0,Value of OTP Bank4 Word0"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "SJC_RESP1,Value of OTP Bank4 Word1"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "MAC0,Value of OTP Bank4 Word2"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "MAC1,Value of OTP Bank4 Word3"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "HWCAP0,Value of OTP Bank4 Word4"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "HWCAP1,Value of OTP Bank4 Word5"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "HWCAP2,Value of OTP Bank4 Word6"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "SWCAP,Value of OTP Bank4 Word7"
|
|
group.long 0x2B0++0x0F
|
|
line.long 0x00 "SCS,Software Controllable Signals Register"
|
|
bitfld.long 0x00 31. " LOCK ,SCS register software programming lock" "Not locked,Locked"
|
|
hexmask.long 0x00 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use"
|
|
bitfld.long 0x00 0. " HAB_JDE ,HAB JTAG Debug Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SCS_SET,Software Controllable Signals Set Register"
|
|
bitfld.long 0x04 31. " LOCK ,SCS register software programming lock" "Not effect,Set"
|
|
hexmask.long 0x04 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use"
|
|
bitfld.long 0x04 0. " HAB_JDE ,HAB JTAG Debug Enable" "Not effect,Set"
|
|
line.long 0x08 "SCS_CLR,Software Controllable Signals Clear Register"
|
|
bitfld.long 0x08 31. " LOCK ,SCS register software programming lock" "Not effect,Cleared"
|
|
hexmask.long 0x08 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use"
|
|
bitfld.long 0x08 0. " HAB_JDE ,HAB JTAG Debug Enable" "Not effect,Cleared"
|
|
line.long 0x0C "SCS_TOG,Software Controllable Signals Toggle Register"
|
|
bitfld.long 0x0C 31. " LOCK ,SCS register software programming lock" "Not toggle,Toggle"
|
|
hexmask.long 0x0C 1.--30. 1. " SPARE ,Unallocated read/write bits for implementation specific software use"
|
|
bitfld.long 0x0C 0. " HAB_JDE ,HAB JTAG Debug Enable" "Not toggle,Toggle"
|
|
rgroup.long 0x2C0++0x03
|
|
line.long 0x00 "VERSION,OTP Controller Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version"
|
|
hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version"
|
|
width 11.
|
|
tree.end
|
|
tree "OWIRE (1-Wire Block)"
|
|
base ad:0x63fa4000
|
|
width 14.
|
|
group.word 0x00++0x9
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
bitfld.word 0x00 7. " RPP ,Reset presence pulse" "No Pulse,Pulse"
|
|
rbitfld.word 0x00 6. " PST ,Presence status" "Not present,Present"
|
|
bitfld.word 0x00 5. " WR0 ,Write 0" "No effect,Written"
|
|
textline " "
|
|
bitfld.word 0x00 4. " WR1 ,Write 1 / Read" "No effect,Written"
|
|
rbitfld.word 0x00 3. " RDST ,Read status" "0,1"
|
|
line.word 0x02 "TIME_DIVIDER,Time Divider Register"
|
|
hexmask.word.byte 0x02 0.--7. 1. " DVDR ,Pre-divider factor"
|
|
line.word 0x04 "RESET,Reset Register"
|
|
bitfld.word 0x04 0. " RST ,Software reset" "No reset,Reset"
|
|
line.word 0x06 "COMMAND,Command Register"
|
|
bitfld.word 0x06 1. " SRA ,Search ROM accelerator" "Deactivated,Switched"
|
|
line.word 0x08 "TX/RX,Transmit/Receive Register"
|
|
hexmask.word.byte 0x08 0.--7. 1. " DATA ,Data byte"
|
|
hgroup.word 0x0A++0x1
|
|
hide.word 0x00 "INTERRUPT,Interrupt Register"
|
|
in
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "INT_EN,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " ERSF ,Receive shift register full interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " ERBF ,Receive buffer full interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " ETSE ,Transmit shift register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ETBE ,Transmit buffer empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " IAS ,Interrupt trigger active state" "Active high,Active low"
|
|
bitfld.word 0x00 0. " EPD ,Presence detect interrupt enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "PERFMON (Performance Monitor)"
|
|
base ad:0x41014000
|
|
width 16.
|
|
group.long 0x00++0x0F
|
|
line.long 0x0 "CTRL,Control Register "
|
|
bitfld.long 0x0 31. " SFTRST ,Reset status" "No reset,Reset"
|
|
bitfld.long 0x0 30. " CLKGATE ,Clocks gate-off" "No,Yes"
|
|
hexmask.long.byte 0x0 16.--23. 1. " IRQ_MID ,Master ID and sub ID associated with the interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 12. " BUS_ERR_IRQ ,AXI transaction error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 11. " LATENCY_IRQ ,Latency threshold interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 10. " TRAP_IRQ ,Address trap interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 9. " BUS_ERR_IRQ_EN ,AXI transaction error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " LATENCY_IRQ_EN ,Latency threshold interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " TRAP_IRQ_EN ,Address trap interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " LATENCY_ENABLE ,PerfMon AXI Latency Threshold Functions Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " TRAP_IN_RANGE ,Debug trap function master address match range select" "Outside range,Inside range"
|
|
bitfld.long 0x0 4. " TRAP_ENABLE ,PerfMon AXI Address Trap functions enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " READ_EN ,Transaction type monitor select" "WRITE,READ"
|
|
bitfld.long 0x0 2. " CLR ,PerfMon Statistics registers clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 1. " SNAP ,Snapshot statistics into shadow registers" "No snapshot,Snapshot"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RUN ,PerfMon operation enable" "Disabled,Enabled"
|
|
line.long 0x4 "CTRL_SET,Control Register Set"
|
|
bitfld.long 0x4 31. " SFTRST ,Reset status" "No effect,Set"
|
|
bitfld.long 0x4 30. " CLKGATE ,Clocks gate-off" "No effect,Set"
|
|
hexmask.long.byte 0x4 16.--23. 1. " IRQ_MID ,Master ID and sub ID associated with the interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 12. " BUS_ERR_IRQ ,AXI transaction error interrupt" "No effect,Set"
|
|
bitfld.long 0x4 11. " LATENCY_IRQ ,Latency threshold interrupt" "No effect,Set"
|
|
bitfld.long 0x4 10. " TRAP_IRQ ,Address trap interrupt" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x4 9. " BUS_ERR_IRQ_EN ,AXI transaction error interrupt enable" "No effect,Set"
|
|
bitfld.long 0x4 8. " LATENCY_IRQ_EN ,Latency threshold interrupt enable" "No effect,Set"
|
|
bitfld.long 0x4 7. " TRAP_IRQ_EN ,Address trap interrupt enable" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x4 6. " LATENCY_ENABLE ,PerfMon AXI Latency Threshold Functions Enable" "No effect,Set"
|
|
bitfld.long 0x4 5. " TRAP_IN_RANGE ,Debug trap function master address match range select" "No effect,Set"
|
|
bitfld.long 0x4 4. " TRAP_ENABLE ,PerfMon AXI Address Trap functions enable" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x4 3. " READ_EN ,Transaction type monitor select" "No effect,Set"
|
|
bitfld.long 0x4 2. " CLR ,PerfMon Statistics registers clear" "No effect,Set"
|
|
bitfld.long 0x4 1. " SNAP ,Snapshot statistics into shadow registers" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x4 0. " RUN ,PerfMon operation enable" "No effect,Set"
|
|
line.long 0x8 "CTRL_CLR,Control Register Clear"
|
|
bitfld.long 0x8 31. " SFTRST ,Reset status" "No effect,Cleared"
|
|
bitfld.long 0x8 30. " CLKGATE ,Clocks gate-off" "No effect,Cleared"
|
|
hexmask.long.byte 0x8 16.--23. 1. " IRQ_MID ,Master ID and sub ID associated with the interrupt"
|
|
textline " "
|
|
bitfld.long 0x8 12. " BUS_ERR_IRQ ,AXI transaction error interrupt" "No effect,Cleared"
|
|
bitfld.long 0x8 11. " LATENCY_IRQ ,Latency threshold interrupt" "No effect,Cleared"
|
|
bitfld.long 0x8 10. " TRAP_IRQ ,Address trap interrupt" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x8 9. " BUS_ERR_IRQ_EN ,AXI transaction error interrupt enable" "No effect,Cleared"
|
|
bitfld.long 0x8 8. " LATENCY_IRQ_EN ,Latency threshold interrupt enable" "No effect,Cleared"
|
|
bitfld.long 0x8 7. " TRAP_IRQ_EN ,Address trap interrupt enable" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x8 6. " LATENCY_ENABLE ,PerfMon AXI Latency Threshold Functions Enable" "No effect,Cleared"
|
|
bitfld.long 0x8 5. " TRAP_IN_RANGE ,Debug trap function master address match range select" "No effect,Cleared"
|
|
bitfld.long 0x8 4. " TRAP_ENABLE ,PerfMon AXI Address Trap functions enable" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x8 3. " READ_EN ,Transaction type monitor select" "No effect,Cleared"
|
|
bitfld.long 0x8 2. " CLR ,PerfMon Statistics registers clear" "No effect,Cleared"
|
|
bitfld.long 0x8 1. " SNAP ,Snapshot statistics into shadow registers" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x8 0. " RUN ,PerfMon operation enable" "No effect,Cleared"
|
|
line.long 0xC "CTRL_TOG,Control Register Toggle"
|
|
bitfld.long 0xC 31. " SFTRST ,Reset status" "Not toggled,Toggled"
|
|
bitfld.long 0xC 30. " CLKGATE ,Clocks gate-off" "Not toggled,Toggled"
|
|
hexmask.long.byte 0xC 16.--23. 1. " IRQ_MID ,Master ID and sub ID associated with the interrupt"
|
|
textline " "
|
|
bitfld.long 0xC 12. " BUS_ERR_IRQ ,AXI transaction error interrupt" "Not toggled,Toggled"
|
|
bitfld.long 0xC 11. " LATENCY_IRQ ,Latency threshold interrupt" "Not toggled,Toggled"
|
|
bitfld.long 0xC 10. " TRAP_IRQ ,Address trap interrupt" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0xC 9. " BUS_ERR_IRQ_EN ,AXI transaction error interrupt enable" "Not toggled,Toggled"
|
|
bitfld.long 0xC 8. " LATENCY_IRQ_EN ,Latency threshold interrupt enable" "Not toggled,Toggled"
|
|
bitfld.long 0xC 7. " TRAP_IRQ_EN ,Address trap interrupt enable" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0xC 6. " LATENCY_ENABLE ,PerfMon AXI Latency Threshold Functions Enable" "Not toggled,Toggled"
|
|
bitfld.long 0xC 5. " TRAP_IN_RANGE ,Debug trap function master address match range select" "Not toggled,Toggled"
|
|
bitfld.long 0xC 4. " TRAP_ENABLE ,PerfMon AXI Address Trap functions enable" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0xC 3. " READ_EN ,Transaction type monitor select" "Not toggled,Toggled"
|
|
bitfld.long 0xC 2. " CLR ,PerfMon Statistics registers clear" "Not toggled,Toggled"
|
|
bitfld.long 0xC 1. " SNAP ,Snapshot statistics into shadow registers" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0xC 0. " RUN ,PerfMon operation enable" "Not toggled,Toggled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MASTER_EN,Master Enable Register"
|
|
bitfld.long 0x00 11. " MSHC ,Performance monitoring and statistics collection on MSHC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FEC ,Performance monitoring and statistics collection on FEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SDMA ,Performance monitoring and statistics collection on SDMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " eLCDIF ,Performance monitoring and statistics collection on eLCDIF enable" "Disabled,Enabled"
|
|
sif cpuis("IMX502")||cpuis("IMX503")
|
|
bitfld.long 0x00 6. " AHBMAX ,Performance monitoring and statistics collection on AHBMAX enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 7. " EPDC ,Performance monitoring and statistics collection on EPDC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " AHBMAX ,Performance monitoring and statistics collection on AHBMAX enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " BCH32 ,Performance monitoring and statistics collection on BCH32 enable" "Disabled,Enabled"
|
|
sif cpuis("IMX502")||cpuis("IMX507")
|
|
bitfld.long 0x00 3. " USBOH1 ,Performance monitoring and statistics collection on USBOH1 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 4. " GPU2D ,Performance monitoring and statistics collection on GPU2D enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " USBOH1 ,Performance monitoring and statistics collection on USBOH1 enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " ePXP ,Performance monitoring and statistics collection on ePXP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DCO ,Performance monitoring and statistics collection on DCP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ARM ,Performance monitoring and statistics collection on ARM Core enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TRAP_ADDR_LOW,Trap Range Low Address Register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TRAP_ADDR_HIGH,Trap Range High Address Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "LAT_THRESHOLD,Latency Threshold Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VALUE ,12-bit transaction latency threshold"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ACTIVE_CYCLE,Active Cycle Count Register"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "TRANSFER_COUNT,Transfer Count Register"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TOTAL_LATENCY,Total Latency Count Register"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "DATA_COUNT,Total Data Count Register"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "MAX_LATENCY,Maximum Latency Register"
|
|
bitfld.long 0x00 30.--31. " ADBURST ,axi_adburst signal associated with the worst latency transaction" "0,1,2,3"
|
|
bitfld.long 0x00 26.--29. " ALEN ,axi_alen signal associated with the worst latency transaction" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
bitfld.long 0x00 23.--25. " ASIZE ,axi_asize signal associated with the worst latency transaction" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x00 15.--22. 1. " TAGID ,Master ID and Sub ID associated with the worst latency transaction"
|
|
hexmask.long.word 0x00 0.--11. 1. " COUNT ,Worst transfer latency"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DEBUG,Debug Register"
|
|
bitfld.long 0x00 1. " TOTAL_CYCLE_CLR_EN ,Internal Total Cycle Register Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ERR_MID ,Bus Error IRQ MID Record" "Disabled,Enabled"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Major version"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Minor version"
|
|
textline " "
|
|
hexmask.long.byte 0x00 24.--31. 1. " STEP ,Stepping"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "PWM (Pulse Width Modulation)"
|
|
tree "PWM1"
|
|
base ad:0x53FB4000
|
|
width 8.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots"
|
|
bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped"
|
|
bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped"
|
|
bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k"
|
|
hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value"
|
|
bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PWMSR,PWM Status Register"
|
|
eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark"
|
|
textline " "
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..."
|
|
else
|
|
bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..."
|
|
endif
|
|
line.long 0x08 "PWMIR,PWM Interrupt Register"
|
|
bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
if (((per.l(ad:0x53FB4000+0x00))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PWMPR,PWM Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "PWMCNR,PWM Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWM2"
|
|
base ad:0x53FB8000
|
|
width 8.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots"
|
|
bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped"
|
|
bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped"
|
|
bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k"
|
|
hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value"
|
|
bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PWMSR,PWM Status Register"
|
|
eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark"
|
|
textline " "
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..."
|
|
else
|
|
bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..."
|
|
endif
|
|
line.long 0x08 "PWMIR,PWM Interrupt Register"
|
|
bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
if (((per.l(ad:0x53FB8000+0x00))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PWMPR,PWM Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "PWMCNR,PWM Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "ePXP (Enhanced Pixel Pipeline)"
|
|
base ad:0x4100C000
|
|
width 15.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "CTRL,Control Register 0"
|
|
bitfld.long 0x00 31. " SFTRST ,Clocks with the PXP and holds LP state" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Not gated,Gated"
|
|
bitfld.long 0x00 28. " EN_REPEAT ,Enable the PXP to run continuously" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " INTERLACED_OUTPUT ,Output data write method" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " INTERLACED_INPUT ,Input data fetch method" "PROGRESSIVE,Reserved,FIELD0,FIELD1"
|
|
bitfld.long 0x00 23. " BLOCK_SIZE ,Select the block size to process" "8x8,16x16"
|
|
bitfld.long 0x00 22. " ALPHA_OUTPUT ,Alpha component override with PXP_OUTSIZE[ALPHA]" "Retain,Override"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IN_PLACE ,Alpha blend operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CROP ,Output image crop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SCALE ,Output image scale enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " S0_FORMAT ,Source 0 buffer format" "Reserved,RGB888,Reserved,Reserved,RGB565,RGB555,Reserved,Reserved,YUV422,YUV420,UYVY1P422,VYUY1P422,YUV2P422,YUV2P420,YVU2P422,YVU2P420"
|
|
bitfld.long 0x00 11. " VFLIP ,Output buffer flipped vertically" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HFLIP ,Output buffer flipped horizontally" "No,Yes"
|
|
bitfld.long 0x00 8.--9. " ROTATE ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270"
|
|
bitfld.long 0x00 4.--7. " OUTBUF_FORMAT ,Output framebuffer format" "ARGB8888,RGB888,RGB888P,ARGB1555,RGB565,RGB555,Reserved,YUV444,MONOC8,MONOC4,UYVY1P422,VYUY1P422,YUV2P422,YUV2P420,YVU2P422,YVU2P420"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_LCD_HANDSHAKE ,Enable handshake with LCD controller" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEXT_IRQ_EN ,Next command interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRQ_EN ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Enables PXP operation with specified parameters" "Disabled,Enabled"
|
|
line.long 0x04 "CTRL_SET,Control Set Register 0"
|
|
bitfld.long 0x04 31. " SFTRST ,Clocks with the PXP and holds LP state set" "No effect,Set"
|
|
bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set"
|
|
bitfld.long 0x04 28. " EN_REPEAT ,Enable the PXP to run continuously" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 26.--27. " INTERLACED_OUTPUT ,Output data write method" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " INTERLACED_INPUT ,Input data fetch method" "PROGRESSIVE,Reserved,FIELD0,FIELD1"
|
|
bitfld.long 0x04 23. " BLOCK_SIZE ,Select the block size to process" "No effect,Set"
|
|
bitfld.long 0x04 22. " ALPHA_OUTPUT ,Alpha component override with PXP_OUTSIZE[ALPHA]" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 21. " IN_PLACE ,Alpha blend operation enable" "No effect,Set"
|
|
bitfld.long 0x04 19. " CROP ,Output image crop enable" "No effect,Set"
|
|
bitfld.long 0x04 18. " SCALE ,Output image scale enable" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " S0_FORMAT ,Source 0 buffer format" "Reserved,RGB888,Reserved,Reserved,RGB565,RGB555,Reserved,Reserved,YUV422,YUV420,UYVY1P422,VYUY1P422,YUV2P422,YUV2P420,YVU2P422,YVU2P420"
|
|
bitfld.long 0x04 11. " VFLIP ,Output buffer flipped vertically" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HFLIP ,Output buffer flipped horizontally" "No effect,Set"
|
|
bitfld.long 0x04 8.--9. " ROTATE ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270"
|
|
bitfld.long 0x04 4.--7. " OUTBUF_FORMAT ,Output framebuffer format" "ARGB8888,RGB888,RGB888P,ARGB1555,RGB565,RGB555,Reserved,YUV444,MONOC8,MONOC4,UYVY1P422,VYUY1P422,YUV2P422,YUV2P420,YVU2P422,YVU2P420"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ENABLE_LCD_HANDSHAKE ,Enable handshake with LCD controller" "No effect,Set"
|
|
bitfld.long 0x04 2. " NEXT_IRQ_EN ,Next command interrupt enable" "No effect,Set"
|
|
bitfld.long 0x04 1. " IRQ_EN ,Interrupt enable" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Enables PXP operation with specified parameters" "No effect,Set"
|
|
line.long 0x08 "CTRL_CLR,Control Clear Register 0"
|
|
bitfld.long 0x08 31. " SFTRST ,Clocks with the PXP and holds LP state" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Cleared"
|
|
bitfld.long 0x08 28. " EN_REPEAT ,Enable the PXP to run continuously" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 26.--27. " INTERLACED_OUTPUT ,Output data write method" "PROGRESSIVE,FIELD0,FIELD1,INTERLACED"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " INTERLACED_INPUT ,Input data fetch method" "PROGRESSIVE,Reserved,FIELD0,FIELD1"
|
|
bitfld.long 0x08 23. " BLOCK_SIZE ,Select the block size to process" "No effect,Cleared"
|
|
bitfld.long 0x08 22. " ALPHA_OUTPUT ,Alpha component override with PXP_OUTSIZE[ALPHA]" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " IN_PLACE ,Alpha blend operation enable" "No effect,Cleared"
|
|
bitfld.long 0x08 19. " CROP ,Output image crop enable" "No effect,Cleared"
|
|
bitfld.long 0x08 18. " SCALE ,Output image scale enable" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " S0_FORMAT ,Source 0 buffer format" "Reserved,RGB888,Reserved,Reserved,RGB565,RGB555,Reserved,Reserved,YUV422,YUV420,UYVY1P422,VYUY1P422,YUV2P422,YUV2P420,YVU2P422,YVU2P420"
|
|
bitfld.long 0x08 11. " VFLIP ,Output buffer flipped vertically" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HFLIP ,Output buffer flipped horizontally" "No effect,Cleared"
|
|
bitfld.long 0x08 8.--9. " ROTATE ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270"
|
|
bitfld.long 0x08 4.--7. " OUTBUF_FORMAT ,Output framebuffer format" "ARGB8888,RGB888,RGB888P,ARGB1555,RGB565,RGB555,Reserved,YUV444,MONOC8,MONOC4,UYVY1P422,VYUY1P422,YUV2P422,YUV2P420,YVU2P422,YVU2P420"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ENABLE_LCD_HANDSHAKE ,Enable handshake with LCD controller" "No effect,Celared"
|
|
bitfld.long 0x08 2. " NEXT_IRQ_EN ,Next command interrupt enable" "No effect,Cleared"
|
|
bitfld.long 0x08 1. " IRQ_EN ,Interrupt enable" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ENABLE ,Enables PXP operation with specified parameters" "No effect,Cleared"
|
|
line.long 0x0C "CTRL_TOG,Control Toggle Register 0"
|
|
bitfld.long 0x0C 31. " SFTRST ,Clocks with the PXP and holds LP state" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 30. " CLKGATE ,Gates off the clocks to the block" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 28. " EN_REPEAT ,Enable the PXP to run continuously" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " BLOCK_SIZE ,Select the block size to process" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 22. " ROT_POS ,Place of rotation in the PXP datapath" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 11. " VFLIP ,Output buffer flipped vertically" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " HFLIP ,Output buffer flipped horizontally" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 8.--9. " ROTATE ,Clockwise rotation at the output buffer" "ROT_0,ROT_90,ROT_180,ROT_270"
|
|
bitfld.long 0x0C 4. " EN_LCD_H ,Enable handshake with LCD controller" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " LUT_DMA_IRQ_EN ,LUT DMA interrupt enable" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 2. " NEXT_IRQ_EN ,Next command interrupt enable" "Not toggled,Toggled"
|
|
bitfld.long 0x0C 1. " IRQ_EN ,Interrupt enable" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " ENABLE ,Enables PXP operation with specified parameters" "Not toggled,Toggled"
|
|
line.long 0x10 "STAT,Status Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered"
|
|
hexmask.long.byte 0x10 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered"
|
|
textline " "
|
|
bitfld.long 0x10 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 3. " NEXT_IRQ ,Next Command issue" "Not issued,Issued"
|
|
bitfld.long 0x10 2. " AXI_READ_ERROR ,PXP encountered an AXI read error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x10 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error" "No error,Error"
|
|
bitfld.long 0x10 0. " IRQ ,Current PXP interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x14 "STAT_SET,Status Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered"
|
|
hexmask.long.byte 0x14 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 3. " NEXT_IRQ ,Next Command issue" "No effect,Set"
|
|
bitfld.long 0x14 2. " AXI_READ_ERROR ,PXP encountered an AXI read error" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x14 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error" "No effect,Set"
|
|
bitfld.long 0x14 0. " IRQ ,Current PXP interrupt status" "No effect,Set"
|
|
line.long 0x18 "STAT_CLR,Status Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered"
|
|
hexmask.long.byte 0x18 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered"
|
|
textline " "
|
|
bitfld.long 0x18 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 3. " NEXT_IRQ ,Next Command issue" "No effect,Cleared"
|
|
bitfld.long 0x18 2. " AXI_READ_ERROR ,PXP encountered an AXI read error" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x18 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error" "No effect,Cleared"
|
|
bitfld.long 0x18 0. " IRQ ,Current PXP interrupt status" "No effect,Cleared"
|
|
line.long 0x1C "STAT_TOG,Status Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered"
|
|
textline " "
|
|
bitfld.long 0x1C 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 3. " NEXT_IRQ ,Next Command issue" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 2. " AXI_READ_ERROR ,PXP encountered an AXI read error" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error" "Not toggled,Toggled"
|
|
bitfld.long 0x1C 0. " IRQ ,Current PXP interrupt status" "Not toggled,Toggled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "OUTBUF,Output Frame Buffer Pointer"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "OUTBUF2,Output Frame Buffer Pointer 2"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "OUTSIZE,Output Buffer Size"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ALPHA ,Alpha component"
|
|
hexmask.long.word 0x00 12.--23. 1. " WIDTH ,Number of horizontal pixels (non-rotated)"
|
|
hexmask.long.word 0x00 0.--11. 1. " HEIGHT ,Number of vertical pixels (non-rotated)"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "S0BUF,Source 0 Input Buffer Pointer (RGB/luma)"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "S0UBUF,Source 0 U/Cb or 2 Plane UV Input Buffer Pointer"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "S0VBUF,Source 0 V/Cr Input Buffer Pointer"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "S0PARAM,Source 0 (video) Buffer Parameters"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XBASE ,Horizontal offset location (NxN block)"
|
|
hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Vertical offset location (NxN block)"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Indicates number of horizontal NxN blocks in the image (non-rotated)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Indicates the number of vertical NxN blocks in the image (non-rotated)"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "S0BACKGROUND,Source 0 Background Color"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "S0CROP,Source 0 Cropping Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XBASE ,Horizontal offset location (NxN block)"
|
|
hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Vertical offset location (NxN block)"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Indicates number of horizontal NxN blocks in the image (non-rotated)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Indicates the number of vertical NxN blocks in the image (non-rotated)"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "S0SCALE,Source 0 Scale Factor Register"
|
|
hexmask.long.word 0x00 16.--30. 1. " YSCALE ,Y scaling factor for the S0 source buffer (fixed point [3].[12])"
|
|
hexmask.long.word 0x00 0.--14. 1. " XSCALE ,X scaling factor for the S0 source buffer (fixed point [3].[12])"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "S0OFFSET,Source 0 Scale Offset Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " YOFFSET ,Y scaling offset (fraction 0.[12])"
|
|
hexmask.long.word 0x00 0.--11. 1. " XOFFSET ,X scaling offset (fraction 0.[12])"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CSCCOEF0,Color Space Conversion Coefficient Register 0"
|
|
bitfld.long 0x00 31. " YCBCR_MODE ,Conversion mode" "YUV -> RGB,YCbCr -> RGB"
|
|
bitfld.long 0x00 30. " BYPASS ,Bypass the CSC unit in the scaling engine" "Not bypassed,Bypassed"
|
|
textline " "
|
|
hexmask.long.word 0x00 18.--28. 1. " C0 ,Two's complement Y multiplier coefficient"
|
|
hexmask.long.word 0x00 9.--17. 1. " UV_OFFSET ,Two's complement phase offset implicit for CbCr data"
|
|
hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Two's complement amplitude offset implicit in the Y data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CSCCOEF1,Color Space Conversion Coefficient Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " C1 ,Two's complement Red V/Cr multiplier coefficient"
|
|
hexmask.long.word 0x00 0.--10. 1. " C4 ,Two's complement Blue U/Cb multiplier coefficient"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CSCCOEF2,Color Space Conversion Coefficient Register 2"
|
|
hexmask.long.word 0x00 16.--26. 1. " C2 ,Two's complement Green V/Cr multiplier coefficient"
|
|
hexmask.long.word 0x00 0.--10. 1. " C3 ,Two's complement Green U/Cb multiplier coefficient"
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "NEXT,Next Frame Pointer"
|
|
hexmask.long 0x00 2.--31. 0x4 " POINTER ,Pointer to a data structure containing register values to be used when processing the next frame"
|
|
bitfld.long 0x00 0. " ENABLED ,Next frame functionality enable (reload operation)" "Disabled,Enabled"
|
|
line.long 0x04 "NEXT_SET,Next Frame Pointer"
|
|
hexmask.long 0x04 2.--31. 0x4 " POINTER ,Pointer to a data structure containing register values to be used when processing the next frame"
|
|
bitfld.long 0x04 0. " ENABLED ,Next frame functionality enable (reload operation)" "No effect,Set"
|
|
line.long 0x08 "NEXT_CLR,Next Frame Pointer"
|
|
hexmask.long 0x08 2.--31. 0x4 " POINTER ,Pointer to a data structure containing register values to be used when processing the next frame"
|
|
bitfld.long 0x08 0. " ENABLED ,Next frame functionality enable (reload operation)" "No effect,Cleared"
|
|
line.long 0x0C "NEXT_TOG,Next Frame Pointer"
|
|
hexmask.long 0x0C 2.--31. 0x4 " POINTER ,Pointer to a data structure containing register values to be used when processing the next frame"
|
|
bitfld.long 0x0C 0. " ENABLED ,Next frame functionality enable (reload operation)" "Not toggled,Toggled"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "S0COLORKEYLOW,S0 Color Key Low"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to S0 buffer"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "S0COLORKEYHIGH,S0 Color Key High"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to S0 buffer"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "OLCOLORKEYLOW,Overlay Color Key Low"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to OL buffer"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "OLCOLORKEYHIGH,Overlay Color Key High"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to OL buffer"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "DEBUG,Debug Register"
|
|
width 12.
|
|
tree "Overlay registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "OL0,Overlay 0 Buffer Pointer"
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "OL__SIZE0,Overlay 0 Size"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Indicates number of horizontal NxN blocks in the image (non-rotated)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Indicates the number of vertical NxN blocks in the image (non-rotated)"
|
|
if (d.l((ad:0x4100C000)+0x200+0x20)&0x6)==0x2||(d.l((ad:0x4100C000)+0x200+0x20)&0x6)==0x4
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM0,Overlay 0 Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 0 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
elif (d.l((ad:0x4100C000)+0x200+0x20)&0x6)==0x6
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM0,Overlay 0 Parameters"
|
|
bitfld.long 0x00 16.--19. " ROP ,Raster operation to be performed when enabled" "MASKOL,MASKNOTOL,MASKOLNOT,MERGEOL,MERGENOTOL,MERGEOLNOT,NOTCOPYOL,NOT,NOTMASKOL,MOTMERGEOL,XOROL,NOTXOROL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 0 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
else
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM0,Overlay 0 Parameters"
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 0 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "OL1,Overlay 1 Buffer Pointer"
|
|
group.long (0x220+0x10)++0x03
|
|
line.long 0x00 "OL__SIZE1,Overlay 1 Size"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Indicates number of horizontal NxN blocks in the image (non-rotated)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Indicates the number of vertical NxN blocks in the image (non-rotated)"
|
|
if (d.l((ad:0x4100C000)+0x220+0x20)&0x6)==0x2||(d.l((ad:0x4100C000)+0x220+0x20)&0x6)==0x4
|
|
group.long (0x220+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM1,Overlay 1 Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 1 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
elif (d.l((ad:0x4100C000)+0x220+0x20)&0x6)==0x6
|
|
group.long (0x220+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM1,Overlay 1 Parameters"
|
|
bitfld.long 0x00 16.--19. " ROP ,Raster operation to be performed when enabled" "MASKOL,MASKNOTOL,MASKOLNOT,MERGEOL,MERGENOTOL,MERGEOLNOT,NOTCOPYOL,NOT,NOTMASKOL,MOTMERGEOL,XOROL,NOTXOROL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 1 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
else
|
|
group.long (0x220+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM1,Overlay 1 Parameters"
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 1 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "OL2,Overlay 2 Buffer Pointer"
|
|
group.long (0x240+0x10)++0x03
|
|
line.long 0x00 "OL__SIZE2,Overlay 2 Size"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Indicates number of horizontal NxN blocks in the image (non-rotated)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Indicates the number of vertical NxN blocks in the image (non-rotated)"
|
|
if (d.l((ad:0x4100C000)+0x240+0x20)&0x6)==0x2||(d.l((ad:0x4100C000)+0x240+0x20)&0x6)==0x4
|
|
group.long (0x240+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM2,Overlay 2 Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 2 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
elif (d.l((ad:0x4100C000)+0x240+0x20)&0x6)==0x6
|
|
group.long (0x240+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM2,Overlay 2 Parameters"
|
|
bitfld.long 0x00 16.--19. " ROP ,Raster operation to be performed when enabled" "MASKOL,MASKNOTOL,MASKOLNOT,MERGEOL,MERGENOTOL,MERGEOLNOT,NOTCOPYOL,NOT,NOTMASKOL,MOTMERGEOL,XOROL,NOTXOROL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 2 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
else
|
|
group.long (0x240+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM2,Overlay 2 Parameters"
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 2 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "OL3,Overlay 3 Buffer Pointer"
|
|
group.long (0x260+0x10)++0x03
|
|
line.long 0x00 "OL__SIZE3,Overlay 3 Size"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Indicates number of horizontal NxN blocks in the image (non-rotated)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Indicates the number of vertical NxN blocks in the image (non-rotated)"
|
|
if (d.l((ad:0x4100C000)+0x260+0x20)&0x6)==0x2||(d.l((ad:0x4100C000)+0x260+0x20)&0x6)==0x4
|
|
group.long (0x260+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM3,Overlay 3 Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 3 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
elif (d.l((ad:0x4100C000)+0x260+0x20)&0x6)==0x6
|
|
group.long (0x260+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM3,Overlay 3 Parameters"
|
|
bitfld.long 0x00 16.--19. " ROP ,Raster operation to be performed when enabled" "MASKOL,MASKNOTOL,MASKOLNOT,MERGEOL,MERGENOTOL,MERGEOLNOT,NOTCOPYOL,NOT,NOTMASKOL,MOTMERGEOL,XOROL,NOTXOROL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 3 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
else
|
|
group.long (0x260+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM3,Overlay 3 Parameters"
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 3 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "OL4,Overlay 4 Buffer Pointer"
|
|
group.long (0x280+0x10)++0x03
|
|
line.long 0x00 "OL__SIZE4,Overlay 4 Size"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Indicates number of horizontal NxN blocks in the image (non-rotated)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Indicates the number of vertical NxN blocks in the image (non-rotated)"
|
|
if (d.l((ad:0x4100C000)+0x280+0x20)&0x6)==0x2||(d.l((ad:0x4100C000)+0x280+0x20)&0x6)==0x4
|
|
group.long (0x280+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM4,Overlay 4 Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 4 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
elif (d.l((ad:0x4100C000)+0x280+0x20)&0x6)==0x6
|
|
group.long (0x280+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM4,Overlay 4 Parameters"
|
|
bitfld.long 0x00 16.--19. " ROP ,Raster operation to be performed when enabled" "MASKOL,MASKNOTOL,MASKOLNOT,MERGEOL,MERGENOTOL,MERGEOLNOT,NOTCOPYOL,NOT,NOTMASKOL,MOTMERGEOL,XOROL,NOTXOROL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 4 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
else
|
|
group.long (0x280+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM4,Overlay 4 Parameters"
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 4 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "OL5,Overlay 5 Buffer Pointer"
|
|
group.long (0x2A0+0x10)++0x03
|
|
line.long 0x00 "OL__SIZE5,Overlay 5 Size"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Indicates number of horizontal NxN blocks in the image (non-rotated)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Indicates the number of vertical NxN blocks in the image (non-rotated)"
|
|
if (d.l((ad:0x4100C000)+0x2A0+0x20)&0x6)==0x2||(d.l((ad:0x4100C000)+0x2A0+0x20)&0x6)==0x4
|
|
group.long (0x2A0+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM5,Overlay 5 Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 5 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
elif (d.l((ad:0x4100C000)+0x2A0+0x20)&0x6)==0x6
|
|
group.long (0x2A0+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM5,Overlay 5 Parameters"
|
|
bitfld.long 0x00 16.--19. " ROP ,Raster operation to be performed when enabled" "MASKOL,MASKNOTOL,MASKOLNOT,MERGEOL,MERGENOTOL,MERGEOLNOT,NOTCOPYOL,NOT,NOTMASKOL,MOTMERGEOL,XOROL,NOTXOROL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 5 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
else
|
|
group.long (0x2A0+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM5,Overlay 5 Parameters"
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 5 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "OL6,Overlay 6 Buffer Pointer"
|
|
group.long (0x2C0+0x10)++0x03
|
|
line.long 0x00 "OL__SIZE6,Overlay 6 Size"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Indicates number of horizontal NxN blocks in the image (non-rotated)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Indicates the number of vertical NxN blocks in the image (non-rotated)"
|
|
if (d.l((ad:0x4100C000)+0x2C0+0x20)&0x6)==0x2||(d.l((ad:0x4100C000)+0x2C0+0x20)&0x6)==0x4
|
|
group.long (0x2C0+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM6,Overlay 6 Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 6 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
elif (d.l((ad:0x4100C000)+0x2C0+0x20)&0x6)==0x6
|
|
group.long (0x2C0+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM6,Overlay 6 Parameters"
|
|
bitfld.long 0x00 16.--19. " ROP ,Raster operation to be performed when enabled" "MASKOL,MASKNOTOL,MASKOLNOT,MERGEOL,MERGENOTOL,MERGEOLNOT,NOTCOPYOL,NOT,NOTMASKOL,MOTMERGEOL,XOROL,NOTXOROL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 6 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
else
|
|
group.long (0x2C0+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM6,Overlay 6 Parameters"
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 6 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "OL7,Overlay 7 Buffer Pointer"
|
|
group.long (0x2E0+0x10)++0x03
|
|
line.long 0x00 "OL__SIZE7,Overlay 7 Size"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Indicates number of horizontal NxN blocks in the image (non-rotated)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Indicates the number of vertical NxN blocks in the image (non-rotated)"
|
|
if (d.l((ad:0x4100C000)+0x2E0+0x20)&0x6)==0x2||(d.l((ad:0x4100C000)+0x2E0+0x20)&0x6)==0x4
|
|
group.long (0x2E0+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM7,Overlay 7 Parameters"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 7 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
elif (d.l((ad:0x4100C000)+0x2E0+0x20)&0x6)==0x6
|
|
group.long (0x2E0+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM7,Overlay 7 Parameters"
|
|
bitfld.long 0x00 16.--19. " ROP ,Raster operation to be performed when enabled" "MASKOL,MASKNOTOL,MASKOLNOT,MERGEOL,MERGENOTOL,MERGEOLNOT,NOTCOPYOL,NOT,NOTMASKOL,MOTMERGEOL,XOROL,NOTXOROL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 7 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
else
|
|
group.long (0x2E0+0x20)++0x03
|
|
line.long 0x00 "OL__PARAM7,Overlay 7 Parameters"
|
|
bitfld.long 0x00 4.--7. " FORMAT ,Overlay 7 input buffer format" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..."
|
|
bitfld.long 0x00 3. " ENABLE_COLORKEY ,Colorkey functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Alpha value construction for this overlay" "Embedded,Override,Multiply,ROPs"
|
|
bitfld.long 0x00 0. " ENABLE ,Overlay active" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 15.
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "CSC2CTRL,Color Space Conversion Control Register"
|
|
bitfld.long 0x00 1.--2. " CSC_MODE ,Methods of CSC unit operates on pixels when the CSC is not bypassed (converted from)" "YUV to RGB,YCbCr to RGB,RGB to YUV,RGB to YCbCr"
|
|
bitfld.long 0x00 0. " BYPASS ,Bypass CSC2 unit" "Not bypassed,Bypassed"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "CSC2COEF0,Color Space Conversion Coefficient Register 0"
|
|
hexmask.long.word 0x00 16.--26. 1. " A2 ,Two's complement coefficient offset"
|
|
hexmask.long.word 0x00 0.--10. 1. " A1 ,Two's complement coefficient offset"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "CSC2COEF1,Color Space Conversion Coefficient Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " B1 ,Two's complement coefficient offset"
|
|
hexmask.long.word 0x00 0.--10. 1. " A3 ,Two's complement coefficient offset"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "CSC2COEF2,Color Space Conversion Coefficient Register 2"
|
|
hexmask.long.word 0x00 16.--26. 1. " B3 ,Two's complement coefficient offset"
|
|
hexmask.long.word 0x00 0.--10. 1. " B2 ,Two's complement coefficient offset"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "CSC2COEF3,Color Space Conversion Coefficient Register 3"
|
|
hexmask.long.word 0x00 16.--26. 1. " C2 ,Two's complement coefficient offset"
|
|
hexmask.long.word 0x00 0.--10. 1. " C1 ,Two's complement coefficient offset"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "CSC2COEF4,Color Space Conversion Coefficient Register 4"
|
|
hexmask.long.word 0x00 16.--24. 1. " D1 ,Two's complement coefficient integer offset to be added"
|
|
hexmask.long.word 0x00 0.--10. 1. " C3 ,Two's complement coefficient offset"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "CSC2COEF5,Color Space Conversion Coefficient Register 5"
|
|
hexmask.long.word 0x00 16.--24. 1. " D3 ,Two's complement coefficient integer offset to be added"
|
|
hexmask.long.word 0x00 0.--8. 1. " D2 ,Two's complement D1 coefficient integer offset to be added"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "LUT_CTRL,Lookup Table Control Register"
|
|
bitfld.long 0x00 31. " BYPASS ,bypass the LUT memory resource completely" "Not bypassed,Bypassed"
|
|
hexmask.long.word 0x00 0.--13. 1. " ADDR ,LUT indexed address pointer"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "LUT,Lookup Table Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Lookup Table Data"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "HIST_CTRL,Histogram Control Register"
|
|
bitfld.long 0x00 4.--5. " PANEL_MODE ,Specifies the EPDC panel grayscale depth" "4-bit,8-bit,16-bit,32-bit"
|
|
bitfld.long 0x00 3. " STATUS[3] ,Bitmap pixels were fully contained within the 4-bit grayscale histogram" "Not contained,Contained"
|
|
bitfld.long 0x00 2. " STATUS[2] ,Bitmap pixels were fully contained within the 3-bit grayscale histogram" "Not contained,Contained"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STATUS[1] ,Bitmap pixels were fully contained within the 2-bit grayscale histogram" "Not contained,Contained"
|
|
bitfld.long 0x00 0. " STATUS[0] ,Bitmap pixels were fully contained within the black/white histogram" "Not contained,Contained"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "HIST2_PARAM,2-level Histogram Parameter Register"
|
|
bitfld.long 0x00 8.--12. " VALUE1 ,White value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " VALUE0 ,Black value for 2-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "HIST4_PARAM,4-level Histogram Parameter Register"
|
|
bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 (White) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 4-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "HIST8_PARAM0,8-level Histogram Parameter 0 Register"
|
|
bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "HIST8_PARAM1,-level Histogram Parameter 1 Register"
|
|
bitfld.long 0x00 24.--28. " VALUE7 ,GRAY7 (White) value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " VALUE6 ,GRAY6 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " VALUE5 ,GRAY5 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " VALUE4 ,GRAY4 value for 8-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "HIST16_PARAM0,16-level Histogram Parameter 0 Register"
|
|
bitfld.long 0x00 24.--28. " VALUE3 ,GRAY3 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " VALUE2 ,GRAY2 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " VALUE1 ,GRAY1 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " VALUE0 ,GRAY0 (Black) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "HIST16_PARAM1,16-level Histogram Parameter 1 Register"
|
|
bitfld.long 0x00 24.--28. " VALUE7 ,GRAY7 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " VALUE6 ,GRAY6 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " VALUE5 ,GRAY5 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " VALUE4 ,GRAY4 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "HIST16_PARAM2,16-level Histogram Parameter 2 Register"
|
|
bitfld.long 0x00 24.--28. " VALUE11 ,GRAY11 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " VALUE10 ,GRAY10 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " VALUE9 ,GRAY9 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " VALUE8 ,GRAY8 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "HIST16_PARAM3,16-level Histogram Parameter 3 Register"
|
|
bitfld.long 0x00 24.--28. " VALUE15 ,GRAY15 (White) value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " VALUE14 ,GRAY14 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. " VALUE13 ,GRAY13 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 0.--4. " VALUE12 ,GRAY12 value for 16-level histogram" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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width 0x0B
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tree.end
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tree "QOSC (Quality Of Service Controller)"
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base ad:0x41012000
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width 19.
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group.long 0x00++0x0F
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line.long 0x0 "CTRL,QoS Control Register "
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bitfld.long 0x0 31. " SFTRST ,Soft Reset" "No reset,Reset"
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bitfld.long 0x0 30. " CLKGATE ,Gate off the clocks" "No,Yes"
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textline " "
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bitfld.long 0x0 4.--5. " LCDIF_PRIORITY_BOOST ,eLCDIF Higher Priority Allow" "Disable,Inc priority,Highest priority,?..."
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bitfld.long 0x0 2.--3. " EPCD_PRIORITY_BOOST ,EPDC Higher Priority Allow" "Disable,Inc priority,Highest priority,?..."
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textline " "
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bitfld.long 0x0 1. " XLATE_AXI_MODE ,Translation AXI QoS info into EMI priority - Priority 0 allow" "Disallow,Allow"
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bitfld.long 0x0 0. " EMI_PRIORITY_MODE ,AXI and EMI priority values separation" "Passthrough,Manual"
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line.long 0x4 "CTRL_SET,QoS Control Register Set"
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bitfld.long 0x4 31. " SFTRST ,Soft Reset" "No effect,Set"
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bitfld.long 0x4 30. " CLKGATE ,Gate off the clocks" "No effect,Set"
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textline " "
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bitfld.long 0x4 4.--5. " LCDIF_PRIORITY_BOOST ,eLCDIF Higher Priority Allow" "No effect,Set,Set,Set"
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bitfld.long 0x4 2.--3. " EPCD_PRIORITY_BOOST ,EPDC Higher Priority Allow" "No effect,Set,Set,Set"
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textline " "
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bitfld.long 0x4 1. " XLATE_AXI_MODE ,Translation AXI QoS info into EMI priority - Priority 0 allow" "No effect,Set"
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bitfld.long 0x4 0. " EMI_PRIORITY_MODE ,AXI and EMI priority values separation" "No effect,Set"
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line.long 0x8 "CTRL_CLR,QoS Control Register Clear"
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bitfld.long 0x8 31. " SFTRST ,Soft ReCleared" "No effect,Cleared"
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bitfld.long 0x8 30. " CLKGATE ,Gate off the clocks" "No effect,Cleared"
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textline " "
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bitfld.long 0x8 4.--5. " LCDIF_PRIORITY_BOOST ,eLCDIF Higher Priority Allow" "No effect,Cleared,Cleared,Cleared"
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bitfld.long 0x8 2.--3. " EPCD_PRIORITY_BOOST ,EPDC Higher Priority Allow" "No effect,Cleared,Cleared,Cleared"
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textline " "
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bitfld.long 0x8 1. " XLATE_AXI_MODE ,Translation AXI QoS info into EMI priority - Priority 0 allow" "No effect,Cleared"
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bitfld.long 0x8 0. " EMI_PRIORITY_MODE ,AXI and EMI priority values separation" "No effect,Cleared"
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line.long 0xC "CTRL_TOG,QoS Control Register Toggle"
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bitfld.long 0xC 31. " SFTRST ,Soft Reset" "Not toggled,Toggled"
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bitfld.long 0xC 30. " CLKGATE ,Gate off the clocks" "Not toggled,Toggled"
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textline " "
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bitfld.long 0xC 4.--5. " LCDIF_PRIORITY_BOOST ,eLCDIF Higher Priority Allow" "Not toggled,Toggled,Set,Set"
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bitfld.long 0xC 2.--3. " EPCD_PRIORITY_BOOST ,EPDC Higher Priority Allow" "Not toggled,Toggled,Set,Set"
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textline " "
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bitfld.long 0xC 1. " XLATE_AXI_MODE ,Translation AXI QoS info into EMI priority - Priority 0 allow" "Not toggled,Toggled"
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bitfld.long 0xC 0. " EMI_PRIORITY_MODE ,AXI and EMI priority values separation" "Not toggled,Toggled"
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group.long 0x10++0x0F
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line.long 0x0 "AXI_QOS0,AXI QOS Register "
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bitfld.long 0x0 28.--30. " M1_2_ARQOS ,MasterID 3 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. " M1_2_AWQOS ,MasterID 3 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 20.--22. " M1_1_ARQOS ,MasterID 2 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x0 16.--18. " M1_1_AWQOS ,MasterID 2 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 12.--14. " M1_0_ARQOS ,MasterID 1 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. " M1_0_AWQOS ,MasterID 1 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x0 4.--6. " M0_ARQOS ,MasterID 0 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. " M0_AWQOS ,MasterID 0 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
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line.long 0x4 "AXI_QOS0_SET,AXI QOS Register Set"
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bitfld.long 0x4 28.--30. " M1_2_ARQOS ,MasterID 3 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 24.--26. " M1_2_AWQOS ,MasterID 3 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 20.--22. " M1_1_ARQOS ,MasterID 2 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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textline " "
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bitfld.long 0x4 16.--18. " M1_1_AWQOS ,MasterID 2 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 12.--14. " M1_0_ARQOS ,MasterID 1 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 8.--10. " M1_0_AWQOS ,MasterID 1 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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textline " "
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bitfld.long 0x4 4.--6. " M0_ARQOS ,MasterID 0 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 0.--2. " M0_AWQOS ,MasterID 0 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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line.long 0x8 "AXI_QOS0_CLR,AXI QOS Register Clear"
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bitfld.long 0x8 28.--30. " M1_2_ARQOS ,MasterID 3 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 24.--26. " M1_2_AWQOS ,MasterID 3 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 20.--22. " M1_1_ARQOS ,MasterID 2 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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textline " "
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bitfld.long 0x8 16.--18. " M1_1_AWQOS ,MasterID 2 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 12.--14. " M1_0_ARQOS ,MasterID 1 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 8.--10. " M1_0_AWQOS ,MasterID 1 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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textline " "
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bitfld.long 0x8 4.--6. " M0_ARQOS ,MasterID 0 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 0.--2. " M0_AWQOS ,MasterID 0 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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line.long 0xC "AXI_QOS0_TOG,AXI QOS Register Toggle"
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bitfld.long 0xC 28.--30. " M1_2_ARQOS ,MasterID 3 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 24.--26. " M1_2_AWQOS ,MasterID 3 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 20.--22. " M1_1_ARQOS ,MasterID 2 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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textline " "
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bitfld.long 0xC 16.--18. " M1_1_AWQOS ,MasterID 2 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 12.--14. " M1_0_ARQOS ,MasterID 1 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 8.--10. " M1_0_AWQOS ,MasterID 1 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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textline " "
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bitfld.long 0xC 4.--6. " M0_ARQOS ,MasterID 0 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 0.--2. " M0_AWQOS ,MasterID 0 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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group.long 0x20++0x0F
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line.long 0x0 "AXI_QOS1,AXI QOS Register "
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bitfld.long 0x0 28.--30. " M5_ARQOS ,MasterID 7 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. " M5_AWQOS ,MasterID 7 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 20.--22. " M4_ARQOS ,MasterID 6 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x0 16.--18. " M4_AWQOS ,MasterID 6 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 12.--14. " M3_ARQOS ,MasterID 5 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. " M3_AWQOS ,MasterID 5 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x0 4.--6. " M2_ARQOS ,MasterID 4 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. " M2_AWQOS ,MasterID 4 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
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line.long 0x4 "AXI_QOS1_SET,AXI QOS Register Set"
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bitfld.long 0x4 28.--30. " M5_ARQOS ,MasterID 7 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 24.--26. " M5_AWQOS ,MasterID 7 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 20.--22. " M4_ARQOS ,MasterID 6 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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textline " "
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bitfld.long 0x4 16.--18. " M4_AWQOS ,MasterID 6 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 12.--14. " M3_ARQOS ,MasterID 5 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 8.--10. " M3_AWQOS ,MasterID 5 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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textline " "
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bitfld.long 0x4 4.--6. " M2_ARQOS ,MasterID 4 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 0.--2. " M2_AWQOS ,MasterID 4 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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line.long 0x8 "AXI_QOS1_CLR,AXI QOS Register Clear"
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bitfld.long 0x8 28.--30. " M5_ARQOS ,MasterID 7 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 24.--26. " M5_AWQOS ,MasterID 7 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 20.--22. " M4_ARQOS ,MasterID 6 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
textline " "
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bitfld.long 0x8 16.--18. " M4_AWQOS ,MasterID 6 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 12.--14. " M3_ARQOS ,MasterID 5 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
bitfld.long 0x8 8.--10. " M3_AWQOS ,MasterID 5 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
textline " "
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|
bitfld.long 0x8 4.--6. " M2_ARQOS ,MasterID 4 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 0.--2. " M2_AWQOS ,MasterID 4 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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line.long 0xC "AXI_QOS1_TOG,AXI QOS Register Toggle"
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bitfld.long 0xC 28.--30. " M5_ARQOS ,MasterID 7 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 24.--26. " M5_AWQOS ,MasterID 7 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 20.--22. " M4_ARQOS ,MasterID 6 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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textline " "
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bitfld.long 0xC 16.--18. " M4_AWQOS ,MasterID 6 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 12.--14. " M3_ARQOS ,MasterID 5 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 8.--10. " M3_AWQOS ,MasterID 5 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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textline " "
|
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bitfld.long 0xC 4.--6. " M2_ARQOS ,MasterID 4 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 0.--2. " M2_AWQOS ,MasterID 4 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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group.long 0x30++0x0F
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line.long 0x0 "AXI_QOS2,AXI QOS Register "
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bitfld.long 0x0 28.--30. " M9_ARQOS ,MasterID 11 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. " M9_AWQOS ,MasterID 11 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 20.--22. " M8_ARQOS ,MasterID 10 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
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bitfld.long 0x0 16.--18. " M8_AWQOS ,MasterID 10 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12.--14. " M7_ARQOS ,MasterID 9 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--10. " M7_AWQOS ,MasterID 9 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 4.--6. " M6_ARQOS ,MasterID 8 Read Commands QoS Level" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. " M6_AWQOS ,MasterID 8 Write Commands QoS Level" "0,1,2,3,4,5,6,7"
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line.long 0x4 "AXI_QOS2_SET,AXI QOS Register Set"
|
|
bitfld.long 0x4 28.--30. " M9_ARQOS ,MasterID 11 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
bitfld.long 0x4 24.--26. " M9_AWQOS ,MasterID 11 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
bitfld.long 0x4 20.--22. " M8_ARQOS ,MasterID 10 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " M8_AWQOS ,MasterID 10 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
bitfld.long 0x4 12.--14. " M7_ARQOS ,MasterID 9 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
bitfld.long 0x4 8.--10. " M7_AWQOS ,MasterID 9 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
textline " "
|
|
bitfld.long 0x4 4.--6. " M6_ARQOS ,MasterID 8 Read Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
bitfld.long 0x4 0.--2. " M6_AWQOS ,MasterID 8 Write Commands QoS Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
line.long 0x8 "AXI_QOS2_CLR,AXI QOS Register Clear"
|
|
bitfld.long 0x8 28.--30. " M9_ARQOS ,MasterID 11 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
bitfld.long 0x8 24.--26. " M9_AWQOS ,MasterID 11 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
bitfld.long 0x8 20.--22. " M8_ARQOS ,MasterID 10 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " M8_AWQOS ,MasterID 10 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
bitfld.long 0x8 12.--14. " M7_ARQOS ,MasterID 9 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
bitfld.long 0x8 8.--10. " M7_AWQOS ,MasterID 9 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x8 4.--6. " M6_ARQOS ,MasterID 8 Read Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
bitfld.long 0x8 0.--2. " M6_AWQOS ,MasterID 8 Write Commands QoS Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
line.long 0xC "AXI_QOS2_TOG,AXI QOS Register Toggle"
|
|
bitfld.long 0xC 28.--30. " M9_ARQOS ,MasterID 11 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
|
bitfld.long 0xC 24.--26. " M9_AWQOS ,MasterID 11 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
|
bitfld.long 0xC 20.--22. " M8_ARQOS ,MasterID 10 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " M8_AWQOS ,MasterID 10 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
|
bitfld.long 0xC 12.--14. " M7_ARQOS ,MasterID 9 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
|
bitfld.long 0xC 8.--10. " M7_AWQOS ,MasterID 9 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0xC 4.--6. " M6_ARQOS ,MasterID 8 Read Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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|
bitfld.long 0xC 0.--2. " M6_AWQOS ,MasterID 8 Write Commands QoS Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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|
group.long 0x40++0x0F
|
|
line.long 0x0 "EMI_PRIORITY0,EMI Priority Register "
|
|
bitfld.long 0x0 28.--30. " M1_2_RD ,MasterID 3 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24.--26. " M1_2_WR ,MasterID 3 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20.--22. " M1_1_RD ,MasterID 2 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " M1_1_WR ,MasterID 2 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 12.--14. " M1_0_RD ,MasterID 1 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 8.--10. " M1_0_WR ,MasterID 1 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
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|
textline " "
|
|
bitfld.long 0x0 4.--6. " M0_RD ,MasterID 0 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 0.--2. " M0_WR ,MasterID 0 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "EMI_PRIORITY0_SET,EMI Priority Register Set"
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|
bitfld.long 0x4 28.--30. " M1_2_RD ,MasterID 3 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
bitfld.long 0x4 24.--26. " M1_2_WR ,MasterID 3 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
bitfld.long 0x4 20.--22. " M1_1_RD ,MasterID 2 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " M1_1_WR ,MasterID 2 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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|
bitfld.long 0x4 12.--14. " M1_0_RD ,MasterID 1 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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|
bitfld.long 0x4 8.--10. " M1_0_WR ,MasterID 1 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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|
textline " "
|
|
bitfld.long 0x4 4.--6. " M0_RD ,MasterID 0 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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|
bitfld.long 0x4 0.--2. " M0_WR ,MasterID 0 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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|
line.long 0x8 "EMI_PRIORITY0_CLR,EMI Priority Register Clear"
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|
bitfld.long 0x8 28.--30. " M1_2_RD ,MasterID 3 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
bitfld.long 0x8 24.--26. " M1_2_WR ,MasterID 3 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
bitfld.long 0x8 20.--22. " M1_1_RD ,MasterID 2 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
textline " "
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|
bitfld.long 0x8 16.--18. " M1_1_WR ,MasterID 2 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
bitfld.long 0x8 12.--14. " M1_0_RD ,MasterID 1 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
bitfld.long 0x8 8.--10. " M1_0_WR ,MasterID 1 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
textline " "
|
|
bitfld.long 0x8 4.--6. " M0_RD ,MasterID 0 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
bitfld.long 0x8 0.--2. " M0_WR ,MasterID 0 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
line.long 0xC "EMI_PRIORITY0_TOG,EMI Priority Register Toggle"
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|
bitfld.long 0xC 28.--30. " M1_2_RD ,MasterID 3 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 24.--26. " M1_2_WR ,MasterID 3 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 20.--22. " M1_1_RD ,MasterID 2 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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|
textline " "
|
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bitfld.long 0xC 16.--18. " M1_1_WR ,MasterID 2 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 12.--14. " M1_0_RD ,MasterID 1 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 8.--10. " M1_0_WR ,MasterID 1 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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|
textline " "
|
|
bitfld.long 0xC 4.--6. " M0_RD ,MasterID 0 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 0.--2. " M0_WR ,MasterID 0 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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|
group.long 0x50++0x0F
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line.long 0x0 "EMI_PRIORITY1,EMI Priority Register "
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|
bitfld.long 0x0 28.--30. " M5_RD ,MasterID 7 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. " M5_WR ,MasterID 7 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 20.--22. " M4_RD ,MasterID 6 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
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|
textline " "
|
|
bitfld.long 0x0 16.--18. " M4_WR ,MasterID 6 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 12.--14. " M3_RD ,MasterID 5 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. " M3_WR ,MasterID 5 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
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|
textline " "
|
|
bitfld.long 0x0 4.--6. " M2_RD ,MasterID 4 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 0.--2. " M2_WR ,MasterID 4 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
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line.long 0x4 "EMI_PRIORITY1_SET,EMI Priority Register Set"
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bitfld.long 0x4 28.--30. " M5_RD ,MasterID 7 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 24.--26. " M5_WR ,MasterID 7 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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|
bitfld.long 0x4 20.--22. " M4_RD ,MasterID 6 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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|
textline " "
|
|
bitfld.long 0x4 16.--18. " M4_WR ,MasterID 6 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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|
bitfld.long 0x4 12.--14. " M3_RD ,MasterID 5 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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|
bitfld.long 0x4 8.--10. " M3_WR ,MasterID 5 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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|
textline " "
|
|
bitfld.long 0x4 4.--6. " M2_RD ,MasterID 4 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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|
bitfld.long 0x4 0.--2. " M2_WR ,MasterID 4 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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line.long 0x8 "EMI_PRIORITY1_CLR,EMI Priority Register Clear"
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bitfld.long 0x8 28.--30. " M5_RD ,MasterID 7 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
bitfld.long 0x8 24.--26. " M5_WR ,MasterID 7 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 20.--22. " M4_RD ,MasterID 6 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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|
textline " "
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|
bitfld.long 0x8 16.--18. " M4_WR ,MasterID 6 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 12.--14. " M3_RD ,MasterID 5 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 8.--10. " M3_WR ,MasterID 5 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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textline " "
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bitfld.long 0x8 4.--6. " M2_RD ,MasterID 4 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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bitfld.long 0x8 0.--2. " M2_WR ,MasterID 4 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
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line.long 0xC "EMI_PRIORITY1_TOG,EMI Priority Register Toggle"
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bitfld.long 0xC 28.--30. " M5_RD ,MasterID 7 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 24.--26. " M5_WR ,MasterID 7 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 20.--22. " M4_RD ,MasterID 6 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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textline " "
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bitfld.long 0xC 16.--18. " M4_WR ,MasterID 6 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 12.--14. " M3_RD ,MasterID 5 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 8.--10. " M3_WR ,MasterID 5 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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textline " "
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bitfld.long 0xC 4.--6. " M2_RD ,MasterID 4 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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bitfld.long 0xC 0.--2. " M2_WR ,MasterID 4 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
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group.long 0x60++0x0F
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line.long 0x0 "EMI_PRIORITY2,EMI Priority Register "
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bitfld.long 0x0 28.--30. " M9_RD ,MasterID 11 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24.--26. " M9_WR ,MasterID 11 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 20.--22. " M8_RD ,MasterID 10 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
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|
textline " "
|
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bitfld.long 0x0 16.--18. " M8_WR ,MasterID 10 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 12.--14. " M7_RD ,MasterID 9 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. " M7_WR ,MasterID 9 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
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|
textline " "
|
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bitfld.long 0x0 4.--6. " M6_RD ,MasterID 8 Read Commands Priority Level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. " M6_WR ,MasterID 8 Write Commands Priority Level" "0,1,2,3,4,5,6,7"
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line.long 0x4 "EMI_PRIORITY2_SET,EMI Priority Register Set"
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bitfld.long 0x4 28.--30. " M9_RD ,MasterID 11 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 24.--26. " M9_WR ,MasterID 11 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 20.--22. " M8_RD ,MasterID 10 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
textline " "
|
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bitfld.long 0x4 16.--18. " M8_WR ,MasterID 10 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
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bitfld.long 0x4 12.--14. " M7_RD ,MasterID 9 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
bitfld.long 0x4 8.--10. " M7_WR ,MasterID 9 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
|
textline " "
|
|
bitfld.long 0x4 4.--6. " M6_RD ,MasterID 8 Read Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
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bitfld.long 0x4 0.--2. " M6_WR ,MasterID 8 Write Commands Priority Level" "No effect,Set,Set,Set,Set,Set,Set,Set"
|
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line.long 0x8 "EMI_PRIORITY2_CLR,EMI Priority Register Clear"
|
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bitfld.long 0x8 28.--30. " M9_RD ,MasterID 11 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
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bitfld.long 0x8 24.--26. " M9_WR ,MasterID 11 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
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bitfld.long 0x8 20.--22. " M8_RD ,MasterID 10 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " M8_WR ,MasterID 10 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
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bitfld.long 0x8 12.--14. " M7_RD ,MasterID 9 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
bitfld.long 0x8 8.--10. " M7_WR ,MasterID 9 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x8 4.--6. " M6_RD ,MasterID 8 Read Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
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bitfld.long 0x8 0.--2. " M6_WR ,MasterID 8 Write Commands Priority Level" "No effect,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared,Cleared"
|
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line.long 0xC "EMI_PRIORITY2_TOG,EMI Priority Register Toggle"
|
|
bitfld.long 0xC 28.--30. " M9_RD ,MasterID 11 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
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bitfld.long 0xC 24.--26. " M9_WR ,MasterID 11 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
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bitfld.long 0xC 20.--22. " M8_RD ,MasterID 10 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
|
textline " "
|
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bitfld.long 0xC 16.--18. " M8_WR ,MasterID 10 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
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bitfld.long 0xC 12.--14. " M7_RD ,MasterID 9 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
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bitfld.long 0xC 8.--10. " M7_WR ,MasterID 9 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0xC 4.--6. " M6_RD ,MasterID 8 Read Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
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bitfld.long 0xC 0.--2. " M6_WR ,MasterID 8 Write Commands Priority Level" "Not toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled,Toggled"
|
|
group.long 0x70++0x0F
|
|
line.long 0x0 "QOS_DISABLE,AXI Master Disble Register "
|
|
rbitfld.long 0x0 27. " M9_DIS_STAT ,AXI Fabric Master Port 9 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x0 26. " M8_DIS_STAT ,AXI Fabric Master Port 8 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x0 25. " M7_DIS_STAT ,AXI Fabric Master Port 7 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x0 24. " M6_DIS_STAT ,AXI Fabric Master Port 6 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x0 23. " M5_DIS_STAT ,AXI Fabric Master Port 5 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x0 22. " M4_DIS_STAT ,AXI Fabric Master Port 4 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x0 21. " M3_DIS_STAT ,AXI Fabric Master Port 3 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x0 20. " M2_DIS_STAT ,AXI Fabric Master Port 2 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x0 19. " M1_2_DIS_STAT ,AXI Fabric Master Port 1_2 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x0 18. " M1_1_DIS_STAT ,AXI Fabric Master Port 1_1 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x0 17. " M1_0_DIS_STAT ,AXI Fabric Master Port 1_0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " M9_DIS ,Interface Between Master 9 And AXI Fabric Disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 10. " M8_DIS ,Interface Between Master 8 And AXI Fabric Disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 9. " M7_DIS ,Interface Between Master 7 And AXI Fabric Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " M6_DIS ,Interface Between Master 6 And AXI Fabric Disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 7. " M5_DIS ,Interface Between Master 5 And AXI Fabric Disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " M4_DIS ,Interface Between Master 4 And AXI Fabric Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " M3_DIS ,Interface Between Master 3 And AXI Fabric Disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 4. " M2_DIS ,Interface Between Master 2 And AXI Fabric Disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 3. " M1_2_DIS ,Interface Between Master 1_2 And AXI Fabric Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " M1_1_DIS ,Interface Between Master 1_1 And AXI Fabric Disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 1. " M1_0_DIS ,Interface Between Master 1_0 And AXI Fabric Disable" "Enabled,Disabled"
|
|
line.long 0x4 "QOS_DISABLE_SET,AXI Master Disble Register Set"
|
|
rbitfld.long 0x4 27. " M9_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x4 26. " M8_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x4 25. " M7_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x4 24. " M6_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x4 23. " M5_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x4 22. " M4_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x4 21. " M3_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x4 20. " M2_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x4 19. " M1_2_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x4 18. " M1_1_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x4 17. " M1_0_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " M9_DIS ,Interface Between Master 0 And AXI Fabric Disable Set" "No effect,Set"
|
|
bitfld.long 0x4 10. " M8_DIS ,Interface Between Master 0 And AXI Fabric Disable Set" "No effect,Set"
|
|
bitfld.long 0x4 9. " M7_DIS ,Interface Between Master 0 And AXI Fabric Disable Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x4 8. " M6_DIS ,Interface Between Master 0 And AXI Fabric Disable Set" "No effect,Set"
|
|
bitfld.long 0x4 7. " M5_DIS ,Interface Between Master 0 And AXI Fabric Disable Set" "No effect,Set"
|
|
bitfld.long 0x4 6. " M4_DIS ,Interface Between Master 0 And AXI Fabric Disable Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x4 5. " M3_DIS ,Interface Between Master 0 And AXI Fabric Disable Set" "No effect,Set"
|
|
bitfld.long 0x4 4. " M2_DIS ,Interface Between Master 0 And AXI Fabric Disable Set" "No effect,Set"
|
|
bitfld.long 0x4 3. " M1_2_DIS ,Interface Between Master 0 And AXI Fabric Disable Set" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x4 2. " M1_1_DIS ,Interface Between Master 0 And AXI Fabric Disable Set" "No effect,Set"
|
|
bitfld.long 0x4 1. " M1_0_DIS ,Interface Between Master 0 And AXI Fabric Disable Set" "No effect,Set"
|
|
line.long 0x8 "QOS_DISABLE_CLR,AXI Master Disble Register Clear"
|
|
rbitfld.long 0x8 27. " M9_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x8 26. " M8_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x8 25. " M7_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x8 24. " M6_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x8 23. " M5_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x8 22. " M4_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x8 21. " M3_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x8 20. " M2_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x8 19. " M1_2_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x8 18. " M1_1_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0x8 17. " M1_0_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " M9_DIS ,Interface Between Master 0 And AXI Fabric Disable Clear" "No effect,Cleared"
|
|
bitfld.long 0x8 10. " M8_DIS ,Interface Between Master 0 And AXI Fabric Disable Clear" "No effect,Cleared"
|
|
bitfld.long 0x8 9. " M7_DIS ,Interface Between Master 0 And AXI Fabric Disable Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x8 8. " M6_DIS ,Interface Between Master 0 And AXI Fabric Disable Clear" "No effect,Cleared"
|
|
bitfld.long 0x8 7. " M5_DIS ,Interface Between Master 0 And AXI Fabric Disable Clear" "No effect,Cleared"
|
|
bitfld.long 0x8 6. " M4_DIS ,Interface Between Master 0 And AXI Fabric Disable Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x8 5. " M3_DIS ,Interface Between Master 0 And AXI Fabric Disable Clear" "No effect,Cleared"
|
|
bitfld.long 0x8 4. " M2_DIS ,Interface Between Master 0 And AXI Fabric Disable Clear" "No effect,Cleared"
|
|
bitfld.long 0x8 3. " M1_2_DIS ,Interface Between Master 0 And AXI Fabric Disable Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x8 2. " M1_1_DIS ,Interface Between Master 0 And AXI Fabric Disable Clear" "No effect,Cleared"
|
|
bitfld.long 0x8 1. " M1_0_DIS ,Interface Between Master 0 And AXI Fabric Disable Clear" "No effect,Cleared"
|
|
line.long 0xC "QOS_DISABLE_TOG,AXI Master Disble Register Toggle"
|
|
rbitfld.long 0xC 27. " M9_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0xC 26. " M8_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0xC 25. " M7_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0xC 24. " M6_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0xC 23. " M5_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0xC 22. " M4_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0xC 21. " M3_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0xC 20. " M2_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0xC 19. " M1_2_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0xC 18. " M1_1_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
rbitfld.long 0xC 17. " M1_0_DIS_STAT ,AXI Fabric Master Port 0 Status" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0xC 11. " M9_DIS ,Interface Between Master 0 And AXI Fabric Disable Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0xC 10. " M8_DIS ,Interface Between Master 0 And AXI Fabric Disable Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0xC 9. " M7_DIS ,Interface Between Master 0 And AXI Fabric Disable Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0xC 8. " M6_DIS ,Interface Between Master 0 And AXI Fabric Disable Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0xC 7. " M5_DIS ,Interface Between Master 0 And AXI Fabric Disable Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0xC 6. " M4_DIS ,Interface Between Master 0 And AXI Fabric Disable Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0xC 5. " M3_DIS ,Interface Between Master 0 And AXI Fabric Disable Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0xC 4. " M2_DIS ,Interface Between Master 0 And AXI Fabric Disable Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0xC 3. " M1_2_DIS ,Interface Between Master 0 And AXI Fabric Disable Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0xC 2. " M1_1_DIS ,Interface Between Master 0 And AXI Fabric Disable Toggle" "Not toggled,Toggled"
|
|
bitfld.long 0xC 1. " M1_0_DIS ,Interface Between Master 0 And AXI Fabric Disable Toggle" "Not toggled,Toggled"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "VERSION,QoS Version Register"
|
|
hexmask.long.byte 0x00 24.--31. 0x1 " MAJOR ,Major version number"
|
|
hexmask.long.byte 0x00 16.--23. 0x1 " MINOR ,Minor version number"
|
|
hexmask.long.word 0x00 0.--15. 0x1 " STEP ,Stepping number"
|
|
width 0xB
|
|
tree.end
|
|
tree "ROMCP (Read Only Memory Controller Patch)"
|
|
base ad:0x63FB8000
|
|
width 13.
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX6*"))
|
|
group.long 0xD4++0x1F
|
|
line.long 0x00 "ROMPATCH0D,ROMPATCH Data Register 0"
|
|
line.long 0x04 "ROMPATCH1D,ROMPATCH Data Register 1"
|
|
line.long 0x08 "ROMPATCH2D,ROMPATCH Data Register 2"
|
|
line.long 0x0c "ROMPATCH3D,ROMPATCH Data Register 3"
|
|
line.long 0x10 "ROMPATCH4D,ROMPATCH Data Register 4"
|
|
line.long 0x14 "ROMPATCH5D,ROMPATCH Data Register 5"
|
|
line.long 0x18 "ROMPATCH6D,ROMPATCH Data Register 6"
|
|
line.long 0x1c "ROMPATCH7D,ROMPATCH Data Register 7"
|
|
else
|
|
group.long 0xD4++0x1F
|
|
line.long 0x00 "ROMPATCHD7,ROMPATCH Data Register 7"
|
|
line.long 0x04 "ROMPATCHD6,ROMPATCH Data Register 6"
|
|
line.long 0x08 "ROMPATCHD5,ROMPATCH Data Register 5"
|
|
line.long 0x0c "ROMPATCHD4,ROMPATCH Data Register 4"
|
|
line.long 0x10 "ROMPATCHD3,ROMPATCH Data Register 3"
|
|
line.long 0x14 "ROMPATCHD2,ROMPATCH Data Register 2"
|
|
line.long 0x18 "ROMPATCHD1,ROMPATCH Data Register 1"
|
|
line.long 0x1c "ROMPATCHD0,ROMPATCH Data Register 0"
|
|
endif
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "ROMPATCHCNT,ROMPATCH Control Register"
|
|
bitfld.long 0x00 29. " DIS ,ROMPATCH Disable" "No effect,Disabled"
|
|
bitfld.long 0x00 7. " DATAFIX[7] ,Data Fix Enable" "Opcode patch,Data fix"
|
|
bitfld.long 0x00 6. " DATAFIX[6] ,Data Fix Enable" "Opcode patch,Data fix"
|
|
bitfld.long 0x00 5. " DATAFIX[5] ,Data Fix Enable" "Opcode patch,Data fix"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATAFIX[4] ,Data Fix Enable" "Opcode patch,Data fix"
|
|
bitfld.long 0x00 3. " DATAFIX[3] ,Data Fix Enable" "Opcode patch,Data fix"
|
|
bitfld.long 0x00 2. " DATAFIX[2] ,Data Fix Enable" "Opcode patch,Data fix"
|
|
bitfld.long 0x00 1. " DATAFIX[1] ,Data Fix Enable" "Opcode patch,Data fix"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATAFIX[0] ,Data Fix Enable" "Opcode patch,Data fix"
|
|
hgroup.long 0xF8++0x03
|
|
hide.long 0x00 "ROMPATCHENH,ROMPATCH Enable Register High"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "ROMPATCHENL,ROMPATCH Enable Register Low"
|
|
bitfld.long 0x00 15. " ENABLE[15] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ENABLE[14] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ENABLE[13] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENABLE[12] ,Enable Address Comparator" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENABLE[11] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENABLE[10] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENABLE[9] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENABLE[8] ,Enable Address Comparator" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE[7] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENABLE[6] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENABLE[5] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENABLE[4] ,Enable Address Comparator" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE[3] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ENABLE[2] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENABLE[1] ,Enable Address Comparator" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE[0] ,Enable Address Comparator" "Disabled,Enabled"
|
|
sif (cpuis("IMX6*"))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ROMPATCHA0 ,ROMPATCH Address Register 0 "
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR0 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB0 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "ROMPATCHA1 ,ROMPATCH Address Register 1 "
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR1 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB1 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "ROMPATCHA2 ,ROMPATCH Address Register 2 "
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR2 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB2 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "ROMPATCHA3 ,ROMPATCH Address Register 3 "
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR3 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB3 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "ROMPATCHA4 ,ROMPATCH Address Register 4 "
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR4 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB4 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "ROMPATCHA5 ,ROMPATCH Address Register 5 "
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR5 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB5 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "ROMPATCHA6 ,ROMPATCH Address Register 6 "
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR6 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB6 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "ROMPATCHA7 ,ROMPATCH Address Register 7 "
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR7 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB7 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ROMPATCHA8 ,ROMPATCH Address Register 8 "
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR8 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB8 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "ROMPATCHA9 ,ROMPATCH Address Register 9 "
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR9 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB9 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ROMPATCHA10,ROMPATCH Address Register 10"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR10 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB10 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "ROMPATCHA11,ROMPATCH Address Register 11"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR11 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB11 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "ROMPATCHA12,ROMPATCH Address Register 12"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR12 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB12 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "ROMPATCHA13,ROMPATCH Address Register 13"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR13 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB13 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "ROMPATCHA14,ROMPATCH Address Register 14"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR14 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB14 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "ROMPATCHA15,ROMPATCH Address Register 15"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR15 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB15 ,THUMB Comparator Select" "ARM,THUMB"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ROMPATCHA0,ROMPATCH Address Register 0"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR0 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB0 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "ROMPATCHA1,ROMPATCH Address Register 1"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR1 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB1 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "ROMPATCHA2,ROMPATCH Address Register 2"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR2 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB2 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "ROMPATCHA3,ROMPATCH Address Register 3"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR3 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB3 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "ROMPATCHA4,ROMPATCH Address Register 4"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR4 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB4 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "ROMPATCHA5,ROMPATCH Address Register 5"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR5 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB5 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "ROMPATCHA6,ROMPATCH Address Register 6"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR6 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB6 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "ROMPATCHA7,ROMPATCH Address Register 7"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR7 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB7 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ROMPATCHA8,ROMPATCH Address Register 8"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR8 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB8 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "ROMPATCHA9,ROMPATCH Address Register 9"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR9 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB9 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "ROMPATCHA10,ROMPATCH Address Register 10"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR10 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB10 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "ROMPATCHA11,ROMPATCH Address Register 11"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR11 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB11 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "ROMPATCHA12,ROMPATCH Address Register 12"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR12 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB12 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "ROMPATCHA13,ROMPATCH Address Register 13"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR13 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB13 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "ROMPATCHA14,ROMPATCH Address Register 14"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR14 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB14 ,THUMB Comparator Select" "ARM,THUMB"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "ROMPATCHA15,ROMPATCH Address Register 15"
|
|
hexmask.long.tbyte 0x00 1.--22. 0x2 " ADDR15 ,Address Comparator"
|
|
bitfld.long 0x00 0. " THUMB15 ,THUMB Comparator Select" "ARM,THUMB"
|
|
endif
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "ROMPATCHSR,ROMPATCH Status Register"
|
|
eventfld.long 0x00 17. " SW ,ROMC AHB Simultaneous Address Comparisons" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 0.--5. " SOURCE ,ROMPATCH Source Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SDMA (Smart Direct Memory Access Controller)"
|
|
base ad:0x63fb0000
|
|
width 13.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "MC0PTR,AP Channel 0 Pointer Register"
|
|
line.long 0x04 "INTR,Channel Interrupts Register"
|
|
eventfld.long 0x04 31. " HI[31] ,AP HI[31] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 30. " HI[30] ,AP HI[30] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 29. " HI[29] ,AP HI[29] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 28. " HI[28] ,AP HI[28] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 27. " HI[27] ,AP HI[27] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 26. " HI[26] ,AP HI[26] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 25. " HI[25] ,AP HI[25] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 24. " HI[24] ,AP HI[24] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 23. " HI[23] ,AP HI[23] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 22. " HI[22] ,AP HI[22] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 21. " HI[21] ,AP HI[21] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 20. " HI[20] ,AP HI[20] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 19. " HI[19] ,AP HI[19] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 18. " HI[18] ,AP HI[18] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 17. " HI[17] ,AP HI[17] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 16. " HI[16] ,AP HI[16] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 15. " HI[15] ,AP HI[15] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 14. " HI[14] ,AP HI[14] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 13. " HI[13] ,AP HI[13] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 12. " HI[12] ,AP HI[12] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 11. " HI[11] ,AP HI[11] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 10. " HI[10] ,AP HI[10] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " HI[9] ,AP HI[9] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " HI[8] ,AP HI[8] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 7. " HI[7] ,AP HI[7] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " HI[6] ,AP HI[6] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " HI[5] ,AP HI[5] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " HI[4] ,AP HI[4] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " HI[3] ,AP HI[3] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " HI[2] ,AP HI[2] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 1. " HI[1] ,AP HI[1] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " HI[0] ,AP HI[0] Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "STOP_STAT,Channel Stop/Channel Status Register"
|
|
eventfld.long 0x08 31. " HE[31] ,HE[31] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 30. " HE[30] ,HE[30] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 29. " HE[29] ,HE[29] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 28. " HE[28] ,HE[28] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 27. " HE[27] ,HE[27] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 26. " HE[26] ,HE[26] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 25. " HE[25] ,HE[25] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 24. " HE[24] ,HE[24] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 23. " HE[23] ,HE[23] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 22. " HE[22] ,HE[22] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 21. " HE[21] ,HE[21] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 20. " HE[20] ,HE[20] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 19. " HE[19] ,HE[19] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 18. " HE[18] ,HE[18] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 17. " HE[17] ,HE[17] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 16. " HE[16] ,HE[16] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 15. " HE[15] ,HE[15] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 14. " HE[14] ,HE[14] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 13. " HE[13] ,HE[13] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 12. " HE[12] ,HE[12] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 11. " HE[11] ,HE[11] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 10. " HE[10] ,HE[10] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 9. " HE[9] ,HE[9] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 8. " HE[8] ,HE[8] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 7. " HE[7] ,HE[7] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 6. " HE[6] ,HE[6] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 5. " HE[5] ,HE[5] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 4. " HE[4] ,HE[4] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 3. " HE[3] ,HE[3] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 2. " HE[2] ,HE[2] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 1. " HE[1] ,HE[1] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 0. " HE[0] ,HE[0] Stop/Status" "No access,Access"
|
|
line.long 0x0C "HSTART,Channel Start Register"
|
|
eventfld.long 0x0C 31. " HSTART[31] ,Channel 31 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 30. " HSTART[30] ,Channel 30 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 29. " HSTART[29] ,Channel 29 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 28. " HSTART[28] ,Channel 28 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 27. " HSTART[27] ,Channel 27 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 26. " HSTART[26] ,Channel 26 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " HSTART[25] ,Channel 25 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 24. " HSTART[24] ,Channel 24 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 23. " HSTART[23] ,Channel 23 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 22. " HSTART[22] ,Channel 22 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 21. " HSTART[21] ,Channel 21 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 20. " HSTART[20] ,Channel 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " HSTART[19] ,Channel 19 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 18. " HSTART[18] ,Channel 18 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 17. " HSTART[17] ,Channel 17 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 16. " HSTART[16] ,Channel 16 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 15. " HSTART[15] ,Channel 15 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 14. " HSTART[14] ,Channel 14 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " HSTART[13] ,Channel 13 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 12. " HSTART[12] ,Channel 12 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 11. " HSTART[11] ,Channel 11 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 10. " HSTART[10] ,Channel 10 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 9. " HSTART[9] ,Channel 9 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 8. " HSTART[8] ,Channel 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " HSTART[7] ,Channel 7 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 6. " HSTART[6] ,Channel 6 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 5. " HSTART[5] ,Channel 5 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 4. " HSTART[4] ,Channel 4 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 3. " HSTART[3] ,Channel 3 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 2. " HSTART[2] ,Channel 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " HSTART[1] ,Channel 1 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 0. " HSTART[0] ,Channel 0 Enable" "Disabled,Enabled"
|
|
line.long 0x10 "EVTOVR,Channel Event Override Register"
|
|
bitfld.long 0x10 31. " EO[31] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 30. " EO[30] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 29. " EO[29] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 28. " EO[28] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 27. " EO[27] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 26. " EO[26] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EO[25] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 24. " EO[24] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 23. " EO[23] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 22. " EO[22] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 21. " EO[21] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 20. " EO[20] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 19. " EO[19] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 18. " EO[18] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 17. " EO[17] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 16. " EO[16] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 15. " EO[15] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 14. " EO[14] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 13. " EO[13] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 12. " EO[12] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 11. " EO[11] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 10. " EO[10] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 9. " EO[9] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 8. " EO[8] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 7. " EO[7] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 6. " EO[6] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 5. " EO[5] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EO[4] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 3. " EO[3] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 2. " EO[2] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 1. " EO[1] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 0. " EO[0] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "DSPOVR,Channel BP Override Register"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "HOSTOVR,Channel AP Override Register"
|
|
bitfld.long 0x00 31. " HO[31] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 30. " HO[30] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 29. " HO[29] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 28. " HO[28] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 27. " HO[27] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 26. " HO[26] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HO[25] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 24. " HO[24] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 23. " HO[23] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " HO[22] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 21. " HO[21] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 20. " HO[20] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HO[19] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 18. " HO[18] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 17. " HO[17] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HO[16] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 15. " HO[15] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 14. " HO[14] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HO[13] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 12. " HO[12] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 11. " HO[11] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HO[10] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " HO[9] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 8. " HO[8] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HO[7] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 6. " HO[6] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 5. " HO[5] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HO[4] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 3. " HO[3] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 2. " HO[2] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HO[1] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 0. " HO[0] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
sif (cpuis("IMX6*"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EVTPEND,Channel Event Pending Register"
|
|
eventfld.long 0x00 31. " EP[31] ,Channel 31 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " EP[30] ,Channel 30 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " EP[29] ,Channel 29 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " EP[28] ,Channel 28 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " EP[27] ,Channel 27 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " EP[26] ,Channel 26 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " EP[25] ,Channel 25 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " EP[24] ,Channel 24 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " EP[23] ,Channel 23 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " EP[22] ,Channel 22 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " EP[21] ,Channel 21 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " EP[20] ,Channel 20 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " EP[19] ,Channel 19 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " EP[18] ,Channel 18 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " EP[17] ,Channel 17 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " EP[16] ,Channel 16 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " EP[15] ,Channel 15 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " EP[14] ,Channel 14 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " EP[13] ,Channel 13 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " EP[12] ,Channel 12 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " EP[11] ,Channel 11 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " EP[10] ,Channel 10 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " EP[9] ,Channel 9 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " EP[8] ,Channel 8 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " EP[7] ,Channel 7 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " EP[6] ,Channel 6 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " EP[5] ,Channel 5 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " EP[4] ,Channel 4 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " EP[3] ,Channel 3 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " EP[2] ,Channel 2 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EP[1] ,Channel 1 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " EP[0] ,Channel 0 Event Pending" "Not pending,Pending"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "EVTPEND,Channel Event Pending Register"
|
|
bitfld.long 0x00 31. " EP[31] ,Channel 31 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " EP[30] ,Channel 30 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " EP[29] ,Channel 29 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EP[28] ,Channel 28 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " EP[27] ,Channel 27 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " EP[26] ,Channel 26 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EP[25] ,Channel 25 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " EP[24] ,Channel 24 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " EP[23] ,Channel 23 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EP[22] ,Channel 22 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " EP[21] ,Channel 21 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " EP[20] ,Channel 20 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EP[19] ,Channel 19 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " EP[18] ,Channel 18 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " EP[17] ,Channel 17 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EP[16] ,Channel 16 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " EP[15] ,Channel 15 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " EP[14] ,Channel 14 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EP[13] ,Channel 13 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " EP[12] ,Channel 12 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " EP[11] ,Channel 11 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EP[10] ,Channel 10 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " EP[9] ,Channel 9 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " EP[8] ,Channel 8 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EP[7] ,Channel 7 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " EP[6] ,Channel 6 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " EP[5] ,Channel 5 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EP[4] ,Channel 4 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " EP[3] ,Channel 3 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " EP[2] ,Channel 2 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EP[1] ,Channel 1 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " EP[0] ,Channel 0 Event Pending" "Not pending,Pending"
|
|
endif
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "RESET,Reset Register"
|
|
bitfld.long 0x00 1. " RESCHED ,SDMA Reschedule as If a Script had Executed a Done Instruction" "Off,On"
|
|
bitfld.long 0x00 0. " RESET ,Software Reset" "No effect,Reset"
|
|
sif (cpuis("IMX6*"))
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "EVTERR,DMA Request Error Register"
|
|
in
|
|
else
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "EVTERR,DMA Request Error Register"
|
|
bitfld.long 0x00 31. " CHNERR[31] ,Channel 31 Error" "No error,Error"
|
|
bitfld.long 0x00 30. " CHNERR[30] ,Channel 30 Error" "No error,Error"
|
|
bitfld.long 0x00 29. " CHNERR[29] ,Channel 29 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CHNERR[28] ,Channel 28 Error" "No error,Error"
|
|
bitfld.long 0x00 27. " CHNERR[27] ,Channel 27 Error" "No error,Error"
|
|
bitfld.long 0x00 26. " CHNERR[26] ,Channel 26 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CHNERR[25] ,Channel 25 Error" "No error,Error"
|
|
bitfld.long 0x00 24. " CHNERR[24] ,Channel 24 Error" "No error,Error"
|
|
bitfld.long 0x00 23. " CHNERR[23] ,Channel 23 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CHNERR[22] ,Channel 22 Error" "No error,Error"
|
|
bitfld.long 0x00 21. " CHNERR[21] ,Channel 21 Error" "No error,Error"
|
|
bitfld.long 0x00 20. " CHNERR[20] ,Channel 20 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CHNERR[19] ,Channel 19 Error" "No error,Error"
|
|
bitfld.long 0x00 18. " CHNERR[18] ,Channel 18 Error" "No error,Error"
|
|
bitfld.long 0x00 17. " CHNERR[17] ,Channel 17 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CHNERR[16] ,Channel 16 Error" "No error,Error"
|
|
bitfld.long 0x00 15. " CHNERR[15] ,Channel 15 Error" "No error,Error"
|
|
bitfld.long 0x00 14. " CHNERR[14] ,Channel 14 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CHNERR[13] ,Channel 13 Error" "No error,Error"
|
|
bitfld.long 0x00 12. " CHNERR[12] ,Channel 12 Error" "No error,Error"
|
|
bitfld.long 0x00 11. " CHNERR[11] ,Channel 11 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CHNERR[10] ,Channel 10 Error" "No error,Error"
|
|
bitfld.long 0x00 9. " CHNERR[9] ,Channel 9 Error" "No error,Error"
|
|
bitfld.long 0x00 8. " CHNERR[8] ,Channel 8 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHNERR[7] ,Channel 7 Error" "No error,Error"
|
|
bitfld.long 0x00 6. " CHNERR[6] ,Channel 6 Error" "No error,Error"
|
|
bitfld.long 0x00 5. " CHNERR[5] ,Channel 5 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CHNERR[4] ,Channel 4 Error" "No error,Error"
|
|
bitfld.long 0x00 3. " CHNERR[3] ,Channel 3 Error" "No error,Error"
|
|
bitfld.long 0x00 2. " CHNERR[2] ,Channel 2 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHNERR[1] ,Channel 1 Error" "No error,Error"
|
|
bitfld.long 0x00 0. " CHNERR[0] ,Channel 0 Error" "No error,Error"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTRMASK,Channel AP Interrupt Mask Flags Register"
|
|
bitfld.long 0x00 31. " HIMASK[31] ,Channel 31 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " HIMASK[30] ,Channel 30 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " HIMASK[29] ,Channel 29 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " HIMASK[28] ,Channel 28 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " HIMASK[27] ,Channel 27 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " HIMASK[26] ,Channel 26 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HIMASK[25] ,Channel 25 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " HIMASK[24] ,Channel 24 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " HIMASK[23] ,Channel 23 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " HIMASK[22] ,Channel 22 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " HIMASK[21] ,Channel 21 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " HIMASK[20] ,Channel 20 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HIMASK[19] ,Channel 19 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " HIMASK[18] ,Channel 18 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " HIMASK[17] ,Channel 17 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HIMASK[16] ,Channel 16 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " HIMASK[15] ,Channel 15 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " HIMASK[14] ,Channel 14 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HIMASK[13] ,Channel 13 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " HIMASK[12] ,Channel 12 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " HIMASK[11] ,Channel 11 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIMASK[10] ,Channel 10 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " HIMASK[9] ,Channel 9 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " HIMASK[8] ,Channel 8 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIMASK[7] ,Channel 7 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " HIMASK[6] ,Channel 6 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " HIMASK[5] ,Channel 5 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIMASK[4] ,Channel 4 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " HIMASK[3] ,Channel 3 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " HIMASK[2] ,Channel 2 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIMASK[1] ,Channel 1 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " HIMASK[0] ,Channel 0 Interrupt Mask" "Masked,Not masked"
|
|
textline ""
|
|
rgroup.long 0x30++0x7
|
|
sif (cpuis("IMX6*"))
|
|
line.long 0x00 "PSW,Schedule Status Register"
|
|
bitfld.long 0x00 13.--15. " NCP[2:0] ,Next Channel Priority" "No running channel,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " NCR[4:0] ,Next Channel Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CCP[2:0] ,Current Channel Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CCR[4:0] ,Current Channel Register" "No running channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
line.long 0x00 "PSW,Schedule Status Register"
|
|
bitfld.long 0x00 13.--15. " NCP[2:0] ,Next Channel Priority" "No running channel,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " NCR[4:0] ,Next Channel Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " CCP[2:0] ,Current Channel Priority" "No running channel,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CCR[4:0] ,Current Channel Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
line.long 0x04 "EVTERRDBG,DMA Request Error Register for Debug"
|
|
bitfld.long 0x04 31. " CHNERR[31] ,Channel 31 Error" "No error,Error"
|
|
bitfld.long 0x04 30. " CHNERR[30] ,Channel 30 Error" "No error,Error"
|
|
bitfld.long 0x04 29. " CHNERR[29] ,Channel 29 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 28. " CHNERR[28] ,Channel 28 Error" "No error,Error"
|
|
bitfld.long 0x04 27. " CHNERR[27] ,Channel 27 Error" "No error,Error"
|
|
bitfld.long 0x04 26. " CHNERR[26] ,Channel 26 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 25. " CHNERR[25] ,Channel 25 Error" "No error,Error"
|
|
bitfld.long 0x04 24. " CHNERR[24] ,Channel 24 Error" "No error,Error"
|
|
bitfld.long 0x04 23. " CHNERR[23] ,Channel 23 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 22. " CHNERR[22] ,Channel 22 Error" "No error,Error"
|
|
bitfld.long 0x04 21. " CHNERR[21] ,Channel 21 Error" "No error,Error"
|
|
bitfld.long 0x04 20. " CHNERR[20] ,Channel 20 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CHNERR[19] ,Channel 19 Error" "No error,Error"
|
|
bitfld.long 0x04 18. " CHNERR[18] ,Channel 18 Error" "No error,Error"
|
|
bitfld.long 0x04 17. " CHNERR[17] ,Channel 17 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 16. " CHNERR[16] ,Channel 16 Error" "No error,Error"
|
|
bitfld.long 0x04 15. " CHNERR[15] ,Channel 15 Error" "No error,Error"
|
|
bitfld.long 0x04 14. " CHNERR[14] ,Channel 14 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 13. " CHNERR[13] ,Channel 13 Error" "No error,Error"
|
|
bitfld.long 0x04 12. " CHNERR[12] ,Channel 12 Error" "No error,Error"
|
|
bitfld.long 0x04 11. " CHNERR[11] ,Channel 11 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CHNERR[10] ,Channel 10 Error" "No error,Error"
|
|
bitfld.long 0x04 9. " CHNERR[9] ,Channel 9 Error" "No error,Error"
|
|
bitfld.long 0x04 8. " CHNERR[8] ,Channel 8 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CHNERR[7] ,Channel 7 Error" "No error,Error"
|
|
bitfld.long 0x04 6. " CHNERR[6] ,Channel 6 Error" "No error,Error"
|
|
bitfld.long 0x04 5. " CHNERR[5] ,Channel 5 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CHNERR[4] ,Channel 4 Error" "No error,Error"
|
|
bitfld.long 0x04 3. " CHNERR[3] ,Channel 3 Error" "No error,Error"
|
|
bitfld.long 0x04 2. " CHNERR[2] ,Channel 2 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHNERR[1] ,Channel 1 Error" "No error,Error"
|
|
bitfld.long 0x04 0. " CHNERR[0] ,Channel 0 Error" "No error,Error"
|
|
textline ""
|
|
group.long 0x38++0x13
|
|
line.long 0x00 "CONFIG,Configuration Register"
|
|
sif (!cpuis("IMX6*"))
|
|
bitfld.long 0x00 12. " DSPCTRL ,SDMA control mode" "Dual core,Single core"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " RTDOBS ,Real-Time Debug Pins are Used" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACR ,AHB/SDMA Core Clock Ratio" "2x core freq,Core freq"
|
|
bitfld.long 0x00 0.--1. " CSM ,Selects the Context Switch Mode" "Static,Dynamic low power,Dynamic with no loop,Dynamic"
|
|
line.long 0x04 "SDMA_LOCK,SDMA Lock Register"
|
|
bitfld.long 0x04 1. " SRESET_LOCK_CLR ,LOCK bit is cleared on a software reset" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " LOCK ,Access to update SDMA script memory" "Not locked,Locked"
|
|
line.long 0x08 "ONCE_ENB,OnCE Enable Register"
|
|
bitfld.long 0x08 0. " ENB ,OnCE Enable" "Disabled,Enabled"
|
|
line.long 0x0c "ONCE_DATA,OnCE Data Register"
|
|
line.long 0x10 "ONCE_INSTR,OnCE Instruction Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " INSTR ,Instruction Register of the OnCE JTAG Controller"
|
|
rgroup.long 0x4c++0x03
|
|
line.long 0x00 "ONCE_STAT,OnCE Status Register"
|
|
bitfld.long 0x00 12.--15. " PST[3:0] ,Processor Status" "Program,Data,Change of flow,Change of flow in loop,Debug,Functional unit,Sleep,Save,Program in sleep,Data in sleep,Change of flow in sleep,Change flow in loop in sleep,Debug in sleep,Functional unit in sleep,Sleep after reset,Restore"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCV ,RCV Flag" "Cleared,Set"
|
|
bitfld.long 0x00 10. " EDR ,SDMA has Entered Debug Mode After an External Debug Request" "Normal,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ODR ,SDMA has Entered Debug Mode After a OnCE Debug Request" "Normal,Debug"
|
|
bitfld.long 0x00 8. " SWB ,SDMA has Entered Debug Mode After a Software Breakpoint" "Normal,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MST ,OnCE is Controlled from the AP Peripheral Interface" "JTAG,AP"
|
|
bitfld.long 0x00 2. " ECDR[2] ,Event Cell Debug Request from data_cond" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ECDR[1] ,Event Cell Debug Request from addrb_cond" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " ECDR[0] ,Event Cell Debug Request from addra_cond" "Not requested,Requested"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ONCE_CMD,OnCE Command Register"
|
|
bitfld.long 0x00 0.--3. " CMD ,Command" "Rstatus,Dmov,Exec_once,Run_core,Exec_core,Debug_rqst,Rbuffer,?..."
|
|
group.long 0x58++0x7
|
|
line.long 0x00 "ILLINSTADDR,Illegal Instruction Trap Address Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLINSTADDR ,Illegal Instruction Trap Address"
|
|
line.long 0x04 "CHN0ADDR,Channel 0 Boot Address Register"
|
|
bitfld.long 0x04 14. " SMSZ ,Scratch Memory Size" "24,32"
|
|
hexmask.long.word 0x04 0.--13. 1. " CHN0ADDR ,Channel 0 Boot Address"
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "EVT_MIRROR,DMA Requests Register"
|
|
bitfld.long 0x00 31. " EVENTS[31] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " EVENTS[30] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 29. " EVENTS[29] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " EVENTS[28] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 27. " EVENTS[27] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 26. " EVENTS[26] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EVENTS[25] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " EVENTS[24] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EVENTS[23] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " EVENTS[22] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EVENTS[21] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " EVENTS[20] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EVENTS[19] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " EVENTS[18] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENTS[17] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " EVENTS[16] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EVENTS[15] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " EVENTS[14] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EVENTS[13] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " EVENTS[12] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EVENTS[11] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " EVENTS[10] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EVENTS[9] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " EVENTS[8] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EVENTS[7] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " EVENTS[6] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EVENTS[5] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " EVENTS[4] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EVENTS[3] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " EVENTS[2] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EVENTS[1] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " EVENTS[0] ,DMA Request" "Not requested,Requested"
|
|
line.long 0x04 "EVT_MIRROR2,DMA Requests 2 Register"
|
|
bitfld.long 0x04 15. " EVENTS[47] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " EVENTS[46] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 13. " EVENTS[45] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " EVENTS[44] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EVENTS[43] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " EVENTS[42] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EVENTS[41] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " EVENTS[40] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EVENTS[39] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " EVENTS[38] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EVENTS[37] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " EVENTS[36] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EVENTS[35] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " EVENTS[34] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EVENTS[33] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " EVENTS[32] ,DMA Request" "Not requested,Requested"
|
|
textline ""
|
|
group.long 0x70++0x7
|
|
line.long 0x00 "XTRIG_CONF1,Cross-Trigger Events Configuration Register 1"
|
|
bitfld.long 0x00 30. " CNF3 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x00 24.--29. " NUM3[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22. " CNF2 ,Configuration of the SDMA" "Channel,DMA request"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " NUM2[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 14. " CNF1 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x00 8.--13. " NUM1[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CNF0 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x00 0.--5. " NUM0[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "XTRIG_CONF2,Cross-Trigger Events Configuration Register 2"
|
|
bitfld.long 0x04 30. " CNF7 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x04 24.--29. " NUM7[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 22. " CNF6 ,Configuration of the SDMA" "Channel,DMA request"
|
|
textline " "
|
|
bitfld.long 0x04 16.--21. " NUM6[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 14. " CNF5 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x04 8.--13. " NUM5[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 6. " CNF4 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x04 0.--5. " NUM4[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&(!cpuis("IMX6*")))
|
|
group.long 0x7c++0x23
|
|
line.long 0x0 "PRF_CNT_1,Profile Counter 1 Register"
|
|
hexmask.long.word 0x0 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0x0 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0x0 0.--21. 1. " COUNTER ,Counter field"
|
|
line.long 0x4 "PRF_CNT_2,Profile Counter 2 Register"
|
|
hexmask.long.word 0x4 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0x4 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0x4 0.--21. 1. " COUNTER ,Counter field"
|
|
line.long 0x8 "PRF_CNT_3,Profile Counter 3 Register"
|
|
hexmask.long.word 0x8 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0x8 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0x8 0.--21. 1. " COUNTER ,Counter field"
|
|
line.long 0xC "PRF_CNT_4,Profile Counter 4 Register"
|
|
hexmask.long.word 0xC 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0xC 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0xC 0.--21. 1. " COUNTER ,Counter field"
|
|
line.long 0x10 "PRF_CNT_5,Profile Counter 5 Register"
|
|
hexmask.long.word 0x10 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0x10 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0x10 0.--21. 1. " COUNTER ,Counter field"
|
|
line.long 0x14 "PRF_CNT_6,Profile Counter 6 Register"
|
|
hexmask.long.word 0x14 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0x14 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0x14 0.--21. 1. " COUNTER ,Counter field"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "PRF_CFG,Profile Config/Status Register"
|
|
eventfld.long 0x00 13. " ISR ,Profile counter overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 12. " OFL6 ,Profile counter 6 overflow status" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFL5 ,Profile counter 5 overflow status" "No overflow,Overflow"
|
|
bitfld.long 0x00 10. " OFL4 ,Profile counter 4 overflow status" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFL3 ,Profile counter 3 overflow status" "No overflow,Overflow"
|
|
bitfld.long 0x00 8. " OFL2 ,Profile counter 2 overflow status" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OFL1 ,Profile counter 1 overflow status" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " INT_EN_6 ,Interrupt enabled for profile counter 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INT_EN_5 ,Interrupt enabled for profile counter 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INT_EN_4 ,Interrupt enabled for profile counter 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT_EN_3 ,Interrupt enabled for profile counter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INT_EN_2 ,Interrupt enabled for profile counter 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INT_EN_1 ,Interrupt enabled for profile counter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Bit enables the profile counters" "Disabled,Enabled"
|
|
endif
|
|
textline ""
|
|
width 23.
|
|
sif (cpuis("IMX6*"))
|
|
group.long 0x100++0x7F
|
|
line.long 0x0 "SDMAARM_SDMA_CHNPRI0 ,Channel Priority 0 Register"
|
|
bitfld.long 0x0 0.--2. " CHNPRI0 ,Channel 0 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x4 "SDMAARM_SDMA_CHNPRI1 ,Channel Priority 1 Register"
|
|
bitfld.long 0x4 0.--2. " CHNPRI1 ,Channel 1 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x8 "SDMAARM_SDMA_CHNPRI2 ,Channel Priority 2 Register"
|
|
bitfld.long 0x8 0.--2. " CHNPRI2 ,Channel 2 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0xC "SDMAARM_SDMA_CHNPRI3 ,Channel Priority 3 Register"
|
|
bitfld.long 0xC 0.--2. " CHNPRI3 ,Channel 3 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x10 "SDMAARM_SDMA_CHNPRI4 ,Channel Priority 4 Register"
|
|
bitfld.long 0x10 0.--2. " CHNPRI4 ,Channel 4 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x14 "SDMAARM_SDMA_CHNPRI5 ,Channel Priority 5 Register"
|
|
bitfld.long 0x14 0.--2. " CHNPRI5 ,Channel 5 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x18 "SDMAARM_SDMA_CHNPRI6 ,Channel Priority 6 Register"
|
|
bitfld.long 0x18 0.--2. " CHNPRI6 ,Channel 6 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x1C "SDMAARM_SDMA_CHNPRI7 ,Channel Priority 7 Register"
|
|
bitfld.long 0x1C 0.--2. " CHNPRI7 ,Channel 7 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x20 "SDMAARM_SDMA_CHNPRI8 ,Channel Priority 8 Register"
|
|
bitfld.long 0x20 0.--2. " CHNPRI8 ,Channel 8 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x24 "SDMAARM_SDMA_CHNPRI9 ,Channel Priority 9 Register"
|
|
bitfld.long 0x24 0.--2. " CHNPRI9 ,Channel 9 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x28 "SDMAARM_SDMA_CHNPRI10,Channel Priority 10 Register"
|
|
bitfld.long 0x28 0.--2. " CHNPRI10 ,Channel 10 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x2C "SDMAARM_SDMA_CHNPRI11,Channel Priority 11 Register"
|
|
bitfld.long 0x2C 0.--2. " CHNPRI11 ,Channel 11 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x30 "SDMAARM_SDMA_CHNPRI12,Channel Priority 12 Register"
|
|
bitfld.long 0x30 0.--2. " CHNPRI12 ,Channel 12 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x34 "SDMAARM_SDMA_CHNPRI13,Channel Priority 13 Register"
|
|
bitfld.long 0x34 0.--2. " CHNPRI13 ,Channel 13 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x38 "SDMAARM_SDMA_CHNPRI14,Channel Priority 14 Register"
|
|
bitfld.long 0x38 0.--2. " CHNPRI14 ,Channel 14 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x3C "SDMAARM_SDMA_CHNPRI15,Channel Priority 15 Register"
|
|
bitfld.long 0x3C 0.--2. " CHNPRI15 ,Channel 15 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x40 "SDMAARM_SDMA_CHNPRI16,Channel Priority 16 Register"
|
|
bitfld.long 0x40 0.--2. " CHNPRI16 ,Channel 16 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x44 "SDMAARM_SDMA_CHNPRI17,Channel Priority 17 Register"
|
|
bitfld.long 0x44 0.--2. " CHNPRI17 ,Channel 17 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x48 "SDMAARM_SDMA_CHNPRI18,Channel Priority 18 Register"
|
|
bitfld.long 0x48 0.--2. " CHNPRI18 ,Channel 18 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x4C "SDMAARM_SDMA_CHNPRI19,Channel Priority 19 Register"
|
|
bitfld.long 0x4C 0.--2. " CHNPRI19 ,Channel 19 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x50 "SDMAARM_SDMA_CHNPRI20,Channel Priority 20 Register"
|
|
bitfld.long 0x50 0.--2. " CHNPRI20 ,Channel 20 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x54 "SDMAARM_SDMA_CHNPRI21,Channel Priority 21 Register"
|
|
bitfld.long 0x54 0.--2. " CHNPRI21 ,Channel 21 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x58 "SDMAARM_SDMA_CHNPRI22,Channel Priority 22 Register"
|
|
bitfld.long 0x58 0.--2. " CHNPRI22 ,Channel 22 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x5C "SDMAARM_SDMA_CHNPRI23,Channel Priority 23 Register"
|
|
bitfld.long 0x5C 0.--2. " CHNPRI23 ,Channel 23 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x60 "SDMAARM_SDMA_CHNPRI24,Channel Priority 24 Register"
|
|
bitfld.long 0x60 0.--2. " CHNPRI24 ,Channel 24 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x64 "SDMAARM_SDMA_CHNPRI25,Channel Priority 25 Register"
|
|
bitfld.long 0x64 0.--2. " CHNPRI25 ,Channel 25 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x68 "SDMAARM_SDMA_CHNPRI26,Channel Priority 26 Register"
|
|
bitfld.long 0x68 0.--2. " CHNPRI26 ,Channel 26 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x6C "SDMAARM_SDMA_CHNPRI27,Channel Priority 27 Register"
|
|
bitfld.long 0x6C 0.--2. " CHNPRI27 ,Channel 27 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x70 "SDMAARM_SDMA_CHNPRI28,Channel Priority 28 Register"
|
|
bitfld.long 0x70 0.--2. " CHNPRI28 ,Channel 28 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x74 "SDMAARM_SDMA_CHNPRI29,Channel Priority 29 Register"
|
|
bitfld.long 0x74 0.--2. " CHNPRI29 ,Channel 29 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x78 "SDMAARM_SDMA_CHNPRI30,Channel Priority 30 Register"
|
|
bitfld.long 0x78 0.--2. " CHNPRI30 ,Channel 30 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x7C "SDMAARM_SDMA_CHNPRI31,Channel Priority 31 Register"
|
|
bitfld.long 0x7C 0.--2. " CHNPRI31 ,Channel 31 priority" ",1,2,3,4,5,6,7"
|
|
endif
|
|
width 11.
|
|
tree "Channel Enable RAM Registers"
|
|
group.long 0x200++0xbf
|
|
line.long 0x0 "CHNENBL0 ,Channel 0 Enable RAM"
|
|
bitfld.long 0x0 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
line.long 0x4 "CHNENBL1 ,Channel 1 Enable RAM"
|
|
bitfld.long 0x4 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
line.long 0x8 "CHNENBL2 ,Channel 2 Enable RAM"
|
|
bitfld.long 0x8 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
line.long 0xC "CHNENBL3 ,Channel 3 Enable RAM"
|
|
bitfld.long 0xC 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
line.long 0x10 "CHNENBL4 ,Channel 4 Enable RAM"
|
|
bitfld.long 0x10 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
line.long 0x14 "CHNENBL5 ,Channel 5 Enable RAM"
|
|
bitfld.long 0x14 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
line.long 0x18 "CHNENBL6 ,Channel 6 Enable RAM"
|
|
bitfld.long 0x18 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
line.long 0x1C "CHNENBL7 ,Channel 7 Enable RAM"
|
|
bitfld.long 0x1C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
line.long 0x20 "CHNENBL8 ,Channel 8 Enable RAM"
|
|
bitfld.long 0x20 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
line.long 0x24 "CHNENBL9 ,Channel 9 Enable RAM"
|
|
bitfld.long 0x24 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
line.long 0x28 "CHNENBL10,Channel 10 Enable RAM"
|
|
bitfld.long 0x28 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
line.long 0x2C "CHNENBL11,Channel 11 Enable RAM"
|
|
bitfld.long 0x2C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
line.long 0x30 "CHNENBL12,Channel 12 Enable RAM"
|
|
bitfld.long 0x30 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
line.long 0x34 "CHNENBL13,Channel 13 Enable RAM"
|
|
bitfld.long 0x34 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
line.long 0x38 "CHNENBL14,Channel 14 Enable RAM"
|
|
bitfld.long 0x38 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
line.long 0x3C "CHNENBL15,Channel 15 Enable RAM"
|
|
bitfld.long 0x3C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
line.long 0x40 "CHNENBL16,Channel 16 Enable RAM"
|
|
bitfld.long 0x40 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
line.long 0x44 "CHNENBL17,Channel 17 Enable RAM"
|
|
bitfld.long 0x44 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
line.long 0x48 "CHNENBL18,Channel 18 Enable RAM"
|
|
bitfld.long 0x48 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
line.long 0x4C "CHNENBL19,Channel 19 Enable RAM"
|
|
bitfld.long 0x4C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
line.long 0x50 "CHNENBL20,Channel 20 Enable RAM"
|
|
bitfld.long 0x50 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
line.long 0x54 "CHNENBL21,Channel 21 Enable RAM"
|
|
bitfld.long 0x54 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
line.long 0x58 "CHNENBL22,Channel 22 Enable RAM"
|
|
bitfld.long 0x58 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
line.long 0x5C "CHNENBL23,Channel 23 Enable RAM"
|
|
bitfld.long 0x5C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
line.long 0x60 "CHNENBL24,Channel 24 Enable RAM"
|
|
bitfld.long 0x60 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
line.long 0x64 "CHNENBL25,Channel 25 Enable RAM"
|
|
bitfld.long 0x64 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
line.long 0x68 "CHNENBL26,Channel 26 Enable RAM"
|
|
bitfld.long 0x68 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
line.long 0x6C "CHNENBL27,Channel 27 Enable RAM"
|
|
bitfld.long 0x6C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
line.long 0x70 "CHNENBL28,Channel 28 Enable RAM"
|
|
bitfld.long 0x70 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
line.long 0x74 "CHNENBL29,Channel 29 Enable RAM"
|
|
bitfld.long 0x74 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
line.long 0x78 "CHNENBL30,Channel 30 Enable RAM"
|
|
bitfld.long 0x78 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
line.long 0x7C "CHNENBL31,Channel 31 Enable RAM"
|
|
bitfld.long 0x7C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
line.long 0x80 "CHNENBL32,Channel 32 Enable RAM"
|
|
bitfld.long 0x80 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
line.long 0x84 "CHNENBL33,Channel 33 Enable RAM"
|
|
bitfld.long 0x84 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
line.long 0x88 "CHNENBL34,Channel 34 Enable RAM"
|
|
bitfld.long 0x88 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
line.long 0x8C "CHNENBL35,Channel 35 Enable RAM"
|
|
bitfld.long 0x8C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
line.long 0x90 "CHNENBL36,Channel 36 Enable RAM"
|
|
bitfld.long 0x90 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
line.long 0x94 "CHNENBL37,Channel 37 Enable RAM"
|
|
bitfld.long 0x94 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
line.long 0x98 "CHNENBL38,Channel 38 Enable RAM"
|
|
bitfld.long 0x98 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
line.long 0x9C "CHNENBL39,Channel 39 Enable RAM"
|
|
bitfld.long 0x9C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
line.long 0xA0 "CHNENBL40,Channel 40 Enable RAM"
|
|
bitfld.long 0xA0 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
line.long 0xA4 "CHNENBL41,Channel 41 Enable RAM"
|
|
bitfld.long 0xA4 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
line.long 0xA8 "CHNENBL42,Channel 42 Enable RAM"
|
|
bitfld.long 0xA8 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
line.long 0xAC "CHNENBL43,Channel 43 Enable RAM"
|
|
bitfld.long 0xAC 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
line.long 0xB0 "CHNENBL44,Channel 44 Enable RAM"
|
|
bitfld.long 0xB0 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
line.long 0xB4 "CHNENBL45,Channel 45 Enable RAM"
|
|
bitfld.long 0xB4 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
line.long 0xB8 "CHNENBL46,Channel 46 Enable RAM"
|
|
bitfld.long 0xB8 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
line.long 0xBC "CHNENBL47,Channel 47 Enable RAM"
|
|
bitfld.long 0xBC 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
tree.end
|
|
width 10.
|
|
sif (!cpuis("IMX6*"))
|
|
tree "Channel Priority Registers"
|
|
group.long 0x100++0x7f
|
|
line.long 0x0 "CHNPRI0 ,Channel 0 Priority Register"
|
|
bitfld.long 0x0 0.--2. " CHNPRI0 ,Priority of Channel Number 0 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CHNPRI1 ,Channel 1 Priority Register"
|
|
bitfld.long 0x4 0.--2. " CHNPRI1 ,Priority of Channel Number 1 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CHNPRI2 ,Channel 2 Priority Register"
|
|
bitfld.long 0x8 0.--2. " CHNPRI2 ,Priority of Channel Number 2 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0xC "CHNPRI3 ,Channel 3 Priority Register"
|
|
bitfld.long 0xC 0.--2. " CHNPRI3 ,Priority of Channel Number 3 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CHNPRI4 ,Channel 4 Priority Register"
|
|
bitfld.long 0x10 0.--2. " CHNPRI4 ,Priority of Channel Number 4 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CHNPRI5 ,Channel 5 Priority Register"
|
|
bitfld.long 0x14 0.--2. " CHNPRI5 ,Priority of Channel Number 5 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CHNPRI6 ,Channel 6 Priority Register"
|
|
bitfld.long 0x18 0.--2. " CHNPRI6 ,Priority of Channel Number 6 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x1C "CHNPRI7 ,Channel 7 Priority Register"
|
|
bitfld.long 0x1C 0.--2. " CHNPRI7 ,Priority of Channel Number 7 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x20 "CHNPRI8 ,Channel 8 Priority Register"
|
|
bitfld.long 0x20 0.--2. " CHNPRI8 ,Priority of Channel Number 8 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x24 "CHNPRI9 ,Channel 9 Priority Register"
|
|
bitfld.long 0x24 0.--2. " CHNPRI9 ,Priority of Channel Number 9 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x28 "CHNPRI10,Channel 10 Priority Register"
|
|
bitfld.long 0x28 0.--2. " CHNPRI10 ,Priority of Channel Number 10" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x2C "CHNPRI11,Channel 11 Priority Register"
|
|
bitfld.long 0x2C 0.--2. " CHNPRI11 ,Priority of Channel Number 11" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x30 "CHNPRI12,Channel 12 Priority Register"
|
|
bitfld.long 0x30 0.--2. " CHNPRI12 ,Priority of Channel Number 12" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x34 "CHNPRI13,Channel 13 Priority Register"
|
|
bitfld.long 0x34 0.--2. " CHNPRI13 ,Priority of Channel Number 13" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x38 "CHNPRI14,Channel 14 Priority Register"
|
|
bitfld.long 0x38 0.--2. " CHNPRI14 ,Priority of Channel Number 14" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x3C "CHNPRI15,Channel 15 Priority Register"
|
|
bitfld.long 0x3C 0.--2. " CHNPRI15 ,Priority of Channel Number 15" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x40 "CHNPRI16,Channel 16 Priority Register"
|
|
bitfld.long 0x40 0.--2. " CHNPRI16 ,Priority of Channel Number 16" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x44 "CHNPRI17,Channel 17 Priority Register"
|
|
bitfld.long 0x44 0.--2. " CHNPRI17 ,Priority of Channel Number 17" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x48 "CHNPRI18,Channel 18 Priority Register"
|
|
bitfld.long 0x48 0.--2. " CHNPRI18 ,Priority of Channel Number 18" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x4C "CHNPRI19,Channel 19 Priority Register"
|
|
bitfld.long 0x4C 0.--2. " CHNPRI19 ,Priority of Channel Number 19" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x50 "CHNPRI20,Channel 20 Priority Register"
|
|
bitfld.long 0x50 0.--2. " CHNPRI20 ,Priority of Channel Number 20" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x54 "CHNPRI21,Channel 21 Priority Register"
|
|
bitfld.long 0x54 0.--2. " CHNPRI21 ,Priority of Channel Number 21" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x58 "CHNPRI22,Channel 22 Priority Register"
|
|
bitfld.long 0x58 0.--2. " CHNPRI22 ,Priority of Channel Number 22" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x5C "CHNPRI23,Channel 23 Priority Register"
|
|
bitfld.long 0x5C 0.--2. " CHNPRI23 ,Priority of Channel Number 23" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x60 "CHNPRI24,Channel 24 Priority Register"
|
|
bitfld.long 0x60 0.--2. " CHNPRI24 ,Priority of Channel Number 24" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x64 "CHNPRI25,Channel 25 Priority Register"
|
|
bitfld.long 0x64 0.--2. " CHNPRI25 ,Priority of Channel Number 25" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x68 "CHNPRI26,Channel 26 Priority Register"
|
|
bitfld.long 0x68 0.--2. " CHNPRI26 ,Priority of Channel Number 26" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x6C "CHNPRI27,Channel 27 Priority Register"
|
|
bitfld.long 0x6C 0.--2. " CHNPRI27 ,Priority of Channel Number 27" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x70 "CHNPRI28,Channel 28 Priority Register"
|
|
bitfld.long 0x70 0.--2. " CHNPRI28 ,Priority of Channel Number 28" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x74 "CHNPRI29,Channel 29 Priority Register"
|
|
bitfld.long 0x74 0.--2. " CHNPRI29 ,Priority of Channel Number 29" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x78 "CHNPRI30,Channel 30 Priority Register"
|
|
bitfld.long 0x78 0.--2. " CHNPRI30 ,Priority of Channel Number 30" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x7C "CHNPRI31,Channel 31 Priority Register"
|
|
bitfld.long 0x7C 0.--2. " CHNPRI31 ,Priority of Channel Number 31" "No running channel,1,2,3,4,5,6,7"
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "SPBA (Shared Peripheral Bus Arbiter)"
|
|
base ad:0x5003C000
|
|
width 7.
|
|
group.long 0x0++0x7F
|
|
line.long 0x0 "PRR0,Peripheral Right Register 0"
|
|
rbitfld.long 0x0 30.--31. " RMO0 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x0 16.--17. " ROI0 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RAR0[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x0 1. " RAR0[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x0 0. " RAR0[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x4 "PRR1,Peripheral Right Register 0"
|
|
rbitfld.long 0x4 30.--31. " RMO1 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x4 16.--17. " ROI1 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x4 2. " RAR1[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x4 1. " RAR1[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x4 0. " RAR1[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x8 "PRR2,Peripheral Right Register 0"
|
|
rbitfld.long 0x8 30.--31. " RMO2 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x8 16.--17. " ROI2 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x8 2. " RAR2[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x8 1. " RAR2[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x8 0. " RAR2[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0xC "PRR3,Peripheral Right Register 0"
|
|
rbitfld.long 0xC 30.--31. " RMO3 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0xC 16.--17. " ROI3 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0xC 2. " RAR3[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0xC 1. " RAR3[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0xC 0. " RAR3[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x10 "PRR4,Peripheral Right Register 0"
|
|
rbitfld.long 0x10 30.--31. " RMO4 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x10 16.--17. " ROI4 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x10 2. " RAR4[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x10 1. " RAR4[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x10 0. " RAR4[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x14 "PRR5,Peripheral Right Register 0"
|
|
rbitfld.long 0x14 30.--31. " RMO5 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x14 16.--17. " ROI5 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x14 2. " RAR5[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x14 1. " RAR5[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x14 0. " RAR5[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x18 "PRR6,Peripheral Right Register 0"
|
|
rbitfld.long 0x18 30.--31. " RMO6 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x18 16.--17. " ROI6 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x18 2. " RAR6[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x18 1. " RAR6[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x18 0. " RAR6[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x1C "PRR7,Peripheral Right Register 0"
|
|
rbitfld.long 0x1C 30.--31. " RMO7 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x1C 16.--17. " ROI7 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " RAR7[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x1C 1. " RAR7[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x1C 0. " RAR7[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x20 "PRR8,Peripheral Right Register 0"
|
|
rbitfld.long 0x20 30.--31. " RMO8 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x20 16.--17. " ROI8 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x20 2. " RAR8[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x20 1. " RAR8[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x20 0. " RAR8[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x24 "PRR9,Peripheral Right Register 0"
|
|
rbitfld.long 0x24 30.--31. " RMO9 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x24 16.--17. " ROI9 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x24 2. " RAR9[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x24 1. " RAR9[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x24 0. " RAR9[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x28 "PRR10,Peripheral Right Register 0"
|
|
rbitfld.long 0x28 30.--31. " RMO10 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x28 16.--17. " ROI10 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x28 2. " RAR10[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x28 1. " RAR10[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x28 0. " RAR10[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x2C "PRR11,Peripheral Right Register 0"
|
|
rbitfld.long 0x2C 30.--31. " RMO11 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x2C 16.--17. " ROI11 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x2C 2. " RAR11[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x2C 1. " RAR11[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x2C 0. " RAR11[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x30 "PRR12,Peripheral Right Register 0"
|
|
rbitfld.long 0x30 30.--31. " RMO12 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x30 16.--17. " ROI12 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x30 2. " RAR12[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x30 1. " RAR12[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x30 0. " RAR12[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x34 "PRR13,Peripheral Right Register 0"
|
|
rbitfld.long 0x34 30.--31. " RMO13 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x34 16.--17. " ROI13 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x34 2. " RAR13[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x34 1. " RAR13[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x34 0. " RAR13[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x38 "PRR14,Peripheral Right Register 0"
|
|
rbitfld.long 0x38 30.--31. " RMO14 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x38 16.--17. " ROI14 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x38 2. " RAR14[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x38 1. " RAR14[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x38 0. " RAR14[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x3C "PRR15,Peripheral Right Register 0"
|
|
rbitfld.long 0x3C 30.--31. " RMO15 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x3C 16.--17. " ROI15 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x3C 2. " RAR15[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x3C 1. " RAR15[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x3C 0. " RAR15[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x40 "PRR16,Peripheral Right Register 0"
|
|
rbitfld.long 0x40 30.--31. " RMO16 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x40 16.--17. " ROI16 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x40 2. " RAR16[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x40 1. " RAR16[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x40 0. " RAR16[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x44 "PRR17,Peripheral Right Register 0"
|
|
rbitfld.long 0x44 30.--31. " RMO17 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x44 16.--17. " ROI17 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x44 2. " RAR17[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x44 1. " RAR17[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x44 0. " RAR17[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x48 "PRR18,Peripheral Right Register 0"
|
|
rbitfld.long 0x48 30.--31. " RMO18 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x48 16.--17. " ROI18 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x48 2. " RAR18[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x48 1. " RAR18[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x48 0. " RAR18[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x4C "PRR19,Peripheral Right Register 0"
|
|
rbitfld.long 0x4C 30.--31. " RMO19 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x4C 16.--17. " ROI19 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x4C 2. " RAR19[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x4C 1. " RAR19[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x4C 0. " RAR19[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x50 "PRR20,Peripheral Right Register 0"
|
|
rbitfld.long 0x50 30.--31. " RMO20 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x50 16.--17. " ROI20 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x50 2. " RAR20[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x50 1. " RAR20[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x50 0. " RAR20[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x54 "PRR21,Peripheral Right Register 0"
|
|
rbitfld.long 0x54 30.--31. " RMO21 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x54 16.--17. " ROI21 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x54 2. " RAR21[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x54 1. " RAR21[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x54 0. " RAR21[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x58 "PRR22,Peripheral Right Register 0"
|
|
rbitfld.long 0x58 30.--31. " RMO22 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x58 16.--17. " ROI22 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x58 2. " RAR22[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x58 1. " RAR22[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x58 0. " RAR22[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x5C "PRR23,Peripheral Right Register 0"
|
|
rbitfld.long 0x5C 30.--31. " RMO23 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x5C 16.--17. " ROI23 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x5C 2. " RAR23[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x5C 1. " RAR23[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x5C 0. " RAR23[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x60 "PRR24,Peripheral Right Register 0"
|
|
rbitfld.long 0x60 30.--31. " RMO24 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x60 16.--17. " ROI24 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x60 2. " RAR24[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x60 1. " RAR24[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x60 0. " RAR24[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x64 "PRR25,Peripheral Right Register 0"
|
|
rbitfld.long 0x64 30.--31. " RMO25 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x64 16.--17. " ROI25 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x64 2. " RAR25[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x64 1. " RAR25[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x64 0. " RAR25[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x68 "PRR26,Peripheral Right Register 0"
|
|
rbitfld.long 0x68 30.--31. " RMO26 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x68 16.--17. " ROI26 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x68 2. " RAR26[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x68 1. " RAR26[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x68 0. " RAR26[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x6C "PRR27,Peripheral Right Register 0"
|
|
rbitfld.long 0x6C 30.--31. " RMO27 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x6C 16.--17. " ROI27 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x6C 2. " RAR27[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x6C 1. " RAR27[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x6C 0. " RAR27[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x70 "PRR28,Peripheral Right Register 0"
|
|
rbitfld.long 0x70 30.--31. " RMO28 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x70 16.--17. " ROI28 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x70 2. " RAR28[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x70 1. " RAR28[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x70 0. " RAR28[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x74 "PRR29,Peripheral Right Register 0"
|
|
rbitfld.long 0x74 30.--31. " RMO29 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x74 16.--17. " ROI29 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x74 2. " RAR29[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x74 1. " RAR29[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x74 0. " RAR29[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x78 "PRR30,Peripheral Right Register 0"
|
|
rbitfld.long 0x78 30.--31. " RMO30 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x78 16.--17. " ROI30 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x78 2. " RAR30[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x78 1. " RAR30[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x78 0. " RAR30[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
line.long 0x7C "PRR31,Peripheral Right Register 0"
|
|
rbitfld.long 0x7C 30.--31. " RMO31 ,Requesting Master Owner" "Un-owned,Reserved,Owned by another master,Owned by requesting master"
|
|
rbitfld.long 0x7C 16.--17. " ROI31 ,Resource Owner ID" "Un-owned,Master A,Master B,Master C"
|
|
textline " "
|
|
bitfld.long 0x7C 2. " RAR31[2] ,Master C Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x7C 1. " RAR31[1] ,Master B Resource Access Right" "Not allowed,Allowed"
|
|
bitfld.long 0x7C 0. " RAR31[0] ,Master A Resource Access Right" "Not allowed,Allowed"
|
|
width 0xB
|
|
tree.end
|
|
tree "SRC (System Reset Controller)"
|
|
base ad:0x53fd0000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCR,System Reset Controller"
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 25. " DBG_RST_MSK_PG ,Debug reset mask" "Unmasked,Masked"
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 24. " CORE3_ENABLE ,CPU core3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CORE2_ENABLE ,CPU core2 enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 22. " CORE1_ENABLE ,CPU core1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CORES_DBG_RST ,Software reset for debug of arm platform only" "Not asserted,Asserted"
|
|
else
|
|
bitfld.long 0x00 21. " CORES_DBG_RST ,Software reset for debug of arm platform only" "Not asserted,Asserted"
|
|
endif
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 20. " CORE3_DBG_RST ,Software reset for core3 debug only" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " CORE2_DBG_RST ,Software reset for core2 debug only" "Not asserted,Asserted"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="IMXSOLOLITE")
|
|
bitfld.long 0x00 18. " CORE1_DBG_RST ,Software reset for core1 debug only" "Not asserted,Asserted"
|
|
bitfld.long 0x00 17. " CORE0_DBG_RST ,Software reset for core0 debug only" "Not asserted,Asserted"
|
|
else
|
|
bitfld.long 0x00 17. " CORE0_DBG_RST ,Software reset for core0 debug only" "Not asserted,Asserted"
|
|
endif
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMXSOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 16. " CORE3_RST ,Software reset for core3 only" "Not asserted,Asserted"
|
|
bitfld.long 0x00 15. " CORE2_RST ,Software reset for core2 only" "Not asserted,Asserted"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 14. " CORE1_RST ,Software reset for core1 only" "Not asserted,Asserted"
|
|
bitfld.long 0x00 13. " CORE0_RST ,Software reset for core0 only" "Not asserted,Asserted"
|
|
else
|
|
bitfld.long 0x00 13. " CORE0_RST ,Software reset for core0 only" "Not asserted,Asserted"
|
|
endif
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 12. " SW_IPU2_RST ,Software reset for ipu2" "Not asserted,Asserted"
|
|
endif
|
|
endif
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX6*")||cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
textline " "
|
|
bitfld.long 0x00 11. " EIM_RST ,EIM Reset" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7.--10. " MASK_WDOG_RST ,Mask wdog_rst_b source" "Not masked,Not masked,Not masked,Not masked,Not masked,Masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " WARM_RST_BYPASS_COUNT ,Ckil cycles to count before bypassing the MMDC ack for warm reset" "Disabled,16 ckil,32 ckil,64 ckil"
|
|
elif (cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " WARM_RST_BYPASS_COUNT ,XTALI cycles to count before bypassing the MMDC ack for warm reset" "Disabled,16 XTALI,32 XTALI,64 XTALI"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " WARM_RST_BYPASS_COUNT ,Ckil cycles to count before bypassing the emi ack for warm reset" "Disabled,16 ckil,32 ckil,64 ckil"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " SW_OPEN_VG_RST ,Software reset for open_vg" "Not asserted,Asserted"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
textline " "
|
|
bitfld.long 0x00 0. " WARM_RESET_ENABLE ,Warm reset enable bit" "Disabled,Enabled"
|
|
elif (cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 2. " SW_VPU_RST ,Software reset for vpu" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SW_GPU_RST ,Software reset for gpu" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " WARM_RESET_ENABLE ,Warm reset enable bit" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 3. " SW_IPU_RST ,Software reset for ipu" "Not asserted,Asserted"
|
|
bitfld.long 0x00 2. " SW_VPU_RST ,Software reset for vpu" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SW_GPU_RST ,Software reset for gpu" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " WARM_RESET_ENABLE ,Warm reset enable bit" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpu()=="IMX61"||cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpuis("IMX6*"))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SBMR,SRC Boot Mode Register"
|
|
sif cpuis("IMX50*")
|
|
bitfld.long 0x00 27.--29. " TEST_MODE[2:0] ,Test Mode Fuse Select" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
elif (!cpuis("IMX6*"))
|
|
bitfld.long 0x00 26. " BT_FUSE_SEL ,Boot fuse select" "0,1"
|
|
bitfld.long 0x00 24.--25. " BMOD[1:0] ,Boot mode" "0,1,2,3"
|
|
textline " "
|
|
elif (cpuis("IMX6*"))
|
|
hexmask.long.byte 0x00 24.--31. 1. " BOOT_CFG4 ,Boot configuration4"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " BOOT_CFG3 ,Boot configuration3"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BOOT_CFG2 ,Boot configuration2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BOOT_CFG1 ,Boot configuration1"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SBMR,SRC Boot Mode Register"
|
|
bitfld.long 0x00 29.--31. " BT_LPB_FREQ[2:0] ,BT_LPB_FREQ[2:0]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. " BT_HPN_EN ,BT_HPN_EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BT_USB_SRC ,BT_USB_SRC" "0,1"
|
|
bitfld.long 0x00 25.--26. " BT_UART_SRC[1:0] ,BT_UART_SRC" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " BT_LPB[1:0] ,BT_LPB" "0,1,2,3"
|
|
bitfld.long 0x00 21.--22. " BT_OSC_FREQ_SEL[1:0] ,BT_OSC_FREQ_SEL" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " BT_SRC[1:0] ,BT_SDMMC_SRC" "0,1,2,3"
|
|
bitfld.long 0x00 18. " BT_LPB_EN ,BT_LPB_EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " BT_WEIM_MUXED ,Multiplexed address mode" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " BMOD[1:0] ,Sample of boot mode pins after reset" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DIR_BT_DIS ,Value of dir_bt_dis fuse" "0,1"
|
|
bitfld.long 0x00 12. " BT_EEPROM_CFG ,EEPROM device used for load of configuration DCD data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BT_MLC_SEL ,BT_MLC_SEL" "0,1"
|
|
bitfld.long 0x00 7.--8. " BT_MEM_TYPE[1:0] ,Boot Memory Type" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BT_SPARE_SIZE ,Specifies the size of spare bytes, for Nand Flash devices" "0,1"
|
|
bitfld.long 0x00 3.--4. " BT_PAGE_SIZE[1:0] ,BT_PAGE_SIZE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BT_BUS_WIDTH ,NAND Bus width" "0,1"
|
|
bitfld.long 0x00 0.--1. " BT_MEM_CTL[1:0] ,Boot memory control type" "0,1,2,3"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SRSR,SRC Reset Status Register"
|
|
bitfld.long 0x00 16. " WARM_BOOT ,Warm boot indication" "Not initiated,Initiated"
|
|
textline " "
|
|
eventfld.long 0x00 6. " JTAG_SW_RST ,Reset via JTAG SW" "Not software,Software"
|
|
eventfld.long 0x00 5. " JTAG_RST_B ,Reset via HIGH-Z JTAG" "Not HIGH-Z,HIGH-Z"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WDOG_RST_B ,IC Watchdog Time-out reset" "Not WD time-out,WD time-out"
|
|
eventfld.long 0x00 3. " IPP_USER_RESET_B ,Reset via ipp_user_reset_b qulified" "Not ipp_user_reset_b,Ipp_user_reset_b"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
textline " "
|
|
eventfld.long 0x00 0. " IPP_RESET_B ,Reset via ipp_reset_b pin" "Not ipp_reset_b,Ipp_reset_b"
|
|
else
|
|
textline " "
|
|
eventfld.long 0x00 2. " CSU_RESET_B ,Reset via csu_reset_b input" "Not csu_reset_b,Csu_reset_b"
|
|
eventfld.long 0x00 0. " IPP_RESET_B ,Reset via ipp_reset_b pin" "Not ipp_reset_b,Ipp_reset_b"
|
|
endif
|
|
sif (cpuis("IMX6*"))
|
|
rgroup.long 0x014++0x03
|
|
line.long 0x00 "SISR,SRC Interrupt Status Register"
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 8. " CORE3_WDOG_RST_REQ ,Wdog reset request from CPU core3" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " CORE2_WDOG_RST_REQ ,Wdog reset request from CPU core2" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 6. " CORE1_WDOG_RST_REQ ,Wdog reset request from CPU core1" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " CORE0_WDOG_RST_REQ ,Wdog reset request from CPU core0" "Not requested,Requested"
|
|
else
|
|
bitfld.long 0x00 5. " CORE0_WDOG_RST_REQ ,Wdog reset request from CPU core0" "Not requested,Requested"
|
|
endif
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 4. " IPU2_PASSED_RESET ,Interrupt generated to indicate that ipu2 passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " OPEN_VG_PASSED_RESET ,Interrupt generated to indicate that open_vg passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 2. " IPU1_PASSED_RESET ,Interrupt generated to indicate that ipu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " VPU_PASSED_RESET ,Interrupt generated to indicate that vpu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " GPU_PASSED_RESET ,Interrupt generated to indicate that gpu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x014++0x03
|
|
line.long 0x00 "SISR,SRC Interrupt Status Register"
|
|
rbitfld.long 0x00 3. " OPEN_VG_PASSED_RESET ,Open_vg passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
sif (cpu()!="IMX50"&&cpu()!="IMX502"&&cpu()!="IMX503"&&cpu()!="IMX507"&&cpu()!="IMX508")
|
|
textline " "
|
|
bitfld.long 0x00 2. " IPU_PASSED_RESET ,Ipu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " VPU_PASSED_RESET ,Vpu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPU_PASSED_RESET ,Gpu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
group.long 0x018++0x03
|
|
line.long 0x00 "SIMR,SRC Interrupt Mask Register"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")
|
|
bitfld.long 0x00 4. " MASK_IPU2_PASSED_RESET ,Mask interrupt generation due to ipu2 passed reset" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " MASK_OPEN_VG_PASSED_RESET ,Mask interrupt generation due to open_vg passed reset" "Not masked,Masked"
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 2. " MASK_IPU_PASSED_RESET ,Mask interrupt generation due to ipu passed reset" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " MASK_VPU_PASSED_RESET ,Mask interrupt generation due to vpu passed reset" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MASK_GPU_PASSED_RESET ,Mask interrupt generation due to gpu passed reset" "Not masked,Masked"
|
|
sif (cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&cpu()!="IMX50"&&cpu()!="IMX502"&&cpu()!="IMX503"&&cpu()!="IMX507"&&cpu()!="IMX508")
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SBMR2,SRC Boot Mode Register 2"
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 27.--29. " TEST_MODE ,Test mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--25. " BMOD ,Boot mode" "0,1,2,3"
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " RESERVED_FUSES ,Reversed fuses" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BT_FUSE_SEL ,Boot fuse selection" "0,1"
|
|
bitfld.long 0x00 3. " DIR_BT_DIS ,DIR_BT_DIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SEC_CONFIG ,SEC_CONFIG" "0,1,2,3"
|
|
group.long 0x20++0x1F
|
|
line.long 0x0 "GPR1,SRC General Purpose Register 1"
|
|
line.long 0x4 "GPR2,SRC General Purpose Register 2"
|
|
line.long 0x8 "GPR3,SRC General Purpose Register 3"
|
|
line.long 0xC "GPR4,SRC General Purpose Register 4"
|
|
line.long 0x10 "GPR5,SRC General Purpose Register 5"
|
|
line.long 0x14 "GPR6,SRC General Purpose Register 6"
|
|
line.long 0x18 "GPR7,SRC General Purpose Register 7"
|
|
line.long 0x1C "GPR8,SRC General Purpose Register 8"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "GPR10,SRC General Purpose Register 10"
|
|
bitfld.long 0x00 30. " PERSIST_SECONDARY_BOOT ,Identifies which image must be used" "0,1"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "GPR10,SRC General Purpose Register 10"
|
|
sif (cpu()!="IMX6SOLO"||cpu()!="IMX6DUALLITE"||cpu()!="IMX6DUAL")
|
|
bitfld.long 0x00 27. " CORE3_ERROR_STATUS ,Core 3 error status bit" "No error,Error"
|
|
bitfld.long 0x00 26. " CORE2_ERROR_STATUS ,Core 2 error status bit" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " CORE1_ERROR_STATUS ,Core 1 error status bit" "No error,Error"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SRPGC (State Retention Power Gating Controller)"
|
|
base ad:0x53FD8280
|
|
width 8.
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "SRPGCR,SRPG Control Register"
|
|
bitfld.long 0x0 0. " PCR ,Power control" "No switch off,Switch off"
|
|
line.long 0x4 "PUPSCR,Power-up Sequence Control Register"
|
|
bitfld.long 0x4 24.--25. " PG2ISO ,Number of clocks from Last PG (srpgc_pg[0]) de-assertion to ISO de-assertion" "0,1,2,3"
|
|
bitfld.long 0x4 16.--21. " SH2PG ,Number of clocks from SHORT assertion to First PG (srpgc_pg[NO_OF_PG-1]) de-assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x4 8.--13. " SW2SH ,Number of clocks from SWITCH assertion to SHORT assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x4 0.--5. " SW ,Number of clocks to assert SWITCH from Power-up request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x8 "PDNSCR,Power-down Sequence Control Register"
|
|
bitfld.long 0x8 24.--29. " SH2SW ,Number of clocks from SHORT de-assertion to SWITCH de-assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x8 16.--17. " PG2SH ,Number of clocks from last PG (srpgc_pg[NO_OF_PG-1]) assertion to SHORT de-assertion" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x8 8.--13. " ISO2PG ,Number of clocks from ISO assertion to First PG (srpgc_pg[0]) assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x8 0.--5. " ISO ,Number of clocks from Power down request to ISO assertion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0xc "SRPGSR,SRPG Status Register"
|
|
eventfld.long 0xc 0. " PSR ,Power status" "Not powered down,Powered down"
|
|
line.long 0x10 "SRPGDR,SRPG Debug Register"
|
|
bitfld.long 0x10 13. " SH1 ,Srpgc_short_b control in debug mode" "Not forced 1,Foreced 1"
|
|
bitfld.long 0x10 12. " SH0 ,Srpgc_short_b control in debug mode" "Not forced 0,Forced 0"
|
|
textline " "
|
|
bitfld.long 0x10 11. " SW0 ,Srpgc_switch_b control in debug mode" "Not forced 0,Forced 0"
|
|
bitfld.long 0x10 10. " PG0_LAFD ,Srpgc_pg[NO_OF_PG-1](Last asserted and First de-asserted) control in debug mode" "Not forced 0,Forced 0"
|
|
textline " "
|
|
bitfld.long 0x10 9. " PG0 ,Srpgc_pg[NO_OF_PG-2: 0] control in debug mode" "Not forced 0,Forced 0"
|
|
bitfld.long 0x10 8. " ISO0 ,Srpgc_iso control in debug mode" "Not forced 0,Forced 0"
|
|
textline " "
|
|
bitfld.long 0x10 0. " DBG ,Debug control" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SRTC (Secure Real Time Clock)"
|
|
base ad:0x53FA4000
|
|
width 8.
|
|
group.long 0x00++0x3B
|
|
line.long 0x00 "LPSCMR,LP Secure Counter MSB Register"
|
|
line.long 0x04 "LPSCLR,LP Secure Couunter LSB Register"
|
|
hexmask.long.word 0x04 17.--31. 1. " LLPSC ,LSB value of the LP secure counter"
|
|
line.long 0x08 "LPSAR,LP Secure Alarm Register"
|
|
line.long 0x0C "LPSMCR,LP Secure Monotonic Counter Register"
|
|
line.long 0x10 "LPCR,LP Control Register"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
bitfld.long 0x10 18.--22. " SCAL_LP ,SRTC calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
bitfld.long 0x10 16.--17. " SCALM_LP ,Decides the SRTC LP calibration mode" "Disabled,Enabled except coin cell mode,Reserved,Enabled"
|
|
else
|
|
bitfld.long 0x10 18.--22. " SCAL_LP ,SRTC calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 16.--17. " SCALM_LP ,Decides the SRTC LP calibration mode" "Disabled,Enabled except coin cell mode,Reserved,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 15. " IE ,Initialization state exit bit enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " NVE ,Nonvalid state exit bit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " IEIE ,Initialization state exit interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " NVEIE ,Nonvalid state exit interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " NSA ,Nonsecure access" "Not allowed,Allowed"
|
|
bitfld.long 0x10 10. " SV ,Security violation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " LMC ,Lock monotonic counter (write access disable)" "Enabled,Disabled"
|
|
bitfld.long 0x10 8. " LTC ,Lock time counter (write access disable)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ALP ,Alarm interrupt of LP section enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " SI ,Security interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " SAE ,Security alarm enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " WAE ,Wakeup alarm enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " EN_LP ,LP secure time and secure monotonic counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " SWR_LP ,Software reset" "No effect,Reset"
|
|
line.long 0x14 "LPSR,LP Status Register"
|
|
eventfld.long 0x14 15. " IES ,Initialization state exit status bit enable" "Disabled,Enabled"
|
|
eventfld.long 0x14 14. " NVES ,Nonvalid state exit status bit enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x14 12.--13. " STATE_LP ,State LP" "Initialize,Nonvalid,Valid,Failure"
|
|
rbitfld.long 0x14 10.--11. " SM ,Security mode" "Low,?..."
|
|
textline " "
|
|
rbitfld.long 0x14 7.--9. " IT ,IIM throttle" "512,1024,2048,4096,8192,8192,8192,Unlimited"
|
|
eventfld.long 0x14 6. " EAD ,External alarm detected" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x14 5. " TR ,Time rollover" "Disabled,Enabled"
|
|
eventfld.long 0x14 4. " MR ,Monotonic counter rollover" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 3. " ALP ,Alarm flag of LP section" "Not occurred,Occurred"
|
|
eventfld.long 0x14 2. " CTD ,Clock tampering detected" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x14 1. " PGD ,Power supply glitch detected" "Not detected,Detected"
|
|
eventfld.long 0x14 0. " TRI ,Time read invalidate" "Validated,Invalidated"
|
|
line.long 0x18 "LPPDR,LP Power Supply Glitch Detector Register"
|
|
line.long 0x1C "LPGR,LP General Purpose Register"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
bitfld.long 0x1C 31. " SW_ISO ,Software isolation bit" "Not isolated,Isolated"
|
|
bitfld.long 0x1C 30. " SEC_BT ,Secondary boot bit - redundant firmware copy use selection" "Normal,Secondary"
|
|
textline " "
|
|
bitfld.long 0x1C 29. " LPB_STS ,Boot state" "Normal,Low power"
|
|
hexmask.long 0x1C 0.--28. 1. " LPGR ,LP general purpose register"
|
|
else
|
|
bitfld.long 0x1C 31. " SW_ISO ,Software isolation bit" "Not isolated,Isolated"
|
|
hexmask.long 0x1C 0.--28. 1. " LPGR ,LP general purpose register"
|
|
endif
|
|
line.long 0x20 "HPCMR,HP Counter MSB Register [46:15]"
|
|
line.long 0x24 "HPCLR,HP Counter LSB Register [14:0]"
|
|
hexmask.long.word 0x24 17.--31. 1. " LHPC ,LSB value of the HP counter"
|
|
line.long 0x28 "HPAMR,HP Alarm MSB Register [46:15]"
|
|
line.long 0x2C "HPALR,HP Alarm LSB Register [14:0]"
|
|
hexmask.long.word 0x2C 17.--31. 1. " LHPA ,LSB value of the HP alarm"
|
|
line.long 0x30 "HPCR,HP Control Register"
|
|
bitfld.long 0x30 18.--22. " SCAL_HP ,SRTC calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x30 16. " SCALM_HP ,Decides the SRTC HP calibration mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 4. " TS ,Time synchronize" "No action,Synchronized"
|
|
bitfld.long 0x30 3. " EN_HP ,HP time counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 0. " SWR_HP ,Software reset" "No effect,Reset"
|
|
line.long 0x34 "HPISR,HP Interrupt Status Register"
|
|
bitfld.long 0x34 21. " WPLP ,Write pending LP" "Not requested,Requested"
|
|
bitfld.long 0x34 20. " WPHP ,Write pending HP" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x34 19. " WDLP ,Write done LP" "Not requested,Requested"
|
|
eventfld.long 0x34 18. " WDHP ,Write done HP" "Not requested,Requested"
|
|
textline " "
|
|
eventfld.long 0x34 16. " AHP ,Alarm interrupt of HP section" "No interrupt,Interrupt"
|
|
eventfld.long 0x34 15. " PI15 ,Periodic interrupt flag at 32768Hz frequency" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x34 14. " PI14 ,Periodic interrupt flag at 16384Hz frequency" "No interrupt,Interrupt"
|
|
eventfld.long 0x34 13. " PI13 ,Periodic interrupt flag at 8192Hz frequency" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x34 12. " PI12 ,Periodic interrupt flag at 4096Hz frequency" "No interrupt,Interrupt"
|
|
eventfld.long 0x34 11. " PI11 ,Periodic interrupt flag at 2048Hz frequency" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x34 10. " PI10 ,Periodic interrupt flag at 1024Hz frequency" "No interrupt,Interrupt"
|
|
eventfld.long 0x34 9. " PI9 ,Periodic interrupt flag at 512Hz frequency" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x34 8. " PI8 ,Periodic interrupt flag at 256Hz frequency" "No interrupt,Interrupt"
|
|
eventfld.long 0x34 7. " PI7 ,Periodic interrupt flag at 128Hz frequency" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x34 6. " PI6 ,Periodic interrupt flag at 64Hz frequency" "No interrupt,Interrupt"
|
|
eventfld.long 0x34 5. " PI5 ,Periodic interrupt flag at 32Hz frequency" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x34 4. " PI4 ,Periodic interrupt flag at 16Hz frequency" "No interrupt,Interrupt"
|
|
eventfld.long 0x34 3. " PI3 ,Periodic interrupt flag at 8Hz frequency" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x34 2. " PI2 ,Periodic interrupt flag at 4Hz frequency" "No interrupt,Interrupt"
|
|
eventfld.long 0x34 1. " PI1 ,Periodic interrupt flag at 2Hz frequency" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x34 0. " PI0 ,Periodic interrupt flag at 1Hz frequency" "No interrupt,Interrupt"
|
|
line.long 0x38 "HPIENR,HP Interrupt Enable Register"
|
|
bitfld.long 0x38 19. " WDLP ,Write done LP" "Disabled,Enabled"
|
|
bitfld.long 0x38 18. " WDHP ,Write done HP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 16. " AHP ,Alarm interrupt of HP section" "Disabled,Enabled"
|
|
bitfld.long 0x38 15. " PI15 ,Periodic interrupt flag at 32768Hz frequency" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 14. " PI14 ,Periodic interrupt flag at 16384Hz frequency" "Disabled,Enabled"
|
|
bitfld.long 0x38 13. " PI13 ,Periodic interrupt flag at 8192Hz frequency" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 12. " PI12 ,Periodic interrupt flag at 4096Hz frequency" "Disabled,Enabled"
|
|
bitfld.long 0x38 11. " PI11 ,Periodic interrupt flag at 2048Hz frequency" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 10. " PI10 ,Periodic interrupt flag at 1024Hz frequency" "Disabled,Enabled"
|
|
bitfld.long 0x38 9. " PI9 ,Periodic interrupt flag at 512Hz frequency" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 8. " PI8 ,Periodic interrupt flag at 256Hz frequency" "Disabled,Enabled"
|
|
bitfld.long 0x38 7. " PI7 ,Periodic interrupt flag at 128Hz frequency" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 6. " PI6 ,Periodic interrupt flag at 64Hz frequency" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " PI5 ,Periodic interrupt flag at 32Hz frequency" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " PI4 ,Periodic interrupt flag at 16Hz frequency" "Disabled,Enabled"
|
|
bitfld.long 0x38 3. " PI3 ,Periodic interrupt flag at 8Hz frequency" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 2. " PI2 ,Periodic interrupt flag at 4Hz frequency" "Disabled,Enabled"
|
|
bitfld.long 0x38 1. " PI1 ,Periodic interrupt flag at 2Hz frequency" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 0. " PI0 ,Periodic interrupt flag at 1Hz frequency" "Disabled,Enabled"
|
|
width 11.
|
|
tree.end
|
|
tree.open "SSI (Synchronous Serial Interface)"
|
|
tree "SSI1"
|
|
base ad:0x63fcc000
|
|
width 8.
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
if (((per.l((ad:0x63fcc000)+0x10))&0x01)==0x01)
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
else
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
endif
|
|
else
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
endif
|
|
hgroup.long 0x08++0x7
|
|
hide.long 0x00 "SRX0,Receive Data Register 0"
|
|
in
|
|
hide.long 0x04 "SRX1,Receive Data Register 1"
|
|
in
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SCR,SSI Control Register"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes"
|
|
bitfld.long 0x0 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "Low,High"
|
|
bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
in
|
|
elif (cpuis("IMX6*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
bitfld.long 0x00 24. " RFRC ,Receive Frame Complete" "Not reached,Reached"
|
|
bitfld.long 0x00 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached"
|
|
bitfld.long 0x00 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated"
|
|
bitfld.long 0x00 16. " RXT ,Receive Tag Updated" "Not updated,Updated"
|
|
bitfld.long 0x00 15. " RDR1 ,Receive Data Ready 1" "No new data,New data"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RDR0 ,Receive Data Ready 0" "No new data,New data"
|
|
bitfld.long 0x00 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error"
|
|
eventfld.long 0x00 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error"
|
|
eventfld.long 0x00 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error"
|
|
bitfld.long 0x00 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TLS ,Transmit Last Time Slot" "No,Yes"
|
|
bitfld.long 0x00 4. " RLS ,Receive Last Time Slot" "No,Yes"
|
|
bitfld.long 0x00 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full"
|
|
bitfld.long 0x00 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty"
|
|
else
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
in
|
|
endif
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "SIER,SSI Interrupt Enable Register"
|
|
bitfld.long 0x00 24. " RFRC_EN ,Receive Frame Complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TFRC_EN ,Transmit Frame Complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RDMAE ,Receive DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CMDAU_EN ,Command Address Register Updated" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CMDDU_EN ,Command Data Register Updated" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXT_EN ,Receive Tag Updated" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RDR1_EN ,Receive Data Ready 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RDR0_EN ,Receive Data Ready 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TDE1_EN ,Transmit Data Register Empty 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TDE0_EN ,Transmit Data Register Empty 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ROE1_EN ,Receiver Overrun Error 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ROE0_EN ,Receiver Overrun Error 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TUE1_EN ,Transmitter Underrun Error 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TUE0_EN ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TFS_EN ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RFS_EN ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rbitfld.long 0x00 5. " TLS_EN ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 5. " TLS_EN ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 4. " RLS_EN ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RFF1_EN ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RFF0_EN ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFE1_EN ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "STCR,SSI Transmit Configuration Register"
|
|
bitfld.long 0x04 9. " TXBIT0 ,Transmit Bit 0" "Bit 31|15,Bit 0"
|
|
bitfld.long 0x04 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TFDIR ,Transmit Frame Direction" "External,Internal"
|
|
bitfld.long 0x04 5. " TXDIR ,Transmit Clock Direction" "External,Internal"
|
|
bitfld.long 0x04 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x04 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low"
|
|
bitfld.long 0x04 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before"
|
|
line.long 0x08 "SRCR,SSI Receive Configuration Register"
|
|
bitfld.long 0x8 10. " RXEXT ,Receive Data Extension" "Not extended,Extended"
|
|
bitfld.long 0x08 9. " RXBIT0 ,Receive Bit 0" "Bit 31|15,Bit 0"
|
|
bitfld.long 0x08 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RFDIR ,Receive Frame Direction" "External,Internal"
|
|
bitfld.long 0x08 5. " RXDIR ,Receive Clock Direction" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x08 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first"
|
|
bitfld.long 0x08 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x08 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit"
|
|
bitfld.long 0x08 0. " REFS ,Receive Early Frame Sync" "First bit,One before"
|
|
line.long 0x0c "STCCR,SSI Transmit Clock Control Register"
|
|
bitfld.long 0x0c 18. " DIV2 ,Divide By 2" "Bypassed,Div by 2"
|
|
bitfld.long 0x0c 17. " PSR ,Prescaler Range" "Bypassed,Div by 8"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x0C 13.--16. " WL[3:0] ,Word Length Control" "-,-,-,8,10,12,-,16,18,20,22,24,-,?..."
|
|
else
|
|
bitfld.long 0x0C 13.--16. " WL[3:0] ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 8.--12. " DC[4:0] ,Frame Rate Divider Control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " PM[7:0] ,Prescaler Modulus Select"
|
|
line.long 0x10 "SRCCR,SSI Receive Clock Control Register"
|
|
bitfld.long 0x10 18. " DIV2 ,Divide By 2" "Bypassed,Div by 2"
|
|
bitfld.long 0x10 17. " PSR ,Prescaler Range" "Bypassed,Div by 8"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x10 13.--16. " WL[3:0] ,Word Length Control" "-,-,-,8,10,12,-,16,18,20,22,24,-,?..."
|
|
else
|
|
bitfld.long 0x10 13.--16. " WL[3:0] ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 8.--12. " DC[4:0] ,Frame Rate Divider Control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PM[7:0] ,Prescaler Modulus Select"
|
|
line.long 0x14 "SFCSR,SSI FIFO Control/Status Register"
|
|
bitfld.long 0x14 28.--31. " RFCNT1[3:0] ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " TFCNT1[3:0] ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " RFWM1[3:0] ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
textline " "
|
|
bitfld.long 0x14 16.--19. " TFWM1[3:0] ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
bitfld.long 0x14 12.--15. " RFCNT0[3:0] ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " TFCNT0[3:0] ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " RFWM0[3:0] ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
bitfld.long 0x14 0.--3. " TFWM0[3:0] ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
sif (!cpuis("IMX6*")&&cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&!cpuis("IMX50*"))
|
|
group.long 0x30++0x7
|
|
line.long 0x00 "STR,SSI Test Register"
|
|
bitfld.long 0x00 15. " TEST ,Test Mode" "No effect,Test Mode"
|
|
bitfld.long 0x00 14. " RCK2TCK ,Receive Clock to Transmit Clock Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 13. " RFS2TFS ,Receive Frame to Transmit Frame Loop Back" "No effect,Loop back"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RXSTATE ,Receiver State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " TXD2RXD ,Transmit Data to Receive Data Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 6. " TCK2RCK ,Transmit Clock to Receive Clock Loop Back" "No effect,Loop back"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TFS2RFS ,Transmit Frame to Receive Frame Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 0.--4. " TXSTATE ,Transmitter State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "SOR,SSI Option Register"
|
|
bitfld.long 0x04 6. " CLKOFF ,Clock Off" "No effect,Off"
|
|
bitfld.long 0x04 5. " RX_CLR ,Receiver Clear" "No effect,Flushed"
|
|
bitfld.long 0x04 4. " TX_CLR ,Transmitter Clear" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INIT ,Initialize" "No effect,Initialized"
|
|
bitfld.long 0x04 1.--2. " WAIT ,Number wait states" "0,1,2,3"
|
|
bitfld.long 0x04 0. " SYNRST ,Frame Sync Reset" "No reset,Reset"
|
|
endif
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "SACNT,SSI AC97 Control Register"
|
|
hexmask.long.byte 0x00 5.--10. 1. " FRDIV[5:0] ,Frame Rate Divider"
|
|
bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached"
|
|
bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0"
|
|
bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
hgroup.long 0x3c++0x0B
|
|
hide.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
in
|
|
hide.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
in
|
|
hide.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
in
|
|
elif (cpuis("IMX6*"))
|
|
group.long 0x3c++0x0B
|
|
line.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " SACADD ,AC97 Command Address"
|
|
line.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " SACDAT ,AC97 Command Data"
|
|
line.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SATAG ,AC97 Tag Value"
|
|
else
|
|
hgroup.long 0x3c++0x0B
|
|
hide.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
in
|
|
hide.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
in
|
|
hide.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
in
|
|
endif
|
|
textline " "
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "STMSK,SSI Transmit Time Slot Mask Register"
|
|
bitfld.long 0x00 31. " STMSK ,Transmit Mask Bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Transmit Mask Bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Transmit Mask Bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Transmit Mask Bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Transmit Mask Bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Transmit Mask Bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Transmit Mask Bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Transmit Mask Bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Transmit Mask Bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Transmit Mask Bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Transmit Mask Bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Transmit Mask Bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Transmit Mask Bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Transmit Mask Bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Transmit Mask Bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Transmit Mask Bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Transmit Mask Bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Transmit Mask Bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Transmit Mask Bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Transmit Mask Bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Transmit Mask Bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Transmit Mask Bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Transmit Mask Bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Transmit Mask Bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Transmit Mask Bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Transmit Mask Bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Transmit Mask Bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Transmit Mask Bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Transmit Mask Bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Transmit Mask Bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Transmit Mask Bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Transmit Mask Bit 0" "0,1"
|
|
line.long 0x04 "SRMSK,SSI Receive Time Slot Mask Register"
|
|
bitfld.long 0x04 31. " SRMSK ,Receive Mask Bit 31" "0,1"
|
|
bitfld.long 0x04 30. ",Receive Mask Bit 30" "0,1"
|
|
bitfld.long 0x04 29. ",Receive Mask Bit 29" "0,1"
|
|
bitfld.long 0x04 28. ",Receive Mask Bit 28" "0,1"
|
|
bitfld.long 0x04 27. ",Receive Mask Bit 27" "0,1"
|
|
bitfld.long 0x04 26. ",Receive Mask Bit 26" "0,1"
|
|
bitfld.long 0x04 25. ",Receive Mask Bit 25" "0,1"
|
|
bitfld.long 0x04 24. ",Receive Mask Bit 24" "0,1"
|
|
bitfld.long 0x04 23. ",Receive Mask Bit 23" "0,1"
|
|
bitfld.long 0x04 22. ",Receive Mask Bit 22" "0,1"
|
|
bitfld.long 0x04 21. ",Receive Mask Bit 21" "0,1"
|
|
bitfld.long 0x04 20. ",Receive Mask Bit 20" "0,1"
|
|
bitfld.long 0x04 19. ",Receive Mask Bit 19" "0,1"
|
|
bitfld.long 0x04 18. ",Receive Mask Bit 18" "0,1"
|
|
bitfld.long 0x04 17. ",Receive Mask Bit 17" "0,1"
|
|
bitfld.long 0x04 16. ",Receive Mask Bit 16" "0,1"
|
|
bitfld.long 0x04 15. ",Receive Mask Bit 15" "0,1"
|
|
bitfld.long 0x04 14. ",Receive Mask Bit 14" "0,1"
|
|
bitfld.long 0x04 13. ",Receive Mask Bit 13" "0,1"
|
|
bitfld.long 0x04 12. ",Receive Mask Bit 12" "0,1"
|
|
bitfld.long 0x04 11. ",Receive Mask Bit 11" "0,1"
|
|
bitfld.long 0x04 10. ",Receive Mask Bit 10" "0,1"
|
|
bitfld.long 0x04 9. ",Receive Mask Bit 9" "0,1"
|
|
bitfld.long 0x04 8. ",Receive Mask Bit 8" "0,1"
|
|
bitfld.long 0x04 7. ",Receive Mask Bit 7" "0,1"
|
|
bitfld.long 0x04 6. ",Receive Mask Bit 6" "0,1"
|
|
bitfld.long 0x04 5. ",Receive Mask Bit 5" "0,1"
|
|
bitfld.long 0x04 4. ",Receive Mask Bit 4" "0,1"
|
|
bitfld.long 0x04 3. ",Receive Mask Bit 3" "0,1"
|
|
bitfld.long 0x04 2. ",Receive Mask Bit 2" "0,1"
|
|
bitfld.long 0x04 1. ",Receive Mask Bit 1" "0,1"
|
|
bitfld.long 0x04 0. ",Receive Mask Bit 0" "0,1"
|
|
textline " "
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "SACCST,SSI AC97 Channel Status Register"
|
|
setclrfld.long 0x0 9. 0x4 9. 0x8 9. " SACCST9_set/clr ,AC97 Channel Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. 0x4 8. 0x8 8. " SACCST8_set/clr ,AC97 Channel Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x4 7. 0x8 7. " SACCST7_set/clr ,AC97 Channel Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. 0x4 6. 0x8 6. " SACCST6_set/clr ,AC97 Channel Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x4 5. 0x8 5. " SACCST5_set/clr ,AC97 Channel Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. 0x4 4. 0x8 4. " SACCST4_set/clr ,AC97 Channel Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x4 3. 0x8 3. " SACCST3_set/clr ,AC97 Channel Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. 0x4 2. 0x8 2. " SACCST2_set/clr ,AC97 Channel Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x4 1. 0x8 1. " SACCST1_set/clr ,AC97 Channel Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. 0x4 0. 0x8 0. " SACCST0_set/clr ,AC97 Channel Status 0" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SSI2"
|
|
base ad:0x50014000
|
|
width 8.
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
if (((per.l((ad:0x50014000)+0x10))&0x01)==0x01)
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
else
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
endif
|
|
else
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
endif
|
|
hgroup.long 0x08++0x7
|
|
hide.long 0x00 "SRX0,Receive Data Register 0"
|
|
in
|
|
hide.long 0x04 "SRX1,Receive Data Register 1"
|
|
in
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SCR,SSI Control Register"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes"
|
|
bitfld.long 0x0 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "Low,High"
|
|
bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
in
|
|
elif (cpuis("IMX6*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
bitfld.long 0x00 24. " RFRC ,Receive Frame Complete" "Not reached,Reached"
|
|
bitfld.long 0x00 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached"
|
|
bitfld.long 0x00 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated"
|
|
bitfld.long 0x00 16. " RXT ,Receive Tag Updated" "Not updated,Updated"
|
|
bitfld.long 0x00 15. " RDR1 ,Receive Data Ready 1" "No new data,New data"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RDR0 ,Receive Data Ready 0" "No new data,New data"
|
|
bitfld.long 0x00 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error"
|
|
eventfld.long 0x00 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error"
|
|
eventfld.long 0x00 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error"
|
|
bitfld.long 0x00 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TLS ,Transmit Last Time Slot" "No,Yes"
|
|
bitfld.long 0x00 4. " RLS ,Receive Last Time Slot" "No,Yes"
|
|
bitfld.long 0x00 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full"
|
|
bitfld.long 0x00 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty"
|
|
else
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
in
|
|
endif
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "SIER,SSI Interrupt Enable Register"
|
|
bitfld.long 0x00 24. " RFRC_EN ,Receive Frame Complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TFRC_EN ,Transmit Frame Complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RDMAE ,Receive DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CMDAU_EN ,Command Address Register Updated" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CMDDU_EN ,Command Data Register Updated" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXT_EN ,Receive Tag Updated" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RDR1_EN ,Receive Data Ready 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RDR0_EN ,Receive Data Ready 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TDE1_EN ,Transmit Data Register Empty 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TDE0_EN ,Transmit Data Register Empty 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ROE1_EN ,Receiver Overrun Error 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ROE0_EN ,Receiver Overrun Error 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TUE1_EN ,Transmitter Underrun Error 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TUE0_EN ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TFS_EN ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RFS_EN ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rbitfld.long 0x00 5. " TLS_EN ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 5. " TLS_EN ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 4. " RLS_EN ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RFF1_EN ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RFF0_EN ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFE1_EN ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "STCR,SSI Transmit Configuration Register"
|
|
bitfld.long 0x04 9. " TXBIT0 ,Transmit Bit 0" "Bit 31|15,Bit 0"
|
|
bitfld.long 0x04 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TFDIR ,Transmit Frame Direction" "External,Internal"
|
|
bitfld.long 0x04 5. " TXDIR ,Transmit Clock Direction" "External,Internal"
|
|
bitfld.long 0x04 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x04 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low"
|
|
bitfld.long 0x04 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before"
|
|
line.long 0x08 "SRCR,SSI Receive Configuration Register"
|
|
bitfld.long 0x8 10. " RXEXT ,Receive Data Extension" "Not extended,Extended"
|
|
bitfld.long 0x08 9. " RXBIT0 ,Receive Bit 0" "Bit 31|15,Bit 0"
|
|
bitfld.long 0x08 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RFDIR ,Receive Frame Direction" "External,Internal"
|
|
bitfld.long 0x08 5. " RXDIR ,Receive Clock Direction" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x08 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first"
|
|
bitfld.long 0x08 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x08 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit"
|
|
bitfld.long 0x08 0. " REFS ,Receive Early Frame Sync" "First bit,One before"
|
|
line.long 0x0c "STCCR,SSI Transmit Clock Control Register"
|
|
bitfld.long 0x0c 18. " DIV2 ,Divide By 2" "Bypassed,Div by 2"
|
|
bitfld.long 0x0c 17. " PSR ,Prescaler Range" "Bypassed,Div by 8"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x0C 13.--16. " WL[3:0] ,Word Length Control" "-,-,-,8,10,12,-,16,18,20,22,24,-,?..."
|
|
else
|
|
bitfld.long 0x0C 13.--16. " WL[3:0] ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 8.--12. " DC[4:0] ,Frame Rate Divider Control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " PM[7:0] ,Prescaler Modulus Select"
|
|
line.long 0x10 "SRCCR,SSI Receive Clock Control Register"
|
|
bitfld.long 0x10 18. " DIV2 ,Divide By 2" "Bypassed,Div by 2"
|
|
bitfld.long 0x10 17. " PSR ,Prescaler Range" "Bypassed,Div by 8"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x10 13.--16. " WL[3:0] ,Word Length Control" "-,-,-,8,10,12,-,16,18,20,22,24,-,?..."
|
|
else
|
|
bitfld.long 0x10 13.--16. " WL[3:0] ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 8.--12. " DC[4:0] ,Frame Rate Divider Control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PM[7:0] ,Prescaler Modulus Select"
|
|
line.long 0x14 "SFCSR,SSI FIFO Control/Status Register"
|
|
bitfld.long 0x14 28.--31. " RFCNT1[3:0] ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " TFCNT1[3:0] ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " RFWM1[3:0] ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
textline " "
|
|
bitfld.long 0x14 16.--19. " TFWM1[3:0] ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
bitfld.long 0x14 12.--15. " RFCNT0[3:0] ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " TFCNT0[3:0] ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " RFWM0[3:0] ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
bitfld.long 0x14 0.--3. " TFWM0[3:0] ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
sif (!cpuis("IMX6*")&&cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&!cpuis("IMX50*"))
|
|
group.long 0x30++0x7
|
|
line.long 0x00 "STR,SSI Test Register"
|
|
bitfld.long 0x00 15. " TEST ,Test Mode" "No effect,Test Mode"
|
|
bitfld.long 0x00 14. " RCK2TCK ,Receive Clock to Transmit Clock Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 13. " RFS2TFS ,Receive Frame to Transmit Frame Loop Back" "No effect,Loop back"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RXSTATE ,Receiver State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " TXD2RXD ,Transmit Data to Receive Data Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 6. " TCK2RCK ,Transmit Clock to Receive Clock Loop Back" "No effect,Loop back"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TFS2RFS ,Transmit Frame to Receive Frame Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 0.--4. " TXSTATE ,Transmitter State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "SOR,SSI Option Register"
|
|
bitfld.long 0x04 6. " CLKOFF ,Clock Off" "No effect,Off"
|
|
bitfld.long 0x04 5. " RX_CLR ,Receiver Clear" "No effect,Flushed"
|
|
bitfld.long 0x04 4. " TX_CLR ,Transmitter Clear" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INIT ,Initialize" "No effect,Initialized"
|
|
bitfld.long 0x04 1.--2. " WAIT ,Number wait states" "0,1,2,3"
|
|
bitfld.long 0x04 0. " SYNRST ,Frame Sync Reset" "No reset,Reset"
|
|
endif
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "SACNT,SSI AC97 Control Register"
|
|
hexmask.long.byte 0x00 5.--10. 1. " FRDIV[5:0] ,Frame Rate Divider"
|
|
bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached"
|
|
bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0"
|
|
bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
hgroup.long 0x3c++0x0B
|
|
hide.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
in
|
|
hide.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
in
|
|
hide.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
in
|
|
elif (cpuis("IMX6*"))
|
|
group.long 0x3c++0x0B
|
|
line.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " SACADD ,AC97 Command Address"
|
|
line.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " SACDAT ,AC97 Command Data"
|
|
line.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SATAG ,AC97 Tag Value"
|
|
else
|
|
hgroup.long 0x3c++0x0B
|
|
hide.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
in
|
|
hide.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
in
|
|
hide.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
in
|
|
endif
|
|
textline " "
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "STMSK,SSI Transmit Time Slot Mask Register"
|
|
bitfld.long 0x00 31. " STMSK ,Transmit Mask Bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Transmit Mask Bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Transmit Mask Bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Transmit Mask Bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Transmit Mask Bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Transmit Mask Bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Transmit Mask Bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Transmit Mask Bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Transmit Mask Bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Transmit Mask Bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Transmit Mask Bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Transmit Mask Bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Transmit Mask Bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Transmit Mask Bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Transmit Mask Bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Transmit Mask Bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Transmit Mask Bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Transmit Mask Bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Transmit Mask Bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Transmit Mask Bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Transmit Mask Bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Transmit Mask Bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Transmit Mask Bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Transmit Mask Bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Transmit Mask Bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Transmit Mask Bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Transmit Mask Bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Transmit Mask Bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Transmit Mask Bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Transmit Mask Bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Transmit Mask Bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Transmit Mask Bit 0" "0,1"
|
|
line.long 0x04 "SRMSK,SSI Receive Time Slot Mask Register"
|
|
bitfld.long 0x04 31. " SRMSK ,Receive Mask Bit 31" "0,1"
|
|
bitfld.long 0x04 30. ",Receive Mask Bit 30" "0,1"
|
|
bitfld.long 0x04 29. ",Receive Mask Bit 29" "0,1"
|
|
bitfld.long 0x04 28. ",Receive Mask Bit 28" "0,1"
|
|
bitfld.long 0x04 27. ",Receive Mask Bit 27" "0,1"
|
|
bitfld.long 0x04 26. ",Receive Mask Bit 26" "0,1"
|
|
bitfld.long 0x04 25. ",Receive Mask Bit 25" "0,1"
|
|
bitfld.long 0x04 24. ",Receive Mask Bit 24" "0,1"
|
|
bitfld.long 0x04 23. ",Receive Mask Bit 23" "0,1"
|
|
bitfld.long 0x04 22. ",Receive Mask Bit 22" "0,1"
|
|
bitfld.long 0x04 21. ",Receive Mask Bit 21" "0,1"
|
|
bitfld.long 0x04 20. ",Receive Mask Bit 20" "0,1"
|
|
bitfld.long 0x04 19. ",Receive Mask Bit 19" "0,1"
|
|
bitfld.long 0x04 18. ",Receive Mask Bit 18" "0,1"
|
|
bitfld.long 0x04 17. ",Receive Mask Bit 17" "0,1"
|
|
bitfld.long 0x04 16. ",Receive Mask Bit 16" "0,1"
|
|
bitfld.long 0x04 15. ",Receive Mask Bit 15" "0,1"
|
|
bitfld.long 0x04 14. ",Receive Mask Bit 14" "0,1"
|
|
bitfld.long 0x04 13. ",Receive Mask Bit 13" "0,1"
|
|
bitfld.long 0x04 12. ",Receive Mask Bit 12" "0,1"
|
|
bitfld.long 0x04 11. ",Receive Mask Bit 11" "0,1"
|
|
bitfld.long 0x04 10. ",Receive Mask Bit 10" "0,1"
|
|
bitfld.long 0x04 9. ",Receive Mask Bit 9" "0,1"
|
|
bitfld.long 0x04 8. ",Receive Mask Bit 8" "0,1"
|
|
bitfld.long 0x04 7. ",Receive Mask Bit 7" "0,1"
|
|
bitfld.long 0x04 6. ",Receive Mask Bit 6" "0,1"
|
|
bitfld.long 0x04 5. ",Receive Mask Bit 5" "0,1"
|
|
bitfld.long 0x04 4. ",Receive Mask Bit 4" "0,1"
|
|
bitfld.long 0x04 3. ",Receive Mask Bit 3" "0,1"
|
|
bitfld.long 0x04 2. ",Receive Mask Bit 2" "0,1"
|
|
bitfld.long 0x04 1. ",Receive Mask Bit 1" "0,1"
|
|
bitfld.long 0x04 0. ",Receive Mask Bit 0" "0,1"
|
|
textline " "
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "SACCST,SSI AC97 Channel Status Register"
|
|
setclrfld.long 0x0 9. 0x4 9. 0x8 9. " SACCST9_set/clr ,AC97 Channel Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. 0x4 8. 0x8 8. " SACCST8_set/clr ,AC97 Channel Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x4 7. 0x8 7. " SACCST7_set/clr ,AC97 Channel Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. 0x4 6. 0x8 6. " SACCST6_set/clr ,AC97 Channel Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x4 5. 0x8 5. " SACCST5_set/clr ,AC97 Channel Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. 0x4 4. 0x8 4. " SACCST4_set/clr ,AC97 Channel Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x4 3. 0x8 3. " SACCST3_set/clr ,AC97 Channel Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. 0x4 2. 0x8 2. " SACCST2_set/clr ,AC97 Channel Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x4 1. 0x8 1. " SACCST1_set/clr ,AC97 Channel Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. 0x4 0. 0x8 0. " SACCST0_set/clr ,AC97 Channel Status 0" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "TEMPSENSOR (Temperature Sensor)"
|
|
base ad:0x41018080
|
|
width 17.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "ANADIG_CTRL,Control Register"
|
|
hexmask.long.word 0x00 20.--31. 0x1 " TVAL2 ,Output code of the TempSensor VBG based counter"
|
|
hexmask.long.word 0x00 8.--19. 0x1 " TVAL1 ,Output code of the TempSensor VBE based counter"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " FINISHED ,Conversion finished and TVAL1 and TVAL2 fields valid" "Not finished,Finished"
|
|
bitfld.long 0x00 1. " START ,Start a TempSensor conversion cycle" "Not started,Started"
|
|
bitfld.long 0x00 0. " PWD ,Self-power-down behavior of the analog portion of the TempSensor" "Always on,On after START"
|
|
line.long 0x04 "ANADIG_CTRL_SET,Control Register"
|
|
hexmask.long.word 0x04 20.--31. 0x1 " TVAL2 ,Output code of the TempSensor VBG based counter"
|
|
hexmask.long.word 0x04 8.--19. 0x1 " TVAL1 ,Output code of the TempSensor VBE based counter"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " FINISHED ,Conversion finished and TVAL1 and TVAL2 fields valid" "Not finished,Finished"
|
|
bitfld.long 0x04 1. " START ,Start a TempSensor conversion cycle" "Not started,Started"
|
|
bitfld.long 0x04 0. " PWD ,Self-power-down behavior of the analog portion of the TempSensor" "Always on,On after START"
|
|
line.long 0x08 "ANADIG_CTRL_CLR,Control Register"
|
|
hexmask.long.word 0x08 20.--31. 0x1 " TVAL2 ,Output code of the TempSensor VBG based counter"
|
|
hexmask.long.word 0x08 8.--19. 0x1 " TVAL1 ,Output code of the TempSensor VBE based counter"
|
|
textline " "
|
|
rbitfld.long 0x08 2. " FINISHED ,Conversion finished and TVAL1 and TVAL2 fields valid" "Not finished,Finished"
|
|
bitfld.long 0x08 1. " START ,Start a TempSensor conversion cycle" "Not started,Started"
|
|
bitfld.long 0x08 0. " PWD ,Self-power-down behavior of the analog portion of the TempSensor" "Always on,On after START"
|
|
line.long 0x0C "ANADIG_CTRL_TOG,Control Register"
|
|
hexmask.long.word 0x0C 20.--31. 0x1 " TVAL2 ,Output code of the TempSensor VBG based counter"
|
|
hexmask.long.word 0x0C 8.--19. 0x1 " TVAL1 ,Output code of the TempSensor VBE based counter"
|
|
textline " "
|
|
rbitfld.long 0x0C 2. " FINISHED ,Conversion finished and TVAL1 and TVAL2 fields valid" "Not finished,Finished"
|
|
bitfld.long 0x0C 1. " START ,Start a TempSensor conversion cycle" "Not started,Started"
|
|
bitfld.long 0x0C 0. " PWD ,Self-power-down behavior of the analog portion of the TempSensor" "Always on,On after START"
|
|
width 0xB
|
|
tree.end
|
|
tree "TZIC (Interrupt Controller)"
|
|
base ad:0xfffc000
|
|
width 12.
|
|
sif cpuis("IMX50*")
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "INTCTRL,Control Register"
|
|
bitfld.long 0x00 0. " EN ,Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "INTCTRL,Control Register"
|
|
bitfld.long 0x00 31. " NSEN_MASK ,Non-Secure Enable Mask" "Not updated,Updated"
|
|
bitfld.long 0x00 16. " NSEN ,Non-Secure Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "INTTYPE,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 10. " DOM ,Domains" "1 domain,2 domains"
|
|
bitfld.long 0x00 5.--7. " CPUS ,CPU Count" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 0.--4. " ITLINES ,Interrupt Lines" "32,64,96,128,160,192,224,256,288,320,352,384,416,448,480,512,544,576,608,640,672,704,736,768,800,832,864,896,928,960,992,1020"
|
|
group.byte 0x0c++0x3
|
|
line.long 0x00 "PRIOMASK,Priority Mask Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MASK ,Priority Mask"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "SYNCCTRL,Synchronizer Control Register"
|
|
bitfld.long 0x00 0.--1. " SYNCMODE ,Synchronizer Mode" "Low Latency,Low Power,?..."
|
|
line.long 0x04 "DSMINT,DSM Interrupt Holdoff Register"
|
|
bitfld.long 0x04 0. " DSM ,DSM Interrupt Holdoff" "Updated,Not updated"
|
|
sif cpuis("IMX50*")
|
|
group.long 0x80++0xf
|
|
line.long 0x00 "INTSEC0,Interrupt Security 0 Register"
|
|
bitfld.long 0x00 31. " SECURE[31] ,Interrupt 31 Status" "Fast,Normal"
|
|
bitfld.long 0x00 30. " SECURE[30] ,Interrupt 30 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SECURE[29] ,Interrupt 29 Status" "Fast,Normal"
|
|
bitfld.long 0x00 28. " SECURE[28] ,Interrupt 28 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SECURE[27] ,Interrupt 27 Status" "Fast,Normal"
|
|
bitfld.long 0x00 26. " SECURE[26] ,Interrupt 26 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SECURE[25] ,Interrupt 25 Status" "Fast,Normal"
|
|
bitfld.long 0x00 24. " SECURE[24] ,Interrupt 24 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SECURE[23] ,Interrupt 23 Status" "Fast,Normal"
|
|
bitfld.long 0x00 22. " SECURE[22] ,Interrupt 22 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE[21] ,Interrupt 21 Status" "Fast,Normal"
|
|
bitfld.long 0x00 20. " SECURE[20] ,Interrupt 20 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SECURE[19] ,Interrupt 19 Status" "Fast,Normal"
|
|
bitfld.long 0x00 18. " SECURE[18] ,Interrupt 18 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SECURE[17] ,Interrupt 17 Status" "Fast,Normal"
|
|
bitfld.long 0x00 16. " SECURE[16] ,Interrupt 16 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SECURE[15] ,Interrupt 15 Status" "Fast,Normal"
|
|
bitfld.long 0x00 14. " SECURE[14] ,Interrupt 14 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SECURE[13] ,Interrupt 13 Status" "Fast,Normal"
|
|
bitfld.long 0x00 12. " SECURE[12] ,Interrupt 12 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SECURE[11] ,Interrupt 11 Status" "Fast,Normal"
|
|
bitfld.long 0x00 10. " SECURE[10] ,Interrupt 10 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE[9] ,Interrupt 9 Status" "Fast,Normal"
|
|
bitfld.long 0x00 8. " SECURE[8] ,Interrupt 8 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECURE[7] ,Interrupt 7 Status" "Fast,Normal"
|
|
bitfld.long 0x00 6. " SECURE[6] ,Interrupt 6 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SECURE[5] ,Interrupt 5 Status" "Fast,Normal"
|
|
bitfld.long 0x00 4. " SECURE[4] ,Interrupt 4 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SECURE[3] ,Interrupt 3 Status" "Fast,Normal"
|
|
bitfld.long 0x00 2. " SECURE[2] ,Interrupt 2 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SECURE[1] ,Interrupt 1 Status" "Fast,Normal"
|
|
bitfld.long 0x00 0. " SECURE[0] ,Interrupt 0 Status" "Fast,Normal"
|
|
line.long 0x04 "INTSEC1,Interrupt Security 1 Register"
|
|
bitfld.long 0x04 31. " SECURE[63] ,Interrupt 63 Status" "Fast,Normal"
|
|
bitfld.long 0x04 30. " SECURE[62] ,Interrupt 62 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SECURE[61] ,Interrupt 61 Status" "Fast,Normal"
|
|
bitfld.long 0x04 28. " SECURE[60] ,Interrupt 60 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 27. " SECURE[59] ,Interrupt 59 Status" "Fast,Normal"
|
|
bitfld.long 0x04 26. " SECURE[58] ,Interrupt 58 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SECURE[57] ,Interrupt 57 Status" "Fast,Normal"
|
|
bitfld.long 0x04 24. " SECURE[56] ,Interrupt 56 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 23. " SECURE[55] ,Interrupt 55 Status" "Fast,Normal"
|
|
bitfld.long 0x04 22. " SECURE[54] ,Interrupt 54 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SECURE[53] ,Interrupt 53 Status" "Fast,Normal"
|
|
bitfld.long 0x04 20. " SECURE[52] ,Interrupt 52 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SECURE[51] ,Interrupt 51 Status" "Fast,Normal"
|
|
bitfld.long 0x04 18. " SECURE[50] ,Interrupt 50 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 17. " SECURE[49] ,Interrupt 49 Status" "Fast,Normal"
|
|
bitfld.long 0x04 16. " SECURE[48] ,Interrupt 48 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SECURE[47] ,Interrupt 47 Status" "Fast,Normal"
|
|
bitfld.long 0x04 14. " SECURE[46] ,Interrupt 46 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SECURE[45] ,Interrupt 45 Status" "Fast,Normal"
|
|
bitfld.long 0x04 12. " SECURE[44] ,Interrupt 44 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SECURE[43] ,Interrupt 43 Status" "Fast,Normal"
|
|
bitfld.long 0x04 10. " SECURE[42] ,Interrupt 42 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SECURE[41] ,Interrupt 41 Status" "Fast,Normal"
|
|
bitfld.long 0x04 8. " SECURE[40] ,Interrupt 40 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SECURE[39] ,Interrupt 39 Status" "Fast,Normal"
|
|
bitfld.long 0x04 6. " SECURE[38] ,Interrupt 38 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SECURE[37] ,Interrupt 37 Status" "Fast,Normal"
|
|
bitfld.long 0x04 4. " SECURE[36] ,Interrupt 36 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SECURE[35] ,Interrupt 35 Status" "Fast,Normal"
|
|
bitfld.long 0x04 2. " SECURE[34] ,Interrupt 34 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SECURE[33] ,Interrupt 33 Status" "Fast,Normal"
|
|
bitfld.long 0x04 0. " SECURE[32] ,Interrupt 32 Status" "Fast,Normal"
|
|
line.long 0x08 "INTSEC2,Interrupt Security 2 Register"
|
|
bitfld.long 0x08 31. " SECURE[95] ,Interrupt 95 Status" "Fast,Normal"
|
|
bitfld.long 0x08 30. " SECURE[94] ,Interrupt 94 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 29. " SECURE[93] ,Interrupt 93 Status" "Fast,Normal"
|
|
bitfld.long 0x08 28. " SECURE[92] ,Interrupt 92 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 27. " SECURE[91] ,Interrupt 91 Status" "Fast,Normal"
|
|
bitfld.long 0x08 26. " SECURE[90] ,Interrupt 90 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SECURE[89] ,Interrupt 89 Status" "Fast,Normal"
|
|
bitfld.long 0x08 24. " SECURE[88] ,Interrupt 88 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 23. " SECURE[87] ,Interrupt 87 Status" "Fast,Normal"
|
|
bitfld.long 0x08 22. " SECURE[86] ,Interrupt 86 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SECURE[85] ,Interrupt 85 Status" "Fast,Normal"
|
|
bitfld.long 0x08 20. " SECURE[84] ,Interrupt 84 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SECURE[83] ,Interrupt 83 Status" "Fast,Normal"
|
|
bitfld.long 0x08 18. " SECURE[82] ,Interrupt 82 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 17. " SECURE[81] ,Interrupt 81 Status" "Fast,Normal"
|
|
bitfld.long 0x08 16. " SECURE[80] ,Interrupt 80 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 15. " SECURE[79] ,Interrupt 79 Status" "Fast,Normal"
|
|
bitfld.long 0x08 14. " SECURE[78] ,Interrupt 78 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SECURE[77] ,Interrupt 77 Status" "Fast,Normal"
|
|
bitfld.long 0x08 12. " SECURE[76] ,Interrupt 76 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SECURE[75] ,Interrupt 75 Status" "Fast,Normal"
|
|
bitfld.long 0x08 10. " SECURE[74] ,Interrupt 74 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SECURE[73] ,Interrupt 73 Status" "Fast,Normal"
|
|
bitfld.long 0x08 8. " SECURE[72] ,Interrupt 72 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SECURE[71] ,Interrupt 71 Status" "Fast,Normal"
|
|
bitfld.long 0x08 6. " SECURE[70] ,Interrupt 70 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SECURE[69] ,Interrupt 69 Status" "Fast,Normal"
|
|
bitfld.long 0x08 4. " SECURE[68] ,Interrupt 68 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SECURE[67] ,Interrupt 67 Status" "Fast,Normal"
|
|
bitfld.long 0x08 2. " SECURE[66] ,Interrupt 66 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SECURE[65] ,Interrupt 65 Status" "Fast,Normal"
|
|
bitfld.long 0x08 0. " SECURE[64] ,Interrupt 64 Status" "Fast,Normal"
|
|
line.long 0x0c "INTSEC3,Interrupt Security 3 Register"
|
|
bitfld.long 0x0c 31. " SECURE[127] ,Interrupt 127 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 30. " SECURE[126] ,Interrupt 126 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " SECURE[125] ,Interrupt 125 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 28. " SECURE[124] ,Interrupt 124 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " SECURE[123] ,Interrupt 123 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 26. " SECURE[122] ,Interrupt 122 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " SECURE[121] ,Interrupt 121 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 24. " SECURE[120] ,Interrupt 120 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " SECURE[119] ,Interrupt 119 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 22. " SECURE[118] ,Interrupt 118 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " SECURE[117] ,Interrupt 117 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 20. " SECURE[116] ,Interrupt 116 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " SECURE[115] ,Interrupt 115 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 18. " SECURE[114] ,Interrupt 114 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " SECURE[113] ,Interrupt 113 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 16. " SECURE[112] ,Interrupt 112 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " SECURE[111] ,Interrupt 111 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 14. " SECURE[110] ,Interrupt 110 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " SECURE[109] ,Interrupt 109 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 12. " SECURE[108] ,Interrupt 108 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " SECURE[107] ,Interrupt 107 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 10. " SECURE[106] ,Interrupt 106 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " SECURE[105] ,Interrupt 105 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 8. " SECURE[104] ,Interrupt 104 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " SECURE[103] ,Interrupt 103 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 6. " SECURE[102] ,Interrupt 102 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " SECURE[101] ,Interrupt 101 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 4. " SECURE[100] ,Interrupt 100 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " SECURE[99] ,Interrupt 99 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 2. " SECURE[98] ,Interrupt 98 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " SECURE[97] ,Interrupt 97 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 0. " SECURE[96] ,Interrupt 96 Status" "Fast,Normal"
|
|
else
|
|
group.long 0x80++0xf
|
|
line.long 0x00 "INTSEC0,Interrupt Security 0 Register"
|
|
bitfld.long 0x00 31. " SECURE[31] ,Interrupt Secure 31 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 30. " SECURE[30] ,Interrupt Secure 30 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SECURE[29] ,Interrupt Secure 29 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 28. " SECURE[28] ,Interrupt Secure 28 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SECURE[27] ,Interrupt Secure 27 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 26. " SECURE[26] ,Interrupt Secure 26 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SECURE[25] ,Interrupt Secure 25 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 24. " SECURE[24] ,Interrupt Secure 24 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SECURE[23] ,Interrupt Secure 23 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 22. " SECURE[22] ,Interrupt Secure 22 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE[21] ,Interrupt Secure 21 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 20. " SECURE[20] ,Interrupt Secure 20 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SECURE[19] ,Interrupt Secure 19 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 18. " SECURE[18] ,Interrupt Secure 18 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SECURE[17] ,Interrupt Secure 17 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 16. " SECURE[16] ,Interrupt Secure 16 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SECURE[15] ,Interrupt Secure 15 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 14. " SECURE[14] ,Interrupt Secure 14 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SECURE[13] ,Interrupt Secure 13 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 12. " SECURE[12] ,Interrupt Secure 12 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SECURE[11] ,Interrupt Secure 11 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 10. " SECURE[10] ,Interrupt Secure 10 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE[9] ,Interrupt Secure 9 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 8. " SECURE[8] ,Interrupt Secure 8 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECURE[7] ,Interrupt Secure 7 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 6. " SECURE[6] ,Interrupt Secure 6 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SECURE[5] ,Interrupt Secure 5 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 4. " SECURE[4] ,Interrupt Secure 4 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SECURE[3] ,Interrupt Secure 3 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 2. " SECURE[2] ,Interrupt Secure 2 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SECURE[1] ,Interrupt Secure 1 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 0. " SECURE[0] ,Interrupt Secure 0 Status" "Secured,Not secured"
|
|
line.long 0x04 "INTSEC1,Interrupt Security 1 Register"
|
|
bitfld.long 0x04 31. " SECURE[63] ,Interrupt Secure 63 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 30. " SECURE[62] ,Interrupt Secure 62 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SECURE[61] ,Interrupt Secure 61 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 28. " SECURE[60] ,Interrupt Secure 60 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 27. " SECURE[59] ,Interrupt Secure 59 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 26. " SECURE[58] ,Interrupt Secure 58 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SECURE[57] ,Interrupt Secure 57 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 24. " SECURE[56] ,Interrupt Secure 56 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 23. " SECURE[55] ,Interrupt Secure 55 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 22. " SECURE[54] ,Interrupt Secure 54 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SECURE[53] ,Interrupt Secure 53 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 20. " SECURE[52] ,Interrupt Secure 52 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SECURE[51] ,Interrupt Secure 51 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 18. " SECURE[50] ,Interrupt Secure 50 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 17. " SECURE[49] ,Interrupt Secure 49 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 16. " SECURE[48] ,Interrupt Secure 48 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SECURE[47] ,Interrupt Secure 47 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 14. " SECURE[46] ,Interrupt Secure 46 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SECURE[45] ,Interrupt Secure 45 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 12. " SECURE[44] ,Interrupt Secure 44 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SECURE[43] ,Interrupt Secure 43 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 10. " SECURE[42] ,Interrupt Secure 42 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SECURE[41] ,Interrupt Secure 41 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 8. " SECURE[40] ,Interrupt Secure 40 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SECURE[39] ,Interrupt Secure 39 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 6. " SECURE[38] ,Interrupt Secure 38 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SECURE[37] ,Interrupt Secure 37 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 4. " SECURE[36] ,Interrupt Secure 36 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SECURE[35] ,Interrupt Secure 35 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 2. " SECURE[34] ,Interrupt Secure 34 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SECURE[33] ,Interrupt Secure 33 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 0. " SECURE[32] ,Interrupt Secure 32 Status" "Secured,Not secured"
|
|
line.long 0x08 "INTSEC2,Interrupt Security 2 Register"
|
|
bitfld.long 0x08 31. " SECURE[95] ,Interrupt Secure 95 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 30. " SECURE[94] ,Interrupt Secure 94 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 29. " SECURE[93] ,Interrupt Secure 93 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 28. " SECURE[92] ,Interrupt Secure 92 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 27. " SECURE[91] ,Interrupt Secure 91 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 26. " SECURE[90] ,Interrupt Secure 90 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SECURE[89] ,Interrupt Secure 89 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 24. " SECURE[88] ,Interrupt Secure 88 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 23. " SECURE[87] ,Interrupt Secure 87 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 22. " SECURE[86] ,Interrupt Secure 86 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SECURE[85] ,Interrupt Secure 85 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 20. " SECURE[84] ,Interrupt Secure 84 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SECURE[83] ,Interrupt Secure 83 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 18. " SECURE[82] ,Interrupt Secure 82 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 17. " SECURE[81] ,Interrupt Secure 81 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 16. " SECURE[80] ,Interrupt Secure 80 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 15. " SECURE[79] ,Interrupt Secure 79 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 14. " SECURE[78] ,Interrupt Secure 78 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SECURE[77] ,Interrupt Secure 77 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 12. " SECURE[76] ,Interrupt Secure 76 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SECURE[75] ,Interrupt Secure 75 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 10. " SECURE[74] ,Interrupt Secure 74 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SECURE[73] ,Interrupt Secure 73 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 8. " SECURE[72] ,Interrupt Secure 72 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SECURE[71] ,Interrupt Secure 71 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 6. " SECURE[70] ,Interrupt Secure 70 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SECURE[69] ,Interrupt Secure 69 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 4. " SECURE[68] ,Interrupt Secure 68 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SECURE[67] ,Interrupt Secure 67 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 2. " SECURE[66] ,Interrupt Secure 66 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SECURE[65] ,Interrupt Secure 65 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 0. " SECURE[64] ,Interrupt Secure 64 Status" "Secured,Not secured"
|
|
line.long 0x0c "INTSEC3,Interrupt Security 3 Register"
|
|
bitfld.long 0x0c 31. " SECURE[127] ,Interrupt Secure 127 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 30. " SECURE[126] ,Interrupt Secure 126 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " SECURE[125] ,Interrupt Secure 125 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 28. " SECURE[124] ,Interrupt Secure 124 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " SECURE[123] ,Interrupt Secure 123 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 26. " SECURE[122] ,Interrupt Secure 122 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " SECURE[121] ,Interrupt Secure 121 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 24. " SECURE[120] ,Interrupt Secure 120 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " SECURE[119] ,Interrupt Secure 119 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 22. " SECURE[118] ,Interrupt Secure 118 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " SECURE[117] ,Interrupt Secure 117 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 20. " SECURE[116] ,Interrupt Secure 116 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " SECURE[115] ,Interrupt Secure 115 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 18. " SECURE[114] ,Interrupt Secure 114 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " SECURE[113] ,Interrupt Secure 113 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 16. " SECURE[112] ,Interrupt Secure 112 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " SECURE[111] ,Interrupt Secure 111 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 14. " SECURE[110] ,Interrupt Secure 110 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " SECURE[109] ,Interrupt Secure 109 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 12. " SECURE[108] ,Interrupt Secure 108 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " SECURE[107] ,Interrupt Secure 107 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 10. " SECURE[106] ,Interrupt Secure 106 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " SECURE[105] ,Interrupt Secure 105 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 8. " SECURE[104] ,Interrupt Secure 104 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " SECURE[103] ,Interrupt Secure 103 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 6. " SECURE[102] ,Interrupt Secure 102 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " SECURE[101] ,Interrupt Secure 101 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 4. " SECURE[100] ,Interrupt Secure 100 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " SECURE[99] ,Interrupt Secure 99 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 2. " SECURE[98] ,Interrupt Secure 98 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " SECURE[97] ,Interrupt Secure 97 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 0. " SECURE[96] ,Interrupt Secure 96 Status" "Secured,Not secured"
|
|
endif
|
|
group.long 0x100++0xf
|
|
line.long 0x00 "ENSET0,Enable Set 0 Register"
|
|
bitfld.long 0x00 31. " INTENSET[31] ,Interrupt Enable Set 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTENSET[30] ,Interrupt Enable Set 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTENSET[29] ,Interrupt Enable Set 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTENSET[28] ,Interrupt Enable Set 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTENSET[27] ,Interrupt Enable Set 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTENSET[26] ,Interrupt Enable Set 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTENSET[25] ,Interrupt Enable Set 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTENSET[24] ,Interrupt Enable Set 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTENSET[23] ,Interrupt Enable Set 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " INTENSET[22] ,Interrupt Enable Set 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INTENSET[21] ,Interrupt Enable Set 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTENSET[20] ,Interrupt Enable Set 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTENSET[19] ,Interrupt Enable Set 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTENSET[18] ,Interrupt Enable Set 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTENSET[17] ,Interrupt Enable Set 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTENSET[16] ,Interrupt Enable Set 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTENSET[15] ,Interrupt Enable Set 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTENSET[14] ,Interrupt Enable Set 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTENSET[13] ,Interrupt Enable Set 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTENSET[12] ,Interrupt Enable Set 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTENSET[11] ,Interrupt Enable Set 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTENSET[10] ,Interrupt Enable Set 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTENSET[9] ,Interrupt Enable Set 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTENSET[8] ,Interrupt Enable Set 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTENSET[7] ,Interrupt Enable Set 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTENSET[6] ,Interrupt Enable Set 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTENSET[5] ,Interrupt Enable Set 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTENSET[4] ,Interrupt Enable Set 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTENSET[3] ,Interrupt Enable Set 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTENSET[2] ,Interrupt Enable Set 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTENSET[1] ,Interrupt Enable Set 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTENSET[0] ,Interrupt Enable Set 0" "Disabled,Enabled"
|
|
line.long 0x04 "ENSET1,Enable Set 1 Register"
|
|
bitfld.long 0x04 31. " INTENSET[63] ,Interrupt Enable Set 63" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " INTENSET[62] ,Interrupt Enable Set 62" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTENSET[61] ,Interrupt Enable Set 61" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " INTENSET[60] ,Interrupt Enable Set 60" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTENSET[59] ,Interrupt Enable Set 59" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " INTENSET[58] ,Interrupt Enable Set 58" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTENSET[57] ,Interrupt Enable Set 57" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " INTENSET[56] ,Interrupt Enable Set 56" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTENSET[55] ,Interrupt Enable Set 55" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " INTENSET[54] ,Interrupt Enable Set 54" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTENSET[53] ,Interrupt Enable Set 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " INTENSET[52] ,Interrupt Enable Set 52" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTENSET[51] ,Interrupt Enable Set 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " INTENSET[50] ,Interrupt Enable Set 50" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTENSET[49] ,Interrupt Enable Set 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " INTENSET[48] ,Interrupt Enable Set 48" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTENSET[47] ,Interrupt Enable Set 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " INTENSET[46] ,Interrupt Enable Set 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTENSET[45] ,Interrupt Enable Set 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " INTENSET[44] ,Interrupt Enable Set 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTENSET[43] ,Interrupt Enable Set 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " INTENSET[42] ,Interrupt Enable Set 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTENSET[41] ,Interrupt Enable Set 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " INTENSET[40] ,Interrupt Enable Set 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTENSET[39] ,Interrupt Enable Set 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " INTENSET[38] ,Interrupt Enable Set 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTENSET[37] ,Interrupt Enable Set 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " INTENSET[36] ,Interrupt Enable Set 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTENSET[35] ,Interrupt Enable Set 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INTENSET[34] ,Interrupt Enable Set 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTENSET[33] ,Interrupt Enable Set 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INTENSET[32] ,Interrupt Enable Set 32" "Disabled,Enabled"
|
|
line.long 0x08 "ENSET2,Enable Set 2 Register"
|
|
bitfld.long 0x08 31. " INTENSET[95] ,Interrupt Enable Set 95" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " INTENSET[94] ,Interrupt Enable Set 94" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " INTENSET[93] ,Interrupt Enable Set 93" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " INTENSET[92] ,Interrupt Enable Set 92" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " INTENSET[91] ,Interrupt Enable Set 91" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " INTENSET[90] ,Interrupt Enable Set 90" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " INTENSET[89] ,Interrupt Enable Set 89" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " INTENSET[88] ,Interrupt Enable Set 88" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " INTENSET[87] ,Interrupt Enable Set 87" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " INTENSET[86] ,Interrupt Enable Set 86" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " INTENSET[85] ,Interrupt Enable Set 85" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " INTENSET[84] ,Interrupt Enable Set 84" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " INTENSET[83] ,Interrupt Enable Set 83" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " INTENSET[82] ,Interrupt Enable Set 82" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " INTENSET[81] ,Interrupt Enable Set 81" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " INTENSET[80] ,Interrupt Enable Set 80" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " INTENSET[79] ,Interrupt Enable Set 79" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " INTENSET[78] ,Interrupt Enable Set 78" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " INTENSET[77] ,Interrupt Enable Set 77" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " INTENSET[76] ,Interrupt Enable Set 76" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " INTENSET[75] ,Interrupt Enable Set 75" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " INTENSET[74] ,Interrupt Enable Set 74" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " INTENSET[73] ,Interrupt Enable Set 73" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " INTENSET[72] ,Interrupt Enable Set 72" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " INTENSET[71] ,Interrupt Enable Set 71" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " INTENSET[70] ,Interrupt Enable Set 70" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " INTENSET[69] ,Interrupt Enable Set 69" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " INTENSET[68] ,Interrupt Enable Set 68" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " INTENSET[67] ,Interrupt Enable Set 67" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " INTENSET[66] ,Interrupt Enable Set 66" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " INTENSET[65] ,Interrupt Enable Set 65" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " INTENSET[64] ,Interrupt Enable Set 64" "Disabled,Enabled"
|
|
line.long 0x0c "ENSET3,Enable Set 3 Register"
|
|
bitfld.long 0x0c 31. " INTENSET[127] ,Interrupt Enable Set 127" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " INTENSET[126] ,Interrupt Enable Set 126" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " INTENSET[125] ,Interrupt Enable Set 125" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " INTENSET[124] ,Interrupt Enable Set 124" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " INTENSET[123] ,Interrupt Enable Set 123" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " INTENSET[122] ,Interrupt Enable Set 122" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " INTENSET[121] ,Interrupt Enable Set 121" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " INTENSET[120] ,Interrupt Enable Set 120" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " INTENSET[119] ,Interrupt Enable Set 119" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " INTENSET[118] ,Interrupt Enable Set 118" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " INTENSET[117] ,Interrupt Enable Set 117" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " INTENSET[116] ,Interrupt Enable Set 116" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " INTENSET[115] ,Interrupt Enable Set 115" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " INTENSET[114] ,Interrupt Enable Set 114" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " INTENSET[113] ,Interrupt Enable Set 113" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " INTENSET[112] ,Interrupt Enable Set 112" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " INTENSET[111] ,Interrupt Enable Set 111" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " INTENSET[110] ,Interrupt Enable Set 110" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " INTENSET[109] ,Interrupt Enable Set 109" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " INTENSET[108] ,Interrupt Enable Set 108" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " INTENSET[107] ,Interrupt Enable Set 107" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " INTENSET[106] ,Interrupt Enable Set 106" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " INTENSET[105] ,Interrupt Enable Set 105" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " INTENSET[104] ,Interrupt Enable Set 104" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " INTENSET[103] ,Interrupt Enable Set 103" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " INTENSET[102] ,Interrupt Enable Set 102" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " INTENSET[101] ,Interrupt Enable Set 101" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " INTENSET[100] ,Interrupt Enable Set 100" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " INTENSET[99] ,Interrupt Enable Set 99" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " INTENSET[98] ,Interrupt Enable Set 98" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " INTENSET[97] ,Interrupt Enable Set 97" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " INTENSET[96] ,Interrupt Enable Set 96" "Disabled,Enabled"
|
|
group.long 0x180++0xf
|
|
line.long 0x00 "ENCLEAR0,Enable Clear 0 Register"
|
|
bitfld.long 0x00 31. " INTENCLEAR[31] ,Interrupt Enable Clear 31" "No effect,Cleared"
|
|
bitfld.long 0x00 30. " INTENCLEAR[30] ,Interrupt Enable Clear 30" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTENCLEAR[29] ,Interrupt Enable Clear 29" "No effect,Cleared"
|
|
bitfld.long 0x00 28. " INTENCLEAR[28] ,Interrupt Enable Clear 28" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTENCLEAR[27] ,Interrupt Enable Clear 27" "No effect,Cleared"
|
|
bitfld.long 0x00 26. " INTENCLEAR[26] ,Interrupt Enable Clear 26" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTENCLEAR[25] ,Interrupt Enable Clear 25" "No effect,Cleared"
|
|
bitfld.long 0x00 24. " INTENCLEAR[24] ,Interrupt Enable Clear 24" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTENCLEAR[23] ,Interrupt Enable Clear 23" "No effect,Cleared"
|
|
bitfld.long 0x00 22. " INTENCLEAR[22] ,Interrupt Enable Clear 22" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INTENCLEAR[21] ,Interrupt Enable Clear 21" "No effect,Cleared"
|
|
bitfld.long 0x00 20. " INTENCLEAR[20] ,Interrupt Enable Clear 20" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTENCLEAR[19] ,Interrupt Enable Clear 19" "No effect,Cleared"
|
|
bitfld.long 0x00 18. " INTENCLEAR[18] ,Interrupt Enable Clear 18" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTENCLEAR[17] ,Interrupt Enable Clear 17" "No effect,Cleared"
|
|
bitfld.long 0x00 16. " INTENCLEAR[16] ,Interrupt Enable Clear 16" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTENCLEAR[15] ,Interrupt Enable Clear 15" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " INTENCLEAR[14] ,Interrupt Enable Clear 14" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTENCLEAR[13] ,Interrupt Enable Clear 13" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " INTENCLEAR[12] ,Interrupt Enable Clear 12" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTENCLEAR[11] ,Interrupt Enable Clear 11" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " INTENCLEAR[10] ,Interrupt Enable Clear 10" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTENCLEAR[9] ,Interrupt Enable Clear 9" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " INTENCLEAR[8] ,Interrupt Enable Clear 8" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTENCLEAR[7] ,Interrupt Enable Clear 7" "No effect,Cleared"
|
|
bitfld.long 0x00 6. " INTENCLEAR[6] ,Interrupt Enable Clear 6" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTENCLEAR[5] ,Interrupt Enable Clear 5" "No effect,Cleared"
|
|
bitfld.long 0x00 4. " INTENCLEAR[4] ,Interrupt Enable Clear 4" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTENCLEAR[3] ,Interrupt Enable Clear 3" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " INTENCLEAR[2] ,Interrupt Enable Clear 2" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTENCLEAR[1] ,Interrupt Enable Clear 1" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " INTENCLEAR[0] ,Interrupt Enable Clear 0" "No effect,Cleared"
|
|
line.long 0x04 "ENCLEAR1,Enable Clear 1 Register"
|
|
bitfld.long 0x04 31. " INTENCLEAR[63] ,Interrupt Enable Clear 63" "No effect,Cleared"
|
|
bitfld.long 0x04 30. " INTENCLEAR[62] ,Interrupt Enable Clear 62" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTENCLEAR[61] ,Interrupt Enable Clear 61" "No effect,Cleared"
|
|
bitfld.long 0x04 28. " INTENCLEAR[60] ,Interrupt Enable Clear 60" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTENCLEAR[59] ,Interrupt Enable Clear 59" "No effect,Cleared"
|
|
bitfld.long 0x04 26. " INTENCLEAR[58] ,Interrupt Enable Clear 58" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTENCLEAR[57] ,Interrupt Enable Clear 57" "No effect,Cleared"
|
|
bitfld.long 0x04 24. " INTENCLEAR[56] ,Interrupt Enable Clear 56" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTENCLEAR[55] ,Interrupt Enable Clear 55" "No effect,Cleared"
|
|
bitfld.long 0x04 22. " INTENCLEAR[54] ,Interrupt Enable Clear 54" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTENCLEAR[53] ,Interrupt Enable Clear 53" "No effect,Cleared"
|
|
bitfld.long 0x04 20. " INTENCLEAR[52] ,Interrupt Enable Clear 52" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTENCLEAR[51] ,Interrupt Enable Clear 51" "No effect,Cleared"
|
|
bitfld.long 0x04 18. " INTENCLEAR[50] ,Interrupt Enable Clear 50" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTENCLEAR[49] ,Interrupt Enable Clear 49" "No effect,Cleared"
|
|
bitfld.long 0x04 16. " INTENCLEAR[48] ,Interrupt Enable Clear 48" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTENCLEAR[47] ,Interrupt Enable Clear 47" "No effect,Cleared"
|
|
bitfld.long 0x04 14. " INTENCLEAR[46] ,Interrupt Enable Clear 46" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTENCLEAR[45] ,Interrupt Enable Clear 45" "No effect,Cleared"
|
|
bitfld.long 0x04 12. " INTENCLEAR[44] ,Interrupt Enable Clear 44" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTENCLEAR[43] ,Interrupt Enable Clear 43" "No effect,Cleared"
|
|
bitfld.long 0x04 10. " INTENCLEAR[42] ,Interrupt Enable Clear 42" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTENCLEAR[41] ,Interrupt Enable Clear 41" "No effect,Cleared"
|
|
bitfld.long 0x04 8. " INTENCLEAR[40] ,Interrupt Enable Clear 40" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTENCLEAR[39] ,Interrupt Enable Clear 39" "No effect,Cleared"
|
|
bitfld.long 0x04 6. " INTENCLEAR[38] ,Interrupt Enable Clear 38" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTENCLEAR[37] ,Interrupt Enable Clear 37" "No effect,Cleared"
|
|
bitfld.long 0x04 4. " INTENCLEAR[36] ,Interrupt Enable Clear 36" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTENCLEAR[35] ,Interrupt Enable Clear 35" "No effect,Cleared"
|
|
bitfld.long 0x04 2. " INTENCLEAR[34] ,Interrupt Enable Clear 34" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTENCLEAR[33] ,Interrupt Enable Clear 33" "No effect,Cleared"
|
|
bitfld.long 0x04 0. " INTENCLEAR[32] ,Interrupt Enable Clear 32" "No effect,Cleared"
|
|
line.long 0x08 "ENCLEAR2,Enable Clear 2 Register"
|
|
bitfld.long 0x08 31. " INTENCLEAR[95] ,Interrupt Enable Clear 95" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " INTENCLEAR[94] ,Interrupt Enable Clear 94" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 29. " INTENCLEAR[93] ,Interrupt Enable Clear 93" "No effect,Cleared"
|
|
bitfld.long 0x08 28. " INTENCLEAR[92] ,Interrupt Enable Clear 92" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 27. " INTENCLEAR[91] ,Interrupt Enable Clear 91" "No effect,Cleared"
|
|
bitfld.long 0x08 26. " INTENCLEAR[90] ,Interrupt Enable Clear 90" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 25. " INTENCLEAR[89] ,Interrupt Enable Clear 89" "No effect,Cleared"
|
|
bitfld.long 0x08 24. " INTENCLEAR[88] ,Interrupt Enable Clear 88" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 23. " INTENCLEAR[87] ,Interrupt Enable Clear 87" "No effect,Cleared"
|
|
bitfld.long 0x08 22. " INTENCLEAR[86] ,Interrupt Enable Clear 86" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " INTENCLEAR[85] ,Interrupt Enable Clear 85" "No effect,Cleared"
|
|
bitfld.long 0x08 20. " INTENCLEAR[84] ,Interrupt Enable Clear 84" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " INTENCLEAR[83] ,Interrupt Enable Clear 83" "No effect,Cleared"
|
|
bitfld.long 0x08 18. " INTENCLEAR[82] ,Interrupt Enable Clear 82" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " INTENCLEAR[81] ,Interrupt Enable Clear 81" "No effect,Cleared"
|
|
bitfld.long 0x08 16. " INTENCLEAR[80] ,Interrupt Enable Clear 80" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " INTENCLEAR[79] ,Interrupt Enable Clear 79" "No effect,Cleared"
|
|
bitfld.long 0x08 14. " INTENCLEAR[78] ,Interrupt Enable Clear 78" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " INTENCLEAR[77] ,Interrupt Enable Clear 77" "No effect,Cleared"
|
|
bitfld.long 0x08 12. " INTENCLEAR[76] ,Interrupt Enable Clear 76" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " INTENCLEAR[75] ,Interrupt Enable Clear 75" "No effect,Cleared"
|
|
bitfld.long 0x08 10. " INTENCLEAR[74] ,Interrupt Enable Clear 74" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " INTENCLEAR[73] ,Interrupt Enable Clear 73" "No effect,Cleared"
|
|
bitfld.long 0x08 8. " INTENCLEAR[72] ,Interrupt Enable Clear 72" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " INTENCLEAR[71] ,Interrupt Enable Clear 71" "No effect,Cleared"
|
|
bitfld.long 0x08 6. " INTENCLEAR[70] ,Interrupt Enable Clear 70" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " INTENCLEAR[69] ,Interrupt Enable Clear 69" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " INTENCLEAR[68] ,Interrupt Enable Clear 68" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " INTENCLEAR[67] ,Interrupt Enable Clear 67" "No effect,Cleared"
|
|
bitfld.long 0x08 2. " INTENCLEAR[66] ,Interrupt Enable Clear 66" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " INTENCLEAR[65] ,Interrupt Enable Clear 65" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " INTENCLEAR[64] ,Interrupt Enable Clear 64" "No effect,Cleared"
|
|
line.long 0x0c "ENCLEAR3,Enable Clear 3 Register"
|
|
bitfld.long 0x0c 31. " INTENCLEAR[127] ,Interrupt Enable Clear 127" "No effect,Cleared"
|
|
bitfld.long 0x0c 30. " INTENCLEAR[126] ,Interrupt Enable Clear 126" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " INTENCLEAR[125] ,Interrupt Enable Clear 125" "No effect,Cleared"
|
|
bitfld.long 0x0c 28. " INTENCLEAR[124] ,Interrupt Enable Clear 124" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " INTENCLEAR[123] ,Interrupt Enable Clear 123" "No effect,Cleared"
|
|
bitfld.long 0x0c 26. " INTENCLEAR[122] ,Interrupt Enable Clear 122" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " INTENCLEAR[121] ,Interrupt Enable Clear 121" "No effect,Cleared"
|
|
bitfld.long 0x0c 24. " INTENCLEAR[120] ,Interrupt Enable Clear 120" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " INTENCLEAR[119] ,Interrupt Enable Clear 119" "No effect,Cleared"
|
|
bitfld.long 0x0c 22. " INTENCLEAR[118] ,Interrupt Enable Clear 118" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " INTENCLEAR[117] ,Interrupt Enable Clear 117" "No effect,Cleared"
|
|
bitfld.long 0x0c 20. " INTENCLEAR[116] ,Interrupt Enable Clear 116" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " INTENCLEAR[115] ,Interrupt Enable Clear 115" "No effect,Cleared"
|
|
bitfld.long 0x0c 18. " INTENCLEAR[114] ,Interrupt Enable Clear 114" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " INTENCLEAR[113] ,Interrupt Enable Clear 113" "No effect,Cleared"
|
|
bitfld.long 0x0c 16. " INTENCLEAR[112] ,Interrupt Enable Clear 112" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " INTENCLEAR[111] ,Interrupt Enable Clear 111" "No effect,Cleared"
|
|
bitfld.long 0x0c 14. " INTENCLEAR[110] ,Interrupt Enable Clear 110" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " INTENCLEAR[109] ,Interrupt Enable Clear 109" "No effect,Cleared"
|
|
bitfld.long 0x0c 12. " INTENCLEAR[108] ,Interrupt Enable Clear 108" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " INTENCLEAR[107] ,Interrupt Enable Clear 107" "No effect,Cleared"
|
|
bitfld.long 0x0c 10. " INTENCLEAR[106] ,Interrupt Enable Clear 106" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " INTENCLEAR[105] ,Interrupt Enable Clear 105" "No effect,Cleared"
|
|
bitfld.long 0x0c 8. " INTENCLEAR[104] ,Interrupt Enable Clear 104" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " INTENCLEAR[103] ,Interrupt Enable Clear 103" "No effect,Cleared"
|
|
bitfld.long 0x0c 6. " INTENCLEAR[102] ,Interrupt Enable Clear 102" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " INTENCLEAR[101] ,Interrupt Enable Clear 101" "No effect,Cleared"
|
|
bitfld.long 0x0c 4. " INTENCLEAR[100] ,Interrupt Enable Clear 100" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " INTENCLEAR[99] ,Interrupt Enable Clear 99" "No effect,Cleared"
|
|
bitfld.long 0x0c 2. " INTENCLEAR[98] ,Interrupt Enable Clear 98" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " INTENCLEAR[97] ,Interrupt Enable Clear 97" "No effect,Cleared"
|
|
bitfld.long 0x0c 0. " INTENCLEAR[96] ,Interrupt Enable Clear 96" "No effect,Cleared"
|
|
group.long 0x200++0xf
|
|
line.long 0x00 "SRCSET0,Source Set 0 Register"
|
|
bitfld.long 0x00 31. " SRCSET[31] ,Interrupt Source Set 31" "No effect,Set"
|
|
bitfld.long 0x00 30. " SRCSET[30] ,Interrupt Source Set 30" "No effect,Set"
|
|
bitfld.long 0x00 29. " SRCSET[29] ,Interrupt Source Set 29" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SRCSET[28] ,Interrupt Source Set 28" "No effect,Set"
|
|
bitfld.long 0x00 27. " SRCSET[27] ,Interrupt Source Set 27" "No effect,Set"
|
|
bitfld.long 0x00 26. " SRCSET[26] ,Interrupt Source Set 26" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SRCSET[25] ,Interrupt Source Set 25" "No effect,Set"
|
|
bitfld.long 0x00 24. " SRCSET[24] ,Interrupt Source Set 24" "No effect,Set"
|
|
bitfld.long 0x00 23. " SRCSET[23] ,Interrupt Source Set 23" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SRCSET[22] ,Interrupt Source Set 22" "No effect,Set"
|
|
bitfld.long 0x00 21. " SRCSET[21] ,Interrupt Source Set 21" "No effect,Set"
|
|
bitfld.long 0x00 20. " SRCSET[20] ,Interrupt Source Set 20" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SRCSET[19] ,Interrupt Source Set 19" "No effect,Set"
|
|
bitfld.long 0x00 18. " SRCSET[18] ,Interrupt Source Set 18" "No effect,Set"
|
|
bitfld.long 0x00 17. " SRCSET[17] ,Interrupt Source Set 17" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SRCSET[16] ,Interrupt Source Set 16" "No effect,Set"
|
|
bitfld.long 0x00 15. " SRCSET[15] ,Interrupt Source Set 15" "No effect,Set"
|
|
bitfld.long 0x00 14. " SRCSET[14] ,Interrupt Source Set 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SRCSET[13] ,Interrupt Source Set 13" "No effect,Set"
|
|
bitfld.long 0x00 12. " SRCSET[12] ,Interrupt Source Set 12" "No effect,Set"
|
|
bitfld.long 0x00 11. " SRCSET[11] ,Interrupt Source Set 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SRCSET[10] ,Interrupt Source Set 10" "No effect,Set"
|
|
bitfld.long 0x00 9. " SRCSET[9] ,Interrupt Source Set 9" "No effect,Set"
|
|
bitfld.long 0x00 8. " SRCSET[8] ,Interrupt Source Set 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SRCSET[7] ,Interrupt Source Set 7" "No effect,Set"
|
|
bitfld.long 0x00 6. " SRCSET[6] ,Interrupt Source Set 6" "No effect,Set"
|
|
bitfld.long 0x00 5. " SRCSET[5] ,Interrupt Source Set 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SRCSET[4] ,Interrupt Source Set 4" "No effect,Set"
|
|
bitfld.long 0x00 3. " SRCSET[3] ,Interrupt Source Set 3" "No effect,Set"
|
|
bitfld.long 0x00 2. " SRCSET[2] ,Interrupt Source Set 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRCSET[1] ,Interrupt Source Set 1" "No effect,Set"
|
|
bitfld.long 0x00 0. " SRCSET[0] ,Interrupt Source Set 0" "No effect,Set"
|
|
line.long 0x04 "SRCSET1,Source Set 1 Register"
|
|
bitfld.long 0x04 31. " SRCSET[63] ,Interrupt Source Set 63" "No effect,Set"
|
|
bitfld.long 0x04 30. " SRCSET[62] ,Interrupt Source Set 62" "No effect,Set"
|
|
bitfld.long 0x04 29. " SRCSET[61] ,Interrupt Source Set 61" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 28. " SRCSET[60] ,Interrupt Source Set 60" "No effect,Set"
|
|
bitfld.long 0x04 27. " SRCSET[59] ,Interrupt Source Set 59" "No effect,Set"
|
|
bitfld.long 0x04 26. " SRCSET[58] ,Interrupt Source Set 58" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SRCSET[57] ,Interrupt Source Set 57" "No effect,Set"
|
|
bitfld.long 0x04 24. " SRCSET[56] ,Interrupt Source Set 56" "No effect,Set"
|
|
bitfld.long 0x04 23. " SRCSET[55] ,Interrupt Source Set 55" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SRCSET[54] ,Interrupt Source Set 54" "No effect,Set"
|
|
bitfld.long 0x04 21. " SRCSET[53] ,Interrupt Source Set 53" "No effect,Set"
|
|
bitfld.long 0x04 20. " SRCSET[52] ,Interrupt Source Set 52" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SRCSET[51] ,Interrupt Source Set 51" "No effect,Set"
|
|
bitfld.long 0x04 18. " SRCSET[50] ,Interrupt Source Set 50" "No effect,Set"
|
|
bitfld.long 0x04 17. " SRCSET[49] ,Interrupt Source Set 49" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 16. " SRCSET[48] ,Interrupt Source Set 48" "No effect,Set"
|
|
bitfld.long 0x04 15. " SRCSET[47] ,Interrupt Source Set 47" "No effect,Set"
|
|
bitfld.long 0x04 14. " SRCSET[46] ,Interrupt Source Set 46" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SRCSET[45] ,Interrupt Source Set 45" "No effect,Set"
|
|
bitfld.long 0x04 12. " SRCSET[44] ,Interrupt Source Set 44" "No effect,Set"
|
|
bitfld.long 0x04 11. " SRCSET[43] ,Interrupt Source Set 43" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SRCSET[42] ,Interrupt Source Set 42" "No effect,Set"
|
|
bitfld.long 0x04 9. " SRCSET[41] ,Interrupt Source Set 41" "No effect,Set"
|
|
bitfld.long 0x04 8. " SRCSET[40] ,Interrupt Source Set 40" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SRCSET[39] ,Interrupt Source Set 39" "No effect,Set"
|
|
bitfld.long 0x04 6. " SRCSET[38] ,Interrupt Source Set 38" "No effect,Set"
|
|
bitfld.long 0x04 5. " SRCSET[37] ,Interrupt Source Set 37" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SRCSET[36] ,Interrupt Source Set 36" "No effect,Set"
|
|
bitfld.long 0x04 3. " SRCSET[35] ,Interrupt Source Set 35" "No effect,Set"
|
|
bitfld.long 0x04 2. " SRCSET[34] ,Interrupt Source Set 34" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SRCSET[33] ,Interrupt Source Set 33" "No effect,Set"
|
|
bitfld.long 0x04 0. " SRCSET[32] ,Interrupt Source Set 32" "No effect,Set"
|
|
line.long 0x08 "SRCSET2,Source Set 2 Register"
|
|
bitfld.long 0x08 31. " SRCSET[95] ,Interrupt Source Set 95" "No effect,Set"
|
|
bitfld.long 0x08 30. " SRCSET[94] ,Interrupt Source Set 94" "No effect,Set"
|
|
bitfld.long 0x08 29. " SRCSET[93] ,Interrupt Source Set 93" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 28. " SRCSET[92] ,Interrupt Source Set 92" "No effect,Set"
|
|
bitfld.long 0x08 27. " SRCSET[91] ,Interrupt Source Set 91" "No effect,Set"
|
|
bitfld.long 0x08 26. " SRCSET[90] ,Interrupt Source Set 90" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SRCSET[89] ,Interrupt Source Set 89" "No effect,Set"
|
|
bitfld.long 0x08 24. " SRCSET[88] ,Interrupt Source Set 88" "No effect,Set"
|
|
bitfld.long 0x08 23. " SRCSET[87] ,Interrupt Source Set 87" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SRCSET[86] ,Interrupt Source Set 86" "No effect,Set"
|
|
bitfld.long 0x08 21. " SRCSET[85] ,Interrupt Source Set 85" "No effect,Set"
|
|
bitfld.long 0x08 20. " SRCSET[84] ,Interrupt Source Set 84" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SRCSET[83] ,Interrupt Source Set 83" "No effect,Set"
|
|
bitfld.long 0x08 18. " SRCSET[82] ,Interrupt Source Set 82" "No effect,Set"
|
|
bitfld.long 0x08 17. " SRCSET[81] ,Interrupt Source Set 81" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SRCSET[80] ,Interrupt Source Set 80" "No effect,Set"
|
|
bitfld.long 0x08 15. " SRCSET[79] ,Interrupt Source Set 79" "No effect,Set"
|
|
bitfld.long 0x08 14. " SRCSET[78] ,Interrupt Source Set 78" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SRCSET[77] ,Interrupt Source Set 77" "No effect,Set"
|
|
bitfld.long 0x08 12. " SRCSET[76] ,Interrupt Source Set 76" "No effect,Set"
|
|
bitfld.long 0x08 11. " SRCSET[75] ,Interrupt Source Set 75" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SRCSET[74] ,Interrupt Source Set 74" "No effect,Set"
|
|
bitfld.long 0x08 9. " SRCSET[73] ,Interrupt Source Set 73" "No effect,Set"
|
|
bitfld.long 0x08 8. " SRCSET[72] ,Interrupt Source Set 72" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SRCSET[71] ,Interrupt Source Set 71" "No effect,Set"
|
|
bitfld.long 0x08 6. " SRCSET[70] ,Interrupt Source Set 70" "No effect,Set"
|
|
bitfld.long 0x08 5. " SRCSET[69] ,Interrupt Source Set 69" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 4. " SRCSET[68] ,Interrupt Source Set 68" "No effect,Set"
|
|
bitfld.long 0x08 3. " SRCSET[67] ,Interrupt Source Set 67" "No effect,Set"
|
|
bitfld.long 0x08 2. " SRCSET[66] ,Interrupt Source Set 66" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SRCSET[65] ,Interrupt Source Set 65" "No effect,Set"
|
|
bitfld.long 0x08 0. " SRCSET[64] ,Interrupt Source Set 64" "No effect,Set"
|
|
line.long 0x0c "SRCSET3,Source Set 3 Register"
|
|
bitfld.long 0x0c 31. " SRCSET[127] ,Interrupt Source Set 127" "No effect,Set"
|
|
bitfld.long 0x0c 30. " SRCSET[126] ,Interrupt Source Set 126" "No effect,Set"
|
|
bitfld.long 0x0c 29. " SRCSET[125] ,Interrupt Source Set 125" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " SRCSET[124] ,Interrupt Source Set 124" "No effect,Set"
|
|
bitfld.long 0x0c 27. " SRCSET[123] ,Interrupt Source Set 123" "No effect,Set"
|
|
bitfld.long 0x0c 26. " SRCSET[122] ,Interrupt Source Set 122" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " SRCSET[121] ,Interrupt Source Set 121" "No effect,Set"
|
|
bitfld.long 0x0c 24. " SRCSET[120] ,Interrupt Source Set 120" "No effect,Set"
|
|
bitfld.long 0x0c 23. " SRCSET[119] ,Interrupt Source Set 119" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " SRCSET[118] ,Interrupt Source Set 118" "No effect,Set"
|
|
bitfld.long 0x0c 21. " SRCSET[117] ,Interrupt Source Set 117" "No effect,Set"
|
|
bitfld.long 0x0c 20. " SRCSET[116] ,Interrupt Source Set 116" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " SRCSET[115] ,Interrupt Source Set 115" "No effect,Set"
|
|
bitfld.long 0x0c 18. " SRCSET[114] ,Interrupt Source Set 114" "No effect,Set"
|
|
bitfld.long 0x0c 17. " SRCSET[113] ,Interrupt Source Set 113" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " SRCSET[112] ,Interrupt Source Set 112" "No effect,Set"
|
|
bitfld.long 0x0c 15. " SRCSET[111] ,Interrupt Source Set 111" "No effect,Set"
|
|
bitfld.long 0x0c 14. " SRCSET[110] ,Interrupt Source Set 110" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " SRCSET[109] ,Interrupt Source Set 109" "No effect,Set"
|
|
bitfld.long 0x0c 12. " SRCSET[108] ,Interrupt Source Set 108" "No effect,Set"
|
|
bitfld.long 0x0c 11. " SRCSET[107] ,Interrupt Source Set 107" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " SRCSET[106] ,Interrupt Source Set 106" "No effect,Set"
|
|
bitfld.long 0x0c 9. " SRCSET[105] ,Interrupt Source Set 105" "No effect,Set"
|
|
bitfld.long 0x0c 8. " SRCSET[104] ,Interrupt Source Set 104" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " SRCSET[103] ,Interrupt Source Set 103" "No effect,Set"
|
|
bitfld.long 0x0c 6. " SRCSET[102] ,Interrupt Source Set 102" "No effect,Set"
|
|
bitfld.long 0x0c 5. " SRCSET[101] ,Interrupt Source Set 101" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " SRCSET[100] ,Interrupt Source Set 100" "No effect,Set"
|
|
bitfld.long 0x0c 3. " SRCSET[99] ,Interrupt Source Set 99" "No effect,Set"
|
|
bitfld.long 0x0c 2. " SRCSET[98] ,Interrupt Source Set 98" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " SRCSET[97] ,Interrupt Source Set 97" "No effect,Set"
|
|
bitfld.long 0x0c 0. " SRCSET[96] ,Interrupt Source Set 96" "No effect,Set"
|
|
group.long 0x280++0xf
|
|
line.long 0x00 "SRCCLEAR0,Source Clear 0 Register"
|
|
bitfld.long 0x00 31. " SRCCLEAR[31] ,Interrupt Source Clear 31" "No effect,Cleared"
|
|
bitfld.long 0x00 30. " SRCCLEAR[30] ,Interrupt Source Clear 30" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SRCCLEAR[29] ,Interrupt Source Clear 29" "No effect,Cleared"
|
|
bitfld.long 0x00 28. " SRCCLEAR[28] ,Interrupt Source Clear 28" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SRCCLEAR[27] ,Interrupt Source Clear 27" "No effect,Cleared"
|
|
bitfld.long 0x00 26. " SRCCLEAR[26] ,Interrupt Source Clear 26" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SRCCLEAR[25] ,Interrupt Source Clear 25" "No effect,Cleared"
|
|
bitfld.long 0x00 24. " SRCCLEAR[24] ,Interrupt Source Clear 24" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SRCCLEAR[23] ,Interrupt Source Clear 23" "No effect,Cleared"
|
|
bitfld.long 0x00 22. " SRCCLEAR[22] ,Interrupt Source Clear 22" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SRCCLEAR[21] ,Interrupt Source Clear 21" "No effect,Cleared"
|
|
bitfld.long 0x00 20. " SRCCLEAR[20] ,Interrupt Source Clear 20" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SRCCLEAR[19] ,Interrupt Source Clear 19" "No effect,Cleared"
|
|
bitfld.long 0x00 18. " SRCCLEAR[18] ,Interrupt Source Clear 18" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SRCCLEAR[17] ,Interrupt Source Clear 17" "No effect,Cleared"
|
|
bitfld.long 0x00 16. " SRCCLEAR[16] ,Interrupt Source Clear 16" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRCCLEAR[15] ,Interrupt Source Clear 15" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " SRCCLEAR[14] ,Interrupt Source Clear 14" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SRCCLEAR[13] ,Interrupt Source Clear 13" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " SRCCLEAR[12] ,Interrupt Source Clear 12" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SRCCLEAR[11] ,Interrupt Source Clear 11" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " SRCCLEAR[10] ,Interrupt Source Clear 10" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SRCCLEAR[9] ,Interrupt Source Clear 9" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " SRCCLEAR[8] ,Interrupt Source Clear 8" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SRCCLEAR[7] ,Interrupt Source Clear 7" "No effect,Cleared"
|
|
bitfld.long 0x00 6. " SRCCLEAR[6] ,Interrupt Source Clear 6" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SRCCLEAR[5] ,Interrupt Source Clear 5" "No effect,Cleared"
|
|
bitfld.long 0x00 4. " SRCCLEAR[4] ,Interrupt Source Clear 4" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SRCCLEAR[3] ,Interrupt Source Clear 3" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " SRCCLEAR[2] ,Interrupt Source Clear 2" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRCCLEAR[1] ,Interrupt Source Clear 1" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " SRCCLEAR[0] ,Interrupt Source Clear 0" "No effect,Cleared"
|
|
line.long 0x04 "SRCCLEAR1,Source Clear 1 Register"
|
|
bitfld.long 0x04 31. " SRCCLEAR[63] ,Interrupt Source Clear 63" "No effect,Cleared"
|
|
bitfld.long 0x04 30. " SRCCLEAR[62] ,Interrupt Source Clear 62" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SRCCLEAR[61] ,Interrupt Source Clear 61" "No effect,Cleared"
|
|
bitfld.long 0x04 28. " SRCCLEAR[60] ,Interrupt Source Clear 60" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 27. " SRCCLEAR[59] ,Interrupt Source Clear 59" "No effect,Cleared"
|
|
bitfld.long 0x04 26. " SRCCLEAR[58] ,Interrupt Source Clear 58" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SRCCLEAR[57] ,Interrupt Source Clear 57" "No effect,Cleared"
|
|
bitfld.long 0x04 24. " SRCCLEAR[56] ,Interrupt Source Clear 56" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 23. " SRCCLEAR[55] ,Interrupt Source Clear 55" "No effect,Cleared"
|
|
bitfld.long 0x04 22. " SRCCLEAR[54] ,Interrupt Source Clear 54" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SRCCLEAR[53] ,Interrupt Source Clear 53" "No effect,Cleared"
|
|
bitfld.long 0x04 20. " SRCCLEAR[52] ,Interrupt Source Clear 52" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SRCCLEAR[51] ,Interrupt Source Clear 51" "No effect,Cleared"
|
|
bitfld.long 0x04 18. " SRCCLEAR[50] ,Interrupt Source Clear 50" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 17. " SRCCLEAR[49] ,Interrupt Source Clear 49" "No effect,Cleared"
|
|
bitfld.long 0x04 16. " SRCCLEAR[48] ,Interrupt Source Clear 48" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SRCCLEAR[47] ,Interrupt Source Clear 47" "No effect,Cleared"
|
|
bitfld.long 0x04 14. " SRCCLEAR[46] ,Interrupt Source Clear 46" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SRCCLEAR[45] ,Interrupt Source Clear 45" "No effect,Cleared"
|
|
bitfld.long 0x04 12. " SRCCLEAR[44] ,Interrupt Source Clear 44" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SRCCLEAR[43] ,Interrupt Source Clear 43" "No effect,Cleared"
|
|
bitfld.long 0x04 10. " SRCCLEAR[42] ,Interrupt Source Clear 42" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SRCCLEAR[41] ,Interrupt Source Clear 41" "No effect,Cleared"
|
|
bitfld.long 0x04 8. " SRCCLEAR[40] ,Interrupt Source Clear 40" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SRCCLEAR[39] ,Interrupt Source Clear 39" "No effect,Cleared"
|
|
bitfld.long 0x04 6. " SRCCLEAR[38] ,Interrupt Source Clear 38" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SRCCLEAR[37] ,Interrupt Source Clear 37" "No effect,Cleared"
|
|
bitfld.long 0x04 4. " SRCCLEAR[36] ,Interrupt Source Clear 36" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SRCCLEAR[35] ,Interrupt Source Clear 35" "No effect,Cleared"
|
|
bitfld.long 0x04 2. " SRCCLEAR[34] ,Interrupt Source Clear 34" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SRCCLEAR[33] ,Interrupt Source Clear 33" "No effect,Cleared"
|
|
bitfld.long 0x04 0. " SRCCLEAR[32] ,Interrupt Source Clear 32" "No effect,Cleared"
|
|
line.long 0x08 "SRCCLEAR2,Source Clear 2 Register"
|
|
bitfld.long 0x08 31. " SRCCLEAR[95] ,Interrupt Source Clear 95" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " SRCCLEAR[94] ,Interrupt Source Clear 94" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 29. " SRCCLEAR[93] ,Interrupt Source Clear 93" "No effect,Cleared"
|
|
bitfld.long 0x08 28. " SRCCLEAR[92] ,Interrupt Source Clear 92" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 27. " SRCCLEAR[91] ,Interrupt Source Clear 91" "No effect,Cleared"
|
|
bitfld.long 0x08 26. " SRCCLEAR[90] ,Interrupt Source Clear 90" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SRCCLEAR[89] ,Interrupt Source Clear 89" "No effect,Cleared"
|
|
bitfld.long 0x08 24. " SRCCLEAR[88] ,Interrupt Source Clear 88" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 23. " SRCCLEAR[87] ,Interrupt Source Clear 87" "No effect,Cleared"
|
|
bitfld.long 0x08 22. " SRCCLEAR[86] ,Interrupt Source Clear 86" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SRCCLEAR[85] ,Interrupt Source Clear 85" "No effect,Cleared"
|
|
bitfld.long 0x08 20. " SRCCLEAR[84] ,Interrupt Source Clear 84" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SRCCLEAR[83] ,Interrupt Source Clear 83" "No effect,Cleared"
|
|
bitfld.long 0x08 18. " SRCCLEAR[82] ,Interrupt Source Clear 82" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " SRCCLEAR[81] ,Interrupt Source Clear 81" "No effect,Cleared"
|
|
bitfld.long 0x08 16. " SRCCLEAR[80] ,Interrupt Source Clear 80" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " SRCCLEAR[79] ,Interrupt Source Clear 79" "No effect,Cleared"
|
|
bitfld.long 0x08 14. " SRCCLEAR[78] ,Interrupt Source Clear 78" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SRCCLEAR[77] ,Interrupt Source Clear 77" "No effect,Cleared"
|
|
bitfld.long 0x08 12. " SRCCLEAR[76] ,Interrupt Source Clear 76" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SRCCLEAR[75] ,Interrupt Source Clear 75" "No effect,Cleared"
|
|
bitfld.long 0x08 10. " SRCCLEAR[74] ,Interrupt Source Clear 74" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SRCCLEAR[73] ,Interrupt Source Clear 73" "No effect,Cleared"
|
|
bitfld.long 0x08 8. " SRCCLEAR[72] ,Interrupt Source Clear 72" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SRCCLEAR[71] ,Interrupt Source Clear 71" "No effect,Cleared"
|
|
bitfld.long 0x08 6. " SRCCLEAR[70] ,Interrupt Source Clear 70" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SRCCLEAR[69] ,Interrupt Source Clear 69" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " SRCCLEAR[68] ,Interrupt Source Clear 68" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SRCCLEAR[67] ,Interrupt Source Clear 67" "No effect,Cleared"
|
|
bitfld.long 0x08 2. " SRCCLEAR[66] ,Interrupt Source Clear 66" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SRCCLEAR[65] ,Interrupt Source Clear 65" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " SRCCLEAR[64] ,Interrupt Source Clear 64" "No effect,Cleared"
|
|
line.long 0x0c "SRCCLEAR3,Source Clear 3 Register"
|
|
bitfld.long 0x0c 31. " SRCCLEAR[127] ,Interrupt Source Clear 127" "No effect,Cleared"
|
|
bitfld.long 0x0c 30. " SRCCLEAR[126] ,Interrupt Source Clear 126" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " SRCCLEAR[125] ,Interrupt Source Clear 125" "No effect,Cleared"
|
|
bitfld.long 0x0c 28. " SRCCLEAR[124] ,Interrupt Source Clear 124" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " SRCCLEAR[123] ,Interrupt Source Clear 123" "No effect,Cleared"
|
|
bitfld.long 0x0c 26. " SRCCLEAR[122] ,Interrupt Source Clear 122" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " SRCCLEAR[121] ,Interrupt Source Clear 121" "No effect,Cleared"
|
|
bitfld.long 0x0c 24. " SRCCLEAR[120] ,Interrupt Source Clear 120" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " SRCCLEAR[119] ,Interrupt Source Clear 119" "No effect,Cleared"
|
|
bitfld.long 0x0c 22. " SRCCLEAR[118] ,Interrupt Source Clear 118" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " SRCCLEAR[117] ,Interrupt Source Clear 117" "No effect,Cleared"
|
|
bitfld.long 0x0c 20. " SRCCLEAR[116] ,Interrupt Source Clear 116" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " SRCCLEAR[115] ,Interrupt Source Clear 115" "No effect,Cleared"
|
|
bitfld.long 0x0c 18. " SRCCLEAR[114] ,Interrupt Source Clear 114" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " SRCCLEAR[113] ,Interrupt Source Clear 113" "No effect,Cleared"
|
|
bitfld.long 0x0c 16. " SRCCLEAR[112] ,Interrupt Source Clear 112" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " SRCCLEAR[111] ,Interrupt Source Clear 111" "No effect,Cleared"
|
|
bitfld.long 0x0c 14. " SRCCLEAR[110] ,Interrupt Source Clear 110" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " SRCCLEAR[109] ,Interrupt Source Clear 109" "No effect,Cleared"
|
|
bitfld.long 0x0c 12. " SRCCLEAR[108] ,Interrupt Source Clear 108" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " SRCCLEAR[107] ,Interrupt Source Clear 107" "No effect,Cleared"
|
|
bitfld.long 0x0c 10. " SRCCLEAR[106] ,Interrupt Source Clear 106" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " SRCCLEAR[105] ,Interrupt Source Clear 105" "No effect,Cleared"
|
|
bitfld.long 0x0c 8. " SRCCLEAR[104] ,Interrupt Source Clear 104" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " SRCCLEAR[103] ,Interrupt Source Clear 103" "No effect,Cleared"
|
|
bitfld.long 0x0c 6. " SRCCLEAR[102] ,Interrupt Source Clear 102" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " SRCCLEAR[101] ,Interrupt Source Clear 101" "No effect,Cleared"
|
|
bitfld.long 0x0c 4. " SRCCLEAR[100] ,Interrupt Source Clear 100" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " SRCCLEAR[99] ,Interrupt Source Clear 99" "No effect,Cleared"
|
|
bitfld.long 0x0c 2. " SRCCLEAR[98] ,Interrupt Source Clear 98" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " SRCCLEAR[97] ,Interrupt Source Clear 97" "No effect,Cleared"
|
|
bitfld.long 0x0c 0. " SRCCLEAR[96] ,Interrupt Source Clear 96" "No effect,Cleared"
|
|
group.byte 0x400++0x7f
|
|
line.long 0x0 "PRIORITY0 ,Priority 0 Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRIO3 ,Interrupt Priority 3 "
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRIO2 ,Interrupt Priority 2 "
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRIO1 ,Interrupt Priority 1 "
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRIO0 ,Interrupt Priority 0 "
|
|
line.long 0x4 "PRIORITY1 ,Priority 1 Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRIO7 ,Interrupt Priority 7 "
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRIO6 ,Interrupt Priority 6 "
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRIO5 ,Interrupt Priority 5 "
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRIO4 ,Interrupt Priority 4 "
|
|
line.long 0x8 "PRIORITY2 ,Priority 2 Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRIO11 ,Interrupt Priority 11 "
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRIO10 ,Interrupt Priority 10 "
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRIO9 ,Interrupt Priority 9 "
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRIO8 ,Interrupt Priority 8 "
|
|
line.long 0xC "PRIORITY3 ,Priority 3 Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRIO15 ,Interrupt Priority 15 "
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRIO14 ,Interrupt Priority 14 "
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRIO13 ,Interrupt Priority 13 "
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRIO12 ,Interrupt Priority 12 "
|
|
line.long 0x10 "PRIORITY4 ,Priority 4 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRIO19 ,Interrupt Priority 19 "
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRIO18 ,Interrupt Priority 18 "
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRIO17 ,Interrupt Priority 17 "
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRIO16 ,Interrupt Priority 16 "
|
|
line.long 0x14 "PRIORITY5 ,Priority 5 Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRIO23 ,Interrupt Priority 23 "
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRIO22 ,Interrupt Priority 22 "
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRIO21 ,Interrupt Priority 21 "
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRIO20 ,Interrupt Priority 20 "
|
|
line.long 0x18 "PRIORITY6 ,Priority 6 Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRIO27 ,Interrupt Priority 27 "
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRIO26 ,Interrupt Priority 26 "
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRIO25 ,Interrupt Priority 25 "
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRIO24 ,Interrupt Priority 24 "
|
|
line.long 0x1C "PRIORITY7 ,Priority 7 Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRIO31 ,Interrupt Priority 31 "
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRIO30 ,Interrupt Priority 30 "
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRIO29 ,Interrupt Priority 29 "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRIO28 ,Interrupt Priority 28 "
|
|
line.long 0x20 "PRIORITY8 ,Priority 8 Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRIO35 ,Interrupt Priority 35 "
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRIO34 ,Interrupt Priority 34 "
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRIO33 ,Interrupt Priority 33 "
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRIO32 ,Interrupt Priority 32 "
|
|
line.long 0x24 "PRIORITY9 ,Priority 9 Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRIO39 ,Interrupt Priority 39 "
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRIO38 ,Interrupt Priority 38 "
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRIO37 ,Interrupt Priority 37 "
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRIO36 ,Interrupt Priority 36 "
|
|
line.long 0x28 "PRIORITY10,Priority 10 Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRIO43 ,Interrupt Priority 43 "
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRIO42 ,Interrupt Priority 42 "
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRIO41 ,Interrupt Priority 41 "
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRIO40 ,Interrupt Priority 40 "
|
|
line.long 0x2C "PRIORITY11,Priority 11 Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRIO47 ,Interrupt Priority 47 "
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRIO46 ,Interrupt Priority 46 "
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRIO45 ,Interrupt Priority 45 "
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRIO44 ,Interrupt Priority 44 "
|
|
line.long 0x30 "PRIORITY12,Priority 12 Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRIO51 ,Interrupt Priority 51 "
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRIO50 ,Interrupt Priority 50 "
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRIO49 ,Interrupt Priority 49 "
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRIO48 ,Interrupt Priority 48 "
|
|
line.long 0x34 "PRIORITY13,Priority 13 Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRIO55 ,Interrupt Priority 55 "
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRIO54 ,Interrupt Priority 54 "
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRIO53 ,Interrupt Priority 53 "
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRIO52 ,Interrupt Priority 52 "
|
|
line.long 0x38 "PRIORITY14,Priority 14 Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRIO59 ,Interrupt Priority 59 "
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRIO58 ,Interrupt Priority 58 "
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRIO57 ,Interrupt Priority 57 "
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRIO56 ,Interrupt Priority 56 "
|
|
line.long 0x3C "PRIORITY15,Priority 15 Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRIO63 ,Interrupt Priority 63 "
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRIO62 ,Interrupt Priority 62 "
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRIO61 ,Interrupt Priority 61 "
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRIO60 ,Interrupt Priority 60 "
|
|
line.long 0x40 "PRIORITY16,Priority 16 Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRIO67 ,Interrupt Priority 67 "
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRIO66 ,Interrupt Priority 66 "
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRIO65 ,Interrupt Priority 65 "
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRIO64 ,Interrupt Priority 64 "
|
|
line.long 0x44 "PRIORITY17,Priority 17 Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRIO71 ,Interrupt Priority 71 "
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRIO70 ,Interrupt Priority 70 "
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRIO69 ,Interrupt Priority 69 "
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRIO68 ,Interrupt Priority 68 "
|
|
line.long 0x48 "PRIORITY18,Priority 18 Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRIO75 ,Interrupt Priority 75 "
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRIO74 ,Interrupt Priority 74 "
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRIO73 ,Interrupt Priority 73 "
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRIO72 ,Interrupt Priority 72 "
|
|
line.long 0x4C "PRIORITY19,Priority 19 Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRIO79 ,Interrupt Priority 79 "
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRIO78 ,Interrupt Priority 78 "
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRIO77 ,Interrupt Priority 77 "
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRIO76 ,Interrupt Priority 76 "
|
|
line.long 0x50 "PRIORITY20,Priority 20 Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRIO83 ,Interrupt Priority 83 "
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRIO82 ,Interrupt Priority 82 "
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRIO81 ,Interrupt Priority 81 "
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRIO80 ,Interrupt Priority 80 "
|
|
line.long 0x54 "PRIORITY21,Priority 21 Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRIO87 ,Interrupt Priority 87 "
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRIO86 ,Interrupt Priority 86 "
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRIO85 ,Interrupt Priority 85 "
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRIO84 ,Interrupt Priority 84 "
|
|
line.long 0x58 "PRIORITY22,Priority 22 Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRIO91 ,Interrupt Priority 91 "
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRIO90 ,Interrupt Priority 90 "
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRIO89 ,Interrupt Priority 89 "
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRIO88 ,Interrupt Priority 88 "
|
|
line.long 0x5C "PRIORITY23,Priority 23 Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRIO95 ,Interrupt Priority 95 "
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRIO94 ,Interrupt Priority 94 "
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRIO93 ,Interrupt Priority 93 "
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRIO92 ,Interrupt Priority 92 "
|
|
line.long 0x60 "PRIORITY24,Priority 24 Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRIO99 ,Interrupt Priority 99 "
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRIO98 ,Interrupt Priority 98 "
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRIO97 ,Interrupt Priority 97 "
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRIO96 ,Interrupt Priority 96 "
|
|
line.long 0x64 "PRIORITY25,Priority 25 Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRIO103 ,Interrupt Priority 103"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRIO102 ,Interrupt Priority 102"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRIO101 ,Interrupt Priority 101"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRIO100 ,Interrupt Priority 100"
|
|
line.long 0x68 "PRIORITY26,Priority 26 Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRIO107 ,Interrupt Priority 107"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRIO106 ,Interrupt Priority 106"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRIO105 ,Interrupt Priority 105"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRIO104 ,Interrupt Priority 104"
|
|
line.long 0x6C "PRIORITY27,Priority 27 Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRIO111 ,Interrupt Priority 111"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRIO110 ,Interrupt Priority 110"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRIO109 ,Interrupt Priority 109"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRIO108 ,Interrupt Priority 108"
|
|
line.long 0x70 "PRIORITY28,Priority 28 Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRIO115 ,Interrupt Priority 115"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRIO114 ,Interrupt Priority 114"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRIO113 ,Interrupt Priority 113"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRIO112 ,Interrupt Priority 112"
|
|
line.long 0x74 "PRIORITY29,Priority 29 Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRIO119 ,Interrupt Priority 119"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRIO118 ,Interrupt Priority 118"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRIO117 ,Interrupt Priority 117"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRIO116 ,Interrupt Priority 116"
|
|
line.long 0x78 "PRIORITY30,Priority 30 Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRIO123 ,Interrupt Priority 123"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRIO122 ,Interrupt Priority 122"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRIO121 ,Interrupt Priority 121"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRIO120 ,Interrupt Priority 120"
|
|
line.long 0x7C "PRIORITY31,Priority 31 Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRIO127 ,Interrupt Priority 127"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRIO126 ,Interrupt Priority 126"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRIO125 ,Interrupt Priority 125"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRIO124 ,Interrupt Priority 124"
|
|
rgroup.long 0xd00++0xf
|
|
line.long 0x00 "PND0,Pending 0 Register"
|
|
bitfld.long 0x00 31. " PND[31] ,Interrupt Pending 31 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PND[30] ,Interrupt Pending 30 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " PND[29] ,Interrupt Pending 29 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PND[28] ,Interrupt Pending 28 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PND[27] ,Interrupt Pending 27 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PND[26] ,Interrupt Pending 26 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PND[25] ,Interrupt Pending 25 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PND[24] ,Interrupt Pending 24 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " PND[23] ,Interrupt Pending 23 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PND[22] ,Interrupt Pending 22 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " PND[21] ,Interrupt Pending 21 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PND[20] ,Interrupt Pending 20 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PND[19] ,Interrupt Pending 19 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PND[18] ,Interrupt Pending 18 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " PND[17] ,Interrupt Pending 17 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PND[16] ,Interrupt Pending 16 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " PND[15] ,Interrupt Pending 15 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PND[14] ,Interrupt Pending 14 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PND[13] ,Interrupt Pending 13 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PND[12] ,Interrupt Pending 12 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " PND[11] ,Interrupt Pending 11 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PND[10] ,Interrupt Pending 10 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " PND[9] ,Interrupt Pending 9 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PND[8] ,Interrupt Pending 8 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PND[7] ,Interrupt Pending 7 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PND[6] ,Interrupt Pending 6 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " PND[5] ,Interrupt Pending 5 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PND[4] ,Interrupt Pending 4 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " PND[3] ,Interrupt Pending 3 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PND[2] ,Interrupt Pending 2 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PND[1] ,Interrupt Pending 1 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " PND[0] ,Interrupt Pending 0 Status" "Not pending,Pending"
|
|
line.long 0x04 "PND1,Pending 1 Register"
|
|
bitfld.long 0x04 31. " PND[63] ,Interrupt Pending 63 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 30. " PND[62] ,Interrupt Pending 62 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 29. " PND[61] ,Interrupt Pending 61 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 28. " PND[60] ,Interrupt Pending 60 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 27. " PND[59] ,Interrupt Pending 59 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 26. " PND[58] ,Interrupt Pending 58 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 25. " PND[57] ,Interrupt Pending 57 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PND[56] ,Interrupt Pending 56 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 23. " PND[55] ,Interrupt Pending 55 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 22. " PND[54] ,Interrupt Pending 54 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 21. " PND[53] ,Interrupt Pending 53 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 20. " PND[52] ,Interrupt Pending 52 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PND[51] ,Interrupt Pending 51 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 18. " PND[50] ,Interrupt Pending 50 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 17. " PND[49] ,Interrupt Pending 49 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PND[48] ,Interrupt Pending 48 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 15. " PND[47] ,Interrupt Pending 47 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 14. " PND[46] ,Interrupt Pending 46 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PND[45] ,Interrupt Pending 45 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 12. " PND[44] ,Interrupt Pending 44 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 11. " PND[43] ,Interrupt Pending 43 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 10. " PND[42] ,Interrupt Pending 42 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 9. " PND[41] ,Interrupt Pending 41 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " PND[40] ,Interrupt Pending 40 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PND[39] ,Interrupt Pending 39 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " PND[38] ,Interrupt Pending 38 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 5. " PND[37] ,Interrupt Pending 37 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PND[36] ,Interrupt Pending 36 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 3. " PND[35] ,Interrupt Pending 35 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " PND[34] ,Interrupt Pending 34 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PND[33] ,Interrupt Pending 33 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " PND[32] ,Interrupt Pending 32 Status" "Not pending,Pending"
|
|
line.long 0x08 "PND2,Pending 2 Register"
|
|
bitfld.long 0x08 31. " PND[95] ,Interrupt Pending 95 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 30. " PND[94] ,Interrupt Pending 94 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 29. " PND[93] ,Interrupt Pending 93 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 28. " PND[92] ,Interrupt Pending 92 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 27. " PND[91] ,Interrupt Pending 91 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 26. " PND[90] ,Interrupt Pending 90 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 25. " PND[89] ,Interrupt Pending 89 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 24. " PND[88] ,Interrupt Pending 88 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 23. " PND[87] ,Interrupt Pending 87 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 22. " PND[86] ,Interrupt Pending 86 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 21. " PND[85] ,Interrupt Pending 85 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 20. " PND[84] ,Interrupt Pending 84 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PND[83] ,Interrupt Pending 83 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 18. " PND[82] ,Interrupt Pending 82 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 17. " PND[81] ,Interrupt Pending 81 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 16. " PND[80] ,Interrupt Pending 80 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 15. " PND[79] ,Interrupt Pending 79 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 14. " PND[78] ,Interrupt Pending 78 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 13. " PND[77] ,Interrupt Pending 77 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 12. " PND[76] ,Interrupt Pending 76 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 11. " PND[75] ,Interrupt Pending 75 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 10. " PND[74] ,Interrupt Pending 74 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 9. " PND[73] ,Interrupt Pending 73 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 8. " PND[72] ,Interrupt Pending 72 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 7. " PND[71] ,Interrupt Pending 71 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 6. " PND[70] ,Interrupt Pending 70 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 5. " PND[69] ,Interrupt Pending 69 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PND[68] ,Interrupt Pending 68 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 3. " PND[67] ,Interrupt Pending 67 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 2. " PND[66] ,Interrupt Pending 66 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PND[65] ,Interrupt Pending 65 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 0. " PND[64] ,Interrupt Pending 64 Status" "Not pending,Pending"
|
|
line.long 0x0c "PND3,Pending 3 Register"
|
|
bitfld.long 0x0c 31. " PND[127] ,Interrupt Pending 127 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 30. " PND[126] ,Interrupt Pending 126 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 29. " PND[125] ,Interrupt Pending 125 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " PND[124] ,Interrupt Pending 124 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 27. " PND[123] ,Interrupt Pending 123 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 26. " PND[122] ,Interrupt Pending 122 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " PND[121] ,Interrupt Pending 121 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 24. " PND[120] ,Interrupt Pending 120 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 23. " PND[119] ,Interrupt Pending 119 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " PND[118] ,Interrupt Pending 118 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 21. " PND[117] ,Interrupt Pending 117 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 20. " PND[116] ,Interrupt Pending 116 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " PND[115] ,Interrupt Pending 115 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 18. " PND[114] ,Interrupt Pending 114 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 17. " PND[113] ,Interrupt Pending 113 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " PND[112] ,Interrupt Pending 112 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 15. " PND[111] ,Interrupt Pending 111 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 14. " PND[110] ,Interrupt Pending 110 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " PND[109] ,Interrupt Pending 109 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 12. " PND[108] ,Interrupt Pending 108 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 11. " PND[107] ,Interrupt Pending 107 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " PND[106] ,Interrupt Pending 106 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 9. " PND[105] ,Interrupt Pending 105 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 8. " PND[104] ,Interrupt Pending 104 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " PND[103] ,Interrupt Pending 103 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 6. " PND[102] ,Interrupt Pending 102 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 5. " PND[101] ,Interrupt Pending 101 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " PND[100] ,Interrupt Pending 100 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 3. " PND[99] ,Interrupt Pending 99 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 2. " PND[98] ,Interrupt Pending 98 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " PND[97] ,Interrupt Pending 97 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 0. " PND[96] ,Interrupt Pending 96 Status" "Not pending,Pending"
|
|
rgroup.long 0xd80++0xf
|
|
line.long 0x00 "HIPND0,High Priority Pending 0 Register"
|
|
bitfld.long 0x00 31. " HIPND[31] ,High Priority Interrupt Pending 31 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " HIPND[30] ,High Priority Interrupt Pending 30 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " HIPND[29] ,High Priority Interrupt Pending 29 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " HIPND[28] ,High Priority Interrupt Pending 28 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HIPND[27] ,High Priority Interrupt Pending 27 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " HIPND[26] ,High Priority Interrupt Pending 26 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HIPND[25] ,High Priority Interrupt Pending 25 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " HIPND[24] ,High Priority Interrupt Pending 24 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HIPND[23] ,High Priority Interrupt Pending 23 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " HIPND[22] ,High Priority Interrupt Pending 22 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " HIPND[21] ,High Priority Interrupt Pending 21 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " HIPND[20] ,High Priority Interrupt Pending 20 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HIPND[19] ,High Priority Interrupt Pending 19 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " HIPND[18] ,High Priority Interrupt Pending 18 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HIPND[17] ,High Priority Interrupt Pending 17 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " HIPND[16] ,High Priority Interrupt Pending 16 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HIPND[15] ,High Priority Interrupt Pending 15 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " HIPND[14] ,High Priority Interrupt Pending 14 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HIPND[13] ,High Priority Interrupt Pending 13 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " HIPND[12] ,High Priority Interrupt Pending 12 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HIPND[11] ,High Priority Interrupt Pending 11 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HIPND[10] ,High Priority Interrupt Pending 10 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HIPND[9] ,High Priority Interrupt Pending 9 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " HIPND[8] ,High Priority Interrupt Pending 8 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPND[7] ,High Priority Interrupt Pending 7 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " HIPND[6] ,High Priority Interrupt Pending 6 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPND[5] ,High Priority Interrupt Pending 5 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " HIPND[4] ,High Priority Interrupt Pending 4 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HIPND[3] ,High Priority Interrupt Pending 3 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " HIPND[2] ,High Priority Interrupt Pending 2 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPND[1] ,High Priority Interrupt Pending 1 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HIPND[0] ,High Priority Interrupt Pending 0 Status" "Not pending,Pending"
|
|
line.long 0x04 "HIPND1,High Priority Pending 1 Register"
|
|
bitfld.long 0x04 31. " HIPND[63] ,High Priority Interrupt Pending 63 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 30. " HIPND[62] ,High Priority Interrupt Pending 62 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 29. " HIPND[61] ,High Priority Interrupt Pending 61 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 28. " HIPND[60] ,High Priority Interrupt Pending 60 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 27. " HIPND[59] ,High Priority Interrupt Pending 59 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 26. " HIPND[58] ,High Priority Interrupt Pending 58 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 25. " HIPND[57] ,High Priority Interrupt Pending 57 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " HIPND[56] ,High Priority Interrupt Pending 56 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 23. " HIPND[55] ,High Priority Interrupt Pending 55 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 22. " HIPND[54] ,High Priority Interrupt Pending 54 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 21. " HIPND[53] ,High Priority Interrupt Pending 53 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 20. " HIPND[52] ,High Priority Interrupt Pending 52 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 19. " HIPND[51] ,High Priority Interrupt Pending 51 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 18. " HIPND[50] ,High Priority Interrupt Pending 50 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HIPND[49] ,High Priority Interrupt Pending 49 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 16. " HIPND[48] ,High Priority Interrupt Pending 48 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 15. " HIPND[47] ,High Priority Interrupt Pending 47 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 14. " HIPND[46] ,High Priority Interrupt Pending 46 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 13. " HIPND[45] ,High Priority Interrupt Pending 45 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 12. " HIPND[44] ,High Priority Interrupt Pending 44 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 11. " HIPND[43] ,High Priority Interrupt Pending 43 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 10. " HIPND[42] ,High Priority Interrupt Pending 42 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 9. " HIPND[41] ,High Priority Interrupt Pending 41 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " HIPND[40] ,High Priority Interrupt Pending 40 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " HIPND[39] ,High Priority Interrupt Pending 39 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " HIPND[38] ,High Priority Interrupt Pending 38 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 5. " HIPND[37] ,High Priority Interrupt Pending 37 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " HIPND[36] ,High Priority Interrupt Pending 36 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HIPND[35] ,High Priority Interrupt Pending 35 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " HIPND[34] ,High Priority Interrupt Pending 34 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 1. " HIPND[33] ,High Priority Interrupt Pending 33 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " HIPND[32] ,High Priority Interrupt Pending 32 Status" "Not pending,Pending"
|
|
line.long 0x08 "HIPND2,High Priority Pending 2 Register"
|
|
bitfld.long 0x08 31. " HIPND[95] ,High Priority Interrupt Pending 95 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 30. " HIPND[94] ,High Priority Interrupt Pending 94 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 29. " HIPND[93] ,High Priority Interrupt Pending 93 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 28. " HIPND[92] ,High Priority Interrupt Pending 92 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HIPND[91] ,High Priority Interrupt Pending 91 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 26. " HIPND[90] ,High Priority Interrupt Pending 90 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HIPND[89] ,High Priority Interrupt Pending 89 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 24. " HIPND[88] ,High Priority Interrupt Pending 88 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HIPND[87] ,High Priority Interrupt Pending 87 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 22. " HIPND[86] ,High Priority Interrupt Pending 86 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIPND[85] ,High Priority Interrupt Pending 85 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 20. " HIPND[84] ,High Priority Interrupt Pending 84 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIPND[83] ,High Priority Interrupt Pending 83 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 18. " HIPND[82] ,High Priority Interrupt Pending 82 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 17. " HIPND[81] ,High Priority Interrupt Pending 81 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 16. " HIPND[80] ,High Priority Interrupt Pending 80 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIPND[79] ,High Priority Interrupt Pending 79 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 14. " HIPND[78] ,High Priority Interrupt Pending 78 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIPND[77] ,High Priority Interrupt Pending 77 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 12. " HIPND[76] ,High Priority Interrupt Pending 76 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIPND[75] ,High Priority Interrupt Pending 75 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 10. " HIPND[74] ,High Priority Interrupt Pending 74 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIPND[73] ,High Priority Interrupt Pending 73 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 8. " HIPND[72] ,High Priority Interrupt Pending 72 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIPND[71] ,High Priority Interrupt Pending 71 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 6. " HIPND[70] ,High Priority Interrupt Pending 70 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIPND[69] ,High Priority Interrupt Pending 69 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 4. " HIPND[68] ,High Priority Interrupt Pending 68 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIPND[67] ,High Priority Interrupt Pending 67 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 2. " HIPND[66] ,High Priority Interrupt Pending 66 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIPND[65] ,High Priority Interrupt Pending 65 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 0. " HIPND[64] ,High Priority Interrupt Pending 64 Status" "Not pending,Pending"
|
|
line.long 0x0c "HIPND3,High Priority Pending 3 Register"
|
|
bitfld.long 0x0c 31. " HIPND[127] ,High Priority Interrupt Pending 127 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 30. " HIPND[126] ,High Priority Interrupt Pending 126 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " HIPND[125] ,High Priority Interrupt Pending 125 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 28. " HIPND[124] ,High Priority Interrupt Pending 124 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " HIPND[123] ,High Priority Interrupt Pending 123 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 26. " HIPND[122] ,High Priority Interrupt Pending 122 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " HIPND[121] ,High Priority Interrupt Pending 121 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 24. " HIPND[120] ,High Priority Interrupt Pending 120 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " HIPND[119] ,High Priority Interrupt Pending 119 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 22. " HIPND[118] ,High Priority Interrupt Pending 118 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " HIPND[117] ,High Priority Interrupt Pending 117 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 20. " HIPND[116] ,High Priority Interrupt Pending 116 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " HIPND[115] ,High Priority Interrupt Pending 115 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 18. " HIPND[114] ,High Priority Interrupt Pending 114 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " HIPND[113] ,High Priority Interrupt Pending 113 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 16. " HIPND[112] ,High Priority Interrupt Pending 112 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " HIPND[111] ,High Priority Interrupt Pending 111 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 14. " HIPND[110] ,High Priority Interrupt Pending 110 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " HIPND[109] ,High Priority Interrupt Pending 109 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 12. " HIPND[108] ,High Priority Interrupt Pending 108 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " HIPND[107] ,High Priority Interrupt Pending 107 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 10. " HIPND[106] ,High Priority Interrupt Pending 106 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " HIPND[105] ,High Priority Interrupt Pending 105 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 8. " HIPND[104] ,High Priority Interrupt Pending 104 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " HIPND[103] ,High Priority Interrupt Pending 103 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 6. " HIPND[102] ,High Priority Interrupt Pending 102 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " HIPND[101] ,High Priority Interrupt Pending 101 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 4. " HIPND[100] ,High Priority Interrupt Pending 100 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " HIPND[99] ,High Priority Interrupt Pending 99 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 2. " HIPND[98] ,High Priority Interrupt Pending 98 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " HIPND[97] ,High Priority Interrupt Pending 97 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 0. " HIPND[96] ,High Priority Interrupt Pending 96 Status" "Not pending,Pending"
|
|
group.long 0xe00++0xf
|
|
line.long 0x00 "WAKEUP0,High Priority Pending 0 Register"
|
|
bitfld.long 0x00 31. " WAKEUP[31] ,Wakeup Configuration 31" "Not asserted,Asserted"
|
|
bitfld.long 0x00 30. " WAKEUP[30] ,Wakeup Configuration 30" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 29. " WAKEUP[29] ,Wakeup Configuration 29" "Not asserted,Asserted"
|
|
bitfld.long 0x00 28. " WAKEUP[28] ,Wakeup Configuration 28" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WAKEUP[27] ,Wakeup Configuration 27" "Not asserted,Asserted"
|
|
bitfld.long 0x00 26. " WAKEUP[26] ,Wakeup Configuration 26" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WAKEUP[25] ,Wakeup Configuration 25" "Not asserted,Asserted"
|
|
bitfld.long 0x00 24. " WAKEUP[24] ,Wakeup Configuration 24" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WAKEUP[23] ,Wakeup Configuration 23" "Not asserted,Asserted"
|
|
bitfld.long 0x00 22. " WAKEUP[22] ,Wakeup Configuration 22" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAKEUP[21] ,Wakeup Configuration 21" "Not asserted,Asserted"
|
|
bitfld.long 0x00 20. " WAKEUP[20] ,Wakeup Configuration 20" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WAKEUP[19] ,Wakeup Configuration 19" "Not asserted,Asserted"
|
|
bitfld.long 0x00 18. " WAKEUP[18] ,Wakeup Configuration 18" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " WAKEUP[17] ,Wakeup Configuration 17" "Not asserted,Asserted"
|
|
bitfld.long 0x00 16. " WAKEUP[16] ,Wakeup Configuration 16" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAKEUP[15] ,Wakeup Configuration 15" "Not asserted,Asserted"
|
|
bitfld.long 0x00 14. " WAKEUP[14] ,Wakeup Configuration 14" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAKEUP[13] ,Wakeup Configuration 13" "Not asserted,Asserted"
|
|
bitfld.long 0x00 12. " WAKEUP[12] ,Wakeup Configuration 12" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKEUP[11] ,Wakeup Configuration 11" "Not asserted,Asserted"
|
|
bitfld.long 0x00 10. " WAKEUP[10] ,Wakeup Configuration 10" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " WAKEUP[9] ,Wakeup Configuration 9" "Not asserted,Asserted"
|
|
bitfld.long 0x00 8. " WAKEUP[8] ,Wakeup Configuration 8" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WAKEUP[7] ,Wakeup Configuration 7" "Not asserted,Asserted"
|
|
bitfld.long 0x00 6. " WAKEUP[6] ,Wakeup Configuration 6" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WAKEUP[5] ,Wakeup Configuration 5" "Not asserted,Asserted"
|
|
bitfld.long 0x00 4. " WAKEUP[4] ,Wakeup Configuration 4" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKEUP[3] ,Wakeup Configuration 3" "Not asserted,Asserted"
|
|
bitfld.long 0x00 2. " WAKEUP[2] ,Wakeup Configuration 2" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WAKEUP[1] ,Wakeup Configuration 1" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " WAKEUP[0] ,Wakeup Configuration 0" "Not asserted,Asserted"
|
|
line.long 0x04 "WAKEUP1,High Priority Pending 1 Register"
|
|
bitfld.long 0x04 31. " WAKEUP[63] ,Wakeup Configuration 63" "Not asserted,Asserted"
|
|
bitfld.long 0x04 30. " WAKEUP[62] ,Wakeup Configuration 62" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 29. " WAKEUP[61] ,Wakeup Configuration 61" "Not asserted,Asserted"
|
|
bitfld.long 0x04 28. " WAKEUP[60] ,Wakeup Configuration 60" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 27. " WAKEUP[59] ,Wakeup Configuration 59" "Not asserted,Asserted"
|
|
bitfld.long 0x04 26. " WAKEUP[58] ,Wakeup Configuration 58" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 25. " WAKEUP[57] ,Wakeup Configuration 57" "Not asserted,Asserted"
|
|
bitfld.long 0x04 24. " WAKEUP[56] ,Wakeup Configuration 56" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 23. " WAKEUP[55] ,Wakeup Configuration 55" "Not asserted,Asserted"
|
|
bitfld.long 0x04 22. " WAKEUP[54] ,Wakeup Configuration 54" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAKEUP[53] ,Wakeup Configuration 53" "Not asserted,Asserted"
|
|
bitfld.long 0x04 20. " WAKEUP[52] ,Wakeup Configuration 52" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 19. " WAKEUP[51] ,Wakeup Configuration 51" "Not asserted,Asserted"
|
|
bitfld.long 0x04 18. " WAKEUP[50] ,Wakeup Configuration 50" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 17. " WAKEUP[49] ,Wakeup Configuration 49" "Not asserted,Asserted"
|
|
bitfld.long 0x04 16. " WAKEUP[48] ,Wakeup Configuration 48" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 15. " WAKEUP[47] ,Wakeup Configuration 47" "Not asserted,Asserted"
|
|
bitfld.long 0x04 14. " WAKEUP[46] ,Wakeup Configuration 46" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 13. " WAKEUP[45] ,Wakeup Configuration 45" "Not asserted,Asserted"
|
|
bitfld.long 0x04 12. " WAKEUP[44] ,Wakeup Configuration 44" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAKEUP[43] ,Wakeup Configuration 43" "Not asserted,Asserted"
|
|
bitfld.long 0x04 10. " WAKEUP[42] ,Wakeup Configuration 42" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAKEUP[41] ,Wakeup Configuration 41" "Not asserted,Asserted"
|
|
bitfld.long 0x04 8. " WAKEUP[40] ,Wakeup Configuration 40" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 7. " WAKEUP[39] ,Wakeup Configuration 39" "Not asserted,Asserted"
|
|
bitfld.long 0x04 6. " WAKEUP[38] ,Wakeup Configuration 38" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAKEUP[37] ,Wakeup Configuration 37" "Not asserted,Asserted"
|
|
bitfld.long 0x04 4. " WAKEUP[36] ,Wakeup Configuration 36" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAKEUP[35] ,Wakeup Configuration 35" "Not asserted,Asserted"
|
|
bitfld.long 0x04 2. " WAKEUP[34] ,Wakeup Configuration 34" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WAKEUP[33] ,Wakeup Configuration 33" "Not asserted,Asserted"
|
|
bitfld.long 0x04 0. " WAKEUP[32] ,Wakeup Configuration 32" "Not asserted,Asserted"
|
|
line.long 0x08 "WAKEUP2,High Priority Pending 2 Register"
|
|
bitfld.long 0x08 31. " WAKEUP[95] ,Wakeup Configuration 95" "Not asserted,Asserted"
|
|
bitfld.long 0x08 30. " WAKEUP[94] ,Wakeup Configuration 94" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 29. " WAKEUP[93] ,Wakeup Configuration 93" "Not asserted,Asserted"
|
|
bitfld.long 0x08 28. " WAKEUP[92] ,Wakeup Configuration 92" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 27. " WAKEUP[91] ,Wakeup Configuration 91" "Not asserted,Asserted"
|
|
bitfld.long 0x08 26. " WAKEUP[90] ,Wakeup Configuration 90" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 25. " WAKEUP[89] ,Wakeup Configuration 89" "Not asserted,Asserted"
|
|
bitfld.long 0x08 24. " WAKEUP[88] ,Wakeup Configuration 88" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 23. " WAKEUP[87] ,Wakeup Configuration 87" "Not asserted,Asserted"
|
|
bitfld.long 0x08 22. " WAKEUP[86] ,Wakeup Configuration 86" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 21. " WAKEUP[85] ,Wakeup Configuration 85" "Not asserted,Asserted"
|
|
bitfld.long 0x08 20. " WAKEUP[84] ,Wakeup Configuration 84" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 19. " WAKEUP[83] ,Wakeup Configuration 83" "Not asserted,Asserted"
|
|
bitfld.long 0x08 18. " WAKEUP[82] ,Wakeup Configuration 82" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 17. " WAKEUP[81] ,Wakeup Configuration 81" "Not asserted,Asserted"
|
|
bitfld.long 0x08 16. " WAKEUP[80] ,Wakeup Configuration 80" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " WAKEUP[79] ,Wakeup Configuration 79" "Not asserted,Asserted"
|
|
bitfld.long 0x08 14. " WAKEUP[78] ,Wakeup Configuration 78" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 13. " WAKEUP[77] ,Wakeup Configuration 77" "Not asserted,Asserted"
|
|
bitfld.long 0x08 12. " WAKEUP[76] ,Wakeup Configuration 76" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 11. " WAKEUP[75] ,Wakeup Configuration 75" "Not asserted,Asserted"
|
|
bitfld.long 0x08 10. " WAKEUP[74] ,Wakeup Configuration 74" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " WAKEUP[73] ,Wakeup Configuration 73" "Not asserted,Asserted"
|
|
bitfld.long 0x08 8. " WAKEUP[72] ,Wakeup Configuration 72" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 7. " WAKEUP[71] ,Wakeup Configuration 71" "Not asserted,Asserted"
|
|
bitfld.long 0x08 6. " WAKEUP[70] ,Wakeup Configuration 70" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 5. " WAKEUP[69] ,Wakeup Configuration 69" "Not asserted,Asserted"
|
|
bitfld.long 0x08 4. " WAKEUP[68] ,Wakeup Configuration 68" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAKEUP[67] ,Wakeup Configuration 67" "Not asserted,Asserted"
|
|
bitfld.long 0x08 2. " WAKEUP[66] ,Wakeup Configuration 66" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 1. " WAKEUP[65] ,Wakeup Configuration 65" "Not asserted,Asserted"
|
|
bitfld.long 0x08 0. " WAKEUP[64] ,Wakeup Configuration 64" "Not asserted,Asserted"
|
|
line.long 0x0c "WAKEUP3,High Priority Pending 3 Register"
|
|
bitfld.long 0x0c 31. " WAKEUP[127] ,Wakeup Configuration 127" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 30. " WAKEUP[126] ,Wakeup Configuration 126" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " WAKEUP[125] ,Wakeup Configuration 125" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 28. " WAKEUP[124] ,Wakeup Configuration 124" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " WAKEUP[123] ,Wakeup Configuration 123" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 26. " WAKEUP[122] ,Wakeup Configuration 122" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " WAKEUP[121] ,Wakeup Configuration 121" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 24. " WAKEUP[120] ,Wakeup Configuration 120" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " WAKEUP[119] ,Wakeup Configuration 119" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 22. " WAKEUP[118] ,Wakeup Configuration 118" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " WAKEUP[117] ,Wakeup Configuration 117" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 20. " WAKEUP[116] ,Wakeup Configuration 116" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " WAKEUP[115] ,Wakeup Configuration 115" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 18. " WAKEUP[114] ,Wakeup Configuration 114" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " WAKEUP[113] ,Wakeup Configuration 113" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 16. " WAKEUP[112] ,Wakeup Configuration 112" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " WAKEUP[111] ,Wakeup Configuration 111" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 14. " WAKEUP[110] ,Wakeup Configuration 110" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " WAKEUP[109] ,Wakeup Configuration 109" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 12. " WAKEUP[108] ,Wakeup Configuration 108" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " WAKEUP[107] ,Wakeup Configuration 107" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 10. " WAKEUP[106] ,Wakeup Configuration 106" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " WAKEUP[105] ,Wakeup Configuration 105" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 8. " WAKEUP[104] ,Wakeup Configuration 104" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " WAKEUP[103] ,Wakeup Configuration 103" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 6. " WAKEUP[102] ,Wakeup Configuration 102" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " WAKEUP[101] ,Wakeup Configuration 101" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 4. " WAKEUP[100] ,Wakeup Configuration 100" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " WAKEUP[99] ,Wakeup Configuration 99" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 2. " WAKEUP[98] ,Wakeup Configuration 98" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " WAKEUP[97] ,Wakeup Configuration 97" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 0. " WAKEUP[96] ,High Priority Interrupt Pending 96" "Not asserted,Asserted"
|
|
wgroup.long 0xf00++0x3
|
|
line.long 0x00 "SWINT,Software Interrupt Trigger Register"
|
|
bitfld.long 0x00 31. " INTNEG ,Interrupt Negate" "Not negated,Negated"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTID ,Interrupt ID"
|
|
width 0xB
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART1"
|
|
base ad:0x53fbc000
|
|
width 7.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "URXD,UART Receiver Register"
|
|
in
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x00 "UTXD,UART Transmitter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "UCR1,UART Control Register 1"
|
|
bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames"
|
|
bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent"
|
|
bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UCR2,UART Control Register 2"
|
|
bitfld.long 0x04 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored"
|
|
bitfld.long 0x04 13. " CTSC ,CTS Pin Control" "CTS,Receiver"
|
|
textline " "
|
|
bitfld.long 0x04 12. " CTS ,Clear to Send" "High,Low"
|
|
bitfld.long 0x04 11. " ESCEN ,Escape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PREN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PROE ,Parity Odd/Even" "Even,Odd"
|
|
bitfld.long 0x04 6. " STPB ,Number of stop bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WS ,Word Size" "7-bit,8-bit"
|
|
bitfld.long 0x04 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXEN ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RXEN ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SRST ,Software Reset" "Reset,No reset"
|
|
if (((per.long(ad:0x53fbc000+0x90))&0x40)==0x40)
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "DCDDELT interrupt disabled,DCDDELT interrupt enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "RIDELT interrupt disabled,RIDELT interrupt enabled"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "/DCD logic zero,/DCD logic one"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "/RI logic zero,/RI logic 1"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "UCR4,UART Control Register 4"
|
|
bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 9. " INVR ,Inverted Infrared Reception" "Active low,Active high"
|
|
bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "UFCR,UART FIFO Control Register"
|
|
bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "Div by 6,Div by 5,Div by 4,Div by 3,Div by 2,Div by 1,Div by 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE"
|
|
bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "USR1,UART Status Register 1"
|
|
eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low"
|
|
bitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed"
|
|
eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready"
|
|
eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active"
|
|
eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle"
|
|
eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected"
|
|
eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "USR2,UART Status Register 2"
|
|
eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received"
|
|
bitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty"
|
|
eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected"
|
|
eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished"
|
|
eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected"
|
|
eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed"
|
|
bitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected"
|
|
eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready"
|
|
group.long 0x9c++0x3
|
|
line.long 0x00 "UESC,UART Escape Character Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character"
|
|
group.long 0xa0++0x0b
|
|
line.long 0x00 "UTIM,UART Escape Timer Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer"
|
|
line.long 0x04 "UBIR,UART BRM Incremental Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Register"
|
|
line.long 0x08 "UBMR,Modulator Dominator"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator"
|
|
rgroup.long 0xac++0x3
|
|
line.long 0x00 "UBRC,UART Baud Rate Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ONEMS,UART One Millisecond Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "UTS,UART Test Register"
|
|
bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted"
|
|
bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop"
|
|
bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop"
|
|
bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented"
|
|
bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0x53fc0000
|
|
width 7.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "URXD,UART Receiver Register"
|
|
in
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x00 "UTXD,UART Transmitter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "UCR1,UART Control Register 1"
|
|
bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames"
|
|
bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent"
|
|
bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UCR2,UART Control Register 2"
|
|
bitfld.long 0x04 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored"
|
|
bitfld.long 0x04 13. " CTSC ,CTS Pin Control" "CTS,Receiver"
|
|
textline " "
|
|
bitfld.long 0x04 12. " CTS ,Clear to Send" "High,Low"
|
|
bitfld.long 0x04 11. " ESCEN ,Escape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PREN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PROE ,Parity Odd/Even" "Even,Odd"
|
|
bitfld.long 0x04 6. " STPB ,Number of stop bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WS ,Word Size" "7-bit,8-bit"
|
|
bitfld.long 0x04 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXEN ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RXEN ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SRST ,Software Reset" "Reset,No reset"
|
|
if (((per.long(ad:0x53fc0000+0x90))&0x40)==0x40)
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "DCDDELT interrupt disabled,DCDDELT interrupt enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "RIDELT interrupt disabled,RIDELT interrupt enabled"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "/DCD logic zero,/DCD logic one"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "/RI logic zero,/RI logic 1"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "UCR4,UART Control Register 4"
|
|
bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 9. " INVR ,Inverted Infrared Reception" "Active low,Active high"
|
|
bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "UFCR,UART FIFO Control Register"
|
|
bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "Div by 6,Div by 5,Div by 4,Div by 3,Div by 2,Div by 1,Div by 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE"
|
|
bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "USR1,UART Status Register 1"
|
|
eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low"
|
|
bitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed"
|
|
eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready"
|
|
eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active"
|
|
eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle"
|
|
eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected"
|
|
eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "USR2,UART Status Register 2"
|
|
eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received"
|
|
bitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty"
|
|
eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected"
|
|
eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished"
|
|
eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected"
|
|
eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed"
|
|
bitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected"
|
|
eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready"
|
|
group.long 0x9c++0x3
|
|
line.long 0x00 "UESC,UART Escape Character Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character"
|
|
group.long 0xa0++0x0b
|
|
line.long 0x00 "UTIM,UART Escape Timer Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer"
|
|
line.long 0x04 "UBIR,UART BRM Incremental Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Register"
|
|
line.long 0x08 "UBMR,Modulator Dominator"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator"
|
|
rgroup.long 0xac++0x3
|
|
line.long 0x00 "UBRC,UART Baud Rate Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ONEMS,UART One Millisecond Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "UTS,UART Test Register"
|
|
bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted"
|
|
bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop"
|
|
bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop"
|
|
bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented"
|
|
bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART3"
|
|
base ad:0x5000c000
|
|
width 7.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "URXD,UART Receiver Register"
|
|
in
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x00 "UTXD,UART Transmitter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "UCR1,UART Control Register 1"
|
|
bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames"
|
|
bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent"
|
|
bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UCR2,UART Control Register 2"
|
|
bitfld.long 0x04 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored"
|
|
bitfld.long 0x04 13. " CTSC ,CTS Pin Control" "CTS,Receiver"
|
|
textline " "
|
|
bitfld.long 0x04 12. " CTS ,Clear to Send" "High,Low"
|
|
bitfld.long 0x04 11. " ESCEN ,Escape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PREN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PROE ,Parity Odd/Even" "Even,Odd"
|
|
bitfld.long 0x04 6. " STPB ,Number of stop bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WS ,Word Size" "7-bit,8-bit"
|
|
bitfld.long 0x04 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXEN ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RXEN ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SRST ,Software Reset" "Reset,No reset"
|
|
if (((per.long(ad:0x5000c000+0x90))&0x40)==0x40)
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "DCDDELT interrupt disabled,DCDDELT interrupt enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "RIDELT interrupt disabled,RIDELT interrupt enabled"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "/DCD logic zero,/DCD logic one"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "/RI logic zero,/RI logic 1"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "UCR4,UART Control Register 4"
|
|
bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 9. " INVR ,Inverted Infrared Reception" "Active low,Active high"
|
|
bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "UFCR,UART FIFO Control Register"
|
|
bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "Div by 6,Div by 5,Div by 4,Div by 3,Div by 2,Div by 1,Div by 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE"
|
|
bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "USR1,UART Status Register 1"
|
|
eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low"
|
|
bitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed"
|
|
eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready"
|
|
eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active"
|
|
eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle"
|
|
eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected"
|
|
eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "USR2,UART Status Register 2"
|
|
eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received"
|
|
bitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty"
|
|
eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected"
|
|
eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished"
|
|
eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected"
|
|
eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed"
|
|
bitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected"
|
|
eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready"
|
|
group.long 0x9c++0x3
|
|
line.long 0x00 "UESC,UART Escape Character Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character"
|
|
group.long 0xa0++0x0b
|
|
line.long 0x00 "UTIM,UART Escape Timer Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer"
|
|
line.long 0x04 "UBIR,UART BRM Incremental Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Register"
|
|
line.long 0x08 "UBMR,Modulator Dominator"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator"
|
|
rgroup.long 0xac++0x3
|
|
line.long 0x00 "UBRC,UART Baud Rate Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ONEMS,UART One Millisecond Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "UTS,UART Test Register"
|
|
bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted"
|
|
bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop"
|
|
bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop"
|
|
bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented"
|
|
bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART4"
|
|
base ad:0x53ff0000
|
|
width 7.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "URXD,UART Receiver Register"
|
|
in
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x00 "UTXD,UART Transmitter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "UCR1,UART Control Register 1"
|
|
bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames"
|
|
bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent"
|
|
bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UCR2,UART Control Register 2"
|
|
bitfld.long 0x04 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored"
|
|
bitfld.long 0x04 13. " CTSC ,CTS Pin Control" "CTS,Receiver"
|
|
textline " "
|
|
bitfld.long 0x04 12. " CTS ,Clear to Send" "High,Low"
|
|
bitfld.long 0x04 11. " ESCEN ,Escape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PREN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PROE ,Parity Odd/Even" "Even,Odd"
|
|
bitfld.long 0x04 6. " STPB ,Number of stop bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WS ,Word Size" "7-bit,8-bit"
|
|
bitfld.long 0x04 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXEN ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RXEN ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SRST ,Software Reset" "Reset,No reset"
|
|
if (((per.long(ad:0x53ff0000+0x90))&0x40)==0x40)
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "DCDDELT interrupt disabled,DCDDELT interrupt enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "RIDELT interrupt disabled,RIDELT interrupt enabled"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "/DCD logic zero,/DCD logic one"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "/RI logic zero,/RI logic 1"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "UCR4,UART Control Register 4"
|
|
bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 9. " INVR ,Inverted Infrared Reception" "Active low,Active high"
|
|
bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "UFCR,UART FIFO Control Register"
|
|
bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "Div by 6,Div by 5,Div by 4,Div by 3,Div by 2,Div by 1,Div by 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE"
|
|
bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "USR1,UART Status Register 1"
|
|
eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low"
|
|
bitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed"
|
|
eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready"
|
|
eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active"
|
|
eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle"
|
|
eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected"
|
|
eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "USR2,UART Status Register 2"
|
|
eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received"
|
|
bitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty"
|
|
eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected"
|
|
eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished"
|
|
eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected"
|
|
eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed"
|
|
bitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected"
|
|
eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready"
|
|
group.long 0x9c++0x3
|
|
line.long 0x00 "UESC,UART Escape Character Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character"
|
|
group.long 0xa0++0x0b
|
|
line.long 0x00 "UTIM,UART Escape Timer Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer"
|
|
line.long 0x04 "UBIR,UART BRM Incremental Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Register"
|
|
line.long 0x08 "UBMR,Modulator Dominator"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator"
|
|
rgroup.long 0xac++0x3
|
|
line.long 0x00 "UBRC,UART Baud Rate Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ONEMS,UART One Millisecond Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "UTS,UART Test Register"
|
|
bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted"
|
|
bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop"
|
|
bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop"
|
|
bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented"
|
|
bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART5"
|
|
base ad:0x63f90000
|
|
width 7.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "URXD,UART Receiver Register"
|
|
in
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x00 "UTXD,UART Transmitter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "UCR1,UART Control Register 1"
|
|
bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames"
|
|
bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent"
|
|
bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UCR2,UART Control Register 2"
|
|
bitfld.long 0x04 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored"
|
|
bitfld.long 0x04 13. " CTSC ,CTS Pin Control" "CTS,Receiver"
|
|
textline " "
|
|
bitfld.long 0x04 12. " CTS ,Clear to Send" "High,Low"
|
|
bitfld.long 0x04 11. " ESCEN ,Escape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PREN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PROE ,Parity Odd/Even" "Even,Odd"
|
|
bitfld.long 0x04 6. " STPB ,Number of stop bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WS ,Word Size" "7-bit,8-bit"
|
|
bitfld.long 0x04 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXEN ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RXEN ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SRST ,Software Reset" "Reset,No reset"
|
|
if (((per.long(ad:0x63f90000+0x90))&0x40)==0x40)
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "DCDDELT interrupt disabled,DCDDELT interrupt enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "RIDELT interrupt disabled,RIDELT interrupt enabled"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "/DCD logic zero,/DCD logic one"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "/RI logic zero,/RI logic 1"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "UCR4,UART Control Register 4"
|
|
bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 9. " INVR ,Inverted Infrared Reception" "Active low,Active high"
|
|
bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "UFCR,UART FIFO Control Register"
|
|
bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "Div by 6,Div by 5,Div by 4,Div by 3,Div by 2,Div by 1,Div by 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE"
|
|
bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "USR1,UART Status Register 1"
|
|
eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low"
|
|
bitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed"
|
|
eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready"
|
|
eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active"
|
|
eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle"
|
|
eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected"
|
|
eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "USR2,UART Status Register 2"
|
|
eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received"
|
|
bitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty"
|
|
eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected"
|
|
eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished"
|
|
eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected"
|
|
eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed"
|
|
bitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected"
|
|
eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready"
|
|
group.long 0x9c++0x3
|
|
line.long 0x00 "UESC,UART Escape Character Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character"
|
|
group.long 0xa0++0x0b
|
|
line.long 0x00 "UTIM,UART Escape Timer Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer"
|
|
line.long 0x04 "UBIR,UART BRM Incremental Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Register"
|
|
line.long 0x08 "UBMR,Modulator Dominator"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator"
|
|
rgroup.long 0xac++0x3
|
|
line.long 0x00 "UBRC,UART Baud Rate Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ONEMS,UART One Millisecond Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "UTS,UART Test Register"
|
|
bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted"
|
|
bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop"
|
|
bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop"
|
|
bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented"
|
|
bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "USBOH1 (Universal Serial Bus Controller OTG HOST1)"
|
|
base ad:0x53FC4000
|
|
width 20.
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "USB_CTRL,USB Control Register"
|
|
rbitfld.long 0x00 31. " OWIR ,OTG wake-up interrupt request" "Not requested,Requested"
|
|
bitfld.long 0x00 27. " OWIE ,OTG wake-up interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " O_PWR_POL ,OTG power pin polarity" "Low active,High active"
|
|
rbitfld.long 0x00 15. " H1WIR ,Host1 wake-up interrupt request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 11. " H1WIE ,Host1 wake-up interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " H1_PWR_POL ,Host1 power pin polarity" "Low active,High active"
|
|
rgroup.byte 0x804++0x00
|
|
line.byte 0x00 "UTMI_CLK_VLD,UTMI PHY Output Clock Valid Register"
|
|
bitfld.byte 0x00 7. " O_UTMIPHYCLK ,OTG UTMI PHY Clock On Detection" "Not detected,Detected"
|
|
bitfld.byte 0x00 6. " H1_UTMIPHYCLK ,Host1 UTMI PHY Clock On Detection" "Not detected,Detected"
|
|
group.long 0x808++0x0F
|
|
line.long 0x00 "OTG_PHY_CTRL_0,OTH UTMI PHY Control 0 Register"
|
|
bitfld.long 0x00 31. " VLOAD ,Vendor Control Register Load Control" "Enabled,Disabled"
|
|
bitfld.long 0x00 27.--30. " VCONTROL ,UTMI PHY Vcontrol" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,141,5"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CONF2 ,OTG Comparators Active During Suspend" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CONF3 ,15kOhm Pull Down Resistor Connect" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 24. " CHGRDETEN ,Enable Charger Detector" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CHGRDETON ,Charger Detector Power On Control" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 15.--22. 0x1 " VSTATUS ,UTMI PHY Vendor Status"
|
|
bitfld.long 0x00 12. " SUSPENDM ,Suspend Mode (Only For Testing)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RESET ,UTMI PHY Force Reset (Only For Testing)" "No reset,Reset"
|
|
bitfld.long 0x00 9. " OTG_OVER_CUR_POL ,OTG Polarity of Overcurrent" "High active,Low active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OTG_OVER_CUR_DIS ,OTG Disable Overcurrent Detector" "No,Yes"
|
|
bitfld.long 0x00 6. " H1_OVER_CUR_POL ,Host1 polarity of overcurrent" "High active,Low active"
|
|
textline " "
|
|
bitfld.long 0x00 5. " H1_OVER_CUR_DIS ,Host1 disable overcurrent detector" "No,Yes"
|
|
rbitfld.long 0x00 2. " CHRGDET ,UTMI PHY chrgdet detector output" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHRGDET_INT_EN ,Charger detected interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CHRGDET_INT_FLG ,Charger detected interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x04 "OTG_PHY_CTRL_1,OTG UTMI PHY Control Register 1"
|
|
bitfld.long 0x04 31. " HSDRVTIMINGP ,HS driver timing control for PMOS" "2x,8x"
|
|
bitfld.long 0x04 29.--30. " HSDRVTIMINGN ,HS driver timing control for NMOS" "2x,4x,6x,8x"
|
|
textline " "
|
|
bitfld.long 0x04 27.--28. " HSDRVAMPLITUDE ,HS driver amplitude control" "I (I=17.78mA),I+2.5%,I+5%,I+7.5%"
|
|
bitfld.long 0x04 23.--26. " HSDRVSLOPE ,HS driver slope control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 21.--22. " HSDEDVSEL ,Reference voltage for high speed disconnect envelope detector" "556.8mV,568.4mV,580mV,591.6mV"
|
|
bitfld.long 0x04 19.--20. " HSTEDVSEL ,Reference voltage for high speed transmission envelope detector" "104.4mV,116mV,127.6mV,139.2mV"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " FSTUNEVSEL ,Reference voltage control for Calibration circuit" "533.6mV,545.2mV,556.8mV,568.4mV,580mV,591.6mV,603.2mV,614.8mV"
|
|
bitfld.long 0x04 14.--15. " ICPCTRL ,PLL charge pump current control" "Icp (Icp = 40uA),Icp*0.5,Icp*1.5,Icp*2"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " FSRFTSEL ,FS driver rise/fall time control" "Rise time-30%,Rise time,Rise time,Rise time+30%"
|
|
bitfld.long 0x04 10.--11. " LSRFTSEL ,LS driver rise/fall time control" "Rise time-30%,Rise time,Rise time,Rise time+30%"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " PREEMDEPTH/ENPRE ,HS driver pre-emphasis depth" "I (I=17.78mA),I+5%,I+10%,I+20%"
|
|
bitfld.long 0x04 7. " CALBP ,Enables calibration bypass for both dp and dn lines" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2.--6. " EXTCAL ,Controls calibration value externally" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--1. " PLLDIVVALUE ,Selects reference clock" "19.2Mhz,24Mhz,26Mhz,27Mhz"
|
|
line.long 0x08 "USB_CTRL_1,USB Control Register 1"
|
|
bitfld.long 0x08 11. " O_UTMI_ONCLK ,OTG Clock Clockout Enabled On Suspend" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " H1_UTMI_ONCLK ,Host 1 Clock Clockout Enabled On Suspend" "Disabled,Enabled"
|
|
line.long 0x0C "USB_CTRL_2,USB Control Register 2"
|
|
bitfld.long 0x0C 16. " OPMODE_OVERRIDE_EN ,OPMODE Override Enable" "No override,Override"
|
|
bitfld.long 0x0C 14.--15. " OPMODE_OVERRIDE ,OPMODE Override Value" "Normal,Non-driving,Bit-stuffing and NRZI encoding disabled,Normal without SYNC and EOP"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " OVBWK_EN ,OTG VBUS Wakeup Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " OIDWK_EN ,OTG ID Wakeup Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x81C++0x0B
|
|
line.long 0x00 "UH1_PHY_CTRL_0,Host1 UTMI PHY Control 0 Register"
|
|
bitfld.long 0x00 31. " VLOAD ,Vendor Control Register Load Control" "Loaded,Inactive"
|
|
bitfld.long 0x00 27.--30. " VCONTROL ,UTMI PHY Vcontrol" "0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CONF2 ,OTG Comparators Active During Suspend" "Inactive,Active"
|
|
bitfld.long 0x00 25. " CONF3 ,15kOhm Pull Down Resistor Connect" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 24. " CHGRDETEN ,Enable Charger Detector" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CHGRDETON ,Charger Detector Power On Control" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 15.--22. 0x1 " VSTATUS ,UTMI PHY Vendor Status"
|
|
bitfld.long 0x00 12. " SUSPENDM ,Suspend Mode (Only For Testing)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RESET ,UTMI PHY Force Reset (Only For Testing)" "Inactive,Reset"
|
|
rbitfld.long 0x00 2. " CHRGDET ,UTMI PHY chrgdet detector output" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHRGDET_INT_EN ,Charger detected interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CHRGDET_INT_FLG ,Charger detected interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x04 "UH1_PHY_CTRL_1,Host1 UTMI PHY Control Register 1"
|
|
bitfld.long 0x04 31. " HSDRVTIMINGP ,HS driver timing control for PMOS" "2x,8x"
|
|
bitfld.long 0x04 29.--30. " HSDRVTIMINGN ,HS driver timing control for NMOS" "2x,4x,6x,8x"
|
|
textline " "
|
|
bitfld.long 0x04 27.--28. " HSDRVAMPLITUDE ,HS driver amplitude control" "I (I=17.78mA),I+2.5%,I+5%,I+7.5%"
|
|
bitfld.long 0x04 23.--26. " HSDRVSLOPE ,HS driver slope control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 21.--22. " HSDEDVSEL ,Reference voltage for high speed disconnect envelope detector" "556.8mV,568.4mV,580mV,591.6mV"
|
|
bitfld.long 0x04 19.--20. " HSTEDVSEL ,Reference voltage for high speed transmission envelope detector" "104.4mV,116mV,127.6mV,139.2mV"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " FSTUNEVSEL ,Reference voltage control for Calibration circuit" "533.6mV,545.2mV,556.8mV,568.4mV,580mV,591.6mV,603.2mV,614.8mV"
|
|
bitfld.long 0x04 14.--15. " ICPCTRL ,PLL charge pump current control" "Icp (Icp = 40uA),Icp*0.5,Icp*1.5,Icp*2"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " FSRFTSEL ,FS driver rise/fall time control" "Rise time-30%,Rise time,Rise time,Rise time+30%"
|
|
bitfld.long 0x04 10.--11. " LSRFTSEL ,LS driver rise/fall time control" "Rise time-30%,Rise time,Rise time,Rise time+30%"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " PREEMDEPTH/ENPRE ,HS driver pre-emphasis depth" "I (I=17.78mA),I+5%,I+10%,I+20%"
|
|
bitfld.long 0x04 7. " CALBP ,Enables calibration bypass for both dp and dn lines" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2.--6. " EXTCAL ,Controlsk calibration value externally" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--1. " PLLDIVVALUE ,Selects reference clock" "19.2Mhz,24Mhz,26Mhz,27Mhz"
|
|
line.long 0x08 "USB_CLKONOFF_CTRL,USB Clock On/Off Control Register"
|
|
bitfld.long 0x08 18. " H1_AHBCLK_OFF ,Enable/disable the AHB clock for host1" "Enabled,Disabled"
|
|
bitfld.long 0x08 17. " OTG_AHBCLK_OFF ,Enable/disable the AHB clock for OTG" "Enabled,Disabled"
|
|
base ad:0x53F80000
|
|
tree "OTG"
|
|
width 22.
|
|
rgroup.long (0x00+0x0)++0x17
|
|
line.long 0x00 "UOG_ID,Identification Register"
|
|
line.long 0x04 "UOG_HWGENERAL,General Hardware Register"
|
|
hexmask.long.word 0x04 0.--11. 0x1 " HWGENERAL ,HWGENERAL (Should read 0x835)"
|
|
line.long 0x08 "UOG_HWHOST,Host Hardware Parameters Register"
|
|
hexmask.long.byte 0x08 24.--31. 0x1 " TTPER ,VUSB_HS_TT_PERIODIC_CONTEXTS"
|
|
hexmask.long.byte 0x08 16.--23. 0x1 " TTASY ,VUSB_HS_TT_ASYNC_CONTEXTS"
|
|
textline " "
|
|
bitfld.long 0x08 1.--3. " NPORT ,Number of downstream ports (NPORT+1)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0. " HC ,Host capable" "Not supported,Supported"
|
|
line.long 0x0c "UOG_HWDEVICE,Device Hardware Parameters Register"
|
|
hexmask.long.byte 0x0c 1.--5. 1. " DEVEP ,Device endpoint number"
|
|
bitfld.long 0x0c 0. " DC ,Device capable" "Not supported,Supported"
|
|
line.long 0x10 "UOG_HWTXBUF,TX Buffer Hardware Parameters Register"
|
|
bitfld.long 0x10 31. " TXCLR ,VUSB_HS_TX_LOCAL_CONTEXT_REGISTERS" "0,1"
|
|
hexmask.long.byte 0x10 16.--23. 1. " TXCHANADD ,TX buffer size is (2^TXCHANADD)*4 bytes"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " TXADD ,VUSB_HS_TX_ADD"
|
|
hexmask.long.byte 0x10 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer"
|
|
line.long 0x14 "UOG_HWRXBUF,RX Buffer Hardware Parameters Register"
|
|
hexmask.long.byte 0x14 8.--15. 1. " RXADD ,RX buffer size is (2^RXADD)*4 bytes"
|
|
hexmask.long.byte 0x14 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer"
|
|
group.long (0x80+0x0)++0x13
|
|
line.long 0x00 "UOG_GPTIMER0LD,General Purpose Timer #0 Load"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General purpose timer load value"
|
|
line.long 0x04 "UOG_GPTIMER0CTRL,General Purpose Timer #0 Controller"
|
|
bitfld.long 0x04 31. " GPTRUN ,General purpose timer run enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " GPTRST ,General purpose timer reset (load counter value from GPTLD)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 24. " GPTMODE ,General purpose timer mode" "One shot,Repeat"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General purpose timer counter"
|
|
line.long 0x08 "UOG_GPTIMER1LD,General Purpose Timer #1 Load"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General purpose timer load value"
|
|
line.long 0x0C "UOG_GPTIMER1CTRL,General Purpose Timer #1 Controller"
|
|
bitfld.long 0x0C 31. " GPTRUN ,General purpose timer run enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " GPTRST ,General purpose timer reset (load counter value from GPTLD)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " GPTMODE ,General purpose timer mode" "One shot,Repeat"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General purpose timer counter"
|
|
line.long 0x10 "UOG_SBUSCFG,System Bus Config"
|
|
bitfld.long 0x10 0.--2. " AHBBRST ,AHB master interface Burst configuration (IB_UL = incremental burst of unspecified length; ST = single transfer)" "IB_UL,INCR4 -> ST,INCR8 -> INCR4 -> ST,INCR16 -> INCR8 -> INCR4 -> ST,Reserved,INCR4 -> IB_UL,INCR8 -> INCR4 -> IB_UL,INCR16 -> INCR8 -> INCR4 -> IB_UL"
|
|
rgroup.byte (0x100+0x0)++0x00
|
|
line.byte 0x00 "UOG_CAPLENGTH,Capability Register Length"
|
|
rgroup.word (0x102+0x0)++0x01
|
|
line.word 0x00 "UOG_HCIVERSION,Host Controller Interface Version Register"
|
|
rgroup.long (0x104+0x0)++0x07
|
|
line.long 0x00 "UOG_HCSPARAMS,Host Controller Structural Parameters Register"
|
|
bitfld.long 0x00 24.--27. " N_TT[3:0] ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " N_PTT[3:0] ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PI ,Port Indicators" "0,1"
|
|
bitfld.long 0x00 12.--15. " N_CC[3:0] ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " N_PCC[3:0] ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "UOG_HCCPARAMS,Host Controller Capability Parameters Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP[7:0] ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x04 4.--7. " IST[7:4] ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Disabled,Enabled"
|
|
rgroup.word (0x120+0x0)++0x1
|
|
line.word 0x00 "UOG_DCIVERSION,Device Controller Interface Version Register"
|
|
rgroup.long (0x124+0x0)++0x3
|
|
line.long 0x00 "UOG_DCCPARAMS,Device Control Capability Parameters Register"
|
|
bitfld.long 0x00 8. " HC ,Host Capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DC ,Device Capable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
width 22.
|
|
if ((data.long(0x0+ad:0x53F80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x140+0x0)++0x3
|
|
line.long 0x00 "UOG_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size 1" "1024,512,256,128,64,32,16,8"
|
|
bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
group.long (0x144+0x0)++0x3
|
|
line.long 0x00 "UOG_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
bitfld.long 0x00 3. " FRI ,Frame List Rollover" "Not rollover,Rollover"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
elif ((data.long(0x0+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x140+0x0)++0x3
|
|
line.long 0x00 "UOG_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ATDTW ,Add dTD TripWire" "Cleared,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
group.long (0x144+0x0)++0x3
|
|
line.long 0x00 "UOG_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended"
|
|
eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset"
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x140+0x0)++0x3
|
|
line.long 0x00 "UOG_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
group.long (0x144+0x0)++0x3
|
|
line.long 0x00 "UOG_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
if ((data.long(0x0+ad:0x53F80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x148+0x0)++0x3
|
|
line.long 0x00 "UOG_USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SRE ,SOF Received Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRE ,Frame List Rollover Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port Change Detect Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
elif ((data.long(0x0+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x148+0x0)++0x3
|
|
line.long 0x00 "UOG_USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLE ,Sleep interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SRE ,SOF Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " URE ,USB Reset Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCE ,Port Change Detect Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long (0x148+0x0)++0x3
|
|
line.long 0x00 "UOG_USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port Change Detect Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14C+0x0)++0x03
|
|
line.long 0x00 "UOG_FRINDEX,USB Frame Index Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame Index"
|
|
if ((data.long(0x0+ad:0x53F80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x154+0x0)++0x03
|
|
line.long 0x00 "UOG_PERIODICLISTBASE,Host Controller Frame List Base Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base Address (Low)"
|
|
elif ((data.long(0x0+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x154+0x0)++0x03
|
|
line.long 0x00 "UOG_DEVICEADDR,Device Controller USB Device Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 0x2 " USBADR ,Device Address"
|
|
else
|
|
hgroup.long (0x154+0x0)++0x03
|
|
hide.long 0x00 "UOG_PERIODICLISTBASE,Device Controller USB Device Address Register"
|
|
endif
|
|
if ((data.long(0x0+ad:0x53F80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x158+0x0)++0x03
|
|
line.long 0x00 "UOG_ASYNCLISTADDR,Host Controller Next Asynch Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low"
|
|
elif ((data.long(0x0+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x158+0x0)++0x03
|
|
line.long 0x00 "UOG_ASYNCLISTADDR,Device Controller Endpoint List Address Register"
|
|
hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE[31:11] ,Device Controller Endpoint List Address"
|
|
else
|
|
hgroup.long (0x158+0x0)++0x03
|
|
hide.long 0x00 "UOG_ASYNCLISTADDR,Device Controller Endpoint List Address Register"
|
|
endif
|
|
group.long (0x160+0x0)++0x7
|
|
line.long 0x00 "UOG_BURSTSIZE,Host Controller Embedded TT Async Buffer Status Register"
|
|
hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX Burst Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Size"
|
|
line.long 0x04 "UOG_TXFILLTUNING,TX FIFO Fill Tuning Register"
|
|
hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold"
|
|
bitfld.long 0x04 13.--15. " TXSCHEALTH ,Scheduler Health Counter" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler Overhead"
|
|
width 22.
|
|
group.long (0x16C+0x0)++0x03
|
|
line.long 0x00 "UOG_IC_USB,IC_USB Enable"
|
|
bitfld.long 0x00 31. " IC8 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " IC_VDD8 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " IC7 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " IC_VDD7 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " IC6 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " IC_VDD6 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " IC5 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " IC_VDD5 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " IC4 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " IC_VDD4 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " IC3 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " IC_VDD3 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " IC2 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " IC_VDD2 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " IC1 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " IC_VDD1 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
group.long (0x170+0x0)++0x03
|
|
line.long 0x00 "UOG_ULPIVIEW,ULPI Vieport Register"
|
|
bitfld.long 0x00 31. " ULPIWU ,ULPI Wakeup" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "No effect,Read/write"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write"
|
|
bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Not normal,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,ULPI Data Write"
|
|
width 22.
|
|
if ((data.long(0x0+ad:0x53F80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x184+0x0)++0x03
|
|
line.long 0x00 "UOG_PORTSC1,Port 1 Status and Control Register"
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,Reserved,ULPI,Serial"
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device"
|
|
elif ((data.long(0x0+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x184+0x0)++0x03
|
|
line.long 0x00 "UOG_PORTSC1,Port 1 Status and Control Register"
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,Reserved,ULPI,Serial"
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not attached,Attached"
|
|
else
|
|
hgroup.long (0x184+0x0)++0x03
|
|
hide.long 0x00 "UOG_PORTSC1,Port 1 Status and Control Register"
|
|
endif
|
|
group.long 0x1a4++0x03
|
|
line.long 0x00 "UOG_OTGSC,OTG Status Control Register"
|
|
bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " 1MSE ,1 Milisecond Timer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " 1MSS ,1 Milisecond Timer Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " 1MST ,1 Milisecond Timer Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BSE ,B Session End" "Not ended,Ended"
|
|
bitfld.long 0x00 11. " BSV ,B Session Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASV ,A Session Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " AVV ,A VBus Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ID ,USB ID" "A device,B device"
|
|
bitfld.long 0x00 5. " IDPU ,ID Pullup" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DP ,Data Pulsing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VD ,VBUS Discharge" "Not discharged,Discharged"
|
|
group.long (0x1a8+0x0)++0x03
|
|
line.long 0x00 "UOG_USBMODE,USB Device Mode Register"
|
|
bitfld.long 0x00 15. " SRT ,Shorten Reset Time" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CM[1:0] ,Controller Mode" "Idle,Reserved,Device,Host"
|
|
width 22.
|
|
if ((data.long(0x0+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long 0x1ac++0x0b
|
|
line.long 0x00 "UOG_ENDPTSETUPSTAT,Endpoint Setup Status Register"
|
|
bitfld.long 0x00 15. " ENDPTSETUPSTAT[15] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 14. " ENDPTSETUPSTAT[14] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ENDPTSETUPSTAT[13] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 12. " ENDPTSETUPSTAT[12] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENDPTSETUPSTAT[11] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 10. " ENDPTSETUPSTAT[10] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ENDPTSETUPSTAT[09] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 8. " ENDPTSETUPSTAT[08] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENDPTSETUPSTAT[07] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 6. " ENDPTSETUPSTAT[06] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENDPTSETUPSTAT[05] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 4. " ENDPTSETUPSTAT[04] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENDPTSETUPSTAT[03] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 2. " ENDPTSETUPSTAT[02] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENDPTSETUPSTAT[01] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 0. " ENDPTSETUPSTAT[00] ,Setup Endpoint Status" "Not received,Received"
|
|
line.long 0x04 "UOG_ENDPTPRIME,Endpoint Initialization Register"
|
|
bitfld.long 0x04 23. " PETB7 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 22. " PETB6 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 21. " PETB5 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 20. " PETB4 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PETB3 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 18. " PETB2 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PETB1 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 16. " PETB0 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PERB7 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 6. " PERB6 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PERB5 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 4. " PERB4 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PERB3 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 2. " PERB2 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PERB1 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 0. " PERB0 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
line.long 0x08 "UOG_ENDPTFLUSH,Endpoint De-Initialize Register"
|
|
bitfld.long 0x08 23. " FETB7 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 22. " FETB6 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 21. " FETB5 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 20. " FETB4 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 19. " FETB3 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 18. " FETB2 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 17. " FETB1 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 16. " FETB0 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 7. " FERB7 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 6. " FERB6 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 5. " FERB5 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 4. " FERB4 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " FERB3 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 2. " FERB2 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 1. " FERB1 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 0. " FERB0 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
rgroup.long 0x1b8++0x03
|
|
line.long 0x00 "UOG_ENDPTSTAT,Endpoint Status Register"
|
|
bitfld.long 0x00 23. " ETBR7 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 22. " ETBR6 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ETBR5 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " ETBR4 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETBR3 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 18. " ETBR2 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ETBR1 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " ETBR0 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERBR7 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 6. " ERBR6 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ERBR5 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " ERBR4 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERBR3 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ERBR2 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ERBR1 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ERBR0 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
group.long 0x1bc++0x03
|
|
line.long 0x00 "UOG_ENDPTCOMPLETE,Endpoint Compete Register"
|
|
bitfld.long 0x00 23. " ETCE7 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " ETCE6 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ETCE5 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " ETCE4 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETCE3 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " ETCE2 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ETCE1 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " ETCE0 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERCE7 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " ERCE6 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ERCE5 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " ERCE4 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERCE3 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " ERCE2 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ERCE1 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ERCE0 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
else
|
|
hgroup.long 0x1ac++0x13
|
|
hide.long 0x00 "UOG_ENDPTSETUPSTAT,Endpoint Setup Status Register"
|
|
hide.long 0x04 "UOG_ENDPTPRIME,Endpoint Initialization Register"
|
|
hide.long 0x08 "UOG_ENDPTFLUSH,Endpoint De-Initialize Register"
|
|
hide.long 0x0c "UOG_ENDPTSTAT,Endpoint Status Register"
|
|
hide.long 0x10 "UOG_ENDPTCOMPLETE,Endpoint Compete Register"
|
|
endif
|
|
width 16.
|
|
group.long 0x1c0++0x03
|
|
line.long 0x00 "UOG_ENDPTCTRL0,Endpoint Control 0 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,?..."
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,?..."
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "UOG_ENDPTCTRL1,Endpoint Control 1 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "UOG_ENDPTCTRL2,Endpoint Control 2 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UOG_ENDPTCTRL3,Endpoint Control 3 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "UOG_ENDPTCTRL4,Endpoint Control 4 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "UOG_ENDPTCTRL5,Endpoint Control 5 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "UOG_ENDPTCTRL6,Endpoint Control 6 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "UOG_ENDPTCTRL7,Endpoint Control 7 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Host 1"
|
|
width 22.
|
|
rgroup.long (0x00+0x200)++0x17
|
|
line.long 0x00 "UH1_ID,Identification Register"
|
|
line.long 0x04 "UH1_HWGENERAL,General Hardware Register"
|
|
hexmask.long.word 0x04 0.--11. 0x1 " HWGENERAL ,HWGENERAL (Should read 0x835)"
|
|
line.long 0x08 "UH1_HWHOST,Host Hardware Parameters Register"
|
|
hexmask.long.byte 0x08 24.--31. 0x1 " TTPER ,VUSB_HS_TT_PERIODIC_CONTEXTS"
|
|
hexmask.long.byte 0x08 16.--23. 0x1 " TTASY ,VUSB_HS_TT_ASYNC_CONTEXTS"
|
|
textline " "
|
|
bitfld.long 0x08 1.--3. " NPORT ,Number of downstream ports (NPORT+1)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0. " HC ,Host capable" "Not supported,Supported"
|
|
line.long 0x0c "UH1_HWDEVICE,Device Hardware Parameters Register"
|
|
hexmask.long.byte 0x0c 1.--5. 1. " DEVEP ,Device endpoint number"
|
|
bitfld.long 0x0c 0. " DC ,Device capable" "Not supported,Supported"
|
|
line.long 0x10 "UH1_HWTXBUF,TX Buffer Hardware Parameters Register"
|
|
bitfld.long 0x10 31. " TXCLR ,VUSB_HS_TX_LOCAL_CONTEXT_REGISTERS" "0,1"
|
|
hexmask.long.byte 0x10 16.--23. 1. " TXCHANADD ,TX buffer size is (2^TXCHANADD)*4 bytes"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " TXADD ,VUSB_HS_TX_ADD"
|
|
hexmask.long.byte 0x10 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer"
|
|
line.long 0x14 "UH1_HWRXBUF,RX Buffer Hardware Parameters Register"
|
|
hexmask.long.byte 0x14 8.--15. 1. " RXADD ,RX buffer size is (2^RXADD)*4 bytes"
|
|
hexmask.long.byte 0x14 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer"
|
|
group.long (0x80+0x200)++0x13
|
|
line.long 0x00 "UH1_GPTIMER0LD,General Purpose Timer #0 Load"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General purpose timer load value"
|
|
line.long 0x04 "UH1_GPTIMER0CTRL,General Purpose Timer #0 Controller"
|
|
bitfld.long 0x04 31. " GPTRUN ,General purpose timer run enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " GPTRST ,General purpose timer reset (load counter value from GPTLD)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 24. " GPTMODE ,General purpose timer mode" "One shot,Repeat"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General purpose timer counter"
|
|
line.long 0x08 "UH1_GPTIMER1LD,General Purpose Timer #1 Load"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General purpose timer load value"
|
|
line.long 0x0C "UH1_GPTIMER1CTRL,General Purpose Timer #1 Controller"
|
|
bitfld.long 0x0C 31. " GPTRUN ,General purpose timer run enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " GPTRST ,General purpose timer reset (load counter value from GPTLD)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " GPTMODE ,General purpose timer mode" "One shot,Repeat"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General purpose timer counter"
|
|
line.long 0x10 "UH1_SBUSCFG,System Bus Config"
|
|
bitfld.long 0x10 0.--2. " AHBBRST ,AHB master interface Burst configuration (IB_UL = incremental burst of unspecified length; ST = single transfer)" "IB_UL,INCR4 -> ST,INCR8 -> INCR4 -> ST,INCR16 -> INCR8 -> INCR4 -> ST,Reserved,INCR4 -> IB_UL,INCR8 -> INCR4 -> IB_UL,INCR16 -> INCR8 -> INCR4 -> IB_UL"
|
|
rgroup.byte (0x100+0x200)++0x00
|
|
line.byte 0x00 "UH1_CAPLENGTH,Capability Register Length"
|
|
rgroup.word (0x102+0x200)++0x01
|
|
line.word 0x00 "UH1_HCIVERSION,Host Controller Interface Version Register"
|
|
rgroup.long (0x104+0x200)++0x07
|
|
line.long 0x00 "UH1_HCSPARAMS,Host Controller Structural Parameters Register"
|
|
bitfld.long 0x00 24.--27. " N_TT[3:0] ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " N_PTT[3:0] ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PI ,Port Indicators" "0,1"
|
|
bitfld.long 0x00 12.--15. " N_CC[3:0] ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " N_PCC[3:0] ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "UH1_HCCPARAMS,Host Controller Capability Parameters Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP[7:0] ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x04 4.--7. " IST[7:4] ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Disabled,Enabled"
|
|
rgroup.word (0x120+0x200)++0x1
|
|
line.word 0x00 "UH1_DCIVERSION,Device Controller Interface Version Register"
|
|
rgroup.long (0x124+0x200)++0x3
|
|
line.long 0x00 "UH1_DCCPARAMS,Device Control Capability Parameters Register"
|
|
bitfld.long 0x00 8. " HC ,Host Capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DC ,Device Capable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
width 22.
|
|
if ((data.long(0x200+ad:0x53F80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x140+0x200)++0x3
|
|
line.long 0x00 "UH1_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size 1" "1024,512,256,128,64,32,16,8"
|
|
bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
group.long (0x144+0x200)++0x3
|
|
line.long 0x00 "UH1_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted"
|
|
textline " "
|
|
eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
bitfld.long 0x00 3. " FRI ,Frame List Rollover" "Not rollover,Rollover"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
elif ((data.long(0x200+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x140+0x200)++0x3
|
|
line.long 0x00 "UH1_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ATDTW ,Add dTD TripWire" "Cleared,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
group.long (0x144+0x200)++0x3
|
|
line.long 0x00 "UH1_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended"
|
|
eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset"
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x140+0x200)++0x3
|
|
line.long 0x00 "UH1_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
group.long (0x144+0x200)++0x3
|
|
line.long 0x00 "UH1_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
if ((data.long(0x200+ad:0x53F80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x148+0x200)++0x3
|
|
line.long 0x00 "UH1_USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SRE ,SOF Received Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRE ,Frame List Rollover Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port Change Detect Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
elif ((data.long(0x200+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x148+0x200)++0x3
|
|
line.long 0x00 "UH1_USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLE ,Sleep interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SRE ,SOF Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " URE ,USB Reset Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCE ,Port Change Detect Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long (0x148+0x200)++0x3
|
|
line.long 0x00 "UH1_USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port Change Detect Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long (0x14C+0x200)++0x03
|
|
line.long 0x00 "UH1_FRINDEX,USB Frame Index Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame Index"
|
|
if ((data.long(0x200+ad:0x53F80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x154+0x200)++0x03
|
|
line.long 0x00 "UH1_PERIODICLISTBASE,Host Controller Frame List Base Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base Address (Low)"
|
|
elif ((data.long(0x200+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x154+0x200)++0x03
|
|
line.long 0x00 "UH1_DEVICEADDR,Device Controller USB Device Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 0x2 " USBADR ,Device Address"
|
|
else
|
|
hgroup.long (0x154+0x200)++0x03
|
|
hide.long 0x00 "UH1_PERIODICLISTBASE,Device Controller USB Device Address Register"
|
|
endif
|
|
if ((data.long(0x200+ad:0x53F80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x158+0x200)++0x03
|
|
line.long 0x00 "UH1_ASYNCLISTADDR,Host Controller Next Asynch Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low"
|
|
elif ((data.long(0x200+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x158+0x200)++0x03
|
|
line.long 0x00 "UH1_ASYNCLISTADDR,Device Controller Endpoint List Address Register"
|
|
hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE[31:11] ,Device Controller Endpoint List Address"
|
|
else
|
|
hgroup.long (0x158+0x200)++0x03
|
|
hide.long 0x00 "UH1_ASYNCLISTADDR,Device Controller Endpoint List Address Register"
|
|
endif
|
|
group.long (0x160+0x200)++0x7
|
|
line.long 0x00 "UH1_BURSTSIZE,Host Controller Embedded TT Async Buffer Status Register"
|
|
hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX Burst Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Size"
|
|
line.long 0x04 "UH1_TXFILLTUNING,TX FIFO Fill Tuning Register"
|
|
hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold"
|
|
bitfld.long 0x04 13.--15. " TXSCHEALTH ,Scheduler Health Counter" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler Overhead"
|
|
width 22.
|
|
group.long (0x16C+0x200)++0x03
|
|
line.long 0x00 "UH1_IC_USB,IC_USB Enable"
|
|
bitfld.long 0x00 31. " IC8 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " IC_VDD8 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " IC7 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " IC_VDD7 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " IC6 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " IC_VDD6 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " IC5 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " IC_VDD5 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " IC4 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " IC_VDD4 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " IC3 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " IC_VDD3 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " IC2 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " IC_VDD2 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " IC1 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " IC_VDD1 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
group.long (0x170+0x200)++0x03
|
|
line.long 0x00 "UH1_ULPIVIEW,ULPI Vieport Register"
|
|
bitfld.long 0x00 31. " ULPIWU ,ULPI Wakeup" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "No effect,Read/write"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write"
|
|
bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Not normal,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,ULPI Data Write"
|
|
width 22.
|
|
if ((data.long(0x200+ad:0x53F80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x184+0x200)++0x03
|
|
line.long 0x00 "UH1_PORTSC1,Port 1 Status and Control Register"
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,Reserved,ULPI,Serial"
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device"
|
|
elif ((data.long(0x200+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x184+0x200)++0x03
|
|
line.long 0x00 "UH1_PORTSC1,Port 1 Status and Control Register"
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,Reserved,ULPI,Serial"
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,?..."
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not attached,Attached"
|
|
else
|
|
hgroup.long (0x184+0x200)++0x03
|
|
hide.long 0x00 "UH1_PORTSC1,Port 1 Status and Control Register"
|
|
endif
|
|
group.long 0x1a4++0x03
|
|
line.long 0x00 "UH1_OTGSC,OTG Status Control Register"
|
|
bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " 1MSE ,1 Milisecond Timer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " 1MSS ,1 Milisecond Timer Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " 1MST ,1 Milisecond Timer Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BSE ,B Session End" "Not ended,Ended"
|
|
bitfld.long 0x00 11. " BSV ,B Session Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASV ,A Session Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " AVV ,A VBus Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ID ,USB ID" "A device,B device"
|
|
bitfld.long 0x00 5. " IDPU ,ID Pullup" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DP ,Data Pulsing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VD ,VBUS Discharge" "Not discharged,Discharged"
|
|
group.long (0x1a8+0x200)++0x03
|
|
line.long 0x00 "UH1_USBMODE,USB Device Mode Register"
|
|
bitfld.long 0x00 15. " SRT ,Shorten Reset Time" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CM[1:0] ,Controller Mode" "Idle,Reserved,Device,Host"
|
|
width 22.
|
|
if ((data.long(0x200+ad:0x53F80000+0x1a8)&0x3)==0x2)
|
|
group.long 0x1ac++0x0b
|
|
line.long 0x00 "UH1_ENDPTSETUPSTAT,Endpoint Setup Status Register"
|
|
bitfld.long 0x00 15. " ENDPTSETUPSTAT[15] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 14. " ENDPTSETUPSTAT[14] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ENDPTSETUPSTAT[13] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 12. " ENDPTSETUPSTAT[12] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENDPTSETUPSTAT[11] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 10. " ENDPTSETUPSTAT[10] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ENDPTSETUPSTAT[09] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 8. " ENDPTSETUPSTAT[08] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENDPTSETUPSTAT[07] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 6. " ENDPTSETUPSTAT[06] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ENDPTSETUPSTAT[05] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 4. " ENDPTSETUPSTAT[04] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENDPTSETUPSTAT[03] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 2. " ENDPTSETUPSTAT[02] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENDPTSETUPSTAT[01] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 0. " ENDPTSETUPSTAT[00] ,Setup Endpoint Status" "Not received,Received"
|
|
line.long 0x04 "UH1_ENDPTPRIME,Endpoint Initialization Register"
|
|
bitfld.long 0x04 23. " PETB7 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 22. " PETB6 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 21. " PETB5 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 20. " PETB4 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PETB3 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 18. " PETB2 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PETB1 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 16. " PETB0 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PERB7 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 6. " PERB6 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PERB5 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 4. " PERB4 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PERB3 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 2. " PERB2 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PERB1 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 0. " PERB0 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
line.long 0x08 "UH1_ENDPTFLUSH,Endpoint De-Initialize Register"
|
|
bitfld.long 0x08 23. " FETB7 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 22. " FETB6 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 21. " FETB5 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 20. " FETB4 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 19. " FETB3 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 18. " FETB2 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 17. " FETB1 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 16. " FETB0 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 7. " FERB7 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 6. " FERB6 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 5. " FERB5 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 4. " FERB4 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 3. " FERB3 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 2. " FERB2 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x08 1. " FERB1 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 0. " FERB0 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
rgroup.long 0x1b8++0x03
|
|
line.long 0x00 "UH1_ENDPTSTAT,Endpoint Status Register"
|
|
bitfld.long 0x00 23. " ETBR7 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 22. " ETBR6 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ETBR5 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " ETBR4 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETBR3 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 18. " ETBR2 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ETBR1 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " ETBR0 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERBR7 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 6. " ERBR6 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ERBR5 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " ERBR4 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERBR3 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ERBR2 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ERBR1 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ERBR0 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
group.long 0x1bc++0x03
|
|
line.long 0x00 "UH1_ENDPTCOMPLETE,Endpoint Compete Register"
|
|
bitfld.long 0x00 23. " ETCE7 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " ETCE6 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ETCE5 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " ETCE4 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETCE3 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " ETCE2 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ETCE1 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " ETCE0 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERCE7 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " ERCE6 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ERCE5 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " ERCE4 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERCE3 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " ERCE2 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ERCE1 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ERCE0 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
else
|
|
hgroup.long 0x1ac++0x13
|
|
hide.long 0x00 "UH1_ENDPTSETUPSTAT,Endpoint Setup Status Register"
|
|
hide.long 0x04 "UH1_ENDPTPRIME,Endpoint Initialization Register"
|
|
hide.long 0x08 "UH1_ENDPTFLUSH,Endpoint De-Initialize Register"
|
|
hide.long 0x0c "UH1_ENDPTSTAT,Endpoint Status Register"
|
|
hide.long 0x10 "UH1_ENDPTCOMPLETE,Endpoint Compete Register"
|
|
endif
|
|
width 16.
|
|
group.long 0x1c0++0x03
|
|
line.long 0x00 "UH1_ENDPTCTRL0,Endpoint Control 0 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,?..."
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,?..."
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "UH1_ENDPTCTRL1,Endpoint Control 1 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "UH1_ENDPTCTRL2,Endpoint Control 2 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "UH1_ENDPTCTRL3,Endpoint Control 3 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "UH1_ENDPTCTRL4,Endpoint Control 4 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "UH1_ENDPTCTRL5,Endpoint Control 5 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "UH1_ENDPTCTRL6,Endpoint Control 6 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "UH1_ENDPTCTRL7,Endpoint Control 7 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
width 0xb
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "WDOG (Watchdog Timer)"
|
|
base ad:0x53F98000
|
|
width 6.
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "WCR,Watchdog Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog Timeout Field"
|
|
bitfld.word 0x00 7. " WDW ,Watchdog Disable for Wait" "Continue,Suspended"
|
|
bitfld.word 0x00 5. " WDA ,/ipp_wdog Assertion" "Asserted,No effect"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SRS ,Software Reset Signal" "Asserted,No effect"
|
|
bitfld.word 0x00 3. " WDT ,/ipp_wdog Timeout assertion" "No effect,Asserted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " WDE ,Watchdog Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WDBG ,Operation of the WDOG module during DEBUG mode" "Continue,Suspended"
|
|
bitfld.word 0x00 0. " WDZST ,Watchdog Low Power" "Continue,Suspended"
|
|
line.word 0x02 "WSR,Watchdog Service Register"
|
|
rgroup.word 0x04++0x1
|
|
line.word 0x00 "WRSR,Watchdog Reset Status Register"
|
|
bitfld.word 0x00 1. " TOUT ,Indicates whether the reset is the result of a WDOG time-out" "Not time-out,Time-out"
|
|
bitfld.word 0x00 0. " SFTW ,Software Reset" "Not software,Software"
|
|
group.word 0x06++0x3
|
|
line.word 0x00 "WICR,Watchdog Interrupt Control Register"
|
|
bitfld.word 0x00 15. " WIE ,Watchdog Timer Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.word 0x00 14. " WTIS ,Watchdog Timer Interrupt Status" "No interrupt,Interrupt"
|
|
hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog Interrupt Count Timeout"
|
|
line.word 0x02 "WMCR,Watchdog Miscellaneous Control Register"
|
|
bitfld.word 0x02 0. " PDE ,Power Down Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
textline ""
|