12298 lines
933 KiB
Plaintext
12298 lines
933 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: MAX3267x On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2024-01-11 NEJ
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; @Manufacturer: MAXIM - Maxim Integrated Products, Inc.
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; @Doc: Generated (TRACE32, build: 165838.), based on:
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; max32670.svd (Ver. 1.0), max32672.svd (Ver. 1.0),
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; max32675.svd (Ver. 1.0)
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; @Core: Cortex-M4F
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; @Chip: MAX32670, MAX32671, MAX32672, MAX32675
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; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: permax3267x.per 17333 2024-01-15 16:54:40Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
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bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
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textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
sif (cpuis("MAX32672*"))
|
|
tree "ADC (Analog-to-Digtal Converter)"
|
|
base ad:0x40034000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CTRL0,Control Register 0."
|
|
bitfld.long 0x0 4. "RESETB,Reset ADC." "0: reset ADC.,1: activate ADC."
|
|
bitfld.long 0x0 3. "CHOP_FORCE,Chop Force Control." "0: Do not force chop mode.,1: Force chop Mode."
|
|
newline
|
|
bitfld.long 0x0 2. "SKIP_CAL,Skip Calibration Enable." "0: Do not skip calibration.,1: Skip calibration."
|
|
bitfld.long 0x0 1. "BIAS_EN,Bias Enable." "0: Disable Bias.,1: Enable Bias."
|
|
newline
|
|
bitfld.long 0x0 0. "ADC_EN,ADC Enable." "0: Disable ADC.,1: enable ADC."
|
|
line.long 0x4 "CTRL1,Control Register 1."
|
|
hexmask.long.byte 0x4 16.--20. 1. "NUM_SLOTS,Number of slots enabled for the conversion sequence"
|
|
bitfld.long 0x4 8.--10. "AVG,Number of samples to average for each output data code." "0: 1 Sample per output code.,1: 2 Samples per output code.,2: 4 Samples per output code.,3: 8 Samples per output code.,4: 16 Samples per output code.,5: 32 Samples per output code.,?,?"
|
|
newline
|
|
bitfld.long 0x4 7. "TS_SEL,Temp sensor select." "0: Temp sensor is not one of the slots in the..,1: Temp sensor is one of the slots in the sequence."
|
|
bitfld.long 0x4 4.--6. "TRIG_SEL,Hardware trigger source select." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "SAMP_CK_OFF,Sample clock off control." "0: Sample clock always generated.,1: Sample clock generated only when converting."
|
|
bitfld.long 0x4 2. "CNV_MODE,Conversion mode control." "0: Do one conversion sequence.,1: Do continuous conversion sequences."
|
|
newline
|
|
bitfld.long 0x4 1. "TRIG_MODE,Trigger mode control." "0: software trigger mode.,1: hardware trigger mode."
|
|
bitfld.long 0x4 0. "START,Start conversion control." "0: Stop conversions.,1: Start conversions."
|
|
line.long 0x8 "CLKCTRL,Clock Control Register."
|
|
bitfld.long 0x8 4.--6. "CLKDIV,Clock divider control." "0: Divide by 2.,1: Divide by 4.,2: Divide by 8.,3: Divide by 16.,4: Divide by 1.,?,?,?"
|
|
bitfld.long 0x8 0.--1. "CLKSEL,Clock source select." "0: Select HCLK.,1: Select CLK_ADC0.,2: Select CLK_ADC1.,3: Select CLK_ADC2."
|
|
line.long 0xC "SAMPCLKCTRL,Sample Clock Control Register."
|
|
hexmask.long.word 0xC 16.--31. 1. "IDLE_CNT,Number of cycles for SAMPLE_CLK low time."
|
|
hexmask.long.byte 0xC 0.--7. 1. "TRACK_CNT,Number of cycles for SAMPLE_CLK high time."
|
|
line.long 0x10 "CHSEL0,Channel Select Register 0."
|
|
hexmask.long.byte 0x10 24.--28. 1. "slot3_id,channel assignment for slot 3."
|
|
hexmask.long.byte 0x10 16.--20. 1. "slot2_id,channel assignment for slot 2."
|
|
newline
|
|
hexmask.long.byte 0x10 8.--12. 1. "slot1_id,channel assignment for slot 1."
|
|
hexmask.long.byte 0x10 0.--4. 1. "slot0_id,channel assignment for slot 0."
|
|
line.long 0x14 "CHSEL1,Channel Select Register 1."
|
|
hexmask.long.byte 0x14 24.--28. 1. "slot7_id,channel assignment for slot 7."
|
|
hexmask.long.byte 0x14 16.--20. 1. "slot6_id,channel assignment for slot 6."
|
|
newline
|
|
hexmask.long.byte 0x14 8.--12. 1. "slot5_id,channel assignment for slot 5."
|
|
hexmask.long.byte 0x14 0.--4. 1. "slot4_id,channel assignment for slot 4."
|
|
line.long 0x18 "CHSEL2,Channel Select Register 2."
|
|
hexmask.long.byte 0x18 24.--28. 1. "slot11_id,channel assignment for slot 11."
|
|
hexmask.long.byte 0x18 16.--20. 1. "slot10_id,channel assignment for slot 10."
|
|
newline
|
|
hexmask.long.byte 0x18 8.--12. 1. "slot9_id,channel assignment for slot 9."
|
|
hexmask.long.byte 0x18 0.--4. 1. "slot8_id,channel assignment for slot 8."
|
|
line.long 0x1C "CHSEL3,Channel Select Register 3."
|
|
hexmask.long.byte 0x1C 24.--28. 1. "slot15_id,channel assignment for slot 15."
|
|
hexmask.long.byte 0x1C 16.--20. 1. "slot14_id,channel assignment for slot 14."
|
|
newline
|
|
hexmask.long.byte 0x1C 8.--12. 1. "slot13_id,channel assignment for slot 13."
|
|
hexmask.long.byte 0x1C 0.--4. 1. "slot12_id,channel assignment for slot 12."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "RESTART,Restart Count Control Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Number of sample periods to skip before restarting a continuous mode sequence"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "DATAFMT,Channel Data Format Register"
|
|
hexmask.long 0x0 0.--31. 1. "MODE,Data format control"
|
|
line.long 0x4 "FIFODMACTRL,FIFO and DMA control"
|
|
hexmask.long.byte 0x4 8.--15. 1. "THRESH,FIFO Threshold. These bits define the FIFO interrupt threshold."
|
|
bitfld.long 0x4 2.--3. "DATA_FORMAT,DATA format control." "0: Data and Status in FIFO.,1: Only Data in FIFO.,2: Only Raw Data in FIFO.,?"
|
|
newline
|
|
bitfld.long 0x4 1. "FLUSH,FIFO Flush." "0: Normal FIFO operation.,1: Flush FIFO."
|
|
bitfld.long 0x4 0. "DMA_EN,DMA Enable." "0: Disable DMA.,1: Enable DMA."
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x0 "DATA,Data Register (FIFO)."
|
|
bitfld.long 0x0 31. "CLIPPED,Clipped status for the data." "0,1"
|
|
bitfld.long 0x0 24. "INVALID,Invalid status for the data." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "CHAN,Channel for the data."
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Conversion data."
|
|
line.long 0x4 "STATUS,Status Register"
|
|
hexmask.long.byte 0x4 8.--15. 1. "FIFO_LEVEL,Number of entries in FIFO available to read"
|
|
bitfld.long 0x4 2. "FULL,FIFO full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "EMPTY,FIFO Empty" "0,1"
|
|
bitfld.long 0x4 0. "READY,Indication that the ADC is in ON power state" "0,1"
|
|
group.long 0x4C++0xB
|
|
line.long 0x0 "CHSTATUS,Channel Status"
|
|
hexmask.long 0x0 0.--31. 1. "CLIPPED,"
|
|
line.long 0x4 "INTEN,Interrupt Enable Register."
|
|
bitfld.long 0x4 10. "FIFO_OFL," "0,1"
|
|
bitfld.long 0x4 9. "FIFO_UFL," "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FIFO_LVL," "0,1"
|
|
bitfld.long 0x4 7. "CLIPPED," "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "CONV_DONE," "0,1"
|
|
bitfld.long 0x4 5. "SEQ_DONE," "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SEQ_STARTED," "0,1"
|
|
bitfld.long 0x4 3. "START_DET,Conversion start is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "ABORT,Conversion start is aborted." "0,1"
|
|
bitfld.long 0x4 0. "READY,ADC is ready." "0,1"
|
|
line.long 0x8 "INTFL,Interrupt Flags Register."
|
|
eventfld.long 0x8 10. "FIFO_OFL," "0,1"
|
|
eventfld.long 0x8 9. "FIFO_UFL," "0,1"
|
|
newline
|
|
eventfld.long 0x8 8. "FIFO_LVL," "0,1"
|
|
eventfld.long 0x8 7. "CLIPPED," "0,1"
|
|
newline
|
|
eventfld.long 0x8 6. "CONV_DONE," "0,1"
|
|
eventfld.long 0x8 5. "SEQ_DONE," "0,1"
|
|
newline
|
|
eventfld.long 0x8 4. "SEQ_STARTED," "0,1"
|
|
eventfld.long 0x8 3. "START_DET,Conversion start is detected." "0,1"
|
|
newline
|
|
eventfld.long 0x8 2. "ABORT,Conversion start is aborted." "0,1"
|
|
eventfld.long 0x8 0. "READY,ADC is ready." "0,1"
|
|
group.long 0x60++0xB
|
|
line.long 0x0 "SFRADDROFFSET,SFR Address Offset Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "OFFSET,Address Offset for SAR Digital"
|
|
line.long 0x4 "SFRADDR,SFR Address Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADDR,Address to SAR Digital"
|
|
line.long 0x8 "SFRWRDATA,SFR Write Data Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATA,DATA to SAR Digital"
|
|
rgroup.long 0x6C++0x7
|
|
line.long 0x0 "SFRRDDATA,SFR Read Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DATA,DATA from SAR Digital"
|
|
line.long 0x4 "SFRSTATUS,SFR Status Register"
|
|
bitfld.long 0x4 0. "NACK,NACK status for SAR Digital SFR communication" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
base ad:0x40007400
|
|
elif (cpuis("MAX32672*")||cpuis("MAX32675*"))
|
|
base ad:0x40074000
|
|
endif
|
|
tree "AES (Advanced Encryption Standard)"
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTRL,AES Control Register"
|
|
bitfld.long 0x0 8.--9. "TYPE,Encryption Type Selection" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "KEY_SIZE,Encryption Key Size" "0: 128 Bits.,1: 192 Bits.,2: 256 Bits.,?"
|
|
bitfld.long 0x0 5. "OUTPUT_FLUSH,Flush the data output FIFO" "0,1"
|
|
bitfld.long 0x0 4. "INPUT_FLUSH,Flush the data input FIFO" "0,1"
|
|
bitfld.long 0x0 3. "START,Start AES Calculation" "0,1"
|
|
bitfld.long 0x0 2. "DMA_TX_EN,DMA Request To Write Data Input FIFO" "0,1"
|
|
bitfld.long 0x0 1. "DMA_RX_EN,DMA Request To Read Data Output FIFO" "0,1"
|
|
bitfld.long 0x0 0. "EN,AES Enable" "0,1"
|
|
line.long 0x4 "STATUS,AES Status Register"
|
|
bitfld.long 0x4 4. "OUTPUT_FULL,Data output FIFO full status" "0,1"
|
|
bitfld.long 0x4 3. "OUTPUT_EM,Data output FIFO empty status" "0,1"
|
|
bitfld.long 0x4 2. "INPUT_FULL,Data input FIFO full status" "0,1"
|
|
bitfld.long 0x4 1. "INPUT_EM,Data input FIFO empty status" "0,1"
|
|
bitfld.long 0x4 0. "BUSY,AES Busy Status" "0,1"
|
|
line.long 0x8 "INTFL,AES Interrupt Flag Register"
|
|
bitfld.long 0x8 4. "KEY_ONE,KEY_ONE" "0,1"
|
|
bitfld.long 0x8 3. "OV,Data Output FIFO Overrun Interrupt" "0,1"
|
|
bitfld.long 0x8 2. "KEY_ZERO,External AES Key Zero Interrupt" "0,1"
|
|
bitfld.long 0x8 1. "KEY_CHANGE,External AES Key Changed Interrupt" "0,1"
|
|
bitfld.long 0x8 0. "DONE,AES Done Interrupt" "0,1"
|
|
line.long 0xC "INTEN,AES Interrupt Enable Register"
|
|
bitfld.long 0xC 4. "KEY_ONE,KEY_ONE" "0,1"
|
|
bitfld.long 0xC 3. "OV,Data Output FIFO Overrun Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 2. "KEY_ZERO,External AES Key Zero Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 1. "KEY_CHANGE,External AES Key Changed Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 0. "DONE,AES Done Interrupt Enable" "0,1"
|
|
line.long 0x10 "FIFO,AES Data Register"
|
|
bitfld.long 0x10 0. "DATA,AES FIFO" "0,1"
|
|
tree.end
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
base ad:0x40007800
|
|
elif (cpuis("MAX32672*"))
|
|
base ad:0x40205000
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32672*"))
|
|
tree "AES_KEYS (AES Key Registers.)"
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "KEY0,AES Key 0."
|
|
line.long 0x4 "KEY1,AES Key 1."
|
|
line.long 0x8 "KEY2,AES Key 2."
|
|
line.long 0xC "KEY3,AES Key 3."
|
|
line.long 0x10 "KEY4,AES Key 4."
|
|
line.long 0x14 "KEY5,AES Key 5."
|
|
line.long 0x18 "KEY6,AES Key 6."
|
|
line.long 0x1C "KEY7,AES Key 7."
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "AES_KEY0,AES Key 0."
|
|
line.long 0x4 "AES_KEY1,AES Key 1."
|
|
line.long 0x8 "AES_KEY2,AES Key 2."
|
|
line.long 0xC "AES_KEY3,AES Key 3."
|
|
line.long 0x10 "AES_KEY4,AES Key 4."
|
|
line.long 0x14 "AES_KEY5,AES Key 5."
|
|
line.long 0x18 "AES_KEY6,AES Key 6."
|
|
line.long 0x1C "AES_KEY7,AES Key 7."
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32675*"))
|
|
tree "CRC (Cyclic Redundancy Check Engine)"
|
|
base ad:0x4000F000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTRL,CRC Control"
|
|
bitfld.long 0x0 16. "BUSY,CRC Busy" "0,1"
|
|
bitfld.long 0x0 4. "BYTE_SWAP_OUT,Byte Swap CRC Value Output" "0,1"
|
|
bitfld.long 0x0 3. "BYTE_SWAP_IN,Byte Swap CRC Data Input" "0,1"
|
|
bitfld.long 0x0 2. "MSB,MSB Select" "0,1"
|
|
bitfld.long 0x0 1. "DMA_EN,DMA Request Enable" "0,1"
|
|
bitfld.long 0x0 0. "EN,CRC Enable" "0,1"
|
|
line.long 0x4 "DATAIN32,CRC Data Input"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,CRC Data"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x4)++0x1
|
|
line.word 0x0 "DATAIN16[$1],CRC Data Input"
|
|
hexmask.word 0x0 0.--15. 1. "DATA,CRC Data"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "DATAIN8[$1],CRC Data Input"
|
|
hexmask.byte 0x0 0.--7. 1. "DATA,CRC Data"
|
|
repeat.end
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "POLY,CRC Polynomial"
|
|
hexmask.long 0x0 0.--31. 1. "POLY,CRC Polynomial"
|
|
line.long 0x4 "VAL,Current CRC Value"
|
|
hexmask.long 0x4 0.--31. 1. "VALUE,Current CRC Value"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "CTB (Cryptographic Toolbox)"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CTRL,Crypto Control Register."
|
|
rbitfld.long 0x0 31. "DONE,Done. One or more cryptographic calculations complete (logical OR of done flags)." "0: Not Done.,1: Done."
|
|
rbitfld.long 0x0 30. "RDY,Ready. Crypto block ready for more data." "0: Busy.,1: Ready."
|
|
newline
|
|
rbitfld.long 0x0 29. "ERR,AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set the DMA will stop. This bit can only be cleared by resetting the crypto block." "0: No Error.,1: Error."
|
|
bitfld.long 0x0 27. "CPH_DONE,Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation." "0: Not Done.,1: Done."
|
|
newline
|
|
bitfld.long 0x0 26. "HSH_DONE,Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation." "0: Not Done.,1: Done."
|
|
bitfld.long 0x0 25. "GLS_DONE,Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization.." "0: Not Done.,1: Done."
|
|
newline
|
|
bitfld.long 0x0 24. "DMA_DONE,DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation." "0: Not Done.,1: Done."
|
|
bitfld.long 0x0 15. "DMADNEMSK,DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored." "0: DMA_DONE not used in setting CRYPTO_CTRL.DONE bit.,1: DMA_DONE used in setting CRYPTO_CTRL.DONE bit."
|
|
newline
|
|
bitfld.long 0x0 14. "FLAG_MODE,Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep i.e. once set it will remain set until a reset occurs." "0: Unrestricted write (0 or 1) of..,1: Access to CRYPTO_CTRL[27:24] are write 1 to.."
|
|
bitfld.long 0x0 10.--11. "RDSRC,Read FIFO Source Select. This field selects the source of the read FIFO. Typically it is set to use the DMA. To implement a memset() function the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers the.." "0: DMA Disable.,1: DMA Or APB.,2: RNG.,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "WRSRC,Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO it is always written out the DMA. To decrypt or encrypt data the write FIFO source should be set to the cipher.." "0: None.,1: Cipher Output.,2: Read FIFO.,?"
|
|
bitfld.long 0x0 7. "WAIT_POL,Wait Pin Polarity. When the wait pin is enabled this bit selects its active state." "0: Active Low.,1: Active High."
|
|
newline
|
|
bitfld.long 0x0 6. "WAIT_EN,Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready." "0: Disable,1: Enable"
|
|
bitfld.long 0x0 5. "BSI,Byte Swap Input. Note. No byte swap will occur if there is not a full word." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 4. "BSO,Byte Swap Output. Note. No byte swap will occur if there is not a full word." "0: Disable,1: Enable"
|
|
bitfld.long 0x0 2. "SRC,Source Select. This bit selects the hash function and CRC generator input source." "0: Input FIFO,1: Output FIFO"
|
|
newline
|
|
bitfld.long 0x0 1. "INTR,Interrupt Enable. Generates an interrupt when done or error set." "0: Disable,1: Enable"
|
|
bitfld.long 0x0 0. "RST,Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL CIPHER_CTRL HASH_CTRL CRC_CTRL MAA_CTRL (with the exception.." "0: Reset complete.,1: Reset in progress."
|
|
line.long 0x4 "CIPHER_CTRL,Cipher Control Register."
|
|
rbitfld.long 0x4 16.--18. "CCML,CCM L Parameter." "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x4 13.--15. "CCMM,CCM M Parameter." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 12. "DTYPE,GCM/CCM data type." "0,1"
|
|
rbitfld.long 0x4 11. "HVC,H Vector Computation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--10. "MODE,Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB OFB or CTR modes." "0: ECB Mode.,1: CBC Mode.,2: CFB (AES only).,3: OFB (AES only).,4: CTR (AES only).,?,?,?"
|
|
bitfld.long 0x4 4.--6. "CIPHER,Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation." "0: Disabled.,1: AES 128.,2: AES 192.,3: AES 256.,4: DES.,5: Triple DES.,?,?"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "SRC,Source of Random key." "0: User cipher key (0x4000_1060).,?,2: Key from battery-backed register file..,3: Key from battery-backed register file.."
|
|
bitfld.long 0x4 1. "KEY,Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done it sets the appropriate crypto DMA Done flag." "0: No operation/complete.,1: Start operation."
|
|
newline
|
|
bitfld.long 0x4 0. "ENC,Encrypt. Select encryption or decryption of input data." "0: Encrypt.,1: Decrypt."
|
|
line.long 0x8 "HASH_CTRL,HASH Control Register."
|
|
bitfld.long 0x8 5. "LAST,Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding which includes the trailing bit 1 .." "0: No Effect.,1: Last Message Data."
|
|
bitfld.long 0x8 2.--4. "HASH,Hash function selection." "0: Disabled.,1: SHA-1.,2: SHA 224.,3: SHA 256.,4: SHA 384.,5: SHA 512.,?,?"
|
|
newline
|
|
bitfld.long 0x8 1. "XOR,XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad." "0: Disable.,1: Enable."
|
|
bitfld.long 0x8 0. "INIT,Initialize. Initializes hash registers with standard constants." "0: No operation/complete.,1: Start operation."
|
|
line.long 0xC "CRC_CTRL,CRC Control Register."
|
|
bitfld.long 0xC 5. "HRST,Hamming Reset. Reset Hamming code ECC generator for next block." "?,1: Starts reset operation."
|
|
bitfld.long 0xC 4. "HAM,Hamming Code Enable. Enable hamming code calculation." "0: Disable.,1: Enable."
|
|
newline
|
|
bitfld.long 0xC 3. "ENT,Entropy Enable. If the PRNG is enabled this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the.." "0: Disable.,1: Enable."
|
|
bitfld.long 0xC 2. "PRNG,Pseudo Random Number Generator Enable. If entropy is disabled this outputs one byte of pseudo random data per clock cycle. If entropy is enabled data is output at a rate of one bit per clock cycle." "0: Disable.,1: Enable."
|
|
newline
|
|
bitfld.long 0xC 1. "MSB,MSB select. This bit selects the order of calculating CRC on data." "0: LSB First.,1: MSB First."
|
|
bitfld.long 0xC 0. "CRC,Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled." "0: Disable.,1: Enable."
|
|
line.long 0x10 "DMA_SRC,Crypto DMA Source Address."
|
|
hexmask.long 0x10 0.--31. 1. "ADDR,DMA Source Address."
|
|
line.long 0x14 "DMA_DEST,Crypto DMA Destination Address."
|
|
hexmask.long 0x14 0.--31. 1. "ADDR,DMA Destination Address."
|
|
line.long 0x18 "DMA_CNT,Crypto DMA Byte Count."
|
|
hexmask.long 0x18 0.--31. 1. "ADDR,DMA Byte Address."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "DIN[$1],Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any.."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Crypto Data Input. Input can be written to this register instead of using DMA."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x30)++0x3
|
|
line.long 0x0 "DOUT[$1],Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes. this register holds the result of most recent encryption or decryption.."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm."
|
|
repeat.end
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "CRC_POLY,CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit."
|
|
hexmask.long 0x0 0.--31. 1. "POLY,CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit."
|
|
line.long 0x4 "CRC_VAL,CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit."
|
|
hexmask.long 0x4 0.--31. 1. "VAL,CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit."
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "HAM_ECC,Hamming ECC Register."
|
|
bitfld.long 0x0 16. "PAR,Parity. This is the parity of the entire array." "0: Even.,1: Odd."
|
|
hexmask.long.word 0x0 0.--15. 1. "ECC,Hamming ECC Value. These bits are the even parity of their corresponding bit groups."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x50)++0x3
|
|
line.long 0x0 "CIPHER_INIT[$1],Initial Vector. For block cipher operations that use CBC. CFB. OFB. or CNTR modes. this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap.."
|
|
hexmask.long 0x0 0.--31. 1. "IVEC,Initial Vector. For block cipher operations that use CBC CFB OFB or CNTR modes this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits."
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "CIPHER_KEY[$1],Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits."
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits."
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "HASH_DIGEST[$1],This register holds the calculated hash value. This register is affected by the endian swap bits."
|
|
hexmask.long 0x0 0.--31. 1. "HASH,This register holds the calculated hash value. This register is affected by the endian swap bits."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC0)++0x3
|
|
line.long 0x0 "HASH_MSG_SZ[$1],Message Size. This register holds the lowest 32-bit of message size in bytes."
|
|
hexmask.long 0x0 0.--31. 1. "MSGSZ,Message Size. This register holds the lowest 32-bit of message size in bytes."
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xD0)++0x3
|
|
line.long 0x0 "AAD_LENGTH[$1],AAD Length Registers."
|
|
hexmask.long 0x0 0.--31. 1. "LENGTH,AAD length in bytes for AES GCM and CCM operations."
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xD8)++0x3
|
|
line.long 0x0 "PLD_LENGTH[$1],PLD Length Registers."
|
|
hexmask.long 0x0 0.--31. 1. "LENGTH,PLD length in bytes for AES GCM and CCM operations."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xE0)++0x3
|
|
line.long 0x0 "TAGMIC[$1],TAG/MIC Registers."
|
|
hexmask.long 0x0 0.--31. 1. "LENGTH,TAG/MIC output for AES GCM and CCM operations."
|
|
repeat.end
|
|
group.long 0x100++0x37
|
|
line.long 0x0 "SCA_CTRL0,SCA Control 0 Register."
|
|
bitfld.long 0x0 24.--25. "ECCSIZE,ECC Size." "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "MODADDR,MODULO Address Offset."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "OPCODE,SCA Opcode."
|
|
bitfld.long 0x0 6. "HWKEY,Hardware Key Select." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MANPARAM,ECC Parameter Source." "0,1"
|
|
bitfld.long 0x0 4. "ERMEM,Erase Cryptographic Memory." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ABORT,Abort Operation." "0,1"
|
|
bitfld.long 0x0 1. "SCAIE,SCA Interrupt Enable." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 0. "STC,Start Calculation." "0,1"
|
|
line.long 0x4 "SCA_CTRL1,SCA Control 1 Register."
|
|
hexmask.long.word 0x4 8.--17. 1. "CARRYPOS,To set Carry location."
|
|
bitfld.long 0x4 5. "NRNG,NRNG." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "PLUSONE,Enable Carry propagation for the next operation." "0,1"
|
|
bitfld.long 0x4 1. "AUTOCARRY,Automatically propagate the carry for the next operation." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MAN,SCA Mode." "0: Auto Mode,1: Manual Mode"
|
|
line.long 0x8 "SCA_STAT,SCA Status Register."
|
|
bitfld.long 0x8 11. "ALUNEG2,ALU 2 SubSign of the subtraction result for ALU_2." "0,1"
|
|
bitfld.long 0x8 10. "ALUNEG1,ALU 2 SubSign of the subtraction result for ALU_2." "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "GTE2I2,Modulo 2x Result." "0,1"
|
|
bitfld.long 0x8 8. "CARRY,Carry on ongoing operation." "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "MEMERR,SCA Memory Access Error." "0,1"
|
|
bitfld.long 0x8 5. "COMPERR,EC Computation Error." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "FSMERR,FSM Transition Error." "0,1"
|
|
bitfld.long 0x8 3. "PVF2,Point 2 Verification Failed." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PVF1,Point 1 Verification Failed." "0,1"
|
|
bitfld.long 0x8 1. "SCAIF,SCA Interrupt Flag." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "BUSY,SCA Busy." "0,1"
|
|
line.long 0xC "SCA_PPX_ADDR,PPX Coordinate Data Pointer Register."
|
|
hexmask.long 0xC 0.--31. 1. "ADDR,Point P Coordinate Data Pointer."
|
|
line.long 0x10 "SCA_PPY_ADDR,PPY Coordinate Data Pointer Register."
|
|
hexmask.long 0x10 0.--31. 1. "ADDR,Point P Coordinate Data Pointer."
|
|
line.long 0x14 "SCA_PPZ_ADDR,PPZ Coordinate Data Pointer Register."
|
|
hexmask.long 0x14 0.--31. 1. "ADDR,Point P Coordinate Data Pointer."
|
|
line.long 0x18 "SCA_PQX_ADDR,PQX Coordinate Data Pointer Register."
|
|
hexmask.long 0x18 0.--31. 1. "ADDR,Point Q Coordinate Data Pointer."
|
|
line.long 0x1C "SCA_PQY_ADDR,PQY Coordinate Data Pointer Register."
|
|
hexmask.long 0x1C 0.--31. 1. "ADDR,Point Q Coordinate Data Pointer."
|
|
line.long 0x20 "SCA_PQZ_ADDR,PQZ Coordinate Data Pointer Register."
|
|
hexmask.long 0x20 0.--31. 1. "ADDR,Point Q Coordinate Data Pointer."
|
|
line.long 0x24 "SCA_RDSA_ADDR,SCA RDSA Address Register."
|
|
hexmask.long 0x24 0.--31. 1. "ADDR,The starting address of the R portion for R S ECDSA signature."
|
|
line.long 0x28 "SCA_RES_ADDR,SCA Result Address Register."
|
|
hexmask.long 0x28 0.--31. 1. "ADDR,Starting address of result storage."
|
|
line.long 0x2C "SCA_OP_BUFF_ADDR,SCA Operation Buffer Address Register."
|
|
hexmask.long 0x2C 0.--31. 1. "ADDR,Starting address of operation buffer."
|
|
line.long 0x30 "SCA_MODDATA,SCA Modulo Data Input Register."
|
|
hexmask.long 0x30 0.--31. 1. "DATA,Used to load the SCA modulo for modular operations."
|
|
line.long 0x34 "SCA_NRNG,Starting address for NRNG stored in SRAM."
|
|
tree.end
|
|
endif
|
|
tree "DMA (DMA Controller)"
|
|
base ad:0x40028000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "INTEN,DMA Control Register."
|
|
bitfld.long 0x0 7. "CH7,Channel 7 Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 6. "CH6,Channel 6 Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 5. "CH5,Channel 5 Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 4. "CH4,Channel 4 Interrupt Enable." "0: Disable.,1: Enable."
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,Channel 3 Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 2. "CH2,Channel 2 Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 1. "CH1,Channel 1 Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 0. "CH0,Channel 0 Interrupt Enable." "0: Disable.,1: Enable."
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "INTFL,DMA Interrupt Register."
|
|
bitfld.long 0x0 7. "CH7,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
bitfld.long 0x0 6. "CH6,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
bitfld.long 0x0 5. "CH5,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
bitfld.long 0x0 4. "CH4,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
bitfld.long 0x0 2. "CH2,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
bitfld.long 0x0 1. "CH1,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
bitfld.long 0x0 0. "CH0,Channel Interrupt. To clear an interrupt all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40028100 ad:0x40028120 ad:0x40028140 ad:0x40028160 ad:0x40028180 ad:0x400281A0 ad:0x400281C0 ad:0x400281E0)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "CTRL,DMA Channel Control Register."
|
|
bitfld.long 0x0 31. "CTZ_IE,Count-to-zero Interrupts Enable. When enabled the IPEND will be set to 1 whenever a count-to-zero event occurs." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 30. "DIS_IE,Channel Disable Interrupt Enable. When enabled the IPEND will be set to 1 whenever CH_ST changes from 1 to 0." "0: Disable.,1: Enable."
|
|
hexmask.long.byte 0x0 24.--28. 1. "BURST_SIZE,Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field."
|
|
newline
|
|
bitfld.long 0x0 22. "DSTINC,Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 20.--21. "DSTWD,Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width)." "0: Byte.,1: Halfword.,2: Word.,?"
|
|
bitfld.long 0x0 18. "SRCINC,Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals." "0: Disable.,1: Enable."
|
|
newline
|
|
bitfld.long 0x0 16.--17. "SRCWD,Source Width. In most cases this will be the data width of each AHB transactions. However the width will be reduced in the cases where DMA_CNT indicates a smaller value." "0: Byte.,1: Halfword.,2: Word.,?"
|
|
bitfld.long 0x0 14.--15. "TO_CLKDIV,Pre-Scale Select. Selects the Pre-Scale divider for timer clock input." "0: Disable timer.,1: hclk / 256.,2: hclk / 64k.,3: hclk / 16M."
|
|
bitfld.long 0x0 11.--13. "TO_PER,Timeout Period Select." "0: Timeout of 3 to 4 prescale clocks.,1: Timeout of 7 to 8 prescale clocks.,2: Timeout of 15 to 16 prescale clocks.,3: Timeout of 31 to 32 prescale clocks.,4: Timeout of 63 to 64 prescale clocks.,5: Timeout of 127 to 128 prescale clocks.,6: Timeout of 255 to 256 prescale clocks.,7: Timeout of 511 to 512 prescale clocks."
|
|
newline
|
|
bitfld.long 0x0 10. "TO_WAIT,Request Wait Enable. When enabled delay timer start until DMA request transitions from active to inactive." "0: Disable.,1: Enable."
|
|
hexmask.long.byte 0x0 4.--9. 1. "REQUEST,Request Select. Select DMA request line for this channel. If memory-to-memory is selected the channel operates as if the request is always active."
|
|
bitfld.long 0x0 2.--3. "PRI,DMA Priority." "0: Highest Priority.,1: Medium High Priority.,2: Medium Low Priority.,3: Lowest Priority."
|
|
newline
|
|
bitfld.long 0x0 1. "RLDEN,Reload Enable. Setting this bit to 1 enables DMA_SRC DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer.." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 0. "EN,Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0." "0: Disable.,1: Enable."
|
|
line.long 0x4 "STATUS,DMA Channel Status Register."
|
|
eventfld.long 0x4 6. "TO_IF,Time-Out Event Interrupt Flag." "0,1"
|
|
eventfld.long 0x4 4. "BUS_ERR,Bus Error. Indicates that an AHB abort was received and the channel has been disabled." "0,1"
|
|
eventfld.long 0x4 3. "RLD_IF,Reload Event Interrupt Flag." "0,1"
|
|
newline
|
|
eventfld.long 0x4 2. "CTZ_IF,Count-to-Zero (CTZ) Interrupt Flag" "0,1"
|
|
rbitfld.long 0x4 1. "IPEND,Channel Interrupt." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
rbitfld.long 0x4 0. "STATUS,Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration address and count registers for the channel. Whenever this bit is cleared by hardware the DMA_CFG.CHEN bit is also cleared (if not.." "0: Disable.,1: Enable."
|
|
line.long 0x8 "SRC,Source Device Address. If SRCINC=1. the counter bits are incremented by 1.2. or 4. depending on the data width of each AHB cycle. For peripheral transfers. some or all of the actual address bits are fixed. If SRCINC=0. this register remains constant."
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,"
|
|
line.long 0xC "DST,Destination Device Address. For peripheral transfers. some or all of the actual address bits are fixed. If DSTINC=1. this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1. 2. or 4. depending on the data width.."
|
|
hexmask.long 0xC 0.--31. 1. "ADDR,"
|
|
line.long 0x10 "CNT,DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1. 2. or 4 depending on the data width of each AHB cycle. When the counter reaches 0. a.."
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "CNT,DMA Counter."
|
|
line.long 0x14 "SRCRLD,Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition."
|
|
hexmask.long 0x14 0.--30. 1. "ADDR,Source Address Reload Value."
|
|
line.long 0x18 "DSTRLD,Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition."
|
|
hexmask.long 0x18 0.--30. 1. "ADDR,Destination Address Reload Value."
|
|
line.long 0x1C "CNTRLD,DMA Channel Count Reload Register."
|
|
bitfld.long 0x1C 31. "EN,Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs." "0: Disable.,1: Enable."
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "CNT,Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition."
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
repeat 12. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB)(list ad:0x40028100 ad:0x40028104 ad:0x40028108 ad:0x4002810C ad:0x40028110 ad:0x40028114 ad:0x40028118 ad:0x4002811C ad:0x40028120 ad:0x40028124 ad:0x40028128 ad:0x4002812C)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2+0x100)++0x1F
|
|
line.long 0x0 "CTRL,DMA Channel Control Register."
|
|
bitfld.long 0x0 31. "CTZ_IE,Count-to-zero Interrupts Enable. When enabled the IPEND will be set to 1 whenever a count-to-zero event occurs." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 30. "DIS_IE,Channel Disable Interrupt Enable. When enabled the IPEND will be set to 1 whenever CH_ST changes from 1 to 0." "0: Disable.,1: Enable."
|
|
hexmask.long.byte 0x0 24.--28. 1. "BURST_SIZE,Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field."
|
|
newline
|
|
bitfld.long 0x0 22. "DSTINC,Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 20.--21. "DSTWD,Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width)." "0: Byte.,1: Halfword.,2: Word.,?"
|
|
bitfld.long 0x0 18. "SRCINC,Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals." "0: Disable.,1: Enable."
|
|
newline
|
|
bitfld.long 0x0 16.--17. "SRCWD,Source Width. In most cases this will be the data width of each AHB transactions. However the width will be reduced in the cases where DMA_CNT indicates a smaller value." "0: Byte.,1: Halfword.,2: Word.,?"
|
|
bitfld.long 0x0 14.--15. "TO_CLKDIV,Pre-Scale Select. Selects the Pre-Scale divider for timer clock input." "0: Disable timer.,1: hclk / 256.,2: hclk / 64k.,3: hclk / 16M."
|
|
bitfld.long 0x0 11.--13. "TO_PER,Timeout Period Select." "0: Timeout of 3 to 4 prescale clocks.,1: Timeout of 7 to 8 prescale clocks.,2: Timeout of 15 to 16 prescale clocks.,3: Timeout of 31 to 32 prescale clocks.,4: Timeout of 63 to 64 prescale clocks.,5: Timeout of 127 to 128 prescale clocks.,6: Timeout of 255 to 256 prescale clocks.,7: Timeout of 511 to 512 prescale clocks."
|
|
newline
|
|
bitfld.long 0x0 10. "TO_WAIT,Request Wait Enable. When enabled delay timer start until DMA request transitions from active to inactive." "0: Disable.,1: Enable."
|
|
hexmask.long.byte 0x0 4.--9. 1. "REQUEST,Request Select. Select DMA request line for this channel. If memory-to-memory is selected the channel operates as if the request is always active."
|
|
bitfld.long 0x0 2.--3. "PRI,DMA Priority." "0: Highest Priority.,1: Medium High Priority.,2: Medium Low Priority.,3: Lowest Priority."
|
|
newline
|
|
bitfld.long 0x0 1. "RLDEN,Reload Enable. Setting this bit to 1 enables DMA_SRC DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer.." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 0. "EN,Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0." "0: Disable.,1: Enable."
|
|
line.long 0x4 "STATUS,DMA Channel Status Register."
|
|
eventfld.long 0x4 6. "TO_IF,Time-Out Event Interrupt Flag." "0,1"
|
|
eventfld.long 0x4 4. "BUS_ERR,Bus Error. Indicates that an AHB abort was received and the channel has been disabled." "0,1"
|
|
eventfld.long 0x4 3. "RLD_IF,Reload Event Interrupt Flag." "0,1"
|
|
newline
|
|
eventfld.long 0x4 2. "CTZ_IF,Count-to-Zero (CTZ) Interrupt Flag" "0,1"
|
|
rbitfld.long 0x4 1. "IPEND,Channel Interrupt." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
rbitfld.long 0x4 0. "STATUS,Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration address and count registers for the channel. Whenever this bit is cleared by hardware the DMA_CFG.CHEN bit is also cleared (if not.." "0: Disable.,1: Enable."
|
|
line.long 0x8 "SRC,Source Device Address. If SRCINC=1. the counter bits are incremented by 1.2. or 4. depending on the data width of each AHB cycle. For peripheral transfers. some or all of the actual address bits are fixed. If SRCINC=0. this register remains constant."
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,"
|
|
line.long 0xC "DST,Destination Device Address. For peripheral transfers. some or all of the actual address bits are fixed. If DSTINC=1. this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1. 2. or 4. depending on the data width.."
|
|
hexmask.long 0xC 0.--31. 1. "ADDR,"
|
|
line.long 0x10 "CNT,DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1. 2. or 4 depending on the data width of each AHB cycle. When the counter reaches 0. a.."
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "CNT,DMA Counter."
|
|
line.long 0x14 "SRCRLD,Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition."
|
|
hexmask.long 0x14 0.--30. 1. "ADDR,Source Address Reload Value."
|
|
line.long 0x18 "DSTRLD,Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition."
|
|
hexmask.long 0x18 0.--30. 1. "ADDR,Destination Address Reload Value."
|
|
line.long 0x1C "CNTRLD,DMA Channel Count Reload Register."
|
|
bitfld.long 0x1C 31. "EN,Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs." "0: Disable.,1: Enable."
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "CNT,Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition."
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40028100 ad:0x40028104 ad:0x40028108 ad:0x4002810C ad:0x40028110 ad:0x40028114 ad:0x40028118 ad:0x4002811C)
|
|
tree "CH[$1]"
|
|
base $2
|
|
group.long ($2+0x100)++0x1F
|
|
line.long 0x0 "CTRL,DMA Channel Control Register."
|
|
bitfld.long 0x0 31. "CTZ_IE,Count-to-zero Interrupts Enable. When enabled the IPEND will be set to 1 whenever a count-to-zero event occurs." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 30. "DIS_IE,Channel Disable Interrupt Enable. When enabled the IPEND will be set to 1 whenever CH_ST changes from 1 to 0." "0: Disable.,1: Enable."
|
|
hexmask.long.byte 0x0 24.--28. 1. "BURST_SIZE,Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field."
|
|
newline
|
|
bitfld.long 0x0 22. "DSTINC,Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 20.--21. "DSTWD,Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width)." "0: Byte.,1: Halfword.,2: Word.,?"
|
|
bitfld.long 0x0 18. "SRCINC,Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals." "0: Disable.,1: Enable."
|
|
newline
|
|
bitfld.long 0x0 16.--17. "SRCWD,Source Width. In most cases this will be the data width of each AHB transactions. However the width will be reduced in the cases where DMA_CNT indicates a smaller value." "0: Byte.,1: Halfword.,2: Word.,?"
|
|
bitfld.long 0x0 14.--15. "TO_CLKDIV,Pre-Scale Select. Selects the Pre-Scale divider for timer clock input." "0: Disable timer.,1: hclk / 256.,2: hclk / 64k.,3: hclk / 16M."
|
|
bitfld.long 0x0 11.--13. "TO_PER,Timeout Period Select." "0: Timeout of 3 to 4 prescale clocks.,1: Timeout of 7 to 8 prescale clocks.,2: Timeout of 15 to 16 prescale clocks.,3: Timeout of 31 to 32 prescale clocks.,4: Timeout of 63 to 64 prescale clocks.,5: Timeout of 127 to 128 prescale clocks.,6: Timeout of 255 to 256 prescale clocks.,7: Timeout of 511 to 512 prescale clocks."
|
|
newline
|
|
bitfld.long 0x0 10. "TO_WAIT,Request Wait Enable. When enabled delay timer start until DMA request transitions from active to inactive." "0: Disable.,1: Enable."
|
|
hexmask.long.byte 0x0 4.--9. 1. "REQUEST,Request Select. Select DMA request line for this channel. If memory-to-memory is selected the channel operates as if the request is always active."
|
|
bitfld.long 0x0 2.--3. "PRI,DMA Priority." "0: Highest Priority.,1: Medium High Priority.,2: Medium Low Priority.,3: Lowest Priority."
|
|
newline
|
|
bitfld.long 0x0 1. "RLDEN,Reload Enable. Setting this bit to 1 enables DMA_SRC DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer.." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 0. "EN,Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0." "0: Disable.,1: Enable."
|
|
line.long 0x4 "STATUS,DMA Channel Status Register."
|
|
eventfld.long 0x4 6. "TO_IF,Time-Out Event Interrupt Flag." "0,1"
|
|
eventfld.long 0x4 4. "BUS_ERR,Bus Error. Indicates that an AHB abort was received and the channel has been disabled." "0,1"
|
|
eventfld.long 0x4 3. "RLD_IF,Reload Event Interrupt Flag." "0,1"
|
|
newline
|
|
eventfld.long 0x4 2. "CTZ_IF,Count-to-Zero (CTZ) Interrupt Flag" "0,1"
|
|
rbitfld.long 0x4 1. "IPEND,Channel Interrupt." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
rbitfld.long 0x4 0. "STATUS,Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration address and count registers for the channel. Whenever this bit is cleared by hardware the DMA_CFG.CHEN bit is also cleared (if not.." "0: Disable.,1: Enable."
|
|
line.long 0x8 "SRC,Source Device Address. If SRCINC=1. the counter bits are incremented by 1.2. or 4. depending on the data width of each AHB cycle. For peripheral transfers. some or all of the actual address bits are fixed. If SRCINC=0. this register remains constant."
|
|
hexmask.long 0x8 0.--31. 1. "ADDR,"
|
|
line.long 0xC "DST,Destination Device Address. For peripheral transfers. some or all of the actual address bits are fixed. If DSTINC=1. this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1. 2. or 4. depending on the data width.."
|
|
hexmask.long 0xC 0.--31. 1. "ADDR,"
|
|
line.long 0x10 "CNT,DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1. 2. or 4 depending on the data width of each AHB cycle. When the counter reaches 0. a.."
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "CNT,DMA Counter."
|
|
line.long 0x14 "SRCRLD,Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition."
|
|
hexmask.long 0x14 0.--30. 1. "ADDR,Source Address Reload Value."
|
|
line.long 0x18 "DSTRLD,Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition."
|
|
hexmask.long 0x18 0.--30. 1. "ADDR,Destination Address Reload Value."
|
|
line.long 0x1C "CNTRLD,DMA Channel Count Reload Register."
|
|
bitfld.long 0x1C 31. "EN,Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs." "0: Disable.,1: Enable."
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. "CNT,Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition."
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32675*"))
|
|
tree "ECC (Error Correction Coding)"
|
|
base ad:0x40105400
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "EN,ECC Enable Register."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x0 10. "FLASH,Flash ECC Enable." "0,1"
|
|
bitfld.long 0x0 9. "ICC,ICC0 ECC Enable." "0,1"
|
|
bitfld.long 0x0 8. "SRAM,System RAM0 ECC Enable." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 10. "FLASH,Flash ECC Enable." "0: disabled,1: enabled"
|
|
bitfld.long 0x0 9. "ICC0,Instruction Cache 0 ECC Enable." "0: disabled,1: enabled"
|
|
bitfld.long 0x0 8. "RAM,System RAM ECC Enable." "0: disabled,1: enabled"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "FCR (Function Control Register)"
|
|
base ad:0x40000800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "FCTRL0,Register 0."
|
|
bitfld.long 0x0 25. "I2C2_SCL_FILTER_EN,I2C2 SCL Glitch Filter Enable." "0: Filter disabled.,1: Filter enabled."
|
|
bitfld.long 0x0 24. "I2C2_SDA_FILTER_EN,I2C2 SDA Glitch Filter Enable." "0: Filter disabled.,1: Filter enabled."
|
|
bitfld.long 0x0 23. "I2C1_SCL_FILTER_EN,I2C1 SCL Glitch Filter Enable." "0: Filter disabled.,1: Filter enabled."
|
|
newline
|
|
bitfld.long 0x0 22. "I2C1_SDA_FILTER_EN,I2C1 SDA Glitch Filter Enable." "0: Filter disabled.,1: Filter enabled."
|
|
bitfld.long 0x0 21. "I2C0_SCL_FILTER_EN,I2C0 SCL Glitch Filter Enable." "0: Filter disabled.,1: Filter enabled."
|
|
bitfld.long 0x0 20. "I2C0_SDA_FILTER_EN,I2C0 SDA Glitch Filter Enable." "0: Filter disabled.,1: Filter enabled."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 8. "KEYWIPE_SYS,KEYWIPE_SYS." "0,1"
|
|
endif
|
|
bitfld.long 0x0 0.--2. "ERFO_RANGE_SEL,14MHz-32MHz ERFO Frequency Range Select." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "AUTOCAL0,Register 1."
|
|
hexmask.long.word 0x4 23.--31. 1. "TRIM,150MHz HFIO Auto Calibration Trim"
|
|
hexmask.long.word 0x4 8.--19. 1. "GAIN,MU value."
|
|
bitfld.long 0x4 4. "ATOMIC,Atomic mode." "0: Not Running.,1: Running."
|
|
newline
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x4 3. "INVERT,Invert Gain." "0: Not Running.,1: Running."
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 3. "INVERT,Invert Gain." "0: do Not invert trim step.,1: Invert trim step."
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x4 3. "INVERT,Invert Gain." "0: Not Running.,1: Running."
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 2. "LOAD,Load Trim." "0,1"
|
|
bitfld.long 0x4 1. "EN,Autocalibration Run." "0: Not Running.,1: Running."
|
|
bitfld.long 0x4 0. "SEL,Auto-calibration Enable." "0: Disabled.,1: Enabled."
|
|
line.long 0x8 "AUTOCAL1,Register 2."
|
|
hexmask.long.word 0x8 0.--8. 1. "INITIAL,100MHz IPO Trim Automatic Calibration Initial Trim."
|
|
line.long 0xC "AUTOCAL2,Register 3."
|
|
hexmask.long.word 0xC 8.--20. 1. "DIV,100MHz IPO Trim Automatic Calibration Divide Factor."
|
|
hexmask.long.byte 0xC 0.--7. 1. "RUNTIME,100MHz IPO Trim Automatic Calibration Run Time."
|
|
sif (cpuis("MAX32672*"))
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "TS0,Register 4."
|
|
hexmask.long.word 0x0 0.--11. 1. "GAIN,Unsigned gain for temp sensor normalization"
|
|
line.long 0x4 "TS1,Register 5."
|
|
hexmask.long 0x4 0.--31. 1. "OFFSET,Signed offset for temp sensor correction"
|
|
group.long 0x18++0xF
|
|
line.long 0x0 "ADCREFTRIM0,ADC Reference Trim 0"
|
|
hexmask.long.byte 0x0 24.--29. 1. "VX2_TUNE,Controls tuning capacitor in fine DAC (offset binary)"
|
|
bitfld.long 0x0 16.--17. "VCM,Trimming code for VCM output of reference buffer" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "VREFM,Trimming code for VREFM output of reference buffer"
|
|
hexmask.long.byte 0x0 0.--6. 1. "VREFP,Trimming code for VREFP output of reference buffer"
|
|
line.long 0x4 "ADCREFTRIM1,ADC Reference Trim 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "VX2_TUNE,Controls tuning capacitor in fine DAC (offset binary)"
|
|
bitfld.long 0x4 16.--17. "VCM,Trimming code for VCM output of reference buffer" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "VREFM,Trimming code for VREFM output of reference buffer"
|
|
hexmask.long.byte 0x4 0.--6. 1. "VREFP,Trimming code for VREFP output of reference buffer"
|
|
line.long 0x8 "ADCREFTRIM2,ADC Reference Trim 2"
|
|
hexmask.long.byte 0x8 24.--29. 1. "VX2_TUNE,Controls tuning capacitor in fine DAC (offset binary)"
|
|
bitfld.long 0x8 16.--17. "VCM,Trimming code for VCM output of reference buffer" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 12. "IBOOST_2P048,Trimming value for extra drive current in reference buffer outputs. 2.048V" "0,1"
|
|
hexmask.long.byte 0x8 8.--11. 1. "IDRV_2P048,Trimming code for reference buffer drive strength. 2.048V"
|
|
newline
|
|
bitfld.long 0x8 4. "IBOOST_1P25,Trimming value for extra drive current in reference buffer outputs. 2.048V" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "IDRV_IP25,Trimming code for reference buffer drive strength. 1.25V"
|
|
line.long 0xC "ERFOKS,External Radio Frequency Oscillator Kick Start Control Register."
|
|
hexmask.long.word 0xC 0.--15. 1. "CTRL,Kickstart Control for ERFO."
|
|
endif
|
|
tree.end
|
|
tree "FLC (Flash Controller)"
|
|
base ad:0x0
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
tree "FLC0"
|
|
base ad:0x40029000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADDR,Flash Write Address."
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address for next operation."
|
|
line.long 0x4 "CLKDIV,Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller."
|
|
hexmask.long.byte 0x4 0.--7. 1. "CLKDIV,Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller."
|
|
line.long 0x8 "CTRL,Flash Control Register."
|
|
hexmask.long.byte 0x8 28.--31. 1. "UNLOCK,Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed."
|
|
bitfld.long 0x8 25. "LVE,Low Voltage enable." "0,1"
|
|
rbitfld.long 0x8 24. "PEND,Flash Pending. When Flash operation is in progress (busy) Flash reads and writes will fail. When PEND is set write to all Flash registers with exception of the Flash interrupt register are ignored." "0: Idle.,1: Busy."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "ERASE_CODE,Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete."
|
|
bitfld.long 0x8 2. "PGE,Page Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
bitfld.long 0x8 1. "ME,Mass Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
newline
|
|
bitfld.long 0x8 0. "WR,Write. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "INTR,Flash Interrupt Register."
|
|
bitfld.long 0x0 9. "AFIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 8. "DONEIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 1. "AF,Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware." "0: No Failure.,1: Failure occurs."
|
|
newline
|
|
bitfld.long 0x0 0. "DONE,Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
line.long 0x4 "ECCDATA,ECC Data Register."
|
|
hexmask.long.word 0x4 16.--24. 1. "ODD,Error Correction Code Even Data."
|
|
hexmask.long.word 0x4 0.--8. 1. "EVEN,Error Correction Code Odd Data."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "DATA[$1],Flash Write Data."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data next operation."
|
|
repeat.end
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "ACTRL,Access Control Register. Writing the ACTRL register with the following values in the order shown. allows read and write access to the system and user Information block:"
|
|
hexmask.long 0x0 0.--31. 1. "ACTRL,Access control."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "WELR0,WELR0"
|
|
hexmask.long 0x0 0.--31. 1. "WELR0,Access control."
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "WELR1,WELR1"
|
|
hexmask.long 0x0 0.--31. 1. "WELR1,Access control."
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "RLR0,RLR0"
|
|
hexmask.long 0x0 0.--31. 1. "RLR0,Access control."
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "RLR1,RLR1"
|
|
hexmask.long 0x0 0.--31. 1. "RLR1,Access control."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "FLC0"
|
|
base ad:0x40029000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADDR,Flash Write Address."
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address for next operation."
|
|
line.long 0x4 "CLKDIV,Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller."
|
|
hexmask.long.byte 0x4 0.--7. 1. "CLKDIV,Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller."
|
|
line.long 0x8 "CTRL,Flash Control Register."
|
|
hexmask.long.byte 0x8 28.--31. 1. "UNLOCK,Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed."
|
|
bitfld.long 0x8 25. "LVE,Low Voltage enable." "0,1"
|
|
rbitfld.long 0x8 24. "PEND,Flash Pending. When Flash operation is in progress (busy) Flash reads and writes will fail. When PEND is set write to all Flash registers with exception of the Flash interrupt register are ignored." "0: Idle.,1: Busy."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "ERASE_CODE,Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete."
|
|
bitfld.long 0x8 2. "PGE,Page Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
bitfld.long 0x8 1. "ME,Mass Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
newline
|
|
bitfld.long 0x8 0. "WR,Write. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "INTR,Flash Interrupt Register."
|
|
bitfld.long 0x0 9. "AFIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 8. "DONEIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 1. "AF,Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware." "0: No Failure.,1: Failure occurs."
|
|
newline
|
|
bitfld.long 0x0 0. "DONE,Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "ECCDATA,ECC Data Register."
|
|
hexmask.long.word 0x0 16.--24. 1. "ODD,Error Correction Code Even Data."
|
|
hexmask.long.word 0x0 0.--8. 1. "EVEN,Error Correction Code Odd Data."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "DATA$1,Flash Write Data."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data next operation."
|
|
repeat.end
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "ACTRL,Access Control Register. Writing the ACTRL register with the following values in the order shown. allows read and write access to the system and user Information block:"
|
|
hexmask.long 0x0 0.--31. 1. "ACTRL,Access control."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "WELR0,WELR0"
|
|
hexmask.long 0x0 0.--31. 1. "WELR0,Access control."
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "WELR1,WELR1"
|
|
hexmask.long 0x0 0.--31. 1. "WELR1,Access control."
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "RLR0,RLR0"
|
|
hexmask.long 0x0 0.--31. 1. "RLR0,Access control."
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "RLR1,RLR1"
|
|
hexmask.long 0x0 0.--31. 1. "RLR1,Access control."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "FLC1"
|
|
base ad:0x40029400
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADDR,Flash Write Address."
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address for next operation."
|
|
line.long 0x4 "CLKDIV,Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller."
|
|
hexmask.long.byte 0x4 0.--7. 1. "CLKDIV,Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller."
|
|
line.long 0x8 "CTRL,Flash Control Register."
|
|
hexmask.long.byte 0x8 28.--31. 1. "UNLOCK,Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed."
|
|
bitfld.long 0x8 25. "LVE,Low Voltage enable." "0,1"
|
|
rbitfld.long 0x8 24. "PEND,Flash Pending. When Flash operation is in progress (busy) Flash reads and writes will fail. When PEND is set write to all Flash registers with exception of the Flash interrupt register are ignored." "0: Idle.,1: Busy."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "ERASE_CODE,Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete."
|
|
bitfld.long 0x8 2. "PGE,Page Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
bitfld.long 0x8 1. "ME,Mass Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
newline
|
|
bitfld.long 0x8 0. "WR,Write. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "INTR,Flash Interrupt Register."
|
|
bitfld.long 0x0 9. "AFIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 8. "DONEIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 1. "AF,Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware." "0: No Failure.,1: Failure occurs."
|
|
newline
|
|
bitfld.long 0x0 0. "DONE,Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "ECCDATA,ECC Data Register."
|
|
hexmask.long.word 0x0 16.--24. 1. "ODD,Error Correction Code Even Data."
|
|
hexmask.long.word 0x0 0.--8. 1. "EVEN,Error Correction Code Odd Data."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "DATA$1,Flash Write Data."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data next operation."
|
|
repeat.end
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "ACTRL,Access Control Register. Writing the ACTRL register with the following values in the order shown. allows read and write access to the system and user Information block:"
|
|
hexmask.long 0x0 0.--31. 1. "ACTRL,Access control."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "WELR0,WELR0"
|
|
hexmask.long 0x0 0.--31. 1. "WELR0,Access control."
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "WELR1,WELR1"
|
|
hexmask.long 0x0 0.--31. 1. "WELR1,Access control."
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "RLR0,RLR0"
|
|
hexmask.long 0x0 0.--31. 1. "RLR0,Access control."
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "RLR1,RLR1"
|
|
hexmask.long 0x0 0.--31. 1. "RLR1,Access control."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
tree "FLC0"
|
|
base ad:0x40029000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADDR,Flash Write Address."
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address for next operation."
|
|
line.long 0x4 "CLKDIV,Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller."
|
|
hexmask.long.byte 0x4 0.--7. 1. "CLKDIV,Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller."
|
|
line.long 0x8 "CTRL,Flash Control Register."
|
|
hexmask.long.byte 0x8 28.--31. 1. "UNLOCK,Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed."
|
|
bitfld.long 0x8 25. "LVE,Low Voltage enable." "0,1"
|
|
rbitfld.long 0x8 24. "PEND,Flash Pending. When Flash operation is in progress (busy) Flash reads and writes will fail. When PEND is set write to all Flash registers with exception of the Flash interrupt register are ignored." "0: Idle.,1: Busy."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "ERASE_CODE,Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete."
|
|
bitfld.long 0x8 2. "PGE,Page Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
bitfld.long 0x8 1. "ME,Mass Erase. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
newline
|
|
bitfld.long 0x8 0. "WR,Write. This bit is automatically cleared after the operation." "0: No operation/complete.,1: Start operation."
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "INTR,Flash Interrupt Register."
|
|
bitfld.long 0x0 9. "AFIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 8. "DONEIE,Flash Done Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x0 1. "AF,Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware." "0: No Failure.,1: Failure occurs."
|
|
newline
|
|
bitfld.long 0x0 0. "DONE,Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion." "0: No interrupt is pending.,1: An interrupt is pending."
|
|
line.long 0x4 "ECCDATA,ECC Data Register."
|
|
hexmask.long.word 0x4 16.--24. 1. "ODD,Error Correction Code Even Data."
|
|
hexmask.long.word 0x4 0.--8. 1. "EVEN,Error Correction Code Odd Data."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "DATA$1,Flash Write Data."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data next operation."
|
|
repeat.end
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "ACTRL,Access Control Register. Writing the ACTRL register with the following values in the order shown. allows read and write access to the system and user Information block:"
|
|
hexmask.long 0x0 0.--31. 1. "ACTRL,Access control."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "WELR0,WELR0"
|
|
hexmask.long 0x0 0.--31. 1. "WELR0,Access control."
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "WELR1,WELR1"
|
|
hexmask.long 0x0 0.--31. 1. "WELR1,Access control."
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "RLR0,RLR0"
|
|
hexmask.long 0x0 0.--31. 1. "RLR0,Access control."
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "RLR1,RLR1"
|
|
hexmask.long 0x0 0.--31. 1. "RLR1,Access control."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "GCR (Global Control Registers)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "SYSCTRL,System Control."
|
|
bitfld.long 0x0 15. "CHKRES,ROM Checksum Result. This bit is only valid when CHKRD=1." "0: ROM Checksum Correct.,1: ROM Checksum Fail."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x0 14. "SWD_DIS,Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ROMDONE,ROM_DONE status. Used to disable SWD interface during system initialization procedure" "0,1"
|
|
bitfld.long 0x0 5. "FPU_DIS,Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "SBUSARB,System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset." "0: Fixed Burst abritration.,1: Round-robin scheme.,?,?"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 14. "SWD_DIS,Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set)" "0: SWD Enabled.,1: SWD Disabled."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 14. "SWD_DIS,Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set)" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 13. "CCHK,Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set software clearing this bit is ignored and the bit will remain set until the operation is completed." "0: No operation/complete.,1: Start operation."
|
|
newline
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 12. "ROMDONE,ROM_DONE status. Used to disable SWD interface during system initialization procedure" "0,1"
|
|
endif
|
|
bitfld.long 0x0 6. "ICC0_FLUSH,Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4." "0: Normal Code Cache Operation,1: Code Caches and CPU instruction buffer are.."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 5. "FPU_DIS,Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4" "0: FPU Enabled.,1: FPU Disabled."
|
|
bitfld.long 0x0 4. "FLASH_PAGE_FLIP,." "0: Physical layout matches logical layout.,1: Bottom half mapped to logical top half and vice.."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 5. "FPU_DIS,Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4" "0,1"
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 1.--2. "SBUSARB,System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset." "0: Fixed Burst abritration.,1: Round-robin scheme.,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 1.--2. "SBUSARB,System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset." "0: Fixed Burst abritration.,1: Round-robin scheme.,?,?"
|
|
endif
|
|
line.long 0x4 "RST0,Reset."
|
|
bitfld.long 0x4 31. "SYS,System Reset. Setting this bit to 1 resets the CPU core and all peripherals including the watchdog timer." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
bitfld.long 0x4 30. "PERIPH,Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core the watchdog timer and all GPIO pins are unaffected by this reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
newline
|
|
bitfld.long 0x4 29. "SOFT,Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
bitfld.long 0x4 28. "UART2,UART2 Reset. Setting this bit to 1 resets all UART 2 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 26. "ADC,ADC Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
endif
|
|
bitfld.long 0x4 24. "TRNG,TRNG Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 18. "CTB,Crypto Toolbox Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
endif
|
|
bitfld.long 0x4 17. "RTC,Real Time Clock Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
newline
|
|
bitfld.long 0x4 16. "I2C0,I2C0 Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
bitfld.long 0x4 15. "SPI2,SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
newline
|
|
bitfld.long 0x4 14. "SPI1,SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
bitfld.long 0x4 13. "SPI0,SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
newline
|
|
bitfld.long 0x4 12. "UART1,UART1 Reset. Setting this bit to 1 resets all UART 1 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
bitfld.long 0x4 11. "UART0,UART0 Reset. Setting this bit to 1 resets all UART 0 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
newline
|
|
bitfld.long 0x4 8. "TMR3,Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
bitfld.long 0x4 7. "TMR2,Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
newline
|
|
bitfld.long 0x4 6. "TMR1,Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
bitfld.long 0x4 5. "TMR0,Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
newline
|
|
bitfld.long 0x4 3. "GPIO1,GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
bitfld.long 0x4 2. "GPIO0,GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
newline
|
|
bitfld.long 0x4 1. "WDT0,Watchdog Timer Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
bitfld.long 0x4 0. "DMA,DMA Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
line.long 0x8 "CLKCTRL,Clock Control."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
rbitfld.long 0x8 31. "EXTCLK_RDY,External Clock (GPIO0[11] AF2)" "0: Is not Ready.,1: Is Ready."
|
|
rbitfld.long 0x8 29. "INRO_RDY,8kHz Low Frequency Reference Clock Ready." "0: Is not Ready.,1: Is Ready."
|
|
newline
|
|
rbitfld.long 0x8 28. "IBRO_RDY,8MHz HIRC Ready." "0: Is not Ready.,1: Is Ready."
|
|
rbitfld.long 0x8 27. "IPO_RDY,96MHz HIRC Ready." "0: Is not Ready.,1: Is Ready."
|
|
newline
|
|
rbitfld.long 0x8 25. "ERTCO_RDY,32kHz Crystal Oscillator Ready" "0: Is not Ready.,1: Is Ready."
|
|
rbitfld.long 0x8 24. "ERFO_RDY,32MHz Crystal Oscillator Ready" "0: Is not Ready.,1: Is Ready."
|
|
newline
|
|
bitfld.long 0x8 21. "IBRO_VS,8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M." "0: VCore Supply,1: Dedicated 1v regulated supply."
|
|
bitfld.long 0x8 17. "ERTCO_EN,32kHz Crystal Oscillator Enable." "0: Is Disabled.,1: Is Enabled."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
rbitfld.long 0x8 31. "EXTCLK_RDY,External Clock (GPIO0[11] AF2)" "0: Is not Ready.,1: Is Ready."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
rbitfld.long 0x8 31. "EXTCLK_RDY,External Clock (GPIO0[11] AF2)" "0: Is not Ready.,1: Is Ready."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
rbitfld.long 0x8 29. "INRO_RDY,8kHz Low Frequency Reference Clock Ready." "0: Is not Ready.,1: Is Ready."
|
|
rbitfld.long 0x8 28. "IBRO_RDY,8MHz HIRC Ready." "0: Is not Ready.,1: Is Ready."
|
|
newline
|
|
rbitfld.long 0x8 27. "IPO_RDY,96MHz HIRC Ready." "0: Is not Ready.,1: Is Ready."
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
rbitfld.long 0x8 29. "INRO_RDY,8kHz Low Frequency Reference Clock Ready." "0: Is not Ready.,1: Is Ready."
|
|
rbitfld.long 0x8 28. "IBRO_RDY,8MHz HIRC Ready." "0: Is not Ready.,1: Is Ready."
|
|
newline
|
|
rbitfld.long 0x8 27. "IPO_RDY,96MHz HIRC Ready." "0: Is not Ready.,1: Is Ready."
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
rbitfld.long 0x8 25. "ERTCO_RDY,32kHz Crystal Oscillator Ready" "0: Is not Ready.,1: Is Ready."
|
|
newline
|
|
rbitfld.long 0x8 24. "ERFO_RDY,32MHz Crystal Oscillator Ready" "0: Is not Ready.,1: Is Ready."
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
rbitfld.long 0x8 25. "ERTCO_RDY,32kHz Crystal Oscillator Ready" "0: Is not Ready.,1: Is Ready."
|
|
newline
|
|
rbitfld.long 0x8 24. "ERFO_RDY,32MHz Crystal Oscillator Ready" "0: Is not Ready.,1: Is Ready."
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x8 21. "IBRO_VS,8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M." "0: Dedicated 1v regulated supply.,1: VCore Supply"
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x8 21. "IBRO_VS,8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M." "0: VCore Supply,1: Dedicated 1v regulated supply."
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 20. "IBRO_EN,8MHz High Frequency Internal Reference Clock Enable." "0: Is Disabled.,1: Is Enabled."
|
|
bitfld.long 0x8 19. "IPO_EN,96MHz High Frequency Internal Reference Clock Enable." "0: Is Disabled.,1: Is Enabled."
|
|
newline
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x8 17. "ERTCO_EN,32kHz Crystal Oscillator Enable." "0: Is Disabled.,1: Is Enabled."
|
|
endif
|
|
bitfld.long 0x8 16. "ERFO_EN,32MHz Crystal Oscillator Enable." "0: Is Disabled.,1: Is Enabled."
|
|
newline
|
|
bitfld.long 0x8 14.--15. "IPO_DIV,Divides the HIRC96M clock before the system clock prescaler will affect HIRC96M Autocalibration." "0: divide clock by 1,1: divide clock by 2,2: divide clock by 4,3: divide clock by 8"
|
|
rbitfld.long 0x8 13. "SYSCLK_RDY,Clock Ready. This read only bit reflects whether the currently selected system clock source is running." "0: Switchover to the new clock source (as selected..,1: System clock running from CLKSEL clock source."
|
|
newline
|
|
bitfld.long 0x8 9.--11. "SYSCLK_SEL,Clock Source Select. This 3 bit field selects the source for the system clock." "?,?,2: 32MHz Crystal is used for the system clock.,3: 80kHz LIRC is used for the system clock.,4: The internal 96 MHz oscillator is used for the..,5: The internal 8 MHz oscillator is used for the..,6: 32kHz is used for the system clock.,7: External clock on gpio0 11."
|
|
bitfld.long 0x8 6.--8. "SYSCLK_DIV,Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0." "0: Divide by 1.,1: Divide by 2.,2: Divide by 4.,3: Divide by 8.,4: Divide by 16.,5: Divide by 32.,6: Divide by 64.,7: Divide by 128."
|
|
line.long 0xC "PM,Power Management."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0xC 20. "ERFO_BP,32MHz Oscillator Bypass" "0,1"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0xC 20. "ERFO_BP,32MHz Oscillator Bypass" "0: Bypass Disabled.,1: Bypass Enabled."
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0xC 20. "ERFO_BP,32MHz Oscillator Bypass" "0,1"
|
|
endif
|
|
bitfld.long 0xC 17. "IBRO_PD,8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode." "0: Mode is Active.,1: Powered down in DEEPSLEEP."
|
|
newline
|
|
bitfld.long 0xC 16. "IPO_PD,96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode." "0: Mode is Active.,1: Powered down in DEEPSLEEP."
|
|
bitfld.long 0xC 12. "ERFO_PD,32MHz power down. This bit selects 32MHz Crystal power state in DEEPSLEEP mode." "0: Mode is Active.,1: Powered down in DEEPSLEEP."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0xC 9. "AINCOMP_WE,AINCOMP Wake Up Enable. This bit enables AINCOMP as wakeup source." "0: Wake Up Disable.,1: Wake Up Enable."
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 8. "LPUART0_WE,LPUART3 Wake Up Enable. This bit enables LPUART3 as wakeup source." "0: Wake Up Disable.,1: Wake Up Enable."
|
|
newline
|
|
bitfld.long 0xC 7. "LPTMR1_WE,TIMER5 Wake Up Enable. This bit enables TIMER5 as wakeup source." "0: Wake Up Disable.,1: Wake Up Enable."
|
|
bitfld.long 0xC 6. "LPTMR0_WE,TIMER4 Wake Up Enable. This bit enables TIMER4 as wakeup source." "0: Wake Up Disable.,1: Wake Up Enable."
|
|
newline
|
|
bitfld.long 0xC 5. "RTC_WE,RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled the desired RTC alarm must be configured via the RTC control registers." "0: Wake Up Disable.,1: Wake Up Enable."
|
|
bitfld.long 0xC 4. "GPIO_WE,GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set." "0: Wake Up Disable.,1: Wake Up Enable."
|
|
newline
|
|
bitfld.long 0xC 0.--2. "MODE,Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode." "0: Active Mode.,?,?,3: Shutdown Mode.,4: Backup Mode.,?,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PCLKDIV,Peripheral Clock Divider."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x0 16. "DIV_CLK_OUT_EN,DIV_CLK_OUT Enable" "0,1"
|
|
bitfld.long 0x0 14.--15. "DIV_CLK_OUT_CTRL,DIV_CLK_OUT Control" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "AON_CLKDIV,Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 16. "DIV_CLK_OUT_EN,DIV_CLK_OUT Enable" "0: HART clock Disable.,1: HART clock Enable."
|
|
newline
|
|
bitfld.long 0x0 14.--15. "DIV_CLK_OUT_CTRL,DIV_CLK_OUT Control" "0: HART clock off.,1: HART clock HIRC8M Div 2.,2: HART clock XO32M Div 4.,3: HART clock XO32M Div 8."
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 16. "DIV_CLK_OUT_EN,DIV_CLK_OUT Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "DIV_CLK_OUT_CTRL,DIV_CLK_OUT Control" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 0.--2. "AON_CLKDIV,Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 0.--1. "AON_CLKDIV,Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider" "0,1,2,3"
|
|
endif
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "PCLKDIS0,Peripheral Clock Disable."
|
|
bitfld.long 0x0 28. "I2C1,I2C 1 Disable." "0: enable it.,1: disable it."
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 23. "ADC,ADC Clock Disable." "0: enable it.,1: disable it."
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 18. "TMR3,Timer 3 Disable." "0: enable it.,1: disable it."
|
|
newline
|
|
bitfld.long 0x0 17. "TMR2,Timer 2 Disable." "0: enable it.,1: disable it."
|
|
newline
|
|
bitfld.long 0x0 16. "TMR1,Timer 1 Disable." "0: enable it.,1: disable it."
|
|
bitfld.long 0x0 15. "TMR0,Timer 0 Disable." "0: enable it.,1: disable it."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 14. "CTB,Crypto Disable." "0: enable it.,1: disable it."
|
|
endif
|
|
bitfld.long 0x0 13. "I2C0,I2C 0 Disable." "0: enable it.,1: disable it."
|
|
newline
|
|
bitfld.long 0x0 10. "UART1,UART 1 Disable." "0: enable it.,1: disable it."
|
|
bitfld.long 0x0 9. "UART0,UART 0 Disable." "0: enable it.,1: disable it."
|
|
newline
|
|
bitfld.long 0x0 8. "SPI2,SPI 2 Disable." "0: enable it.,1: disable it."
|
|
bitfld.long 0x0 7. "SPI1,SPI 1 Disable." "0: enable it.,1: disable it."
|
|
newline
|
|
bitfld.long 0x0 6. "SPI0,SPI 0 Disable." "0: enable it.,1: disable it."
|
|
bitfld.long 0x0 5. "DMA,DMA Disable." "0: enable it.,1: disable it."
|
|
newline
|
|
bitfld.long 0x0 1. "GPIO1,GPIO1 Disable." "0: enable it.,1: disable it."
|
|
bitfld.long 0x0 0. "GPIO0,GPIO0 Disable." "0: enable it.,1: disable it."
|
|
line.long 0x4 "MEMCTRL,Memory Clock Control Register."
|
|
bitfld.long 0x4 13. "ROMLS_EN,ROM Light Sleep Mode." "0: RAM is active.,1: RAM is in Light Sleep mode."
|
|
bitfld.long 0x4 12. "ICC0LS_EN,ICache RAM Light Sleep Mode." "0: RAM is active.,1: RAM is in Light Sleep mode."
|
|
newline
|
|
bitfld.long 0x4 11. "RAM3LS_EN,System RAM 3 Light Sleep Mode." "0: RAM is active.,1: RAM is in Light Sleep mode."
|
|
bitfld.long 0x4 10. "RAM2LS_EN,System RAM 2 Light Sleep Mode." "0: RAM is active.,1: RAM is in Light Sleep mode."
|
|
newline
|
|
bitfld.long 0x4 9. "RAM1LS_EN,System RAM 1 Light Sleep Mode." "0: RAM is active.,1: RAM is in Light Sleep mode."
|
|
bitfld.long 0x4 8. "RAM0LS_EN,System RAM 0 Light Sleep Mode." "0: RAM is active.,1: RAM is in Light Sleep mode."
|
|
newline
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x4 4. "RAMWS_EN,System RAM Wait State enable" "0,1"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 4. "RAMWS_EN,System RAM Wait State enable" "0: no SRAM wait state.,1: SRAM wait state enabled."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x4 4. "RAMWS_EN,System RAM Wait State enable" "0,1"
|
|
endif
|
|
bitfld.long 0x4 0.--2. "FWS,Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2." "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "MEMZ,Memory Zeroize Control."
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x8 4. "ICC0,Instruction Cache." "0: No operation/complete.,1: Start operation."
|
|
bitfld.long 0x8 3. "RAMCB,System RAM check bit zeroization." "0: No operation/complete.,1: Start operation."
|
|
newline
|
|
bitfld.long 0x8 2. "RAM2,System RAM 2 zeroization." "0: No operation/complete.,1: Start operation."
|
|
bitfld.long 0x8 1. "RAM1,System RAM 1 zeroization." "0: No operation/complete.,1: Start operation."
|
|
newline
|
|
bitfld.long 0x8 0. "RAM0,System RAM 0 Block." "0: No operation/complete.,1: Start operation."
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x8 2. "ICC0,Instruction Cache." "0: No operation/complete.,1: Start operation."
|
|
newline
|
|
bitfld.long 0x8 1. "RAMCB,System RAM check bit zeroization." "0: No operation/complete.,1: Start operation."
|
|
bitfld.long 0x8 0. "RAM,System RAM Block." "0: No operation/complete.,1: Start operation."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x8 2. "ICC0,Instruction Cache." "0: No operation/complete.,1: Start operation."
|
|
bitfld.long 0x8 1. "RAMCB,System RAM check bit zeroization." "0: No operation/complete.,1: Start operation."
|
|
newline
|
|
bitfld.long 0x8 0. "RAM,System RAM Block." "0: No operation/complete.,1: Start operation."
|
|
endif
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "SYSST,System Status Register."
|
|
bitfld.long 0x0 0. "ICELOCK,ARM ICE Lock Status." "0: ICE is unlocked.,1: ICE is locked."
|
|
line.long 0x4 "RST1,Reset 1."
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 25. "QDEC,QDEC Reset." "0: Reset complete.,1: Reset."
|
|
endif
|
|
bitfld.long 0x4 23. "I2S,I2S Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 23. "I2S,I2S Reset." "0: Reset complete.,1: Reset."
|
|
endif
|
|
bitfld.long 0x4 17. "I2C2,I2C2 Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 17. "I2C2,I2C2 Reset." "0: Reset complete.,1: Reset."
|
|
endif
|
|
bitfld.long 0x4 14. "AC,AC Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 14. "AC,AC Reset." "0: Reset complete.,1: Reset."
|
|
endif
|
|
bitfld.long 0x4 10. "AES,AES Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 10. "AES,WDT1 Reset." "0: Reset complete.,1: Reset."
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x4 9. "CRC,CRC Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x4 9. "CRC,CRC Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
|
|
endif
|
|
bitfld.long 0x4 8. "WDT1,WDT1 Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 8. "WDT1,WDT1 Reset." "0: Reset complete.,1: Reset."
|
|
endif
|
|
bitfld.long 0x4 0. "I2C1,I2C1 Reset." "0: Reset complete.,1: Starts reset or indicates reset in progress."
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 0. "I2C1,I2C1 Reset." "0: Reset complete.,1: Reset."
|
|
endif
|
|
line.long 0x8 "PCLKDIS1,Peripheral Clock Disable."
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x8 25. "QDEC,Quadrature Decoder Interface Clock Disable." "0: Enable.,1: Disable."
|
|
endif
|
|
bitfld.long 0x8 23. "I2S,I2S Clock Disable." "0: Enable.,1: Disable."
|
|
newline
|
|
bitfld.long 0x8 21. "I2C2,I2C2 Disable." "0: Enable.,1: Disable."
|
|
bitfld.long 0x8 15. "AES,AES Disable." "0: Enable.,1: Disable."
|
|
newline
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x8 14. "CRC,CRC Disable." "0: Enable.,1: Disable."
|
|
bitfld.long 0x8 5. "WWDT1,WDT1 Disable." "0: Enable.,1: Disable."
|
|
newline
|
|
bitfld.long 0x8 4. "WWDT0,WDT0 Disable." "0: Enable.,1: Disable."
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x8 14. "CRC,CRC Disable." "0: Enable.,1: Disable."
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 11. "ICC0,ICACHE Disable." "0: Enable.,1: Disable."
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x8 5. "WDT1,WDT1 Disable." "0: Enable.,1: Disable."
|
|
newline
|
|
bitfld.long 0x8 4. "WDT0,WDT0 Disable." "0: Enable.,1: Disable."
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x8 5. "WWDT1,WDT1 Disable." "0: Enable.,1: Disable."
|
|
newline
|
|
bitfld.long 0x8 4. "WWDT0,WDT0 Disable." "0: Enable.,1: Disable."
|
|
endif
|
|
newline
|
|
bitfld.long 0x8 2. "TRNG,TRNG Disable." "0: Enable.,1: Disable."
|
|
newline
|
|
bitfld.long 0x8 1. "UART2,UART2 Disable." "0: Enable.,1: Disable."
|
|
line.long 0xC "EVENTEN,Event Enable Register."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0xC 2. "TX,Enable TXEV pin event. When this bit is set TXEV event from the CPU is output to GPIO[21]." "0,1"
|
|
bitfld.long 0xC 1. "RX,Enable RXEV pin event. When this bit is set a logic high of GPIO0[20] will cause an RXEV event to wake the CPU from WFE sleep mode." "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "DMA,Enable DMA event. When this bit is set a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0xC 2. "TX,Enable TXEV pin event. When this bit is set TXEV event from the CPU is output to GPIO[21] (AF1)." "0: Event Disable.,1: Event Enable."
|
|
newline
|
|
bitfld.long 0xC 1. "RX,Enable RXEV pin event. When this bit is set a logic high of GPIO0[20] (AF1) will cause an RXEV event to wake the CPU from WFE sleep mode." "0: Event Disable.,1: Event Enable."
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0xC 2. "TX,Enable TXEV pin event. When this bit is set TXEV event from the CPU is output to GPIO[21]." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "RX,Enable RXEV pin event. When this bit is set a logic high of GPIO0[20] will cause an RXEV event to wake the CPU from WFE sleep mode." "0,1"
|
|
bitfld.long 0xC 0. "DMA,Enable DMA event. When this bit is set a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode." "0,1"
|
|
endif
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "REVISION,Revision Register."
|
|
hexmask.long.word 0x0 0.--15. 1. "REVISION,Manufacturer Chip Revision."
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "SYSIE,System Status Interrupt Enable Register."
|
|
bitfld.long 0x0 0. "ICEUNLOCK,ARM ICE Unlock Interrupt Enable." "0: disabled.,1: enabled."
|
|
group.long 0x64++0xF
|
|
line.long 0x0 "ECCERR,ECC Error Register"
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 5. "FLASH1,ECC Flash1 Error Flag. Write 1 to clear." "0,1"
|
|
bitfld.long 0x0 4. "FLASH0,ECC Flash0 Error Flag. Write 1 to clear." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ICC0,ECC Icache Error Flag. Write 1 to clear." "0,1"
|
|
bitfld.long 0x0 2. "RAM3,ECC System RAM3 Error Flag. Write 1 to clear." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RAM2,ECC System RAM2 Error Flag. Write 1 to clear." "0,1"
|
|
bitfld.long 0x0 0. "RAM0_1,ECC System RAM0 and RAM1 Error Flag. Write 1 to clear." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x0 2. "FLASH,ECC Flash Error Flag. Write 1 to clear." "0,1"
|
|
bitfld.long 0x0 1. "ICC0,ECC Icache Error Flag. Write 1 to clear." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RAM,ECC System RAM0 Error Flag. Write 1 to clear." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 2. "FLASH,ECC Flash Error Flag. Write 1 to clear." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ICC0,ECC Icache Error Flag. Write 1 to clear." "0,1"
|
|
bitfld.long 0x0 0. "RAM,ECC System RAM0 Error Flag. Write 1 to clear." "0,1"
|
|
endif
|
|
line.long 0x4 "ECCCED,ECC Not Double Error Detect Register"
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 5. "FLASH1,ECC Flash1 Error Flag. Write 1 to clear." "0,1"
|
|
bitfld.long 0x4 4. "FLASH0,ECC Flash0 Error Flag. Write 1 to clear." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ICC0,ECC Icache Error Flag. Write 1 to clear." "0,1"
|
|
bitfld.long 0x4 2. "RAM3,ECC System RAM3 Error Flag. Write 1 to clear." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RAM2,ECC System RAM2 Error Flag. Write 1 to clear." "0,1"
|
|
bitfld.long 0x4 0. "RAM0_1,ECC System RAM0 and RAM1 Error Flag. Write 1 to clear." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x4 2. "FLASH,ECC Flash0 Not Double Error Detect. Write 1 to clear." "0,1"
|
|
bitfld.long 0x4 1. "ICC0,ECC Icache Not Double Error Detect. Write 1 to clear." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RAM,ECC System RAM0 Error Flag. Write 1 to clear." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x4 2. "FLASH,ECC Flash0 Not Double Error Detect. Write 1 to clear." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ICC0,ECC Icache Not Double Error Detect. Write 1 to clear." "0,1"
|
|
bitfld.long 0x4 0. "RAM,ECC System RAM0 Error Flag. Write 1 to clear." "0,1"
|
|
endif
|
|
line.long 0x8 "ECCIE,ECC IRQ Enable Register"
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x8 5. "FLASH1,ECC Flash1 Error interrupt enable." "0: interrupt disabled.,1: interrupt enabled."
|
|
bitfld.long 0x8 4. "FLASH0,ECC Flash0 Error interrupt enable." "0: interrupt disabled.,1: interrupt enabled."
|
|
newline
|
|
bitfld.long 0x8 3. "ICC0,ECC Icache Error interrupt enable." "0: interrupt disabled.,1: interrupt enabled."
|
|
bitfld.long 0x8 2. "RAM3,ECC System RAM3 Error interrupt enable." "0: interrupt disabled.,1: interrupt enabled."
|
|
newline
|
|
bitfld.long 0x8 1. "RAM2,ECC System RAM2 Error interrupt enable." "0: interrupt disabled.,1: interrupt enabled."
|
|
bitfld.long 0x8 0. "RAM0_1,ECC System RAM0 and RAM1 Error interrupt enable." "0: interrupt disabled.,1: interrupt enabled."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x8 2. "FLASH,ECC Flash0 NError Interrup Enable" "0,1"
|
|
bitfld.long 0x8 1. "ICC0,ECC Icache0 Error Interrup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RAM,ECC System RAM0 Error Interrup Enable" "0,1"
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x8 2. "FLASH,ECC Flash0 NError Interrup Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ICC0,ECC Icache0 Error Interrup Enable" "0,1"
|
|
bitfld.long 0x8 0. "RAM,ECC System RAM0 Error Interrup Enable" "0,1"
|
|
endif
|
|
line.long 0xC "ECCADDR,ECC Error Address Register"
|
|
bitfld.long 0xC 31. "TAGRAMERR,ECC Error Address/TAG RAM Error." "0,1"
|
|
bitfld.long 0xC 30. "TAGRAMBANK,ECC Error Address/TAG RAM Error Bank." "0,1"
|
|
newline
|
|
hexmask.long.word 0xC 16.--29. 1. "TAGRAMADDR,ECC Error Address/TAG RAM Error Address."
|
|
bitfld.long 0xC 15. "DATARAMERR,ECC Error Address/DATA RAM Error Address." "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "DATARAMBANK,ECC Error Address/DATA RAM Error Bank." "0,1"
|
|
hexmask.long.word 0xC 0.--13. 1. "DATARAMADDR,ECC Error Address/TAG RAM Error Address."
|
|
tree.end
|
|
tree "GPIO (General Purpose Input/Outputs)"
|
|
base ad:0x0
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32672*"))
|
|
tree "GPIO0"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "EN0,GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_EN,Mask of all of the pins on the port."
|
|
line.long 0x4 "EN0_SET,GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x4 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x8 "EN0_CLR,GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0xC "OUTEN,GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port."
|
|
hexmask.long 0xC 0.--31. 1. "EN,Mask of all of the pins on the port."
|
|
line.long 0x10 "OUTEN_SET,GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x14 "OUTEN_CLR,GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x18 "OUT,GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly. or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers."
|
|
hexmask.long 0x18 0.--31. 1. "GPIO_OUT,Mask of all of the pins on the port."
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "OUT_SET,GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1. without affecting other bits in that register."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Mask of all of the pins on the port."
|
|
line.long 0x4 "OUT_CLR,GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0. without affecting other bits in that register."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_OUT_CLR,Mask of all of the pins on the port."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "IN,GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_IN,Mask of all of the pins on the port."
|
|
group.long 0x28++0x17
|
|
line.long 0x0 "INTMODE,GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_INTMODE,Mask of all of the pins on the port."
|
|
line.long 0x4 "INTPOL,GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_INTPOL,Mask of all of the pins on the port."
|
|
line.long 0x8 "INEN,GPIO Input Enable"
|
|
line.long 0xC "INTEN,GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_INTEN,Mask of all of the pins on the port."
|
|
line.long 0x10 "INTEN_SET,GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "GPIO_INTEN_SET,Mask of all of the pins on the port."
|
|
line.long 0x14 "INTEN_CLR,GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "GPIO_INTEN_CLR,Mask of all of the pins on the port."
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "INTFL,GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_INTFL,Mask of all of the pins on the port."
|
|
group.long 0x48++0xF
|
|
line.long 0x0 "INTFL_CLR,GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0. without affecting other bits in that register."
|
|
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x4 "WKEN,GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_WKEN,Mask of all of the pins on the port."
|
|
line.long 0x8 "WKEN_SET,GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0xC "WKEN_CLR,GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
group.long 0x5C++0x23
|
|
line.long 0x0 "DUALEDGE,GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_DUALEDGE,Mask of all of the pins on the port."
|
|
line.long 0x4 "PADCTRL0,GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_PADCTRL0,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
|
|
line.long 0x8 "PADCTRL1,GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
|
|
hexmask.long 0x8 0.--31. 1. "GPIO_PADCTRL1,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
|
|
line.long 0xC "EN1,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_EN1,Mask of all of the pins on the port."
|
|
line.long 0x10 "EN1_SET,GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x14 "EN1_CLR,GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x18 "EN2,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
|
|
hexmask.long 0x18 0.--31. 1. "GPIO_EN2,Mask of all of the pins on the port."
|
|
line.long 0x1C "EN2_SET,GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1. without affecting other bits in that register."
|
|
hexmask.long 0x1C 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x20 "EN2_CLR,GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0. without affecting other bits in that register."
|
|
hexmask.long 0x20 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
group.long 0xA8++0x13
|
|
line.long 0x0 "HYSEN,GPIO Input Hysteresis Enable."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_HYSEN,Mask of all of the pins on the port."
|
|
line.long 0x4 "SRSEL,GPIO Slew Rate Enable Register."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_SRSEL,Mask of all of the pins on the port."
|
|
line.long 0x8 "DS0,GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
|
|
hexmask.long 0x8 0.--31. 1. "GPIO_DS0,Mask of all of the pins on the port."
|
|
line.long 0xC "DS1,GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_DS1,Mask of all of the pins on the port."
|
|
line.long 0x10 "PS,GPIO Pull Select Mode."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
sif (cpuis("MAX32672*"))
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "VSSEL,GPIO Voltage Select."
|
|
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32672*"))
|
|
tree "GPIO1"
|
|
base ad:0x40009000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "EN0,GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_EN,Mask of all of the pins on the port."
|
|
line.long 0x4 "EN0_SET,GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x4 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x8 "EN0_CLR,GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0xC "OUTEN,GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port."
|
|
hexmask.long 0xC 0.--31. 1. "EN,Mask of all of the pins on the port."
|
|
line.long 0x10 "OUTEN_SET,GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x14 "OUTEN_CLR,GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x18 "OUT,GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly. or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers."
|
|
hexmask.long 0x18 0.--31. 1. "GPIO_OUT,Mask of all of the pins on the port."
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "OUT_SET,GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1. without affecting other bits in that register."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Mask of all of the pins on the port."
|
|
line.long 0x4 "OUT_CLR,GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0. without affecting other bits in that register."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_OUT_CLR,Mask of all of the pins on the port."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "IN,GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_IN,Mask of all of the pins on the port."
|
|
group.long 0x28++0x17
|
|
line.long 0x0 "INTMODE,GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_INTMODE,Mask of all of the pins on the port."
|
|
line.long 0x4 "INTPOL,GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_INTPOL,Mask of all of the pins on the port."
|
|
line.long 0x8 "INEN,GPIO Input Enable"
|
|
line.long 0xC "INTEN,GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_INTEN,Mask of all of the pins on the port."
|
|
line.long 0x10 "INTEN_SET,GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "GPIO_INTEN_SET,Mask of all of the pins on the port."
|
|
line.long 0x14 "INTEN_CLR,GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "GPIO_INTEN_CLR,Mask of all of the pins on the port."
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "INTFL,GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_INTFL,Mask of all of the pins on the port."
|
|
group.long 0x48++0xF
|
|
line.long 0x0 "INTFL_CLR,GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0. without affecting other bits in that register."
|
|
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x4 "WKEN,GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_WKEN,Mask of all of the pins on the port."
|
|
line.long 0x8 "WKEN_SET,GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0xC "WKEN_CLR,GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
group.long 0x5C++0x23
|
|
line.long 0x0 "DUALEDGE,GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_DUALEDGE,Mask of all of the pins on the port."
|
|
line.long 0x4 "PADCTRL0,GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_PADCTRL0,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
|
|
line.long 0x8 "PADCTRL1,GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
|
|
hexmask.long 0x8 0.--31. 1. "GPIO_PADCTRL1,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
|
|
line.long 0xC "EN1,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_EN1,Mask of all of the pins on the port."
|
|
line.long 0x10 "EN1_SET,GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x14 "EN1_CLR,GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x18 "EN2,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
|
|
hexmask.long 0x18 0.--31. 1. "GPIO_EN2,Mask of all of the pins on the port."
|
|
line.long 0x1C "EN2_SET,GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1. without affecting other bits in that register."
|
|
hexmask.long 0x1C 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x20 "EN2_CLR,GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0. without affecting other bits in that register."
|
|
hexmask.long 0x20 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
group.long 0xA8++0x13
|
|
line.long 0x0 "HYSEN,GPIO Input Hysteresis Enable."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_HYSEN,Mask of all of the pins on the port."
|
|
line.long 0x4 "SRSEL,GPIO Slew Rate Enable Register."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_SRSEL,Mask of all of the pins on the port."
|
|
line.long 0x8 "DS0,GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
|
|
hexmask.long 0x8 0.--31. 1. "GPIO_DS0,Mask of all of the pins on the port."
|
|
line.long 0xC "DS1,GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_DS1,Mask of all of the pins on the port."
|
|
line.long 0x10 "PS,GPIO Pull Select Mode."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
sif (cpuis("MAX32672*"))
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "VSSEL,GPIO Voltage Select."
|
|
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
tree "GPIO0"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "EN0,GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_EN,Mask of all of the pins on the port."
|
|
line.long 0x4 "EN0_SET,GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x4 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x8 "EN0_CLR,GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0xC "OUTEN,GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port."
|
|
hexmask.long 0xC 0.--31. 1. "EN,Mask of all of the pins on the port."
|
|
line.long 0x10 "OUTEN_SET,GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x14 "OUTEN_CLR,GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x18 "OUT,GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly. or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers."
|
|
hexmask.long 0x18 0.--31. 1. "GPIO_OUT,Mask of all of the pins on the port."
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "OUT_SET,GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1. without affecting other bits in that register."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Mask of all of the pins on the port."
|
|
line.long 0x4 "OUT_CLR,GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0. without affecting other bits in that register."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_OUT_CLR,Mask of all of the pins on the port."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "IN,GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_IN,Mask of all of the pins on the port."
|
|
group.long 0x28++0x17
|
|
line.long 0x0 "INTMODE,GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_INTMODE,Mask of all of the pins on the port."
|
|
line.long 0x4 "INTPOL,GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_INTPOL,Mask of all of the pins on the port."
|
|
line.long 0x8 "INEN,GPIO Input Enable"
|
|
line.long 0xC "INTEN,GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_INTEN,Mask of all of the pins on the port."
|
|
line.long 0x10 "INTEN_SET,GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "GPIO_INTEN_SET,Mask of all of the pins on the port."
|
|
line.long 0x14 "INTEN_CLR,GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "GPIO_INTEN_CLR,Mask of all of the pins on the port."
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "INTFL,GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_INTFL,Mask of all of the pins on the port."
|
|
group.long 0x48++0xF
|
|
line.long 0x0 "INTFL_CLR,GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0. without affecting other bits in that register."
|
|
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x4 "WKEN,GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_WKEN,Mask of all of the pins on the port."
|
|
line.long 0x8 "WKEN_SET,GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0xC "WKEN_CLR,GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
group.long 0x5C++0x23
|
|
line.long 0x0 "DUALEDGE,GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_DUALEDGE,Mask of all of the pins on the port."
|
|
line.long 0x4 "PADCTRL0,GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_PADCTRL0,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
|
|
line.long 0x8 "PADCTRL1,GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
|
|
hexmask.long 0x8 0.--31. 1. "GPIO_PADCTRL1,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
|
|
line.long 0xC "EN1,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_EN1,Mask of all of the pins on the port."
|
|
line.long 0x10 "EN1_SET,GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x14 "EN1_CLR,GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x18 "EN2,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
|
|
hexmask.long 0x18 0.--31. 1. "GPIO_EN2,Mask of all of the pins on the port."
|
|
line.long 0x1C "EN2_SET,GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1. without affecting other bits in that register."
|
|
hexmask.long 0x1C 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x20 "EN2_CLR,GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0. without affecting other bits in that register."
|
|
hexmask.long 0x20 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
group.long 0xA8++0x13
|
|
line.long 0x0 "HYSEN,GPIO Input Hysteresis Enable."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_HYSEN,Mask of all of the pins on the port."
|
|
line.long 0x4 "SRSEL,GPIO Slew Rate Enable Register."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_SRSEL,Mask of all of the pins on the port."
|
|
line.long 0x8 "DS0,GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
|
|
hexmask.long 0x8 0.--31. 1. "GPIO_DS0,Mask of all of the pins on the port."
|
|
line.long 0xC "DS1,GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_DS1,Mask of all of the pins on the port."
|
|
line.long 0x10 "PS,GPIO Pull Select Mode."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
tree.end
|
|
tree "GPIO1"
|
|
base ad:0x40009000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "EN0,GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_EN,Mask of all of the pins on the port."
|
|
line.long 0x4 "EN0_SET,GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x4 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x8 "EN0_CLR,GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0xC "OUTEN,GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port."
|
|
hexmask.long 0xC 0.--31. 1. "EN,Mask of all of the pins on the port."
|
|
line.long 0x10 "OUTEN_SET,GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x14 "OUTEN_CLR,GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x18 "OUT,GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly. or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers."
|
|
hexmask.long 0x18 0.--31. 1. "GPIO_OUT,Mask of all of the pins on the port."
|
|
wgroup.long 0x1C++0x7
|
|
line.long 0x0 "OUT_SET,GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1. without affecting other bits in that register."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_OUT_SET,Mask of all of the pins on the port."
|
|
line.long 0x4 "OUT_CLR,GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0. without affecting other bits in that register."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_OUT_CLR,Mask of all of the pins on the port."
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "IN,GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_IN,Mask of all of the pins on the port."
|
|
group.long 0x28++0x17
|
|
line.long 0x0 "INTMODE,GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_INTMODE,Mask of all of the pins on the port."
|
|
line.long 0x4 "INTPOL,GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_INTPOL,Mask of all of the pins on the port."
|
|
line.long 0x8 "INEN,GPIO Input Enable"
|
|
line.long 0xC "INTEN,GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_INTEN,Mask of all of the pins on the port."
|
|
line.long 0x10 "INTEN_SET,GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "GPIO_INTEN_SET,Mask of all of the pins on the port."
|
|
line.long 0x14 "INTEN_CLR,GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "GPIO_INTEN_CLR,Mask of all of the pins on the port."
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "INTFL,GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_INTFL,Mask of all of the pins on the port."
|
|
group.long 0x48++0xF
|
|
line.long 0x0 "INTFL_CLR,GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0. without affecting other bits in that register."
|
|
hexmask.long 0x0 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x4 "WKEN,GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_WKEN,Mask of all of the pins on the port."
|
|
line.long 0x8 "WKEN_SET,GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1. without affecting other bits in that register."
|
|
hexmask.long 0x8 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0xC "WKEN_CLR,GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0. without affecting other bits in that register."
|
|
hexmask.long 0xC 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
group.long 0x5C++0x23
|
|
line.long 0x0 "DUALEDGE,GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_DUALEDGE,Mask of all of the pins on the port."
|
|
line.long 0x4 "PADCTRL0,GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_PADCTRL0,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
|
|
line.long 0x8 "PADCTRL1,GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port."
|
|
hexmask.long 0x8 0.--31. 1. "GPIO_PADCTRL1,The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode."
|
|
line.long 0xC "EN1,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_EN1,Mask of all of the pins on the port."
|
|
line.long 0x10 "EN1_SET,GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1. without affecting other bits in that register."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x14 "EN1_CLR,GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0. without affecting other bits in that register."
|
|
hexmask.long 0x14 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x18 "EN2,GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port."
|
|
hexmask.long 0x18 0.--31. 1. "GPIO_EN2,Mask of all of the pins on the port."
|
|
line.long 0x1C "EN2_SET,GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1. without affecting other bits in that register."
|
|
hexmask.long 0x1C 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
line.long 0x20 "EN2_CLR,GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0. without affecting other bits in that register."
|
|
hexmask.long 0x20 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
group.long 0xA8++0x13
|
|
line.long 0x0 "HYSEN,GPIO Input Hysteresis Enable."
|
|
hexmask.long 0x0 0.--31. 1. "GPIO_HYSEN,Mask of all of the pins on the port."
|
|
line.long 0x4 "SRSEL,GPIO Slew Rate Enable Register."
|
|
hexmask.long 0x4 0.--31. 1. "GPIO_SRSEL,Mask of all of the pins on the port."
|
|
line.long 0x8 "DS0,GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
|
|
hexmask.long 0x8 0.--31. 1. "GPIO_DS0,Mask of all of the pins on the port."
|
|
line.long 0xC "DS1,GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode."
|
|
hexmask.long 0xC 0.--31. 1. "GPIO_DS1,Mask of all of the pins on the port."
|
|
line.long 0x10 "PS,GPIO Pull Select Mode."
|
|
hexmask.long 0x10 0.--31. 1. "ALL,Mask of all of the pins on the port."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x0
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32672*"))
|
|
tree "I2C0"
|
|
base ad:0x4001D000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTRL,Control Register0."
|
|
bitfld.long 0x0 15. "HS_EN,High speed mode enable" "0,1"
|
|
bitfld.long 0x0 13. "ONE_MST_MODE,SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating.." "0: Standard open-drain operation: drive low for 0..,1: Non-standard push-pull operation: drive low for.."
|
|
newline
|
|
bitfld.long 0x0 12. "CLKSTR_DIS,This bit will disable slave clock stretching when set." "0: Slave clock stretching enabled.,1: Slave clock stretching disabled."
|
|
rbitfld.long 0x0 11. "READ,Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set." "0: Write.,1: Read."
|
|
newline
|
|
bitfld.long 0x0 10. "BB_MODE,Software Output Enable." "0: I2C Outputs SCLO and SDAO disabled.,1: I2C Outputs SCLO and SDAO enabled."
|
|
rbitfld.long 0x0 9. "SDA,SDA status. THis bit reflects the logic gate of SDA signal." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 8. "SCL,SCL status. This bit reflects the logic gate of SCL signal." "0,1"
|
|
bitfld.long 0x0 7. "SDA_OUT,SDA Output. This bits control SDA output when SWOE = 1." "0: Drive SDA low.,1: Release SDA."
|
|
newline
|
|
bitfld.long 0x0 6. "SCL_OUT,SCL Output. This bits control SCL output when SWOE =1." "0: Drive SCL low.,1: Release SCL."
|
|
bitfld.long 0x0 4. "IRXM_ACK,Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0." "0: return ACK (pulling SDA LOW).,1: return NACK (leaving SDA HIGH)."
|
|
newline
|
|
bitfld.long 0x0 3. "IRXM_EN,Interactive Receive Mode." "0: Disable Interactive Receive Mode.,1: Enable Interactive Receive Mode."
|
|
bitfld.long 0x0 2. "GC_ADDR_EN,General Call Address Enable." "0: Ignore Gneral Call Address.,1: Acknowledge general call address."
|
|
newline
|
|
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: Slave Mode.,1: Master Mode."
|
|
bitfld.long 0x0 0. "EN,I2C Enable." "0: Disable I2C.,1: enable I2C."
|
|
line.long 0x4 "STATUS,Status Register."
|
|
rbitfld.long 0x4 5. "MST_BUSY,Clock Mode." "0: Device not actively driving SCL clock cycles.,1: Device operating as master and actively driving.."
|
|
bitfld.long 0x4 4. "TX_FULL,TX Full." "0: Not Empty.,1: Empty."
|
|
newline
|
|
bitfld.long 0x4 3. "TX_EM,TX Empty." "0: Not Empty.,1: Empty."
|
|
rbitfld.long 0x4 2. "RX_FULL,RX Full." "0: Not Full.,1: Full."
|
|
newline
|
|
rbitfld.long 0x4 1. "RX_EM,RX empty." "0: Not Empty.,1: Empty."
|
|
rbitfld.long 0x4 0. "BUSY,Bus Status." "0: I2C Bus Idle.,1: I2C Bus Busy."
|
|
line.long 0x8 "INTFL0,Interrupt Status Register."
|
|
bitfld.long 0x8 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
|
|
bitfld.long 0x8 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
|
|
bitfld.long 0x8 15. "TX_LOCKOUT,Transmit Lock Out Interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "STOP_ERR,Stop Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 13. "START_ERR,Start Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 12. "DNR_ERR,Do Not Respond Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 11. "DATA_ERR,Data NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 10. "ADDR_NACK_ERR,Address NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 9. "TO_ERR,timeout Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 8. "ARB_ERR,Arbritation error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 7. "ADDR_ACK,Address Acknowledge Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 6. "STOP,STOP Interrupt." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
|
|
bitfld.long 0x8 5. "TX_THD,Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
|
|
newline
|
|
bitfld.long 0x8 4. "RX_THD,Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. RX_FIFO equal or more.."
|
|
bitfld.long 0x8 3. "ADDR_MATCH,Slave Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 2. "GC_ADDR_MATCH,Slave General Call Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 1. "IRXM,Interactive Receive Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 0. "DONE,Transfer Done Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
line.long 0xC "INTEN0,Interrupt Enable Register."
|
|
bitfld.long 0xC 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
|
|
bitfld.long 0xC 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
|
|
bitfld.long 0xC 15. "TX_LOCKOUT,TX FIFO Locked Out Interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "STOP_ERR,Out of Sequence STOP condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 13. "START_ERR,Out of Sequence START condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 12. "DNR_ERR,Slave Mode Do Not Respond Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 11. "DATA_ERR,Master Mode Data NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 10. "ADDR_NACK_ERR,Master Mode Address NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 9. "TO_ERR,Timeout Error Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 8. "ARB_ERR,Master Mode Arbitration Lost Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 7. "ADDR_ACK,Received Address ACK from Slave Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "STOP,Stop Interrupt Enable" "0: Interrupt disabled.,1: Interrupt enabled when STOP = 1."
|
|
bitfld.long 0xC 5. "TX_THD,TX FIFO Below Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 4. "RX_THD,RX FIFO Above Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 3. "ADDR_MATCH,Slave mode incoming address match interrupt." "0: Interrupt disabled.,1: Interrupt enabled when ADDR_MATCH = 1."
|
|
newline
|
|
bitfld.long 0xC 2. "GC_ADDR_MATCH,Slave mode general call address match received input enable." "0: Interrupt disabled.,1: Interrupt enabled when GEN_CTRL_ADDR = 1."
|
|
bitfld.long 0xC 1. "IRXM,Description not available." "0: Interrupt disabled.,1: Interrupt enabled when RX_MODE = 1."
|
|
newline
|
|
bitfld.long 0xC 0. "DONE,Transfer Done Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled when DONE = 1."
|
|
line.long 0x10 "INTFL1,Interrupt Status Register 1."
|
|
bitfld.long 0x10 2. "START,START Condition Status Flag." "0,1"
|
|
bitfld.long 0x10 1. "TX_UN,Transmit Underflow Interrupt. When operating as a slave transmitter this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet)." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x10 0. "RX_OV,Receiver Overflow Interrupt. When operating as a slave receiver this bit is set when you reach the first data bit and the RX FIFO and shift register are both full." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
line.long 0x14 "INTEN1,Interrupt Staus Register 1."
|
|
bitfld.long 0x14 2. "START,START Condition Interrupt Enable." "0,1"
|
|
bitfld.long 0x14 1. "TX_UN,Transmit Underflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x14 0. "RX_OV,Receiver Overflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "FIFOLEN,FIFO Configuration Register."
|
|
hexmask.long.byte 0x0 8.--15. 1. "TX_DEPTH,Transmit FIFO Length."
|
|
hexmask.long.byte 0x0 0.--7. 1. "RX_DEPTH,Receive FIFO Length."
|
|
group.long 0x1C++0x2F
|
|
line.long 0x0 "RXCTRL0,Receive Control Register 0."
|
|
hexmask.long.byte 0x0 8.--11. 1. "THD_LVL,Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold."
|
|
bitfld.long 0x0 7. "FLUSH,Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status." "0: FIFO not flushed.,1: Flush RX_FIFO."
|
|
newline
|
|
bitfld.long 0x0 0. "DNR,Do Not Respond." "0: Always respond to address match.,1: Do not respond to address match when RX_FIFO is.."
|
|
line.long 0x4 "RXCTRL1,Receive Control Register 1."
|
|
hexmask.long.byte 0x4 8.--11. 1. "LVL,Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0."
|
|
hexmask.long.byte 0x4 0.--7. 1. "CNT,Receive Count Bits. These bits define the number of bytes to be received in a transaction except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction."
|
|
line.long 0x8 "TXCTRL0,Transmit Control Register 0."
|
|
hexmask.long.byte 0x8 8.--11. 1. "THD_VAL,Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."
|
|
bitfld.long 0x8 7. "FLUSH,Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation." "0: FIFO not flushed.,1: Flush TX_FIFO."
|
|
newline
|
|
bitfld.long 0x8 5. "NACK_FLUSH_DIS,TX FIFO received NACK Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
bitfld.long 0x8 4. "RD_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Read Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
newline
|
|
bitfld.long 0x8 3. "WR_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Write Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
bitfld.long 0x8 2. "GC_ADDR_FLUSH_DIS,TX FIFO General Call Address Match Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
newline
|
|
bitfld.long 0x8 1. "TX_READY_MODE,Transmit FIFO Ready Manual Mode." "0: HW control of I2CTXRDY enabled.,1: HW control of I2CTXRDY disabled."
|
|
bitfld.long 0x8 0. "PRELOAD_MODE,Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match." "0,1"
|
|
line.long 0xC "TXCTRL1,Transmit Control Register 1."
|
|
hexmask.long.byte 0xC 8.--11. 1. "LVL,Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO."
|
|
bitfld.long 0xC 0. "PRELOAD_RDY,Transmit FIFO Preload Ready." "0,1"
|
|
line.long 0x10 "FIFO,Data Register."
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA,Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location."
|
|
line.long 0x14 "MSTCTRL,Master Control Register."
|
|
bitfld.long 0x14 7. "EX_ADDR_EN,Slave Extend Address Select." "0: 7-bit address.,1: 10-bit address."
|
|
bitfld.long 0x14 2. "STOP,Setting this bit to 1 will generate a STOP condition." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "RESTART,Setting this bit to 1 will generate a repeated START." "0,1"
|
|
bitfld.long 0x14 0. "START,Setting this bit to 1 will start a master transfer." "0,1"
|
|
line.long 0x18 "CLKLO,Clock Low Register."
|
|
hexmask.long.word 0x18 0.--8. 1. "LO,Clock low. In master mode these bits define the SCL low period. In slave mode these bits define the time SCL will be held low after data is outputted."
|
|
line.long 0x1C "CLKHI,Clock high Register."
|
|
hexmask.long.word 0x1C 0.--8. 1. "HI,Clock High. In master mode these bits define the SCL high period."
|
|
line.long 0x20 "HSCLK,Clock high Register."
|
|
hexmask.long.byte 0x20 8.--15. 1. "HI,Clock High. This field sets the Hs-Mode clock high count. In Slave mode this is the time SCL is held high after data is output on SDA"
|
|
hexmask.long.byte 0x20 0.--7. 1. "LO,Clock Low. This field sets the Hs-Mode clock low count. In Slave mode this is the time SCL is held low after data is output on SDA."
|
|
line.long 0x24 "TIMEOUT,Timeout Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "SCL_TO_VAL,Timeout"
|
|
line.long 0x28 "SLAVE,Slave Address Register."
|
|
bitfld.long 0x28 15. "EXT_ADDR_EN,Extended Address Select." "0: 7-bit address.,1: 10-bit address."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
hexmask.long.byte 0x28 11.--14. 1. "IDX,Slave Address Index."
|
|
newline
|
|
bitfld.long 0x28 10. "DIS,Slave Address Disable." "0,1"
|
|
endif
|
|
hexmask.long.word 0x28 0.--9. 1. "ADDR,Slave Address."
|
|
line.long 0x2C "DMA,DMA Register."
|
|
bitfld.long 0x2C 1. "RX_EN,RX channel enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x2C 0. "TX_EN,TX channel enable." "0: Disable.,1: Enable."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32672*"))
|
|
tree "I2C1"
|
|
base ad:0x4001E000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTRL,Control Register0."
|
|
bitfld.long 0x0 15. "HS_EN,High speed mode enable" "0,1"
|
|
bitfld.long 0x0 13. "ONE_MST_MODE,SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating.." "0: Standard open-drain operation: drive low for 0..,1: Non-standard push-pull operation: drive low for.."
|
|
newline
|
|
bitfld.long 0x0 12. "CLKSTR_DIS,This bit will disable slave clock stretching when set." "0: Slave clock stretching enabled.,1: Slave clock stretching disabled."
|
|
rbitfld.long 0x0 11. "READ,Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set." "0: Write.,1: Read."
|
|
newline
|
|
bitfld.long 0x0 10. "BB_MODE,Software Output Enable." "0: I2C Outputs SCLO and SDAO disabled.,1: I2C Outputs SCLO and SDAO enabled."
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rbitfld.long 0x0 9. "SDA,SDA status. THis bit reflects the logic gate of SDA signal." "0,1"
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newline
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rbitfld.long 0x0 8. "SCL,SCL status. This bit reflects the logic gate of SCL signal." "0,1"
|
|
bitfld.long 0x0 7. "SDA_OUT,SDA Output. This bits control SDA output when SWOE = 1." "0: Drive SDA low.,1: Release SDA."
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newline
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bitfld.long 0x0 6. "SCL_OUT,SCL Output. This bits control SCL output when SWOE =1." "0: Drive SCL low.,1: Release SCL."
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|
bitfld.long 0x0 4. "IRXM_ACK,Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0." "0: return ACK (pulling SDA LOW).,1: return NACK (leaving SDA HIGH)."
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newline
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bitfld.long 0x0 3. "IRXM_EN,Interactive Receive Mode." "0: Disable Interactive Receive Mode.,1: Enable Interactive Receive Mode."
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|
bitfld.long 0x0 2. "GC_ADDR_EN,General Call Address Enable." "0: Ignore Gneral Call Address.,1: Acknowledge general call address."
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newline
|
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bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: Slave Mode.,1: Master Mode."
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bitfld.long 0x0 0. "EN,I2C Enable." "0: Disable I2C.,1: enable I2C."
|
|
line.long 0x4 "STATUS,Status Register."
|
|
rbitfld.long 0x4 5. "MST_BUSY,Clock Mode." "0: Device not actively driving SCL clock cycles.,1: Device operating as master and actively driving.."
|
|
bitfld.long 0x4 4. "TX_FULL,TX Full." "0: Not Empty.,1: Empty."
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newline
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bitfld.long 0x4 3. "TX_EM,TX Empty." "0: Not Empty.,1: Empty."
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|
rbitfld.long 0x4 2. "RX_FULL,RX Full." "0: Not Full.,1: Full."
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newline
|
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rbitfld.long 0x4 1. "RX_EM,RX empty." "0: Not Empty.,1: Empty."
|
|
rbitfld.long 0x4 0. "BUSY,Bus Status." "0: I2C Bus Idle.,1: I2C Bus Busy."
|
|
line.long 0x8 "INTFL0,Interrupt Status Register."
|
|
bitfld.long 0x8 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
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|
bitfld.long 0x8 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
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|
newline
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hexmask.long.byte 0x8 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
|
|
bitfld.long 0x8 15. "TX_LOCKOUT,Transmit Lock Out Interrupt." "0,1"
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|
newline
|
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bitfld.long 0x8 14. "STOP_ERR,Stop Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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|
bitfld.long 0x8 13. "START_ERR,Start Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 12. "DNR_ERR,Do Not Respond Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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|
bitfld.long 0x8 11. "DATA_ERR,Data NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 10. "ADDR_NACK_ERR,Address NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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|
bitfld.long 0x8 9. "TO_ERR,timeout Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 8. "ARB_ERR,Arbritation error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 7. "ADDR_ACK,Address Acknowledge Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 6. "STOP,STOP Interrupt." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
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|
bitfld.long 0x8 5. "TX_THD,Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
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newline
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bitfld.long 0x8 4. "RX_THD,Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. RX_FIFO equal or more.."
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|
bitfld.long 0x8 3. "ADDR_MATCH,Slave Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 2. "GC_ADDR_MATCH,Slave General Call Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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|
bitfld.long 0x8 1. "IRXM,Interactive Receive Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 0. "DONE,Transfer Done Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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|
line.long 0xC "INTEN0,Interrupt Enable Register."
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bitfld.long 0xC 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
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|
bitfld.long 0xC 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
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newline
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hexmask.long.byte 0xC 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
|
|
bitfld.long 0xC 15. "TX_LOCKOUT,TX FIFO Locked Out Interrupt." "0,1"
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|
newline
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bitfld.long 0xC 14. "STOP_ERR,Out of Sequence STOP condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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|
bitfld.long 0xC 13. "START_ERR,Out of Sequence START condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
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bitfld.long 0xC 12. "DNR_ERR,Slave Mode Do Not Respond Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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|
bitfld.long 0xC 11. "DATA_ERR,Master Mode Data NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
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bitfld.long 0xC 10. "ADDR_NACK_ERR,Master Mode Address NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 9. "TO_ERR,Timeout Error Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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|
newline
|
|
bitfld.long 0xC 8. "ARB_ERR,Master Mode Arbitration Lost Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 7. "ADDR_ACK,Received Address ACK from Slave Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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|
newline
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bitfld.long 0xC 6. "STOP,Stop Interrupt Enable" "0: Interrupt disabled.,1: Interrupt enabled when STOP = 1."
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|
bitfld.long 0xC 5. "TX_THD,TX FIFO Below Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
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bitfld.long 0xC 4. "RX_THD,RX FIFO Above Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 3. "ADDR_MATCH,Slave mode incoming address match interrupt." "0: Interrupt disabled.,1: Interrupt enabled when ADDR_MATCH = 1."
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newline
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bitfld.long 0xC 2. "GC_ADDR_MATCH,Slave mode general call address match received input enable." "0: Interrupt disabled.,1: Interrupt enabled when GEN_CTRL_ADDR = 1."
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|
bitfld.long 0xC 1. "IRXM,Description not available." "0: Interrupt disabled.,1: Interrupt enabled when RX_MODE = 1."
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|
newline
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bitfld.long 0xC 0. "DONE,Transfer Done Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled when DONE = 1."
|
|
line.long 0x10 "INTFL1,Interrupt Status Register 1."
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bitfld.long 0x10 2. "START,START Condition Status Flag." "0,1"
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bitfld.long 0x10 1. "TX_UN,Transmit Underflow Interrupt. When operating as a slave transmitter this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet)." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x10 0. "RX_OV,Receiver Overflow Interrupt. When operating as a slave receiver this bit is set when you reach the first data bit and the RX FIFO and shift register are both full." "0: No Interrupt is Pending.,1: An interrupt is pending."
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|
line.long 0x14 "INTEN1,Interrupt Staus Register 1."
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|
bitfld.long 0x14 2. "START,START Condition Interrupt Enable." "0,1"
|
|
bitfld.long 0x14 1. "TX_UN,Transmit Underflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x14 0. "RX_OV,Receiver Overflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "FIFOLEN,FIFO Configuration Register."
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|
hexmask.long.byte 0x0 8.--15. 1. "TX_DEPTH,Transmit FIFO Length."
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|
hexmask.long.byte 0x0 0.--7. 1. "RX_DEPTH,Receive FIFO Length."
|
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group.long 0x1C++0x2F
|
|
line.long 0x0 "RXCTRL0,Receive Control Register 0."
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|
hexmask.long.byte 0x0 8.--11. 1. "THD_LVL,Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold."
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|
bitfld.long 0x0 7. "FLUSH,Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status." "0: FIFO not flushed.,1: Flush RX_FIFO."
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newline
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bitfld.long 0x0 0. "DNR,Do Not Respond." "0: Always respond to address match.,1: Do not respond to address match when RX_FIFO is.."
|
|
line.long 0x4 "RXCTRL1,Receive Control Register 1."
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hexmask.long.byte 0x4 8.--11. 1. "LVL,Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0."
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hexmask.long.byte 0x4 0.--7. 1. "CNT,Receive Count Bits. These bits define the number of bytes to be received in a transaction except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction."
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line.long 0x8 "TXCTRL0,Transmit Control Register 0."
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hexmask.long.byte 0x8 8.--11. 1. "THD_VAL,Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."
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bitfld.long 0x8 7. "FLUSH,Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation." "0: FIFO not flushed.,1: Flush TX_FIFO."
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newline
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bitfld.long 0x8 5. "NACK_FLUSH_DIS,TX FIFO received NACK Auto Flush Disable." "0: Enabled.,1: Disabled."
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bitfld.long 0x8 4. "RD_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Read Auto Flush Disable." "0: Enabled.,1: Disabled."
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newline
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bitfld.long 0x8 3. "WR_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Write Auto Flush Disable." "0: Enabled.,1: Disabled."
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bitfld.long 0x8 2. "GC_ADDR_FLUSH_DIS,TX FIFO General Call Address Match Auto Flush Disable." "0: Enabled.,1: Disabled."
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newline
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bitfld.long 0x8 1. "TX_READY_MODE,Transmit FIFO Ready Manual Mode." "0: HW control of I2CTXRDY enabled.,1: HW control of I2CTXRDY disabled."
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bitfld.long 0x8 0. "PRELOAD_MODE,Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match." "0,1"
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line.long 0xC "TXCTRL1,Transmit Control Register 1."
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hexmask.long.byte 0xC 8.--11. 1. "LVL,Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO."
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bitfld.long 0xC 0. "PRELOAD_RDY,Transmit FIFO Preload Ready." "0,1"
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line.long 0x10 "FIFO,Data Register."
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hexmask.long.byte 0x10 0.--7. 1. "DATA,Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location."
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line.long 0x14 "MSTCTRL,Master Control Register."
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bitfld.long 0x14 7. "EX_ADDR_EN,Slave Extend Address Select." "0: 7-bit address.,1: 10-bit address."
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bitfld.long 0x14 2. "STOP,Setting this bit to 1 will generate a STOP condition." "0,1"
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newline
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bitfld.long 0x14 1. "RESTART,Setting this bit to 1 will generate a repeated START." "0,1"
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bitfld.long 0x14 0. "START,Setting this bit to 1 will start a master transfer." "0,1"
|
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line.long 0x18 "CLKLO,Clock Low Register."
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hexmask.long.word 0x18 0.--8. 1. "LO,Clock low. In master mode these bits define the SCL low period. In slave mode these bits define the time SCL will be held low after data is outputted."
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line.long 0x1C "CLKHI,Clock high Register."
|
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hexmask.long.word 0x1C 0.--8. 1. "HI,Clock High. In master mode these bits define the SCL high period."
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line.long 0x20 "HSCLK,Clock high Register."
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hexmask.long.byte 0x20 8.--15. 1. "HI,Clock High. This field sets the Hs-Mode clock high count. In Slave mode this is the time SCL is held high after data is output on SDA"
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hexmask.long.byte 0x20 0.--7. 1. "LO,Clock Low. This field sets the Hs-Mode clock low count. In Slave mode this is the time SCL is held low after data is output on SDA."
|
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line.long 0x24 "TIMEOUT,Timeout Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "SCL_TO_VAL,Timeout"
|
|
line.long 0x28 "SLAVE,Slave Address Register."
|
|
bitfld.long 0x28 15. "EXT_ADDR_EN,Extended Address Select." "0: 7-bit address.,1: 10-bit address."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
hexmask.long.byte 0x28 11.--14. 1. "IDX,Slave Address Index."
|
|
newline
|
|
bitfld.long 0x28 10. "DIS,Slave Address Disable." "0,1"
|
|
endif
|
|
hexmask.long.word 0x28 0.--9. 1. "ADDR,Slave Address."
|
|
line.long 0x2C "DMA,DMA Register."
|
|
bitfld.long 0x2C 1. "RX_EN,RX channel enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x2C 0. "TX_EN,TX channel enable." "0: Disable.,1: Enable."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32672*"))
|
|
tree "I2C2"
|
|
base ad:0x4001F000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTRL,Control Register0."
|
|
bitfld.long 0x0 15. "HS_EN,High speed mode enable" "0,1"
|
|
bitfld.long 0x0 13. "ONE_MST_MODE,SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating.." "0: Standard open-drain operation: drive low for 0..,1: Non-standard push-pull operation: drive low for.."
|
|
newline
|
|
bitfld.long 0x0 12. "CLKSTR_DIS,This bit will disable slave clock stretching when set." "0: Slave clock stretching enabled.,1: Slave clock stretching disabled."
|
|
rbitfld.long 0x0 11. "READ,Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set." "0: Write.,1: Read."
|
|
newline
|
|
bitfld.long 0x0 10. "BB_MODE,Software Output Enable." "0: I2C Outputs SCLO and SDAO disabled.,1: I2C Outputs SCLO and SDAO enabled."
|
|
rbitfld.long 0x0 9. "SDA,SDA status. THis bit reflects the logic gate of SDA signal." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 8. "SCL,SCL status. This bit reflects the logic gate of SCL signal." "0,1"
|
|
bitfld.long 0x0 7. "SDA_OUT,SDA Output. This bits control SDA output when SWOE = 1." "0: Drive SDA low.,1: Release SDA."
|
|
newline
|
|
bitfld.long 0x0 6. "SCL_OUT,SCL Output. This bits control SCL output when SWOE =1." "0: Drive SCL low.,1: Release SCL."
|
|
bitfld.long 0x0 4. "IRXM_ACK,Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0." "0: return ACK (pulling SDA LOW).,1: return NACK (leaving SDA HIGH)."
|
|
newline
|
|
bitfld.long 0x0 3. "IRXM_EN,Interactive Receive Mode." "0: Disable Interactive Receive Mode.,1: Enable Interactive Receive Mode."
|
|
bitfld.long 0x0 2. "GC_ADDR_EN,General Call Address Enable." "0: Ignore Gneral Call Address.,1: Acknowledge general call address."
|
|
newline
|
|
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: Slave Mode.,1: Master Mode."
|
|
bitfld.long 0x0 0. "EN,I2C Enable." "0: Disable I2C.,1: enable I2C."
|
|
line.long 0x4 "STATUS,Status Register."
|
|
rbitfld.long 0x4 5. "MST_BUSY,Clock Mode." "0: Device not actively driving SCL clock cycles.,1: Device operating as master and actively driving.."
|
|
bitfld.long 0x4 4. "TX_FULL,TX Full." "0: Not Empty.,1: Empty."
|
|
newline
|
|
bitfld.long 0x4 3. "TX_EM,TX Empty." "0: Not Empty.,1: Empty."
|
|
rbitfld.long 0x4 2. "RX_FULL,RX Full." "0: Not Full.,1: Full."
|
|
newline
|
|
rbitfld.long 0x4 1. "RX_EM,RX empty." "0: Not Empty.,1: Empty."
|
|
rbitfld.long 0x4 0. "BUSY,Bus Status." "0: I2C Bus Idle.,1: I2C Bus Busy."
|
|
line.long 0x8 "INTFL0,Interrupt Status Register."
|
|
bitfld.long 0x8 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
|
|
bitfld.long 0x8 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
|
|
bitfld.long 0x8 15. "TX_LOCKOUT,Transmit Lock Out Interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "STOP_ERR,Stop Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 13. "START_ERR,Start Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 12. "DNR_ERR,Do Not Respond Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 11. "DATA_ERR,Data NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 10. "ADDR_NACK_ERR,Address NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 9. "TO_ERR,timeout Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 8. "ARB_ERR,Arbritation error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 7. "ADDR_ACK,Address Acknowledge Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 6. "STOP,STOP Interrupt." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
|
|
bitfld.long 0x8 5. "TX_THD,Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
|
|
newline
|
|
bitfld.long 0x8 4. "RX_THD,Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. RX_FIFO equal or more.."
|
|
bitfld.long 0x8 3. "ADDR_MATCH,Slave Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 2. "GC_ADDR_MATCH,Slave General Call Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 1. "IRXM,Interactive Receive Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 0. "DONE,Transfer Done Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
line.long 0xC "INTEN0,Interrupt Enable Register."
|
|
bitfld.long 0xC 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
|
|
bitfld.long 0xC 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
|
|
bitfld.long 0xC 15. "TX_LOCKOUT,TX FIFO Locked Out Interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "STOP_ERR,Out of Sequence STOP condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 13. "START_ERR,Out of Sequence START condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 12. "DNR_ERR,Slave Mode Do Not Respond Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 11. "DATA_ERR,Master Mode Data NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 10. "ADDR_NACK_ERR,Master Mode Address NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 9. "TO_ERR,Timeout Error Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 8. "ARB_ERR,Master Mode Arbitration Lost Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 7. "ADDR_ACK,Received Address ACK from Slave Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "STOP,Stop Interrupt Enable" "0: Interrupt disabled.,1: Interrupt enabled when STOP = 1."
|
|
bitfld.long 0xC 5. "TX_THD,TX FIFO Below Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 4. "RX_THD,RX FIFO Above Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 3. "ADDR_MATCH,Slave mode incoming address match interrupt." "0: Interrupt disabled.,1: Interrupt enabled when ADDR_MATCH = 1."
|
|
newline
|
|
bitfld.long 0xC 2. "GC_ADDR_MATCH,Slave mode general call address match received input enable." "0: Interrupt disabled.,1: Interrupt enabled when GEN_CTRL_ADDR = 1."
|
|
bitfld.long 0xC 1. "IRXM,Description not available." "0: Interrupt disabled.,1: Interrupt enabled when RX_MODE = 1."
|
|
newline
|
|
bitfld.long 0xC 0. "DONE,Transfer Done Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled when DONE = 1."
|
|
line.long 0x10 "INTFL1,Interrupt Status Register 1."
|
|
bitfld.long 0x10 2. "START,START Condition Status Flag." "0,1"
|
|
bitfld.long 0x10 1. "TX_UN,Transmit Underflow Interrupt. When operating as a slave transmitter this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet)." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x10 0. "RX_OV,Receiver Overflow Interrupt. When operating as a slave receiver this bit is set when you reach the first data bit and the RX FIFO and shift register are both full." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
line.long 0x14 "INTEN1,Interrupt Staus Register 1."
|
|
bitfld.long 0x14 2. "START,START Condition Interrupt Enable." "0,1"
|
|
bitfld.long 0x14 1. "TX_UN,Transmit Underflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x14 0. "RX_OV,Receiver Overflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "FIFOLEN,FIFO Configuration Register."
|
|
hexmask.long.byte 0x0 8.--15. 1. "TX_DEPTH,Transmit FIFO Length."
|
|
hexmask.long.byte 0x0 0.--7. 1. "RX_DEPTH,Receive FIFO Length."
|
|
group.long 0x1C++0x2F
|
|
line.long 0x0 "RXCTRL0,Receive Control Register 0."
|
|
hexmask.long.byte 0x0 8.--11. 1. "THD_LVL,Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold."
|
|
bitfld.long 0x0 7. "FLUSH,Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status." "0: FIFO not flushed.,1: Flush RX_FIFO."
|
|
newline
|
|
bitfld.long 0x0 0. "DNR,Do Not Respond." "0: Always respond to address match.,1: Do not respond to address match when RX_FIFO is.."
|
|
line.long 0x4 "RXCTRL1,Receive Control Register 1."
|
|
hexmask.long.byte 0x4 8.--11. 1. "LVL,Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0."
|
|
hexmask.long.byte 0x4 0.--7. 1. "CNT,Receive Count Bits. These bits define the number of bytes to be received in a transaction except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction."
|
|
line.long 0x8 "TXCTRL0,Transmit Control Register 0."
|
|
hexmask.long.byte 0x8 8.--11. 1. "THD_VAL,Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."
|
|
bitfld.long 0x8 7. "FLUSH,Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation." "0: FIFO not flushed.,1: Flush TX_FIFO."
|
|
newline
|
|
bitfld.long 0x8 5. "NACK_FLUSH_DIS,TX FIFO received NACK Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
bitfld.long 0x8 4. "RD_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Read Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
newline
|
|
bitfld.long 0x8 3. "WR_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Write Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
bitfld.long 0x8 2. "GC_ADDR_FLUSH_DIS,TX FIFO General Call Address Match Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
newline
|
|
bitfld.long 0x8 1. "TX_READY_MODE,Transmit FIFO Ready Manual Mode." "0: HW control of I2CTXRDY enabled.,1: HW control of I2CTXRDY disabled."
|
|
bitfld.long 0x8 0. "PRELOAD_MODE,Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match." "0,1"
|
|
line.long 0xC "TXCTRL1,Transmit Control Register 1."
|
|
hexmask.long.byte 0xC 8.--11. 1. "LVL,Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO."
|
|
bitfld.long 0xC 0. "PRELOAD_RDY,Transmit FIFO Preload Ready." "0,1"
|
|
line.long 0x10 "FIFO,Data Register."
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA,Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location."
|
|
line.long 0x14 "MSTCTRL,Master Control Register."
|
|
bitfld.long 0x14 7. "EX_ADDR_EN,Slave Extend Address Select." "0: 7-bit address.,1: 10-bit address."
|
|
bitfld.long 0x14 2. "STOP,Setting this bit to 1 will generate a STOP condition." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "RESTART,Setting this bit to 1 will generate a repeated START." "0,1"
|
|
bitfld.long 0x14 0. "START,Setting this bit to 1 will start a master transfer." "0,1"
|
|
line.long 0x18 "CLKLO,Clock Low Register."
|
|
hexmask.long.word 0x18 0.--8. 1. "LO,Clock low. In master mode these bits define the SCL low period. In slave mode these bits define the time SCL will be held low after data is outputted."
|
|
line.long 0x1C "CLKHI,Clock high Register."
|
|
hexmask.long.word 0x1C 0.--8. 1. "HI,Clock High. In master mode these bits define the SCL high period."
|
|
line.long 0x20 "HSCLK,Clock high Register."
|
|
hexmask.long.byte 0x20 8.--15. 1. "HI,Clock High. This field sets the Hs-Mode clock high count. In Slave mode this is the time SCL is held high after data is output on SDA"
|
|
hexmask.long.byte 0x20 0.--7. 1. "LO,Clock Low. This field sets the Hs-Mode clock low count. In Slave mode this is the time SCL is held low after data is output on SDA."
|
|
line.long 0x24 "TIMEOUT,Timeout Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "SCL_TO_VAL,Timeout"
|
|
line.long 0x28 "SLAVE,Slave Address Register."
|
|
bitfld.long 0x28 15. "EXT_ADDR_EN,Extended Address Select." "0: 7-bit address.,1: 10-bit address."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
hexmask.long.byte 0x28 11.--14. 1. "IDX,Slave Address Index."
|
|
newline
|
|
bitfld.long 0x28 10. "DIS,Slave Address Disable." "0,1"
|
|
endif
|
|
hexmask.long.word 0x28 0.--9. 1. "ADDR,Slave Address."
|
|
line.long 0x2C "DMA,DMA Register."
|
|
bitfld.long 0x2C 1. "RX_EN,RX channel enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x2C 0. "TX_EN,TX channel enable." "0: Disable.,1: Enable."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
tree "I2C0"
|
|
base ad:0x4001D000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTRL,Control Register0."
|
|
bitfld.long 0x0 15. "HS_EN,High speed mode enable" "0,1"
|
|
bitfld.long 0x0 13. "ONE_MST_MODE,SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating.." "0: Standard open-drain operation: drive low for 0..,1: Non-standard push-pull operation: drive low for.."
|
|
newline
|
|
bitfld.long 0x0 12. "CLKSTR_DIS,This bit will disable slave clock stretching when set." "0: Slave clock stretching enabled.,1: Slave clock stretching disabled."
|
|
rbitfld.long 0x0 11. "READ,Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set." "0: Write.,1: Read."
|
|
newline
|
|
bitfld.long 0x0 10. "BB_MODE,Software Output Enable." "0: I2C Outputs SCLO and SDAO disabled.,1: I2C Outputs SCLO and SDAO enabled."
|
|
rbitfld.long 0x0 9. "SDA,SDA status. THis bit reflects the logic gate of SDA signal." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 8. "SCL,SCL status. This bit reflects the logic gate of SCL signal." "0,1"
|
|
bitfld.long 0x0 7. "SDA_OUT,SDA Output. This bits control SDA output when SWOE = 1." "0: Drive SDA low.,1: Release SDA."
|
|
newline
|
|
bitfld.long 0x0 6. "SCL_OUT,SCL Output. This bits control SCL output when SWOE =1." "0: Drive SCL low.,1: Release SCL."
|
|
bitfld.long 0x0 4. "IRXM_ACK,Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0." "0: return ACK (pulling SDA LOW).,1: return NACK (leaving SDA HIGH)."
|
|
newline
|
|
bitfld.long 0x0 3. "IRXM_EN,Interactive Receive Mode." "0: Disable Interactive Receive Mode.,1: Enable Interactive Receive Mode."
|
|
bitfld.long 0x0 2. "GC_ADDR_EN,General Call Address Enable." "0: Ignore Gneral Call Address.,1: Acknowledge general call address."
|
|
newline
|
|
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: Slave Mode.,1: Master Mode."
|
|
bitfld.long 0x0 0. "EN,I2C Enable." "0: Disable I2C.,1: enable I2C."
|
|
line.long 0x4 "STATUS,Status Register."
|
|
rbitfld.long 0x4 5. "MST_BUSY,Clock Mode." "0: Device not actively driving SCL clock cycles.,1: Device operating as master and actively driving.."
|
|
bitfld.long 0x4 4. "TX_FULL,TX Full." "0: Not Empty.,1: Empty."
|
|
newline
|
|
bitfld.long 0x4 3. "TX_EM,TX Empty." "0: Not Empty.,1: Empty."
|
|
rbitfld.long 0x4 2. "RX_FULL,RX Full." "0: Not Full.,1: Full."
|
|
newline
|
|
rbitfld.long 0x4 1. "RX_EM,RX empty." "0: Not Empty.,1: Empty."
|
|
rbitfld.long 0x4 0. "BUSY,Bus Status." "0: I2C Bus Idle.,1: I2C Bus Busy."
|
|
line.long 0x8 "INTFL0,Interrupt Status Register."
|
|
bitfld.long 0x8 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
|
|
bitfld.long 0x8 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
|
|
bitfld.long 0x8 15. "TX_LOCKOUT,Transmit Lock Out Interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "STOP_ERR,Stop Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 13. "START_ERR,Start Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 12. "DNR_ERR,Do Not Respond Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 11. "DATA_ERR,Data NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 10. "ADDR_NACK_ERR,Address NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 9. "TO_ERR,timeout Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 8. "ARB_ERR,Arbritation error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 7. "ADDR_ACK,Address Acknowledge Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 6. "STOP,STOP Interrupt." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
|
|
bitfld.long 0x8 5. "TX_THD,Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
|
|
newline
|
|
bitfld.long 0x8 4. "RX_THD,Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. RX_FIFO equal or more.."
|
|
bitfld.long 0x8 3. "ADDR_MATCH,Slave Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 2. "GC_ADDR_MATCH,Slave General Call Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
bitfld.long 0x8 1. "IRXM,Interactive Receive Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x8 0. "DONE,Transfer Done Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
line.long 0xC "INTEN0,Interrupt Enable Register."
|
|
bitfld.long 0xC 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
|
|
bitfld.long 0xC 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
|
|
bitfld.long 0xC 15. "TX_LOCKOUT,TX FIFO Locked Out Interrupt." "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "STOP_ERR,Out of Sequence STOP condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 13. "START_ERR,Out of Sequence START condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 12. "DNR_ERR,Slave Mode Do Not Respond Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 11. "DATA_ERR,Master Mode Data NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 10. "ADDR_NACK_ERR,Master Mode Address NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 9. "TO_ERR,Timeout Error Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 8. "ARB_ERR,Master Mode Arbitration Lost Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 7. "ADDR_ACK,Received Address ACK from Slave Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "STOP,Stop Interrupt Enable" "0: Interrupt disabled.,1: Interrupt enabled when STOP = 1."
|
|
bitfld.long 0xC 5. "TX_THD,TX FIFO Below Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 4. "RX_THD,RX FIFO Above Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 3. "ADDR_MATCH,Slave mode incoming address match interrupt." "0: Interrupt disabled.,1: Interrupt enabled when ADDR_MATCH = 1."
|
|
newline
|
|
bitfld.long 0xC 2. "GC_ADDR_MATCH,Slave mode general call address match received input enable." "0: Interrupt disabled.,1: Interrupt enabled when GEN_CTRL_ADDR = 1."
|
|
bitfld.long 0xC 1. "IRXM,Description not available." "0: Interrupt disabled.,1: Interrupt enabled when RX_MODE = 1."
|
|
newline
|
|
bitfld.long 0xC 0. "DONE,Transfer Done Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled when DONE = 1."
|
|
line.long 0x10 "INTFL1,Interrupt Status Register 1."
|
|
bitfld.long 0x10 2. "START,START Condition Status Flag." "0,1"
|
|
bitfld.long 0x10 1. "TX_UN,Transmit Underflow Interrupt. When operating as a slave transmitter this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet)." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x10 0. "RX_OV,Receiver Overflow Interrupt. When operating as a slave receiver this bit is set when you reach the first data bit and the RX FIFO and shift register are both full." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
line.long 0x14 "INTEN1,Interrupt Staus Register 1."
|
|
bitfld.long 0x14 2. "START,START Condition Interrupt Enable." "0,1"
|
|
bitfld.long 0x14 1. "TX_UN,Transmit Underflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x14 0. "RX_OV,Receiver Overflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "FIFOLEN,FIFO Configuration Register."
|
|
hexmask.long.byte 0x0 8.--15. 1. "TX_DEPTH,Transmit FIFO Length."
|
|
hexmask.long.byte 0x0 0.--7. 1. "RX_DEPTH,Receive FIFO Length."
|
|
group.long 0x1C++0x2F
|
|
line.long 0x0 "RXCTRL0,Receive Control Register 0."
|
|
hexmask.long.byte 0x0 8.--11. 1. "THD_LVL,Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold."
|
|
bitfld.long 0x0 7. "FLUSH,Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status." "0: FIFO not flushed.,1: Flush RX_FIFO."
|
|
newline
|
|
bitfld.long 0x0 0. "DNR,Do Not Respond." "0: Always respond to address match.,1: Do not respond to address match when RX_FIFO is.."
|
|
line.long 0x4 "RXCTRL1,Receive Control Register 1."
|
|
hexmask.long.byte 0x4 8.--11. 1. "LVL,Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0."
|
|
hexmask.long.byte 0x4 0.--7. 1. "CNT,Receive Count Bits. These bits define the number of bytes to be received in a transaction except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction."
|
|
line.long 0x8 "TXCTRL0,Transmit Control Register 0."
|
|
hexmask.long.byte 0x8 8.--11. 1. "THD_VAL,Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."
|
|
bitfld.long 0x8 7. "FLUSH,Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation." "0: FIFO not flushed.,1: Flush TX_FIFO."
|
|
newline
|
|
bitfld.long 0x8 5. "NACK_FLUSH_DIS,TX FIFO received NACK Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
bitfld.long 0x8 4. "RD_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Read Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
newline
|
|
bitfld.long 0x8 3. "WR_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Write Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
bitfld.long 0x8 2. "GC_ADDR_FLUSH_DIS,TX FIFO General Call Address Match Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
newline
|
|
bitfld.long 0x8 1. "TX_READY_MODE,Transmit FIFO Ready Manual Mode." "0: HW control of I2CTXRDY enabled.,1: HW control of I2CTXRDY disabled."
|
|
bitfld.long 0x8 0. "PRELOAD_MODE,Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match." "0,1"
|
|
line.long 0xC "TXCTRL1,Transmit Control Register 1."
|
|
hexmask.long.byte 0xC 8.--11. 1. "LVL,Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO."
|
|
bitfld.long 0xC 0. "PRELOAD_RDY,Transmit FIFO Preload Ready." "0,1"
|
|
line.long 0x10 "FIFO,Data Register."
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA,Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location."
|
|
line.long 0x14 "MSTCTRL,Master Control Register."
|
|
bitfld.long 0x14 7. "EX_ADDR_EN,Slave Extend Address Select." "0: 7-bit address.,1: 10-bit address."
|
|
bitfld.long 0x14 2. "STOP,Setting this bit to 1 will generate a STOP condition." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "RESTART,Setting this bit to 1 will generate a repeated START." "0,1"
|
|
bitfld.long 0x14 0. "START,Setting this bit to 1 will start a master transfer." "0,1"
|
|
line.long 0x18 "CLKLO,Clock Low Register."
|
|
hexmask.long.word 0x18 0.--8. 1. "LO,Clock low. In master mode these bits define the SCL low period. In slave mode these bits define the time SCL will be held low after data is outputted."
|
|
line.long 0x1C "CLKHI,Clock high Register."
|
|
hexmask.long.word 0x1C 0.--8. 1. "HI,Clock High. In master mode these bits define the SCL high period."
|
|
line.long 0x20 "HSCLK,Clock high Register."
|
|
hexmask.long.byte 0x20 8.--15. 1. "HI,Clock High. This field sets the Hs-Mode clock high count. In Slave mode this is the time SCL is held high after data is output on SDA"
|
|
hexmask.long.byte 0x20 0.--7. 1. "LO,Clock Low. This field sets the Hs-Mode clock low count. In Slave mode this is the time SCL is held low after data is output on SDA."
|
|
line.long 0x24 "TIMEOUT,Timeout Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "SCL_TO_VAL,Timeout"
|
|
line.long 0x28 "SLAVE,Slave Address Register."
|
|
bitfld.long 0x28 15. "EXT_ADDR_EN,Extended Address Select." "0: 7-bit address.,1: 10-bit address."
|
|
hexmask.long.word 0x28 0.--9. 1. "ADDR,Slave Address."
|
|
line.long 0x2C "DMA,DMA Register."
|
|
bitfld.long 0x2C 1. "RX_EN,RX channel enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x2C 0. "TX_EN,TX channel enable." "0: Disable.,1: Enable."
|
|
tree.end
|
|
tree "I2C1"
|
|
base ad:0x4001E000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTRL,Control Register0."
|
|
bitfld.long 0x0 15. "HS_EN,High speed mode enable" "0,1"
|
|
bitfld.long 0x0 13. "ONE_MST_MODE,SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating.." "0: Standard open-drain operation: drive low for 0..,1: Non-standard push-pull operation: drive low for.."
|
|
newline
|
|
bitfld.long 0x0 12. "CLKSTR_DIS,This bit will disable slave clock stretching when set." "0: Slave clock stretching enabled.,1: Slave clock stretching disabled."
|
|
rbitfld.long 0x0 11. "READ,Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set." "0: Write.,1: Read."
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bitfld.long 0x0 10. "BB_MODE,Software Output Enable." "0: I2C Outputs SCLO and SDAO disabled.,1: I2C Outputs SCLO and SDAO enabled."
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rbitfld.long 0x0 9. "SDA,SDA status. THis bit reflects the logic gate of SDA signal." "0,1"
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rbitfld.long 0x0 8. "SCL,SCL status. This bit reflects the logic gate of SCL signal." "0,1"
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bitfld.long 0x0 7. "SDA_OUT,SDA Output. This bits control SDA output when SWOE = 1." "0: Drive SDA low.,1: Release SDA."
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bitfld.long 0x0 6. "SCL_OUT,SCL Output. This bits control SCL output when SWOE =1." "0: Drive SCL low.,1: Release SCL."
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bitfld.long 0x0 4. "IRXM_ACK,Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0." "0: return ACK (pulling SDA LOW).,1: return NACK (leaving SDA HIGH)."
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bitfld.long 0x0 3. "IRXM_EN,Interactive Receive Mode." "0: Disable Interactive Receive Mode.,1: Enable Interactive Receive Mode."
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bitfld.long 0x0 2. "GC_ADDR_EN,General Call Address Enable." "0: Ignore Gneral Call Address.,1: Acknowledge general call address."
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newline
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bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: Slave Mode.,1: Master Mode."
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bitfld.long 0x0 0. "EN,I2C Enable." "0: Disable I2C.,1: enable I2C."
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line.long 0x4 "STATUS,Status Register."
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rbitfld.long 0x4 5. "MST_BUSY,Clock Mode." "0: Device not actively driving SCL clock cycles.,1: Device operating as master and actively driving.."
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bitfld.long 0x4 4. "TX_FULL,TX Full." "0: Not Empty.,1: Empty."
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bitfld.long 0x4 3. "TX_EM,TX Empty." "0: Not Empty.,1: Empty."
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rbitfld.long 0x4 2. "RX_FULL,RX Full." "0: Not Full.,1: Full."
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rbitfld.long 0x4 1. "RX_EM,RX empty." "0: Not Empty.,1: Empty."
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rbitfld.long 0x4 0. "BUSY,Bus Status." "0: I2C Bus Idle.,1: I2C Bus Busy."
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line.long 0x8 "INTFL0,Interrupt Status Register."
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bitfld.long 0x8 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
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bitfld.long 0x8 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
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newline
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hexmask.long.byte 0x8 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
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bitfld.long 0x8 15. "TX_LOCKOUT,Transmit Lock Out Interrupt." "0,1"
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bitfld.long 0x8 14. "STOP_ERR,Stop Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 13. "START_ERR,Start Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 12. "DNR_ERR,Do Not Respond Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 11. "DATA_ERR,Data NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 10. "ADDR_NACK_ERR,Address NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 9. "TO_ERR,timeout Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 8. "ARB_ERR,Arbritation error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 7. "ADDR_ACK,Address Acknowledge Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 6. "STOP,STOP Interrupt." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
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bitfld.long 0x8 5. "TX_THD,Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
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bitfld.long 0x8 4. "RX_THD,Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. RX_FIFO equal or more.."
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bitfld.long 0x8 3. "ADDR_MATCH,Slave Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 2. "GC_ADDR_MATCH,Slave General Call Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 1. "IRXM,Interactive Receive Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 0. "DONE,Transfer Done Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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line.long 0xC "INTEN0,Interrupt Enable Register."
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bitfld.long 0xC 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
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bitfld.long 0xC 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
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newline
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hexmask.long.byte 0xC 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
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bitfld.long 0xC 15. "TX_LOCKOUT,TX FIFO Locked Out Interrupt." "0,1"
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newline
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bitfld.long 0xC 14. "STOP_ERR,Out of Sequence STOP condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 13. "START_ERR,Out of Sequence START condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
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bitfld.long 0xC 12. "DNR_ERR,Slave Mode Do Not Respond Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 11. "DATA_ERR,Master Mode Data NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
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bitfld.long 0xC 10. "ADDR_NACK_ERR,Master Mode Address NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 9. "TO_ERR,Timeout Error Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
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bitfld.long 0xC 8. "ARB_ERR,Master Mode Arbitration Lost Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 7. "ADDR_ACK,Received Address ACK from Slave Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
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bitfld.long 0xC 6. "STOP,Stop Interrupt Enable" "0: Interrupt disabled.,1: Interrupt enabled when STOP = 1."
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bitfld.long 0xC 5. "TX_THD,TX FIFO Below Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
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bitfld.long 0xC 4. "RX_THD,RX FIFO Above Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 3. "ADDR_MATCH,Slave mode incoming address match interrupt." "0: Interrupt disabled.,1: Interrupt enabled when ADDR_MATCH = 1."
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newline
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bitfld.long 0xC 2. "GC_ADDR_MATCH,Slave mode general call address match received input enable." "0: Interrupt disabled.,1: Interrupt enabled when GEN_CTRL_ADDR = 1."
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bitfld.long 0xC 1. "IRXM,Description not available." "0: Interrupt disabled.,1: Interrupt enabled when RX_MODE = 1."
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newline
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bitfld.long 0xC 0. "DONE,Transfer Done Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled when DONE = 1."
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line.long 0x10 "INTFL1,Interrupt Status Register 1."
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bitfld.long 0x10 2. "START,START Condition Status Flag." "0,1"
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bitfld.long 0x10 1. "TX_UN,Transmit Underflow Interrupt. When operating as a slave transmitter this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet)." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x10 0. "RX_OV,Receiver Overflow Interrupt. When operating as a slave receiver this bit is set when you reach the first data bit and the RX FIFO and shift register are both full." "0: No Interrupt is Pending.,1: An interrupt is pending."
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line.long 0x14 "INTEN1,Interrupt Staus Register 1."
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bitfld.long 0x14 2. "START,START Condition Interrupt Enable." "0,1"
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bitfld.long 0x14 1. "TX_UN,Transmit Underflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x14 0. "RX_OV,Receiver Overflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
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rgroup.long 0x18++0x3
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line.long 0x0 "FIFOLEN,FIFO Configuration Register."
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hexmask.long.byte 0x0 8.--15. 1. "TX_DEPTH,Transmit FIFO Length."
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hexmask.long.byte 0x0 0.--7. 1. "RX_DEPTH,Receive FIFO Length."
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group.long 0x1C++0x2F
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line.long 0x0 "RXCTRL0,Receive Control Register 0."
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hexmask.long.byte 0x0 8.--11. 1. "THD_LVL,Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold."
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bitfld.long 0x0 7. "FLUSH,Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status." "0: FIFO not flushed.,1: Flush RX_FIFO."
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newline
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bitfld.long 0x0 0. "DNR,Do Not Respond." "0: Always respond to address match.,1: Do not respond to address match when RX_FIFO is.."
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line.long 0x4 "RXCTRL1,Receive Control Register 1."
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hexmask.long.byte 0x4 8.--11. 1. "LVL,Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0."
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hexmask.long.byte 0x4 0.--7. 1. "CNT,Receive Count Bits. These bits define the number of bytes to be received in a transaction except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction."
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line.long 0x8 "TXCTRL0,Transmit Control Register 0."
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hexmask.long.byte 0x8 8.--11. 1. "THD_VAL,Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."
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bitfld.long 0x8 7. "FLUSH,Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation." "0: FIFO not flushed.,1: Flush TX_FIFO."
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newline
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bitfld.long 0x8 5. "NACK_FLUSH_DIS,TX FIFO received NACK Auto Flush Disable." "0: Enabled.,1: Disabled."
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bitfld.long 0x8 4. "RD_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Read Auto Flush Disable." "0: Enabled.,1: Disabled."
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newline
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bitfld.long 0x8 3. "WR_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Write Auto Flush Disable." "0: Enabled.,1: Disabled."
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bitfld.long 0x8 2. "GC_ADDR_FLUSH_DIS,TX FIFO General Call Address Match Auto Flush Disable." "0: Enabled.,1: Disabled."
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newline
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bitfld.long 0x8 1. "TX_READY_MODE,Transmit FIFO Ready Manual Mode." "0: HW control of I2CTXRDY enabled.,1: HW control of I2CTXRDY disabled."
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bitfld.long 0x8 0. "PRELOAD_MODE,Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match." "0,1"
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line.long 0xC "TXCTRL1,Transmit Control Register 1."
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hexmask.long.byte 0xC 8.--11. 1. "LVL,Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO."
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bitfld.long 0xC 0. "PRELOAD_RDY,Transmit FIFO Preload Ready." "0,1"
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line.long 0x10 "FIFO,Data Register."
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hexmask.long.byte 0x10 0.--7. 1. "DATA,Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location."
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line.long 0x14 "MSTCTRL,Master Control Register."
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bitfld.long 0x14 7. "EX_ADDR_EN,Slave Extend Address Select." "0: 7-bit address.,1: 10-bit address."
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bitfld.long 0x14 2. "STOP,Setting this bit to 1 will generate a STOP condition." "0,1"
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newline
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bitfld.long 0x14 1. "RESTART,Setting this bit to 1 will generate a repeated START." "0,1"
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bitfld.long 0x14 0. "START,Setting this bit to 1 will start a master transfer." "0,1"
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line.long 0x18 "CLKLO,Clock Low Register."
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hexmask.long.word 0x18 0.--8. 1. "LO,Clock low. In master mode these bits define the SCL low period. In slave mode these bits define the time SCL will be held low after data is outputted."
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line.long 0x1C "CLKHI,Clock high Register."
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hexmask.long.word 0x1C 0.--8. 1. "HI,Clock High. In master mode these bits define the SCL high period."
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line.long 0x20 "HSCLK,Clock high Register."
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hexmask.long.byte 0x20 8.--15. 1. "HI,Clock High. This field sets the Hs-Mode clock high count. In Slave mode this is the time SCL is held high after data is output on SDA"
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hexmask.long.byte 0x20 0.--7. 1. "LO,Clock Low. This field sets the Hs-Mode clock low count. In Slave mode this is the time SCL is held low after data is output on SDA."
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line.long 0x24 "TIMEOUT,Timeout Register"
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hexmask.long.word 0x24 0.--15. 1. "SCL_TO_VAL,Timeout"
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line.long 0x28 "SLAVE,Slave Address Register."
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bitfld.long 0x28 15. "EXT_ADDR_EN,Extended Address Select." "0: 7-bit address.,1: 10-bit address."
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hexmask.long.word 0x28 0.--9. 1. "ADDR,Slave Address."
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line.long 0x2C "DMA,DMA Register."
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bitfld.long 0x2C 1. "RX_EN,RX channel enable." "0: Disable.,1: Enable."
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bitfld.long 0x2C 0. "TX_EN,TX channel enable." "0: Disable.,1: Enable."
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tree.end
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tree "I2C2"
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base ad:0x4001F000
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group.long 0x0++0x17
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line.long 0x0 "CTRL,Control Register0."
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bitfld.long 0x0 15. "HS_EN,High speed mode enable" "0,1"
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bitfld.long 0x0 13. "ONE_MST_MODE,SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating.." "0: Standard open-drain operation: drive low for 0..,1: Non-standard push-pull operation: drive low for.."
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newline
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bitfld.long 0x0 12. "CLKSTR_DIS,This bit will disable slave clock stretching when set." "0: Slave clock stretching enabled.,1: Slave clock stretching disabled."
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rbitfld.long 0x0 11. "READ,Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set." "0: Write.,1: Read."
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newline
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bitfld.long 0x0 10. "BB_MODE,Software Output Enable." "0: I2C Outputs SCLO and SDAO disabled.,1: I2C Outputs SCLO and SDAO enabled."
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rbitfld.long 0x0 9. "SDA,SDA status. THis bit reflects the logic gate of SDA signal." "0,1"
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newline
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rbitfld.long 0x0 8. "SCL,SCL status. This bit reflects the logic gate of SCL signal." "0,1"
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bitfld.long 0x0 7. "SDA_OUT,SDA Output. This bits control SDA output when SWOE = 1." "0: Drive SDA low.,1: Release SDA."
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newline
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bitfld.long 0x0 6. "SCL_OUT,SCL Output. This bits control SCL output when SWOE =1." "0: Drive SCL low.,1: Release SCL."
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bitfld.long 0x0 4. "IRXM_ACK,Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0." "0: return ACK (pulling SDA LOW).,1: return NACK (leaving SDA HIGH)."
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newline
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bitfld.long 0x0 3. "IRXM_EN,Interactive Receive Mode." "0: Disable Interactive Receive Mode.,1: Enable Interactive Receive Mode."
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bitfld.long 0x0 2. "GC_ADDR_EN,General Call Address Enable." "0: Ignore Gneral Call Address.,1: Acknowledge general call address."
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newline
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bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: Slave Mode.,1: Master Mode."
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bitfld.long 0x0 0. "EN,I2C Enable." "0: Disable I2C.,1: enable I2C."
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line.long 0x4 "STATUS,Status Register."
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rbitfld.long 0x4 5. "MST_BUSY,Clock Mode." "0: Device not actively driving SCL clock cycles.,1: Device operating as master and actively driving.."
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bitfld.long 0x4 4. "TX_FULL,TX Full." "0: Not Empty.,1: Empty."
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newline
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bitfld.long 0x4 3. "TX_EM,TX Empty." "0: Not Empty.,1: Empty."
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rbitfld.long 0x4 2. "RX_FULL,RX Full." "0: Not Full.,1: Full."
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newline
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rbitfld.long 0x4 1. "RX_EM,RX empty." "0: Not Empty.,1: Empty."
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rbitfld.long 0x4 0. "BUSY,Bus Status." "0: I2C Bus Idle.,1: I2C Bus Busy."
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line.long 0x8 "INTFL0,Interrupt Status Register."
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bitfld.long 0x8 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
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bitfld.long 0x8 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
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newline
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hexmask.long.byte 0x8 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
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bitfld.long 0x8 15. "TX_LOCKOUT,Transmit Lock Out Interrupt." "0,1"
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newline
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bitfld.long 0x8 14. "STOP_ERR,Stop Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 13. "START_ERR,Start Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 12. "DNR_ERR,Do Not Respond Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 11. "DATA_ERR,Data NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 10. "ADDR_NACK_ERR,Address NACK Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 9. "TO_ERR,timeout Error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 8. "ARB_ERR,Arbritation error Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 7. "ADDR_ACK,Address Acknowledge Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 6. "STOP,STOP Interrupt." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
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bitfld.long 0x8 5. "TX_THD,Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. TX_FIFO has equal or.."
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newline
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bitfld.long 0x8 4. "RX_THD,Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level." "0: No interrupt is pending.,1: An interrupt is pending. RX_FIFO equal or more.."
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bitfld.long 0x8 3. "ADDR_MATCH,Slave Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x8 2. "GC_ADDR_MATCH,Slave General Call Address Match Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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bitfld.long 0x8 1. "IRXM,Interactive Receive Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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newline
|
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bitfld.long 0x8 0. "DONE,Transfer Done Interrupt." "0: No Interrupt is Pending.,1: An interrupt is pending."
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line.long 0xC "INTEN0,Interrupt Enable Register."
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bitfld.long 0xC 23. "WR_ADDR_MATCH,Slave Write Address Match Interrupt" "0,1"
|
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bitfld.long 0xC 22. "RD_ADDR_MATCH,Slave Read Address Match Interrupt" "0,1"
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newline
|
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hexmask.long.byte 0xC 16.--21. 1. "MAMI,Multiple Address Match Interrupt"
|
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bitfld.long 0xC 15. "TX_LOCKOUT,TX FIFO Locked Out Interrupt." "0,1"
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newline
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bitfld.long 0xC 14. "STOP_ERR,Out of Sequence STOP condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 13. "START_ERR,Out of Sequence START condition detected interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
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bitfld.long 0xC 12. "DNR_ERR,Slave Mode Do Not Respond Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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bitfld.long 0xC 11. "DATA_ERR,Master Mode Data NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
|
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bitfld.long 0xC 10. "ADDR_NACK_ERR,Master Mode Address NACK Received Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
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bitfld.long 0xC 9. "TO_ERR,Timeout Error Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
|
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bitfld.long 0xC 8. "ARB_ERR,Master Mode Arbitration Lost Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
|
|
bitfld.long 0xC 7. "ADDR_ACK,Received Address ACK from Slave Interrupt." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
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bitfld.long 0xC 6. "STOP,Stop Interrupt Enable" "0: Interrupt disabled.,1: Interrupt enabled when STOP = 1."
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bitfld.long 0xC 5. "TX_THD,TX FIFO Below Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
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newline
|
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bitfld.long 0xC 4. "RX_THD,RX FIFO Above Treshold Level Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled."
|
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bitfld.long 0xC 3. "ADDR_MATCH,Slave mode incoming address match interrupt." "0: Interrupt disabled.,1: Interrupt enabled when ADDR_MATCH = 1."
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newline
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bitfld.long 0xC 2. "GC_ADDR_MATCH,Slave mode general call address match received input enable." "0: Interrupt disabled.,1: Interrupt enabled when GEN_CTRL_ADDR = 1."
|
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bitfld.long 0xC 1. "IRXM,Description not available." "0: Interrupt disabled.,1: Interrupt enabled when RX_MODE = 1."
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newline
|
|
bitfld.long 0xC 0. "DONE,Transfer Done Interrupt Enable." "0: Interrupt disabled.,1: Interrupt enabled when DONE = 1."
|
|
line.long 0x10 "INTFL1,Interrupt Status Register 1."
|
|
bitfld.long 0x10 2. "START,START Condition Status Flag." "0,1"
|
|
bitfld.long 0x10 1. "TX_UN,Transmit Underflow Interrupt. When operating as a slave transmitter this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet)." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x10 0. "RX_OV,Receiver Overflow Interrupt. When operating as a slave receiver this bit is set when you reach the first data bit and the RX FIFO and shift register are both full." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
line.long 0x14 "INTEN1,Interrupt Staus Register 1."
|
|
bitfld.long 0x14 2. "START,START Condition Interrupt Enable." "0,1"
|
|
bitfld.long 0x14 1. "TX_UN,Transmit Underflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
newline
|
|
bitfld.long 0x14 0. "RX_OV,Receiver Overflow Interrupt Enable." "0: No Interrupt is Pending.,1: An interrupt is pending."
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "FIFOLEN,FIFO Configuration Register."
|
|
hexmask.long.byte 0x0 8.--15. 1. "TX_DEPTH,Transmit FIFO Length."
|
|
hexmask.long.byte 0x0 0.--7. 1. "RX_DEPTH,Receive FIFO Length."
|
|
group.long 0x1C++0x2F
|
|
line.long 0x0 "RXCTRL0,Receive Control Register 0."
|
|
hexmask.long.byte 0x0 8.--11. 1. "THD_LVL,Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold."
|
|
bitfld.long 0x0 7. "FLUSH,Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status." "0: FIFO not flushed.,1: Flush RX_FIFO."
|
|
newline
|
|
bitfld.long 0x0 0. "DNR,Do Not Respond." "0: Always respond to address match.,1: Do not respond to address match when RX_FIFO is.."
|
|
line.long 0x4 "RXCTRL1,Receive Control Register 1."
|
|
hexmask.long.byte 0x4 8.--11. 1. "LVL,Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0."
|
|
hexmask.long.byte 0x4 0.--7. 1. "CNT,Receive Count Bits. These bits define the number of bytes to be received in a transaction except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction."
|
|
line.long 0x8 "TXCTRL0,Transmit Control Register 0."
|
|
hexmask.long.byte 0x8 8.--11. 1. "THD_VAL,Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."
|
|
bitfld.long 0x8 7. "FLUSH,Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation." "0: FIFO not flushed.,1: Flush TX_FIFO."
|
|
newline
|
|
bitfld.long 0x8 5. "NACK_FLUSH_DIS,TX FIFO received NACK Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
bitfld.long 0x8 4. "RD_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Read Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
newline
|
|
bitfld.long 0x8 3. "WR_ADDR_FLUSH_DIS,TX FIFO Slave Address Match Write Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
bitfld.long 0x8 2. "GC_ADDR_FLUSH_DIS,TX FIFO General Call Address Match Auto Flush Disable." "0: Enabled.,1: Disabled."
|
|
newline
|
|
bitfld.long 0x8 1. "TX_READY_MODE,Transmit FIFO Ready Manual Mode." "0: HW control of I2CTXRDY enabled.,1: HW control of I2CTXRDY disabled."
|
|
bitfld.long 0x8 0. "PRELOAD_MODE,Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match." "0,1"
|
|
line.long 0xC "TXCTRL1,Transmit Control Register 1."
|
|
hexmask.long.byte 0xC 8.--11. 1. "LVL,Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO."
|
|
bitfld.long 0xC 0. "PRELOAD_RDY,Transmit FIFO Preload Ready." "0,1"
|
|
line.long 0x10 "FIFO,Data Register."
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA,Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location."
|
|
line.long 0x14 "MSTCTRL,Master Control Register."
|
|
bitfld.long 0x14 7. "EX_ADDR_EN,Slave Extend Address Select." "0: 7-bit address.,1: 10-bit address."
|
|
bitfld.long 0x14 2. "STOP,Setting this bit to 1 will generate a STOP condition." "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "RESTART,Setting this bit to 1 will generate a repeated START." "0,1"
|
|
bitfld.long 0x14 0. "START,Setting this bit to 1 will start a master transfer." "0,1"
|
|
line.long 0x18 "CLKLO,Clock Low Register."
|
|
hexmask.long.word 0x18 0.--8. 1. "LO,Clock low. In master mode these bits define the SCL low period. In slave mode these bits define the time SCL will be held low after data is outputted."
|
|
line.long 0x1C "CLKHI,Clock high Register."
|
|
hexmask.long.word 0x1C 0.--8. 1. "HI,Clock High. In master mode these bits define the SCL high period."
|
|
line.long 0x20 "HSCLK,Clock high Register."
|
|
hexmask.long.byte 0x20 8.--15. 1. "HI,Clock High. This field sets the Hs-Mode clock high count. In Slave mode this is the time SCL is held high after data is output on SDA"
|
|
hexmask.long.byte 0x20 0.--7. 1. "LO,Clock Low. This field sets the Hs-Mode clock low count. In Slave mode this is the time SCL is held low after data is output on SDA."
|
|
line.long 0x24 "TIMEOUT,Timeout Register"
|
|
hexmask.long.word 0x24 0.--15. 1. "SCL_TO_VAL,Timeout"
|
|
line.long 0x28 "SLAVE,Slave Address Register."
|
|
bitfld.long 0x28 15. "EXT_ADDR_EN,Extended Address Select." "0: 7-bit address.,1: 10-bit address."
|
|
hexmask.long.word 0x28 0.--9. 1. "ADDR,Slave Address."
|
|
line.long 0x2C "DMA,DMA Register."
|
|
bitfld.long 0x2C 1. "RX_EN,RX channel enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x2C 0. "TX_EN,TX channel enable." "0: Disable.,1: Enable."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "I2S (Inter-Integrated Sound)"
|
|
base ad:0x40060000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL0CH0,Global mode channel."
|
|
hexmask.long.byte 0x0 24.--31. 1. "RX_THD_VAL,depth of receive FIFO for threshold interrupt generation."
|
|
bitfld.long 0x0 20. "FIFO_LSB,Bit Field Control." "0,1"
|
|
bitfld.long 0x0 19. "RST,Write 1 to reset channel." "0,1"
|
|
bitfld.long 0x0 18. "FLUSH,Flushes the TX/RX FIFO buffer." "0,1"
|
|
bitfld.long 0x0 17. "RX_EN,RX channel enable." "0,1"
|
|
bitfld.long 0x0 16. "TX_EN,TX channel enable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "WSIZE,Data size when write to FIFO." "0,1,2,3"
|
|
rbitfld.long 0x0 12.--13. "STEREO,Stereo mode of I2S." "0,1,2,3"
|
|
bitfld.long 0x0 11. "EXT_SEL,External SCK/WS selection." "0,1"
|
|
rbitfld.long 0x0 10. "ALIGN,Align to MSB or LSB." "0,1"
|
|
rbitfld.long 0x0 9. "MSB_LOC,MSB location." "0,1"
|
|
bitfld.long 0x0 8. "WS_POL,WS polarity select." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CH_MODE,SCK Select." "0,1,2,3"
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 5. "PDM_INV,Invert PDM." "0,1"
|
|
bitfld.long 0x0 4. "USEDDR,DDR." "0,1"
|
|
bitfld.long 0x0 3. "PDM_EN,PDM Enable." "0,1"
|
|
bitfld.long 0x0 2. "PDM_FILT,PDM Filter." "0,1"
|
|
endif
|
|
bitfld.long 0x0 1. "LSB_FIRST,LSB Transmit Receive First." "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CTRL1CH0,Local channel Setup."
|
|
hexmask.long.word 0x0 16.--31. 1. "CLKDIV,I2S clock frequency divisor."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x0 15. "ADJST,LSB/MSB Justify." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 15. "ADJUST,LSB/MSB Justify." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 15. "ADJST,LSB/MSB Justify." "0,1"
|
|
endif
|
|
hexmask.long.byte 0x0 9.--13. 1. "SMP_SIZE,I2S sample size length."
|
|
bitfld.long 0x0 8. "EN,I2S clock enable." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "BITS_WORD,I2S word length."
|
|
sif (cpuis("MAX32672*"))
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FILTCH0,Filter."
|
|
endif
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "DMACH0,DMA Control."
|
|
hexmask.long.byte 0x0 24.--31. 1. "RX_LVL,Number of data word in the RX FIFO."
|
|
hexmask.long.byte 0x0 16.--23. 1. "TX_LVL,Number of data word in the TX FIFO."
|
|
bitfld.long 0x0 15. "DMA_RX_EN,RX DMA channel enable." "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "DMA_RX_THD_VAL,RX FIFO Level DMA Trigger."
|
|
bitfld.long 0x0 7. "DMA_TX_EN,TX DMA channel enable." "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "DMA_TX_THD_VAL,TX FIFO Level DMA Trigger."
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "FIFOCH0,I2S Fifo."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Load/unload location for TX and RX FIFO buffers."
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "INTFL,ISR Status."
|
|
bitfld.long 0x0 3. "TX_HE_CH0,Status for interrupt when TX FIFO is half empty." "0,1"
|
|
bitfld.long 0x0 2. "TX_OB_CH0,Status for interrupt when TX FIFO has only one byte remaining." "0,1"
|
|
bitfld.long 0x0 1. "RX_THD_CH0,Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field." "0,1"
|
|
bitfld.long 0x0 0. "RX_OV_CH0,Status for RX FIFO Overrun interrupt." "0,1"
|
|
line.long 0x4 "INTEN,Interrupt Enable."
|
|
bitfld.long 0x4 3. "TX_HE_CH0,Enable for interrupt when TX FIFO is half empty." "0,1"
|
|
bitfld.long 0x4 2. "TX_OB_CH0,Enable for interrupt when TX FIFO has only one byte remaining." "0,1"
|
|
bitfld.long 0x4 1. "RX_THD_CH0,Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field." "0,1"
|
|
bitfld.long 0x4 0. "RX_OV_CH0,Enable for RX FIFO Overrun interrupt." "0,1"
|
|
line.long 0x8 "EXTSETUP,Ext Control."
|
|
hexmask.long.byte 0x8 0.--4. 1. "EXT_BITS_WORD,Word Length for ch_mode."
|
|
sif (cpuis("MAX32672*"))
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "WKEN,Wakeup Enable."
|
|
line.long 0x4 "WKFL,Wakeup Flags."
|
|
endif
|
|
tree.end
|
|
tree "ICC (Instruction Cache Controller)"
|
|
base ad:0x4002A000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "INFO,Cache ID Register."
|
|
hexmask.long.byte 0x0 10.--15. 1. "ID,Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter."
|
|
hexmask.long.byte 0x0 6.--9. 1. "PARTNUM,Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter."
|
|
hexmask.long.byte 0x0 0.--5. 1. "RELNUM,Release Number. Identifies the RTL release version."
|
|
line.long 0x4 "SZ,Memory Configuration Register."
|
|
hexmask.long.word 0x4 16.--31. 1. "MEM,Main Memory Size. Indicates the total size in units of 128 Kbytes of code memory accessible to the cache controller."
|
|
hexmask.long.word 0x4 0.--15. 1. "CCH,Cache Size. Indicates total size in Kbytes of cache."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "CTRL,Cache Control and Status Register."
|
|
rbitfld.long 0x0 16. "RDY,Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0 the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill.." "0: Not Ready.,1: Ready."
|
|
bitfld.long 0x0 0. "EN,Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated." "0: Cache Bypassed. Instruction data is stored in..,1: Cache Enabled."
|
|
group.long 0x700++0x3
|
|
line.long 0x0 "INVALIDATE,Invalidate All Registers."
|
|
hexmask.long 0x0 0.--31. 1. "INVALID,Invalidate."
|
|
tree.end
|
|
tree "MCR (Miscellaneous Control Registers)"
|
|
base ad:0x40106C00
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "RST,Reset control register 0."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x0 3. "rtc,Setting this bit will reset the Real-Time Clock." "?,1: Reset Real-Time Clock."
|
|
bitfld.long 0x0 2. "lpuart0,Setting this bit will reset LPUART0." "?,1: Reset LPUART0."
|
|
newline
|
|
bitfld.long 0x0 1. "lptmr1,Setting this bit will reset LPTMR1." "?,1: Reset LPTMR1."
|
|
bitfld.long 0x0 0. "lptmr0,Setting this bit will reset LPTMR0." "?,1: Reset LPTMR0."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 2. "LPUART0,Low Power UART0 Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
bitfld.long 0x0 1. "LPTMR1,Low Power Timer1 Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
newline
|
|
bitfld.long 0x0 0. "LPTMR0,Low Power Timer0 Reset." "0: Reset complete.,1: Starts Reset or indicates reset in progress."
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 2. "LPUART0,Low Power UART0 Reset." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LPTMR1,Low Power Timer1 Reset." "0,1"
|
|
bitfld.long 0x0 0. "LPTMR0,Low Power Timer0 Reset." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "CLKCTRL,Clock Control."
|
|
bitfld.long 0x0 17. "ERTCO_EN,32KHz Crystal Oscillator Enable." "0: Is Disabled.,1: Is Enabled."
|
|
bitfld.long 0x0 16. "ERTCO_PD,32KHz Crystal Oscillator Power Down." "0,1"
|
|
line.long 0x4 "AINCOMP,AIN Comparator."
|
|
hexmask.long.byte 0x4 28.--31. 1. "PSEL_COMP1,Positive input select for AIN Comparator 1"
|
|
hexmask.long.byte 0x4 24.--27. 1. "NSEL_COMP1,Negative input select for AIN Comparator 1"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "PSEL_COMP0,Positive input select for AIN Comparator 0"
|
|
hexmask.long.byte 0x4 16.--19. 1. "NSEL_COMP0,Negative input select for AIN Comparator 0."
|
|
newline
|
|
bitfld.long 0x4 2.--3. "HYST,AIN Comparator Hysteresis control." "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "PD,AIN Comparator Power Down control." "0,1,2,3"
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32672*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "LPPIOCTRL,Low-power peripheral IO control."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x0 7. "LPUART0_RTS,Setting this bit will enable the low-power UART 0 (UART3) RTS pin while operating in low-power modes." "0: Disable LPUART0 RTS pin.,1: Enable LPUART0 RTS pin."
|
|
bitfld.long 0x0 6. "LPUART0_CTS,Setting this bit will enable the low-power UART 0 (UART3) CTS pin while operating in low-power modes." "0: Disable LPUART0 CTS pin.,1: Enable LPUART0 CTS pin."
|
|
newline
|
|
bitfld.long 0x0 5. "LPUART0_TX,Setting this bit will enable the low-power UART 0 (UART3) TX pin while operating in low-power modes." "0: Disable LPUART0 TX pin.,1: Enable LPUART0 TX pin."
|
|
bitfld.long 0x0 4. "LPUART0_RX,Setting this bit will enable the low-power UART 0 (UART3) RX pin while operating in low-power modes." "0: Disable LPUART0 RX pin.,1: Enable LPUART0 RX pin."
|
|
newline
|
|
bitfld.long 0x0 3. "LPTMR1_O,Setting this bit will enable the low-power timer 1 (timer 5) output pin while operating in low-power modes." "0: Disable LPTMR1 output pin.,1: Enable LPTMR1 output pin."
|
|
bitfld.long 0x0 2. "LPTMR1_I,Setting this bit will enable the low-power timer 1 (timer 5) input pin while operating in low-power modes." "0: Disable LPTMR1 input pin.,1: Enable LPTMR1 input pin."
|
|
newline
|
|
bitfld.long 0x0 1. "LPTMR0_O,Setting this bit will enable the low-power timer 0 (timer 4) output pin while operating in low-power modes." "0: Disable LPTMR0 output pin.,1: Enable LPTMR0 output pin."
|
|
bitfld.long 0x0 0. "LPTMR0_I,Setting this bit will enable the low-power timer 0 (timer 4) input pin while operating in low-power modes." "0: Disable LPTMR0 input pin.,1: Enable LPTMR0 input pin."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 7. "LPUART0_RTS,Enable control for LPUART0 RTS." "0,1"
|
|
bitfld.long 0x0 6. "LPUART0_CTS,Enable control for LPUART0 CTS." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LPUART0_TX,Enable control for LPUART0 TX." "0,1"
|
|
bitfld.long 0x0 4. "LPUART0_RX,Enable control for LPUART0 RX." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LPTMR1_O,Enable control for LPTMR1 output." "0,1"
|
|
bitfld.long 0x0 2. "LPTMR1_I,Enable control for LPTMR1 input." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LPTMR0_O,Enable control for LPTMR0 output." "0,1"
|
|
endif
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CLKDIS,Peripheral clock control register."
|
|
bitfld.long 0x0 2. "lpuart0,Clearing this bit will enable the low-power UART 0 (UART3) peripheral clock." "0: Enable LPUART0 clock.,1: Disable LPUART0 clock."
|
|
bitfld.long 0x0 1. "lptmr1,Clearing this bit will enable the low-power timer 1 (timer 5) peripheral clock." "0: Enable LPTMR1 clock.,1: Disable LPTMR1 clock."
|
|
newline
|
|
bitfld.long 0x0 0. "lptmr0,Clearing this bit will enable the low-power timer 0 (timer 4) peripheral clock." "0: Enable LPTMR0 clock.,1: Disable LPTMR0 clock."
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "PCLKDIS,Low Power Peripheral Clock Disable."
|
|
bitfld.long 0x0 2. "LPUART0,Low Power UART0 Clock Disable." "0: enable it.,1: disable it."
|
|
bitfld.long 0x0 1. "LPTMR1,Low Power Timer1 Clock Disable." "0: enable it.,1: disable it."
|
|
newline
|
|
bitfld.long 0x0 0. "LPTMR0,Low Power Timer0 Clock Disable." "0: enable it.,1: disable it."
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "AESKEY,AES Key Pointer and Status."
|
|
hexmask.long.word 0x0 0.--15. 1. "PTR,AESKEY Pointer and Status."
|
|
line.long 0x4 "ADC_CFG0,ADC Cfig Register0."
|
|
bitfld.long 0x4 3. "REF_SEL,Reference Select" "0,1"
|
|
bitfld.long 0x4 2. "EXT_REF,External Reference" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LP_50K_DIS,Disable 50K divider option in low power modes" "0: Enable.,1: Disable."
|
|
bitfld.long 0x4 0. "LP_5K_DIS,Disable 5K divider option in low power modes" "0: Enable.,1: Disable."
|
|
line.long 0x8 "ADC_CFG1,ADC Config Register1."
|
|
bitfld.long 0x8 12. "CH12_PU_DYN,ADC PU Dynamic Control for CH12" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
bitfld.long 0x8 11. "CH11_PU_DYN,ADC PU Dynamic Control for CH11" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
newline
|
|
bitfld.long 0x8 10. "CH10_PU_DYN,ADC PU Dynamic Control for CH10" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
bitfld.long 0x8 9. "CH9_PU_DYN,ADC PU Dynamic Control for CH9" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
newline
|
|
bitfld.long 0x8 8. "CH8_PU_DYN,ADC PU Dynamic Control for CH8" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
bitfld.long 0x8 7. "CH7_PU_DYN,ADC PU Dynamic Control for CH7" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
newline
|
|
bitfld.long 0x8 6. "CH6_PU_DYN,ADC PU Dynamic Control for CH6" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
bitfld.long 0x8 5. "CH5_PU_DYN,ADC PU Dynamic Control for CH5" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
newline
|
|
bitfld.long 0x8 4. "CH4_PU_DYN,ADC PU Dynamic Control for CH4" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
bitfld.long 0x8 3. "CH3_PU_DYN,ADC PU Dynamic Control for CH3" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
newline
|
|
bitfld.long 0x8 2. "CH2_PU_DYN,ADC PU Dynamic Control for CH2" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
bitfld.long 0x8 1. "CH1_PU_DYN,ADC PU Dynamic Control for CH1" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
newline
|
|
bitfld.long 0x8 0. "CH0_PU_DYN,ADC PU Dynamic Control for CH0" "0: divider select always used.,1: divider select only used when channel is selected."
|
|
line.long 0xC "ADC_CFG2,ADC Config Register2."
|
|
bitfld.long 0xC 24.--25. "CH12,Divider Select for channel 12" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
bitfld.long 0xC 22.--23. "CH11,Divider Select for channel 11" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
newline
|
|
bitfld.long 0xC 20.--21. "CH10,Divider Select for channel 10" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
bitfld.long 0xC 18.--19. "CH9,Divider Select for channel 9" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
newline
|
|
bitfld.long 0xC 16.--17. "CH8,Divider Select for channel 8" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
bitfld.long 0xC 14.--15. "CH7,Divider Select for channel 7" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
newline
|
|
bitfld.long 0xC 12.--13. "CH6,Divider Select for channel 6" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
bitfld.long 0xC 10.--11. "CH5,Divider Select for channel 5" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
newline
|
|
bitfld.long 0xC 8.--9. "CH4,Divider Select for channel 4" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
bitfld.long 0xC 6.--7. "CH3,Divider Select for channel 3" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
newline
|
|
bitfld.long 0xC 4.--5. "CH2,Divider Select for channel 2" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
bitfld.long 0xC 2.--3. "CH1,Divider Select for channel 1" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "CH0,Divider Select for channel 0" "0: Pass through no divider.,1: Divide by 2 5Kohm.,2: Divide by 2 50Kohm.,?"
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CLKDIS,Low Power Peripheral Clock Disable."
|
|
bitfld.long 0x0 2. "LPUART0,Low Power UART0 Clock Disable." "0,1"
|
|
bitfld.long 0x0 1. "LPTMR1,Low Power Timer1 Clock Disable." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LPTMR0,Low Power Timer0 Clock Disable." "0,1"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
base ad:0x40106800
|
|
elif (cpuis("MAX32672*")||cpuis("MAX32675*"))
|
|
base ad:0x40006800
|
|
endif
|
|
tree "PWRSEQ (Power Sequencer)"
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "LPCN,Low Power Control Register."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x0 31. "ERTCO_PD,ERTCO Powerdown." "0,1"
|
|
bitfld.long 0x0 6. "VCORE_DET_BYPASS,Block Auto-Detect" "0: enable,1: disable"
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 31. "TM_PWRSEQ,TBD" "0,1"
|
|
bitfld.long 0x0 30. "TM_LPMODE,TBD" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 31. "TM_PWRSEQ,TBD" "0,1"
|
|
bitfld.long 0x0 30. "TM_LPMODE,TBD" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 29. "ERTCO_EN,XRTCO remains on in all power modes if this bit is set otherwise it is controled by the LP controller" "0,1"
|
|
bitfld.long 0x0 28. "INRO_EN,INRO remains on in all power modes if this bit is set otherwise it is controled by the LP controller" "0,1"
|
|
newline
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 27. "VBBMON_DIS,VBB Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes." "0: Enable if Bandgap is ON (default),1: Disabled."
|
|
endif
|
|
bitfld.long 0x0 25. "PORVDDMON_DIS,VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods." "0: Disabled.,1: Enabled."
|
|
newline
|
|
bitfld.long 0x0 22. "VDDAMON_DIS,VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes." "0: Enable if Bandgap is ON (default),1: Disabled."
|
|
bitfld.long 0x0 20. "VCOREMON_DIS,VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes." "0: Enable,1: Disabled."
|
|
newline
|
|
bitfld.long 0x0 17. "VCORE_EXT,Use external VCORE for 1V supply" "0: disable,1: use Vcore for retention."
|
|
bitfld.long 0x0 16. "LDO_DIS,Disable Main LDO" "0: Enable,1: Disabled."
|
|
newline
|
|
bitfld.long 0x0 12. "VCOREPOR_DIS,VDDC (Vcore) Power on reset Monitor Disable.This bit controls the Power-On Reset monitor on VDDC supply in" "0: Enable,1: Disabled."
|
|
bitfld.long 0x0 11. "BG_DIS,Bandgap OFF. This controls the System Bandgap in DeepSleep mode." "0: Bandgap is always ON.,1: Bandgap is OFF in DeepSleep mode (default)."
|
|
newline
|
|
bitfld.long 0x0 10. "FASTWK_EN,Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical)." "0: Disabled.,1: Enabled."
|
|
bitfld.long 0x0 9. "STORAGE_EN,STORAGE Mode ENable. This bit allows low-power background mode operations while the CPU is in DeepSleep." "0: Disabled.,1: Enabled."
|
|
newline
|
|
bitfld.long 0x0 8. "RETREG_EN,Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode." "0: Disabled.,1: Enabled."
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x0 7. "FVDDEN,Flash VDD Enable force the flash VDD to remain enabled during LP modes." "0: enable,1: disable"
|
|
newline
|
|
bitfld.long 0x0 6. "VCORE_DET_BYPASS,Block Auto-Detect" "0: enable,1: disable"
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 6. "VCORE_DET_BYPASS,Block Auto-Detect" "0: enable,1: disable"
|
|
endif
|
|
newline
|
|
bitfld.long 0x0 4.--5. "OVR,Operating Voltage Range" "0: 0.9V 24MHz,1: 1.0V 48MHz,2: 1.1V 96MHz,?"
|
|
bitfld.long 0x0 3. "RAM3RET_EN,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 3 retention."
|
|
newline
|
|
bitfld.long 0x0 2. "RAM2RET_EN,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 2 retention."
|
|
bitfld.long 0x0 1. "RAM1RET_EN,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 1 retention."
|
|
newline
|
|
bitfld.long 0x0 0. "RAM0RET_EN,System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit." "0: Disable Ram Retention.,1: Enable System RAM 0 retention."
|
|
line.long 0x4 "LPWKST0,Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x4 0. "ST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected using PM.GPIOWKEN register and the.." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
hexmask.long 0x4 0.--30. 1. "ST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected using PM.GPIOWKEN register and the.."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x4 0. "ST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected using PM.GPIOWKEN register and the.." "0,1"
|
|
endif
|
|
line.long 0x8 "LPWKEN0,Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0."
|
|
hexmask.long 0x8 0.--30. 1. "EN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register."
|
|
line.long 0xC "LPWKST1,Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0xC 0. "ST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected using PM.GPIOWKEN register and the.." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
hexmask.long 0xC 0.--30. 1. "ST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected using PM.GPIOWKEN register and the.."
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0xC 0. "ST,Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected using PM.GPIOWKEN register and the.." "0,1"
|
|
endif
|
|
line.long 0x10 "LPWKEN1,Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1."
|
|
hexmask.long 0x10 0.--30. 1. "EN,Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register."
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "LPPWKST,Low Power Peripheral Wakeup Status Register."
|
|
sif (cpuis("MAX32672*"))
|
|
eventfld.long 0x0 16. "BACKUP,BBMODE Wakeup Flag." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
rbitfld.long 0x0 6. "AINCOMP1_OUT,AINCOMP1 Status." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 5. "AINCOMP0_OUT,AINCOMP0 Status." "0,1"
|
|
eventfld.long 0x0 4. "AINCOMP1,AINCOMP1 Wakeup Flag." "0,1"
|
|
newline
|
|
eventfld.long 0x0 3. "AINCOMP0,AINCOMP0 Wakeup Flag." "0,1"
|
|
eventfld.long 0x0 2. "LPUART0,LPUART0 Wakeup Flag." "0,1"
|
|
newline
|
|
eventfld.long 0x0 1. "LPTMR1,LPTMR1 Wakeup Flag." "0,1"
|
|
eventfld.long 0x0 0. "LPTMR0,LPTM0 Wakeup Flag." "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
bitfld.long 0x0 2. "LPUART0,LPUART0 Wakeup Flag." "0,1"
|
|
bitfld.long 0x0 1. "LPTMR1,LPTMR1 Wakeup Flag." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LPTMR0,LPTM0 Wakeup Flag." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 2. "LPUART0,LPUART0 Wakeup Flag." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LPTMR1,LPTMR1 Wakeup Flag." "0,1"
|
|
bitfld.long 0x0 0. "LPTMR0,LPTM0 Wakeup Flag." "0,1"
|
|
endif
|
|
line.long 0x4 "LPPWKEN,Low Power Peripheral Wakeup Enable Register."
|
|
sif (cpuis("MAX32672*"))
|
|
bitfld.long 0x4 4. "AINCOMP1,AINCOMP1 Wakeup Enable. This bit allows wakeup from the AINCOMP1." "0,1"
|
|
bitfld.long 0x4 3. "AINCOMP0,AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0." "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 2. "LPUART0,LPUART Wakeup Enable. This bit allows wakeup from the LPUART." "0,1"
|
|
bitfld.long 0x4 1. "LPTMR1,TIMER5 Wakeup Enable. This bit allows wakeup from the TIMER5." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LPTMR0,TIMER4 Wakeup Enable. This bit allows wakeup from the TIMER4." "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "LPMEMSD,Low Power Memory Shutdown Control."
|
|
bitfld.long 0x0 3. "RAM3,System RAM block 3 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode."
|
|
bitfld.long 0x0 2. "RAM2,System RAM block 2 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode."
|
|
newline
|
|
bitfld.long 0x0 1. "RAM1,System RAM block 1 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode."
|
|
bitfld.long 0x0 0. "RAM0,System RAM block 0 Shut Down." "0: Normal Operating Mode.,1: Shutdown Mode."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
group.long 0x48++0x7
|
|
line.long 0x0 "GP0,General Purpose Register 0"
|
|
line.long 0x4 "GP1,General Purpose Register 1"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
group.long 0x48++0x7
|
|
line.long 0x0 "GPR0,General Purpose Register 0."
|
|
line.long 0x4 "GPR1,General Purpose Register 1."
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MAX32672*"))
|
|
tree "QDEC (Quadrature Encoder Interface)"
|
|
base ad:0x40063000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTRL,Control Register."
|
|
bitfld.long 0x0 16.--18. "psc," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8. "sticky," "0,1"
|
|
bitfld.long 0x0 7. "rst_maxcnt," "0,1"
|
|
bitfld.long 0x0 6. "rst_index," "0,1"
|
|
bitfld.long 0x0 4.--5. "filter," "0,1,2,3"
|
|
bitfld.long 0x0 3. "swap," "0,1"
|
|
bitfld.long 0x0 1.--2. "mode," "0,1,2,3"
|
|
bitfld.long 0x0 0. "en," "0,1"
|
|
line.long 0x4 "INTFL,Interrupt Flag Register."
|
|
eventfld.long 0x4 6. "move," "0,1"
|
|
eventfld.long 0x4 5. "dir," "0,1"
|
|
eventfld.long 0x4 4. "capture," "0,1"
|
|
eventfld.long 0x4 3. "maxcnt," "0,1"
|
|
eventfld.long 0x4 2. "compare," "0,1"
|
|
eventfld.long 0x4 1. "qerr," "0,1"
|
|
eventfld.long 0x4 0. "index," "0,1"
|
|
line.long 0x8 "INTEN,Interrupt Enable Register."
|
|
bitfld.long 0x8 6. "move," "0,1"
|
|
bitfld.long 0x8 5. "dir," "0,1"
|
|
bitfld.long 0x8 4. "capture," "0,1"
|
|
bitfld.long 0x8 3. "maxcnt," "0,1"
|
|
bitfld.long 0x8 2. "compare," "0,1"
|
|
bitfld.long 0x8 1. "qerr," "0,1"
|
|
bitfld.long 0x8 0. "index," "0,1"
|
|
line.long 0xC "MAXCNT,Maximum Count Register."
|
|
hexmask.long 0xC 0.--31. 1. "maxcnt,"
|
|
line.long 0x10 "INITIAL,Initial Count Register."
|
|
hexmask.long 0x10 0.--31. 1. "initial,"
|
|
line.long 0x14 "COMPARE,Compare Register."
|
|
hexmask.long 0x14 0.--31. 1. "compare,"
|
|
rgroup.long 0x18++0xF
|
|
line.long 0x0 "INDEX,Index Register. count captured when QEI fired"
|
|
hexmask.long 0x0 0.--31. 1. "index,"
|
|
line.long 0x4 "CAPTURE,Capture Register. counter captured when QES fired"
|
|
hexmask.long 0x4 0.--31. 1. "capture,"
|
|
line.long 0x8 "STATUS,Status Register."
|
|
bitfld.long 0x8 0. "dir," "0,1"
|
|
line.long 0xC "POSITION,Count Register. raw counter value"
|
|
hexmask.long 0xC 0.--31. 1. "position,"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CAPDLY,delay CAPTURE"
|
|
hexmask.long 0x0 0.--31. 1. "capdly,"
|
|
tree.end
|
|
endif
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0x40106000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "SEC,RTC Second Counter. This register contains the 32-bit second counter."
|
|
hexmask.long.byte 0x0 0.--7. 1. "SEC,Seconds Counter."
|
|
line.long 0x4 "SSEC,RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00."
|
|
hexmask.long.byte 0x4 0.--7. 1. "SSEC,Sub-Seconds Counter (12-bit)."
|
|
line.long 0x8 "TODA,Time-of-day Alarm."
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "TOD_ALARM,Time-of-day Alarm."
|
|
line.long 0xC "SSECA,RTC sub-second alarm. This register contains the reload value for the sub-second alarm."
|
|
hexmask.long 0xC 0.--31. 1. "SSEC_ALARM,This register contains the reload value for the sub-second alarm."
|
|
line.long 0x10 "CTRL,RTC Control Register."
|
|
bitfld.long 0x10 15. "WR_EN,Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits." "0: Not active,1: Active"
|
|
bitfld.long 0x10 14. "RD_EN,Asynchronous Counter Read Enable." "0,1"
|
|
bitfld.long 0x10 9.--10. "SQW_SEL,Frequency Output Selection. When SQE=1 these bits specify the output frequency on the SQW pin." "0: 1 Hz (Compensated).,1: 512 Hz (Compensated).,2: 4 KHz.,3: RTC Input Clock / 8."
|
|
bitfld.long 0x10 8. "SQW_EN,Square Wave Output Enable." "0: Not active,1: Active"
|
|
newline
|
|
rbitfld.long 0x10 7. "SSEC_ALARM,Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor." "0: Not active,1: Active"
|
|
rbitfld.long 0x10 6. "TOD_ALARM,Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor." "0: Not active,1: Active"
|
|
bitfld.long 0x10 5. "RDY_IE,RTC Ready Interrupt Enable." "0: Disable.,1: Enable."
|
|
bitfld.long 0x10 4. "RDY,RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register." "0: Register has not updated.,1: Ready."
|
|
newline
|
|
rbitfld.long 0x10 3. "BUSY,RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware." "0: Idle.,1: Busy."
|
|
bitfld.long 0x10 2. "SSEC_ALARM_IE,Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0." "0: Disable.,1: Enable."
|
|
bitfld.long 0x10 1. "TOD_ALARM_IE,Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0." "0: Disable.,1: Enable."
|
|
bitfld.long 0x10 0. "EN,Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0." "0: Disable.,1: Enable."
|
|
line.long 0x14 "TRIM,RTC Trim Register."
|
|
hexmask.long.tbyte 0x14 8.--31. 1. "VRTC_TMR,VBAT Timer Value. When RTC is running off of VBAT this field is incremented every 32 seconds."
|
|
hexmask.long.byte 0x14 0.--7. 1. "TRIM,RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value with a maximum correction of +/- 127ppm."
|
|
line.long 0x18 "OSCCTRL,RTC Oscillator Control Register."
|
|
bitfld.long 0x18 5. "SQW_32K,RTC 32kHz Square Wave Output" "0,1"
|
|
bitfld.long 0x18 4. "BYPASS,RTC Crystal Bypass" "0,1"
|
|
tree.end
|
|
tree "SIR (System Initialization Registers)"
|
|
base ad:0x40000400
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*"))
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "SIR_STATUS,System Initialization Status Register."
|
|
bitfld.long 0x0 1. "CFG_ERR,Configuration Error Flag." "0,1"
|
|
bitfld.long 0x0 0. "CFG_VALID,Configuration Valid Flag." "0,1"
|
|
line.long 0x4 "SIR_ADDR,Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1)."
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,"
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "STATUS,System Initialization Status Register."
|
|
bitfld.long 0x0 2. "USER_CFG_ERR,User Configuration Error Flag." "0,1"
|
|
bitfld.long 0x0 1. "CFG_ERR,Configuration Error Flag." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CFG_VALID,Configuration Valid Flag." "0,1"
|
|
line.long 0x4 "ADDR,Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1)."
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,"
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "SIR_STATUS,System Initialization Status Register."
|
|
bitfld.long 0x0 1. "CFG_ERR,Configuration Error Flag." "0,1"
|
|
bitfld.long 0x0 0. "CFG_VALID,Configuration Valid Flag." "0,1"
|
|
line.long 0x4 "SIR_ADDR,Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1)."
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,"
|
|
endif
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32675*"))
|
|
tree "SPI0"
|
|
base ad:0x40046000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO32,Register for reading and writing the FIFO."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "FIFO16[$1],Register for reading and writing the FIFO."
|
|
hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "FIFO8[$1],Register for reading and writing the FIFO."
|
|
hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CTRL0,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SS_ACTIVE,Slave Select when in Master mode selects which Slave devices are selected. More than one Slave device can be selected."
|
|
bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.."
|
|
newline
|
|
bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.."
|
|
bitfld.long 0x0 4. "SS_IO,Slave Select 0 IO direction to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1."
|
|
newline
|
|
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode."
|
|
bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled."
|
|
line.long 0x4 "CTRL1,Register for controlling SPI peripheral."
|
|
hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive."
|
|
hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit."
|
|
line.long 0x8 "CTRL2,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity each Slave Select can have unique polarity."
|
|
bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?"
|
|
hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character."
|
|
newline
|
|
bitfld.long 0x8 1. "CLKPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3"
|
|
bitfld.long 0x8 0. "CLKPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.."
|
|
line.long 0xC "SSTIME,Register for controlling SPI peripheral/Slave Select Timing."
|
|
hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay."
|
|
hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1."
|
|
line.long 0x10 "CLKCTRL,Register for controlling SPI clock rate."
|
|
hexmask.long.byte 0x10 16.--19. 1. "CLKDIV,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."
|
|
hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode reload[15:8]."
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode reload[7:0]."
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "DMA,Register for controlling DMA."
|
|
bitfld.long 0x0 31. "DMA_RX_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled."
|
|
hexmask.long.byte 0x0 24.--29. 1. "RX_LVL,Count of entries in RX FIFO."
|
|
newline
|
|
bitfld.long 0x0 23. "RX_FLUSH,Clear RX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.."
|
|
bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "RX_THD_VAL,Receive FIFO level that will trigger a DMA request also level for threshold status. When RX FIFO has more than this many bytes the associated events and conditions are triggered."
|
|
bitfld.long 0x0 15. "DMA_TX_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TX_LVL,Count of entries in TX FIFO."
|
|
bitfld.long 0x0 7. "TX_FLUSH,Clear TX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Transmit FIFO clears any pending TX.."
|
|
newline
|
|
bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled."
|
|
hexmask.long.byte 0x0 0.--4. 1. "TX_THD_VAL,Transmit FIFO level that will trigger a DMA request also level for threshold status. When TX FIFO has fewer than this many bytes the associated events and conditions are triggered."
|
|
line.long 0x4 "INTFL,Register for reading and clearing interrupt flags. All bits are write 1 to clear."
|
|
bitfld.long 0x4 15. "RX_UN,Receive FIFO Underrun set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 14. "RX_OV,Receive FIFO Overrun set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 13. "TX_UN,Transmit FIFO Underrun set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 12. "TX_OV,Transmit FIFO Overrun set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 11. "MST_DONE,Master Done set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 2. "RX_THD,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 1. "TX_EM,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 0. "TX_THD,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x8 "INTEN,Register for enabling interrupts."
|
|
bitfld.long 0x8 15. "RX_UN,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 14. "RX_OV,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 13. "TX_UN,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 12. "TX_OV,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 11. "MST_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 2. "RX_THD,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 1. "TX_EM,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 0. "TX_THD,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
line.long 0xC "WKFL,Register for wake up flags. All bits in this register are write 1 to clear."
|
|
bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 2. "RX_THD,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0xC 1. "TX_EM,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 0. "TX_THD,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x10 "WKEN,Register for wake up enable."
|
|
bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 2. "RX_THD,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
newline
|
|
bitfld.long 0x10 1. "TX_EM,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 0. "TX_THD,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "STAT,SPI Status register."
|
|
bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode set when transaction starts cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode set when Slave Select is asserted cleared when Slave Select is.." "0: SPI not active.,1: SPI active."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32675*"))
|
|
tree "SPI1"
|
|
base ad:0x40047000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO32,Register for reading and writing the FIFO."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "FIFO16[$1],Register for reading and writing the FIFO."
|
|
hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "FIFO8[$1],Register for reading and writing the FIFO."
|
|
hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CTRL0,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SS_ACTIVE,Slave Select when in Master mode selects which Slave devices are selected. More than one Slave device can be selected."
|
|
bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.."
|
|
newline
|
|
bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.."
|
|
bitfld.long 0x0 4. "SS_IO,Slave Select 0 IO direction to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1."
|
|
newline
|
|
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode."
|
|
bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled."
|
|
line.long 0x4 "CTRL1,Register for controlling SPI peripheral."
|
|
hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive."
|
|
hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit."
|
|
line.long 0x8 "CTRL2,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity each Slave Select can have unique polarity."
|
|
bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?"
|
|
hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character."
|
|
newline
|
|
bitfld.long 0x8 1. "CLKPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3"
|
|
bitfld.long 0x8 0. "CLKPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.."
|
|
line.long 0xC "SSTIME,Register for controlling SPI peripheral/Slave Select Timing."
|
|
hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay."
|
|
hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1."
|
|
line.long 0x10 "CLKCTRL,Register for controlling SPI clock rate."
|
|
hexmask.long.byte 0x10 16.--19. 1. "CLKDIV,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."
|
|
hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode reload[15:8]."
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode reload[7:0]."
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "DMA,Register for controlling DMA."
|
|
bitfld.long 0x0 31. "DMA_RX_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled."
|
|
hexmask.long.byte 0x0 24.--29. 1. "RX_LVL,Count of entries in RX FIFO."
|
|
newline
|
|
bitfld.long 0x0 23. "RX_FLUSH,Clear RX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.."
|
|
bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "RX_THD_VAL,Receive FIFO level that will trigger a DMA request also level for threshold status. When RX FIFO has more than this many bytes the associated events and conditions are triggered."
|
|
bitfld.long 0x0 15. "DMA_TX_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TX_LVL,Count of entries in TX FIFO."
|
|
bitfld.long 0x0 7. "TX_FLUSH,Clear TX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Transmit FIFO clears any pending TX.."
|
|
newline
|
|
bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled."
|
|
hexmask.long.byte 0x0 0.--4. 1. "TX_THD_VAL,Transmit FIFO level that will trigger a DMA request also level for threshold status. When TX FIFO has fewer than this many bytes the associated events and conditions are triggered."
|
|
line.long 0x4 "INTFL,Register for reading and clearing interrupt flags. All bits are write 1 to clear."
|
|
bitfld.long 0x4 15. "RX_UN,Receive FIFO Underrun set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 14. "RX_OV,Receive FIFO Overrun set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 13. "TX_UN,Transmit FIFO Underrun set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 12. "TX_OV,Transmit FIFO Overrun set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 11. "MST_DONE,Master Done set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 2. "RX_THD,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 1. "TX_EM,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 0. "TX_THD,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x8 "INTEN,Register for enabling interrupts."
|
|
bitfld.long 0x8 15. "RX_UN,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 14. "RX_OV,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 13. "TX_UN,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 12. "TX_OV,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 11. "MST_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 2. "RX_THD,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 1. "TX_EM,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 0. "TX_THD,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
line.long 0xC "WKFL,Register for wake up flags. All bits in this register are write 1 to clear."
|
|
bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 2. "RX_THD,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0xC 1. "TX_EM,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 0. "TX_THD,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x10 "WKEN,Register for wake up enable."
|
|
bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 2. "RX_THD,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
newline
|
|
bitfld.long 0x10 1. "TX_EM,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 0. "TX_THD,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "STAT,SPI Status register."
|
|
bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode set when transaction starts cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode set when Slave Select is asserted cleared when Slave Select is.." "0: SPI not active.,1: SPI active."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32675*"))
|
|
tree "SPI2"
|
|
base ad:0x40048000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO32,Register for reading and writing the FIFO."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "FIFO16[$1],Register for reading and writing the FIFO."
|
|
hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "FIFO8[$1],Register for reading and writing the FIFO."
|
|
hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CTRL0,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SS_ACTIVE,Slave Select when in Master mode selects which Slave devices are selected. More than one Slave device can be selected."
|
|
bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.."
|
|
newline
|
|
bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.."
|
|
bitfld.long 0x0 4. "SS_IO,Slave Select 0 IO direction to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1."
|
|
newline
|
|
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode."
|
|
bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled."
|
|
line.long 0x4 "CTRL1,Register for controlling SPI peripheral."
|
|
hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive."
|
|
hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit."
|
|
line.long 0x8 "CTRL2,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity each Slave Select can have unique polarity."
|
|
bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?"
|
|
hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character."
|
|
newline
|
|
bitfld.long 0x8 1. "CLKPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3"
|
|
bitfld.long 0x8 0. "CLKPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.."
|
|
line.long 0xC "SSTIME,Register for controlling SPI peripheral/Slave Select Timing."
|
|
hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay."
|
|
hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1."
|
|
line.long 0x10 "CLKCTRL,Register for controlling SPI clock rate."
|
|
hexmask.long.byte 0x10 16.--19. 1. "CLKDIV,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."
|
|
hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode reload[15:8]."
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode reload[7:0]."
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "DMA,Register for controlling DMA."
|
|
bitfld.long 0x0 31. "DMA_RX_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled."
|
|
hexmask.long.byte 0x0 24.--29. 1. "RX_LVL,Count of entries in RX FIFO."
|
|
newline
|
|
bitfld.long 0x0 23. "RX_FLUSH,Clear RX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.."
|
|
bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "RX_THD_VAL,Receive FIFO level that will trigger a DMA request also level for threshold status. When RX FIFO has more than this many bytes the associated events and conditions are triggered."
|
|
bitfld.long 0x0 15. "DMA_TX_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TX_LVL,Count of entries in TX FIFO."
|
|
bitfld.long 0x0 7. "TX_FLUSH,Clear TX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Transmit FIFO clears any pending TX.."
|
|
newline
|
|
bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled."
|
|
hexmask.long.byte 0x0 0.--4. 1. "TX_THD_VAL,Transmit FIFO level that will trigger a DMA request also level for threshold status. When TX FIFO has fewer than this many bytes the associated events and conditions are triggered."
|
|
line.long 0x4 "INTFL,Register for reading and clearing interrupt flags. All bits are write 1 to clear."
|
|
bitfld.long 0x4 15. "RX_UN,Receive FIFO Underrun set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 14. "RX_OV,Receive FIFO Overrun set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 13. "TX_UN,Transmit FIFO Underrun set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 12. "TX_OV,Transmit FIFO Overrun set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 11. "MST_DONE,Master Done set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 2. "RX_THD,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 1. "TX_EM,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 0. "TX_THD,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x8 "INTEN,Register for enabling interrupts."
|
|
bitfld.long 0x8 15. "RX_UN,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 14. "RX_OV,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 13. "TX_UN,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 12. "TX_OV,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 11. "MST_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 2. "RX_THD,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 1. "TX_EM,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 0. "TX_THD,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
line.long 0xC "WKFL,Register for wake up flags. All bits in this register are write 1 to clear."
|
|
bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 2. "RX_THD,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0xC 1. "TX_EM,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 0. "TX_THD,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x10 "WKEN,Register for wake up enable."
|
|
bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 2. "RX_THD,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
newline
|
|
bitfld.long 0x10 1. "TX_EM,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 0. "TX_THD,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "STAT,SPI Status register."
|
|
bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode set when transaction starts cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode set when Slave Select is asserted cleared when Slave Select is.." "0: SPI not active.,1: SPI active."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "SPI0"
|
|
base ad:0x40046000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO32,Register for reading and writing the FIFO."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "FIFO16[$1],Register for reading and writing the FIFO."
|
|
hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "FIFO8[$1],Register for reading and writing the FIFO."
|
|
hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CTRL0,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SS_ACTIVE,Slave Select when in Master mode selects which Slave devices are selected. More than one Slave device can be selected."
|
|
bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.."
|
|
newline
|
|
bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.."
|
|
bitfld.long 0x0 4. "SS_IO,Slave Select 0 IO direction to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1."
|
|
newline
|
|
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode."
|
|
bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled."
|
|
line.long 0x4 "CTRL1,Register for controlling SPI peripheral."
|
|
hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive."
|
|
hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit."
|
|
line.long 0x8 "CTRL2,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity each Slave Select can have unique polarity."
|
|
bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?"
|
|
hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character."
|
|
newline
|
|
bitfld.long 0x8 4. "SCLK_FB_INV,SCLK_FB_INV." "0,1"
|
|
bitfld.long 0x8 1. "CLKPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3"
|
|
newline
|
|
bitfld.long 0x8 0. "CLKPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.."
|
|
line.long 0xC "SSTIME,Register for controlling SPI peripheral/Slave Select Timing."
|
|
hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay."
|
|
hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1."
|
|
line.long 0x10 "CLKCTRL,Register for controlling SPI clock rate."
|
|
hexmask.long.byte 0x10 16.--19. 1. "CLKDIV,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."
|
|
hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode reload[15:8]."
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode reload[7:0]."
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "DMA,Register for controlling DMA."
|
|
bitfld.long 0x0 31. "DMA_RX_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled."
|
|
hexmask.long.byte 0x0 24.--29. 1. "RX_LVL,Count of entries in RX FIFO."
|
|
newline
|
|
bitfld.long 0x0 23. "RX_FLUSH,Clear RX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.."
|
|
bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "RX_THD_VAL,Receive FIFO level that will trigger a DMA request also level for threshold status. When RX FIFO has more than this many bytes the associated events and conditions are triggered."
|
|
bitfld.long 0x0 15. "DMA_TX_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TX_LVL,Count of entries in TX FIFO."
|
|
bitfld.long 0x0 7. "TX_FLUSH,Clear TX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Transmit FIFO clears any pending TX.."
|
|
newline
|
|
bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled."
|
|
hexmask.long.byte 0x0 0.--4. 1. "TX_THD_VAL,Transmit FIFO level that will trigger a DMA request also level for threshold status. When TX FIFO has fewer than this many bytes the associated events and conditions are triggered."
|
|
line.long 0x4 "INTFL,Register for reading and clearing interrupt flags. All bits are write 1 to clear."
|
|
bitfld.long 0x4 15. "RX_UN,Receive FIFO Underrun set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 14. "RX_OV,Receive FIFO Overrun set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 13. "TX_UN,Transmit FIFO Underrun set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 12. "TX_OV,Transmit FIFO Overrun set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 11. "MST_DONE,Master Done set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 2. "RX_THD,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 1. "TX_EM,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 0. "TX_THD,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x8 "INTEN,Register for enabling interrupts."
|
|
bitfld.long 0x8 15. "RX_UN,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 14. "RX_OV,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 13. "TX_UN,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 12. "TX_OV,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 11. "MST_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 2. "RX_THD,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 1. "TX_EM,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 0. "TX_THD,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
line.long 0xC "WKFL,Register for wake up flags. All bits in this register are write 1 to clear."
|
|
bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 2. "RX_THD,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0xC 1. "TX_EM,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 0. "TX_THD,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x10 "WKEN,Register for wake up enable."
|
|
bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 2. "RX_THD,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
newline
|
|
bitfld.long 0x10 1. "TX_EM,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 0. "TX_THD,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "STAT,SPI Status register."
|
|
bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode set when transaction starts cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode set when Slave Select is asserted cleared when Slave Select is.." "0: SPI not active.,1: SPI active."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "SPI1"
|
|
base ad:0x40047000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO32,Register for reading and writing the FIFO."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "FIFO16[$1],Register for reading and writing the FIFO."
|
|
hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "FIFO8[$1],Register for reading and writing the FIFO."
|
|
hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CTRL0,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SS_ACTIVE,Slave Select when in Master mode selects which Slave devices are selected. More than one Slave device can be selected."
|
|
bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.."
|
|
newline
|
|
bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.."
|
|
bitfld.long 0x0 4. "SS_IO,Slave Select 0 IO direction to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1."
|
|
newline
|
|
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode."
|
|
bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled."
|
|
line.long 0x4 "CTRL1,Register for controlling SPI peripheral."
|
|
hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive."
|
|
hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit."
|
|
line.long 0x8 "CTRL2,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity each Slave Select can have unique polarity."
|
|
bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?"
|
|
hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character."
|
|
newline
|
|
bitfld.long 0x8 4. "SCLK_FB_INV,SCLK_FB_INV." "0,1"
|
|
bitfld.long 0x8 1. "CLKPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3"
|
|
newline
|
|
bitfld.long 0x8 0. "CLKPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.."
|
|
line.long 0xC "SSTIME,Register for controlling SPI peripheral/Slave Select Timing."
|
|
hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay."
|
|
hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1."
|
|
line.long 0x10 "CLKCTRL,Register for controlling SPI clock rate."
|
|
hexmask.long.byte 0x10 16.--19. 1. "CLKDIV,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."
|
|
hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode reload[15:8]."
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode reload[7:0]."
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "DMA,Register for controlling DMA."
|
|
bitfld.long 0x0 31. "DMA_RX_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled."
|
|
hexmask.long.byte 0x0 24.--29. 1. "RX_LVL,Count of entries in RX FIFO."
|
|
newline
|
|
bitfld.long 0x0 23. "RX_FLUSH,Clear RX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.."
|
|
bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "RX_THD_VAL,Receive FIFO level that will trigger a DMA request also level for threshold status. When RX FIFO has more than this many bytes the associated events and conditions are triggered."
|
|
bitfld.long 0x0 15. "DMA_TX_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TX_LVL,Count of entries in TX FIFO."
|
|
bitfld.long 0x0 7. "TX_FLUSH,Clear TX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Transmit FIFO clears any pending TX.."
|
|
newline
|
|
bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled."
|
|
hexmask.long.byte 0x0 0.--4. 1. "TX_THD_VAL,Transmit FIFO level that will trigger a DMA request also level for threshold status. When TX FIFO has fewer than this many bytes the associated events and conditions are triggered."
|
|
line.long 0x4 "INTFL,Register for reading and clearing interrupt flags. All bits are write 1 to clear."
|
|
bitfld.long 0x4 15. "RX_UN,Receive FIFO Underrun set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 14. "RX_OV,Receive FIFO Overrun set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 13. "TX_UN,Transmit FIFO Underrun set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 12. "TX_OV,Transmit FIFO Overrun set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 11. "MST_DONE,Master Done set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 2. "RX_THD,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 1. "TX_EM,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 0. "TX_THD,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x8 "INTEN,Register for enabling interrupts."
|
|
bitfld.long 0x8 15. "RX_UN,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 14. "RX_OV,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 13. "TX_UN,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 12. "TX_OV,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 11. "MST_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 2. "RX_THD,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 1. "TX_EM,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 0. "TX_THD,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
line.long 0xC "WKFL,Register for wake up flags. All bits in this register are write 1 to clear."
|
|
bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 2. "RX_THD,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0xC 1. "TX_EM,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 0. "TX_THD,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x10 "WKEN,Register for wake up enable."
|
|
bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 2. "RX_THD,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
newline
|
|
bitfld.long 0x10 1. "TX_EM,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 0. "TX_THD,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "STAT,SPI Status register."
|
|
bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode set when transaction starts cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode set when Slave Select is asserted cleared when Slave Select is.." "0: SPI not active.,1: SPI active."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "SPI2"
|
|
base ad:0x40048000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FIFO32,Register for reading and writing the FIFO."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2)++0x1
|
|
line.word 0x0 "FIFO16[$1],Register for reading and writing the FIFO."
|
|
hexmask.word 0x0 0.--15. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "FIFO8[$1],Register for reading and writing the FIFO."
|
|
hexmask.byte 0x0 0.--7. 1. "DATA,Read to pull from RX FIFO write to put into TX FIFO."
|
|
repeat.end
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CTRL0,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SS_ACTIVE,Slave Select when in Master mode selects which Slave devices are selected. More than one Slave device can be selected."
|
|
bitfld.long 0x0 8. "SS_CTRL,Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction." "0: SPI De-asserts Slave Select at the end of a..,1: SPI leaves Slave Select asserted at the end of a.."
|
|
newline
|
|
bitfld.long 0x0 5. "START,Start Transmit." "?,1: Master Initiates a transaction this bit is self.."
|
|
bitfld.long 0x0 4. "SS_IO,Slave Select 0 IO direction to support Multi-Master mode Slave Select 0 can be input in Master mode. This bit has no effect in slave mode." "0: Slave select 0 is output.,1: Slave Select 0 is input only valid if MMEN=1."
|
|
newline
|
|
bitfld.long 0x0 1. "MST_MODE,Master Mode Enable." "0: SPI is Slave mode.,1: SPI is Master mode."
|
|
bitfld.long 0x0 0. "EN,SPI Enable." "0: SPI is disabled.,1: SPI is enabled."
|
|
line.long 0x4 "CTRL1,Register for controlling SPI peripheral."
|
|
hexmask.long.word 0x4 16.--31. 1. "RX_NUM_CHAR,Nubmer of Characters to receive."
|
|
hexmask.long.word 0x4 0.--15. 1. "TX_NUM_CHAR,Nubmer of Characters to transmit."
|
|
line.long 0x8 "CTRL2,Register for controlling SPI peripheral."
|
|
hexmask.long.byte 0x8 16.--23. 1. "SS_POL,Slave Select Polarity each Slave Select can have unique polarity."
|
|
bitfld.long 0x8 15. "THREE_WIRE,Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire." "0: Use four wire mode (Mono only).,1: Use three wire mode."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "DATA_WIDTH,SPI Data width." "0: 1 data pin.,1: 2 data pins.,2: 4 data pins.,?"
|
|
hexmask.long.byte 0x8 8.--11. 1. "NUMBITS,Number of Bits per character."
|
|
newline
|
|
bitfld.long 0x8 4. "SCLK_FB_INV,SCLK_FB_INV." "0,1"
|
|
bitfld.long 0x8 1. "CLKPOL,Clock Polarity." "0: Normal Clock. Use when in SPI Mode 0 and Mode 1,1: Inverted Clock. Use when in SPI Mode 2 and Mode 3"
|
|
newline
|
|
bitfld.long 0x8 0. "CLKPHA,Clock Phase." "0: Data Sampled on clock rising edge. Use when in..,1: Data Sampled on clock falling edge. Use when in.."
|
|
line.long 0xC "SSTIME,Register for controlling SPI peripheral/Slave Select Timing."
|
|
hexmask.long.byte 0xC 16.--23. 1. "INACT,Slave Select Inactive delay."
|
|
hexmask.long.byte 0xC 8.--15. 1. "POST,Slave Select Post delay 2."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "PRE,Slave Select Pre delay 1."
|
|
line.long 0x10 "CLKCTRL,Register for controlling SPI clock rate."
|
|
hexmask.long.byte 0x10 16.--19. 1. "CLKDIV,System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."
|
|
hexmask.long.byte 0x10 8.--15. 1. "HI,High duty cycle control. In timer mode reload[15:8]."
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "LO,Low duty cycle control. In timer mode reload[7:0]."
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "DMA,Register for controlling DMA."
|
|
bitfld.long 0x0 31. "DMA_RX_EN,RX DMA Enable." "0: RX DMA requests are disabled any pending DMA..,1: RX DMA requests are enabled."
|
|
hexmask.long.byte 0x0 24.--29. 1. "RX_LVL,Count of entries in RX FIFO."
|
|
newline
|
|
bitfld.long 0x0 23. "RX_FLUSH,Clear RX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Receive FIFO clears any pending RX.."
|
|
bitfld.long 0x0 22. "RX_FIFO_EN,Receive FIFO enabled for SPI transactions." "0: Receive FIFO is not enabled.,1: Receive FIFO is enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "RX_THD_VAL,Receive FIFO level that will trigger a DMA request also level for threshold status. When RX FIFO has more than this many bytes the associated events and conditions are triggered."
|
|
bitfld.long 0x0 15. "DMA_TX_EN,TX DMA Enable." "0: TX DMA requests are disabled andy pending DMA..,1: TX DMA requests are enabled."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "TX_LVL,Count of entries in TX FIFO."
|
|
bitfld.long 0x0 7. "TX_FLUSH,Clear TX FIFO clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side." "?,1: Clear the Transmit FIFO clears any pending TX.."
|
|
newline
|
|
bitfld.long 0x0 6. "TX_FIFO_EN,Transmit FIFO enabled for SPI transactions." "0: Transmit FIFO is not enabled.,1: Transmit FIFO is enabled."
|
|
hexmask.long.byte 0x0 0.--4. 1. "TX_THD_VAL,Transmit FIFO level that will trigger a DMA request also level for threshold status. When TX FIFO has fewer than this many bytes the associated events and conditions are triggered."
|
|
line.long 0x4 "INTFL,Register for reading and clearing interrupt flags. All bits are write 1 to clear."
|
|
bitfld.long 0x4 15. "RX_UN,Receive FIFO Underrun set when the AMBA side attempts to read data from an empty receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 14. "RX_OV,Receive FIFO Overrun set when the SPI side attempts to write to a full receive FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 13. "TX_UN,Transmit FIFO Underrun set when the SPI side attempts to read data from an empty transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 12. "TX_OV,Transmit FIFO Overrun set when the AMBA side attempts to write data to a full transmit FIFO." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 11. "MST_DONE,Master Done set when SPI Master has completed any transactions." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 9. "ABORT,Slave Abort Detected." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 8. "FAULT,Multi-Master Mode Fault." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 5. "SSD,Slave Select Deasserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 4. "SSA,Slave Select Asserted." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 3. "RX_FULL,RX FIFO FULL." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 2. "RX_THD,RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0x4 1. "TX_EM,TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0x4 0. "TX_THD,TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x8 "INTEN,Register for enabling interrupts."
|
|
bitfld.long 0x8 15. "RX_UN,Receive FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 14. "RX_OV,Receive FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 13. "TX_UN,Transmit FIFO Underrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 12. "TX_OV,Transmit FIFO Overrun interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 11. "MST_DONE,Master Done interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 9. "ABORT,Slave Abort Detected interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 8. "FAULT,Multi-Master Mode Fault interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 5. "SSD,Slave Select Deasserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 4. "SSA,Slave Select Asserted interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 3. "RX_FULL,RX FIFO FULL interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 2. "RX_THD,RX FIFO Threshold Crossed interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
bitfld.long 0x8 1. "TX_EM,TX FIFO Empty interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
newline
|
|
bitfld.long 0x8 0. "TX_THD,TX FIFO Threshold interrupt enable." "0: Interrupt is disabled.,1: Interrupt is enabled."
|
|
line.long 0xC "WKFL,Register for wake up flags. All bits in this register are write 1 to clear."
|
|
bitfld.long 0xC 3. "RX_FULL,Wake on RX FIFO Full." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 2. "RX_THD,Wake on RX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
newline
|
|
bitfld.long 0xC 1. "TX_EM,Wake on TX FIFO Empty." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
bitfld.long 0xC 0. "TX_THD,Wake on TX FIFO Threshold Crossed." "?,1: Flag is set when value read is 1. Write 1 to.."
|
|
line.long 0x10 "WKEN,Register for wake up enable."
|
|
bitfld.long 0x10 3. "RX_FULL,Wake on RX FIFO Full Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 2. "RX_THD,Wake on RX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
newline
|
|
bitfld.long 0x10 1. "TX_EM,Wake on TX FIFO Empty Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
bitfld.long 0x10 0. "TX_THD,Wake on TX FIFO Threshold Crossed Enable." "0: Wakeup source disabled.,1: Wakeup source enabled."
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "STAT,SPI Status register."
|
|
bitfld.long 0x0 0. "BUSY,SPI active status. In Master mode set when transaction starts cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode set when Slave Select is asserted cleared when Slave Select is.." "0: SPI not active.,1: SPI active."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "TIMERS"
|
|
base ad:0x0
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32675*"))
|
|
tree "TMR0"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CNT,Timer Counter Register."
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
|
|
line.long 0x4 "CMP,Timer Compare Register."
|
|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
|
|
line.long 0x8 "PWM,Timer PWM Register."
|
|
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
|
|
line.long 0xC "INTFL,Timer Interrupt Status Register."
|
|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
|
|
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
|
|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
|
|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
|
|
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
|
|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
|
|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
|
|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
|
|
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
|
|
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
|
|
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
|
|
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
|
|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
|
|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32675*"))
|
|
tree "TMR1"
|
|
base ad:0x40011000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CNT,Timer Counter Register."
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
|
|
line.long 0x4 "CMP,Timer Compare Register."
|
|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
|
|
line.long 0x8 "PWM,Timer PWM Register."
|
|
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
|
|
line.long 0xC "INTFL,Timer Interrupt Status Register."
|
|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
|
|
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
|
|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
|
|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
|
|
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
|
|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
|
|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
|
|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
|
|
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
|
|
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
|
|
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
|
|
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
|
|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
|
|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32675*"))
|
|
tree "TMR2"
|
|
base ad:0x40012000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CNT,Timer Counter Register."
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
|
|
line.long 0x4 "CMP,Timer Compare Register."
|
|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
|
|
line.long 0x8 "PWM,Timer PWM Register."
|
|
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
|
|
line.long 0xC "INTFL,Timer Interrupt Status Register."
|
|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
|
|
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
|
|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
|
|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
|
|
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
|
|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
|
|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
|
|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
|
|
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
|
|
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
|
|
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
|
|
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
|
|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
|
|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32675*"))
|
|
tree "TMR3"
|
|
base ad:0x40013000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CNT,Timer Counter Register."
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
|
|
line.long 0x4 "CMP,Timer Compare Register."
|
|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
|
|
line.long 0x8 "PWM,Timer PWM Register."
|
|
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
|
|
line.long 0xC "INTFL,Timer Interrupt Status Register."
|
|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
|
|
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
|
|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
|
|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
|
|
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
|
|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
|
|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
|
|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
|
|
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
|
|
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
|
|
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
|
|
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
|
|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
|
|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32675*"))
|
|
tree "TMR4"
|
|
base ad:0x40114000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CNT,Timer Counter Register."
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
|
|
line.long 0x4 "CMP,Timer Compare Register."
|
|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
|
|
line.long 0x8 "PWM,Timer PWM Register."
|
|
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
|
|
line.long 0xC "INTFL,Timer Interrupt Status Register."
|
|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
|
|
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
|
|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
|
|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
|
|
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
|
|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
|
|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
|
|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
|
|
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
|
|
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
|
|
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
|
|
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
|
|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
|
|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32675*"))
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|
tree "TMR5"
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|
base ad:0x40115000
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group.long 0x0++0x1F
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line.long 0x0 "CNT,Timer Counter Register."
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|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
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|
line.long 0x4 "CMP,Timer Compare Register."
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|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
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|
line.long 0x8 "PWM,Timer PWM Register."
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hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
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|
line.long 0xC "INTFL,Timer Interrupt Status Register."
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|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
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bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
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bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
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bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
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|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
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|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
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bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
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|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
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|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
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|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
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|
newline
|
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bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
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|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
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hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
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bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
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bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
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bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
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|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
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|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "TMR0"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CNT,Timer Counter Register."
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
|
|
line.long 0x4 "CMP,Timer Compare Register."
|
|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
|
|
line.long 0x8 "PWM,Timer PWM Register."
|
|
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
|
|
line.long 0xC "INTFL,Timer Interrupt Status Register."
|
|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
|
|
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
|
|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
|
|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
|
|
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
|
|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
|
|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
|
|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
|
|
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
|
|
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
|
|
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
|
|
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
|
|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
|
|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "TMR1"
|
|
base ad:0x40011000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CNT,Timer Counter Register."
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
|
|
line.long 0x4 "CMP,Timer Compare Register."
|
|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
|
|
line.long 0x8 "PWM,Timer PWM Register."
|
|
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
|
|
line.long 0xC "INTFL,Timer Interrupt Status Register."
|
|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
|
|
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
|
|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
|
|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
|
|
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
|
|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
|
|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
|
|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
|
|
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
|
|
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
|
|
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
|
|
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
|
|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
|
|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "TMR2"
|
|
base ad:0x40012000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CNT,Timer Counter Register."
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
|
|
line.long 0x4 "CMP,Timer Compare Register."
|
|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
|
|
line.long 0x8 "PWM,Timer PWM Register."
|
|
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
|
|
line.long 0xC "INTFL,Timer Interrupt Status Register."
|
|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
|
|
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
|
|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
|
|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
|
|
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
|
|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
|
|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
|
|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
|
|
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
|
|
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
|
|
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
|
|
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
|
|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
|
|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "TMR3"
|
|
base ad:0x40013000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CNT,Timer Counter Register."
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
|
|
line.long 0x4 "CMP,Timer Compare Register."
|
|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
|
|
line.long 0x8 "PWM,Timer PWM Register."
|
|
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
|
|
line.long 0xC "INTFL,Timer Interrupt Status Register."
|
|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
|
|
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
|
|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
|
|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
|
|
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
|
|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
|
|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
|
|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
|
|
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
|
|
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
|
|
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
|
|
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
|
|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
|
|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "TMR4"
|
|
base ad:0x40114000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CNT,Timer Counter Register."
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
|
|
line.long 0x4 "CMP,Timer Compare Register."
|
|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
|
|
line.long 0x8 "PWM,Timer PWM Register."
|
|
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
|
|
line.long 0xC "INTFL,Timer Interrupt Status Register."
|
|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
|
|
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
|
|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
|
|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
|
|
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
|
|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
|
|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
|
|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
|
|
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
|
|
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
|
|
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
|
|
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
|
|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
|
|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MAX32672*"))
|
|
tree "TMR5"
|
|
base ad:0x40115000
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "CNT,Timer Counter Register."
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,The current count value for the timer. This field increments as the timer counts."
|
|
line.long 0x4 "CMP,Timer Compare Register."
|
|
hexmask.long 0x4 0.--31. 1. "COMPARE,The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer."
|
|
line.long 0x8 "PWM,Timer PWM Register."
|
|
hexmask.long 0x8 0.--31. 1. "PWM,Timer PWM Match:"
|
|
line.long 0xC "INTFL,Timer Interrupt Status Register."
|
|
bitfld.long 0xC 25. "WR_DIS_B,Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 24. "WRDONE_B,Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 16. "IRQ_B,Interrupt Flag for Timer B." "0,1"
|
|
bitfld.long 0xC 9. "WR_DIS_A,Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration." "0,1"
|
|
bitfld.long 0xC 8. "WRDONE_A,Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain." "0,1"
|
|
bitfld.long 0xC 0. "IRQ_A,Interrupt Flag for Timer A." "0,1"
|
|
line.long 0x10 "CTRL0,Timer Control Register."
|
|
bitfld.long 0x10 31. "EN_B,Enable for Timer B" "0,1"
|
|
bitfld.long 0x10 30. "CLKEN_B,Write 1 to Enable CLK_TMR for Timer B" "0,1"
|
|
bitfld.long 0x10 29. "RST_B,Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears." "0,1"
|
|
bitfld.long 0x10 28. "PWMCKBD_B,PWM Phase A-Prime Output Disable for Timer B" "0,1"
|
|
bitfld.long 0x10 27. "NOLLPOL_B,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 26. "NOLHPOL_B,PWM Phase A (Non-Overlapping High) Polarity for Timer B" "0,1"
|
|
bitfld.long 0x10 25. "PWMSYNC_B,PWM Synchronization Mode for Timer B" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "POL_B,Timer Polarity for Timer B" "0,1"
|
|
hexmask.long.byte 0x10 20.--23. 1. "CLKDIV_B,Clock Divider Select for Timer B"
|
|
hexmask.long.byte 0x10 16.--19. 1. "MODE_B,Mode Select for Timer B"
|
|
bitfld.long 0x10 15. "EN_A,Enable for Timer A" "0,1"
|
|
bitfld.long 0x10 14. "CLKEN_A,Write 1 to Enable CLK_TMR for Timer A" "0,1"
|
|
bitfld.long 0x10 13. "RST_A,Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears." "0,1"
|
|
bitfld.long 0x10 12. "PWMCKBD_A,PWM Phase A-Prime Output Disable for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "NOLLPOL_A,PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 10. "NOLHPOL_A,PWM Phase A (Non-Overlapping High) Polarity for Timer A" "0,1"
|
|
bitfld.long 0x10 9. "PWMSYNC_A,PWM Synchronization Mode for Timer A" "0,1"
|
|
bitfld.long 0x10 8. "POL_A,Timer Polarity for Timer A" "0,1"
|
|
hexmask.long.byte 0x10 4.--7. 1. "CLKDIV_A,Clock Divider Select for Timer A"
|
|
hexmask.long.byte 0x10 0.--3. 1. "MODE_A,Mode Select for Timer A"
|
|
line.long 0x14 "NOLCMP,Timer Non-Overlapping Compare Register."
|
|
hexmask.long.byte 0x14 24.--31. 1. "HI_B,Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 16.--23. 1. "LO_B,Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
hexmask.long.byte 0x14 8.--15. 1. "HI_A,Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A."
|
|
hexmask.long.byte 0x14 0.--7. 1. "LO_A,Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime."
|
|
line.long 0x18 "CTRL1,Timer Configuration Register."
|
|
bitfld.long 0x18 31. "CASCADE,Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1." "0,1"
|
|
bitfld.long 0x18 28. "WE_B,Wake-Up Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 27. "SW_CAPEVENT_B,Software Capture Event for Timer B" "0,1"
|
|
bitfld.long 0x18 25.--26. "CAPEVENT_SEL_B,Capture Event Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 24. "IE_B,Interrupt Enable for Timer B" "0,1"
|
|
bitfld.long 0x18 23. "NEGTRIG_B,Negative Edge Trigger for Event for Timer B" "0,1"
|
|
bitfld.long 0x18 20.--22. "EVENT_SEL_B,Event Select for Timer B" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x18 19. "CLKRDY_B,CLK_TMR Ready Flag for Timer B" "0,1"
|
|
bitfld.long 0x18 18. "CLKEN_B,Timer B Enable Status" "0,1"
|
|
bitfld.long 0x18 16.--17. "CLKSEL_B,Timer Clock Select for Timer B" "0,1,2,3"
|
|
bitfld.long 0x18 14. "OUTBEN_A,PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A" "0,1"
|
|
bitfld.long 0x18 13. "OUTEN_A,OUT_OE_O Enable for Modes 0 1 and 5 for Timer A" "0,1"
|
|
bitfld.long 0x18 12. "WE_A,Wake-Up Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 11. "SW_CAPEVENT_A,Software Capture Event for Timer A" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9.--10. "CAPEVENT_SEL_A,Capture Event Select for Timer A" "0,1,2,3"
|
|
bitfld.long 0x18 8. "IE_A,Interrupt Enable for Timer A" "0,1"
|
|
bitfld.long 0x18 7. "NEGTRIG_A,Negative Edge Trigger for Event for Timer A" "0,1"
|
|
bitfld.long 0x18 4.--6. "EVENT_SEL_A,Event Select for Timer A" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3. "CLKRDY_A,CLK_TMR Ready Flag for Timer A" "0,1"
|
|
bitfld.long 0x18 2. "CLKEN_A,Timer A Enable Status" "0,1"
|
|
bitfld.long 0x18 0.--1. "CLKSEL_A,Timer Clock Select for Timer A" "0,1,2,3"
|
|
line.long 0x1C "WKFL,Timer Wakeup Status Register."
|
|
bitfld.long 0x1C 16. "B,Wake-Up Flag for Timer B" "0,1"
|
|
bitfld.long 0x1C 0. "A,Wake-Up Flag for Timer A" "0,1"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MAX32672*"))
|
|
tree "TRIMSIR (Trim System Initilazation Registers)"
|
|
base ad:0x40105400
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "BB_SIR2,System Init. Configuration Register 2."
|
|
hexmask.long.word 0x0 16.--31. 1. "TRIM_IBRO,HIRC8M Trim"
|
|
bitfld.long 0x0 13. "FL1ECCEN,Flash 1 ECC Enable" "0: ECC Disabled.,1: ECC Enabled."
|
|
bitfld.long 0x0 12. "FL0ECCEN,Flash 0 ECC Enable" "0: ECC Disabled.,1: ECC Enabled."
|
|
bitfld.long 0x0 11. "ICC0ECCEN,ICC 0 ECC Enable" "0: ECC Disabled.,1: ECC Enabled."
|
|
bitfld.long 0x0 10. "RAM3ECCEN,RAM 3 ECC Enable" "0: ECC Disabled.,1: ECC Enabled."
|
|
newline
|
|
bitfld.long 0x0 9. "RAM2ECCEN,RAM 2 ECC Enable" "0: ECC Disabled.,1: ECC Enabled."
|
|
bitfld.long 0x0 8. "RAM0_1ECCEN,RAM 0 and RAM 1 ECC Enable" "0: ECC Disabled.,1: ECC Enabled."
|
|
hexmask.long.byte 0x0 0.--5. 1. "TRIM_IBRO_RBIAS,HIRC8M Trim"
|
|
line.long 0x4 "BB_SIR3,System Init. Configuration Register 3."
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "BB_SIR6,System Init. Configuration Register 6."
|
|
hexmask.long.byte 0x0 9.--13. 1. "RTCX2TRIM,RTCX2 Trim"
|
|
hexmask.long.byte 0x0 4.--8. 1. "RTCX1TRIM,RTCX1 Trim"
|
|
tree.end
|
|
endif
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x4004D000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTRL,TRNG Control Register."
|
|
bitfld.long 0x0 15. "KEYWIPE,To wipe the Battery Backed key." "0,1"
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32672*"))
|
|
bitfld.long 0x0 4. "AESKG_SYS,AESKG_SYS." "0,1"
|
|
bitfld.long 0x0 3. "AESKG_USR,AES Key Generate. When enabled the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the.." "0,1"
|
|
bitfld.long 0x0 2. "HEALTH_EN,Enable IRQ generation when a health test fails." "0,1"
|
|
bitfld.long 0x0 0. "ODHT,Start On-Demand health test." "0,1"
|
|
endif
|
|
sif (cpuis("MAX32675*"))
|
|
bitfld.long 0x0 3. "KEYGEN,AES Key Generate. When enabled the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the.." "0,1"
|
|
endif
|
|
bitfld.long 0x0 1. "RND_IE,To enable IRQ generation when a new 32-bit Random number is ready." "0: Disable,1: Enable"
|
|
line.long 0x4 "STATUS,Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled. read returns 0x0000 0000."
|
|
sif (cpuis("MAX32670*")||cpuis("MAX32671*")||cpuis("MAX32672*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. "LD_CNT,LD_CNT."
|
|
bitfld.long 0x4 4. "AESKGD,AESKGD." "0,1"
|
|
bitfld.long 0x4 3. "SRCFAIL,Entropy source has failed." "0,1"
|
|
bitfld.long 0x4 2. "HT,Health test status." "0,1"
|
|
bitfld.long 0x4 1. "ODHT,On-Demand health test status." "0,1"
|
|
endif
|
|
bitfld.long 0x4 0. "RDY,32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1." "0: TRNG Busy,1: 32 bit random data is ready"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "DATA,Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled. read returns 0x0000 0000."
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled read returns 0x0000 0000."
|
|
tree.end
|
|
tree "UART (Universal Asynchronous Receiver Transmitter)"
|
|
base ad:0x0
|
|
tree "UART0"
|
|
base ad:0x40042000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Control register"
|
|
bitfld.long 0x0 22. "DESM,RX Dual Edge Sampling Mode" "0,1"
|
|
bitfld.long 0x0 21. "FDM,Fractional Division Mode" "0,1"
|
|
bitfld.long 0x0 20. "UCAGM,UART Clock Auto Gating mode" "0,1"
|
|
bitfld.long 0x0 19. "BCLKRDY,Baud clock Ready read only bit" "0,1"
|
|
bitfld.long 0x0 18. "DPFE_EN,Data/Parity bit frame error detection enable" "0,1"
|
|
bitfld.long 0x0 16.--17. "BCLKSRC,To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock." "0: apb clock,1: Clock 1,2: Clock 2,3: Clock 3"
|
|
bitfld.long 0x0 15. "BCLKEN,Baud clock enable" "0,1"
|
|
bitfld.long 0x0 14. "RTSDC,Hardware Flow Control RTS Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "HFC_EN,Enables/disables hardware flow control" "0,1"
|
|
bitfld.long 0x0 12. "STOPBITS,Selects the number of stop bits that will be generated" "0,1"
|
|
bitfld.long 0x0 10.--11. "CHAR_SIZE,Selects UART character size" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
|
|
bitfld.long 0x0 9. "RX_FLUSH,Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
|
|
bitfld.long 0x0 8. "TX_FLUSH,Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
|
|
bitfld.long 0x0 7. "CTS_DIS,CTS Sampling Disable" "0,1"
|
|
bitfld.long 0x0 6. "PAR_MD,Selects parity based on 1s or 0s count (when PAREN=1)" "0,1"
|
|
bitfld.long 0x0 5. "PAR_EO,when PAREN=1 selects odd or even parity odd is 1 even is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PAR_EN,Parity Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RX_THD_VAL,This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "TX_LVL,Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS)"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RX_LVL,Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS)"
|
|
bitfld.long 0x0 7. "TX_FULL,Read-only flag indicating the TX FIFO state" "0,1"
|
|
bitfld.long 0x0 6. "TX_EM,Read-only flag indicating the TX FIFO state" "0,1"
|
|
bitfld.long 0x0 5. "RX_FULL,Read-only flag indicating the RX FIFO state" "0,1"
|
|
bitfld.long 0x0 4. "RX_EM,Read-only flag indicating the RX FIFO state" "0,1"
|
|
bitfld.long 0x0 1. "RX_BUSY,Read-only flag indicating the UART receiver status" "0,1"
|
|
bitfld.long 0x0 0. "TX_BUSY,Read-only flag indicating the UART transmit status" "0,1"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "INT_EN,Interrupt Enable control register"
|
|
bitfld.long 0x0 6. "TX_HE,Enable Interrupt For TX FIFO has half empty" "0,1"
|
|
bitfld.long 0x0 4. "RX_THD,Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD" "0,1"
|
|
bitfld.long 0x0 3. "RX_OV,Enable Interrupt For RX FIFO Overrun Error" "0,1"
|
|
bitfld.long 0x0 2. "CTS_EV,Enable Interrupt For CTS signal change Error" "0,1"
|
|
bitfld.long 0x0 1. "RX_PAR,Enable Interrupt For RX Parity Error" "0,1"
|
|
bitfld.long 0x0 0. "RX_FERR,Enable Interrupt For RX Frame Error" "0,1"
|
|
line.long 0x4 "INT_FL,Interrupt status flags Control register"
|
|
bitfld.long 0x4 6. "TX_HE,Flag for interrupt when TX FIFO is half empty" "0,1"
|
|
bitfld.long 0x4 4. "RX_THD,Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field" "0,1"
|
|
bitfld.long 0x4 3. "RX_OV,Flag for RX FIFO Overrun interrupt" "0,1"
|
|
bitfld.long 0x4 2. "CTS_EV,Flag for CTS signal change interrupt (hardware flow control disabled)" "0,1"
|
|
bitfld.long 0x4 1. "RX_PAR,Flag for RX Parity Error interrupt" "0,1"
|
|
bitfld.long 0x4 0. "RX_FERR,Flag for RX Frame Error Interrupt." "0,1"
|
|
line.long 0x8 "CLKDIV,Clock Divider register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "CLKDIV,Baud rate divisor value"
|
|
line.long 0xC "OSR,Over Sampling Rate register"
|
|
bitfld.long 0xC 0.--2. "OSR,OSR" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "TXPEEK,TX FIFO Output Peek register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA,Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field."
|
|
line.long 0x14 "PNR,Pin register"
|
|
bitfld.long 0x14 1. "RTS,This bit controls the value to apply on the RTS IO. If set to 1 the RTS IO is set to high level. If set to 0 the RTS IO is set to low level." "0,1"
|
|
rbitfld.long 0x14 0. "CTS,Current sampled value of CTS IO" "0,1"
|
|
line.long 0x18 "FIFO,FIFO Read/Write register"
|
|
bitfld.long 0x18 8. "RX_PAR,Parity error flag for next byte to be read from FIFO." "0,1"
|
|
hexmask.long.byte 0x18 0.--7. 1. "DATA,Load/unload location for TX and RX FIFO buffers."
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "DMA,DMA Configuration register"
|
|
bitfld.long 0x0 9. "RX_EN,RX DMA channel enable" "0,1"
|
|
hexmask.long.byte 0x0 5.--8. 1. "RX_THD_VAL,Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory."
|
|
bitfld.long 0x0 4. "TX_EN,TX DMA channel enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TX_THD_VAL,TX FIFO Level DMA Trigger If the TX FIFO level is less than this value then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory."
|
|
line.long 0x4 "WKEN,Wake up enable Control register"
|
|
bitfld.long 0x4 2. "RX_THD,Wake-Up Enable for RX FIFO Threshold Met" "0,1"
|
|
bitfld.long 0x4 1. "RX_FULL,Wake-Up Enable for RX FIFO Full" "0,1"
|
|
bitfld.long 0x4 0. "RX_NE,Wake-Up Enable for RX FIFO Not Empty" "0,1"
|
|
line.long 0x8 "WKFL,Wake up Flags register"
|
|
bitfld.long 0x8 2. "RX_THD,Wake-Up Flag for RX FIFO Threshold Met" "0,1"
|
|
bitfld.long 0x8 1. "RX_FULL,Wake-Up Flag for RX FIFO Full" "0,1"
|
|
bitfld.long 0x8 0. "RX_NE,Wake-Up Flag for RX FIFO Not Empty" "0,1"
|
|
tree.end
|
|
tree "UART1"
|
|
base ad:0x40043000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Control register"
|
|
bitfld.long 0x0 22. "DESM,RX Dual Edge Sampling Mode" "0,1"
|
|
bitfld.long 0x0 21. "FDM,Fractional Division Mode" "0,1"
|
|
bitfld.long 0x0 20. "UCAGM,UART Clock Auto Gating mode" "0,1"
|
|
bitfld.long 0x0 19. "BCLKRDY,Baud clock Ready read only bit" "0,1"
|
|
bitfld.long 0x0 18. "DPFE_EN,Data/Parity bit frame error detection enable" "0,1"
|
|
bitfld.long 0x0 16.--17. "BCLKSRC,To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock." "0: apb clock,1: Clock 1,2: Clock 2,3: Clock 3"
|
|
bitfld.long 0x0 15. "BCLKEN,Baud clock enable" "0,1"
|
|
bitfld.long 0x0 14. "RTSDC,Hardware Flow Control RTS Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "HFC_EN,Enables/disables hardware flow control" "0,1"
|
|
bitfld.long 0x0 12. "STOPBITS,Selects the number of stop bits that will be generated" "0,1"
|
|
bitfld.long 0x0 10.--11. "CHAR_SIZE,Selects UART character size" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
|
|
bitfld.long 0x0 9. "RX_FLUSH,Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
|
|
bitfld.long 0x0 8. "TX_FLUSH,Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
|
|
bitfld.long 0x0 7. "CTS_DIS,CTS Sampling Disable" "0,1"
|
|
bitfld.long 0x0 6. "PAR_MD,Selects parity based on 1s or 0s count (when PAREN=1)" "0,1"
|
|
bitfld.long 0x0 5. "PAR_EO,when PAREN=1 selects odd or even parity odd is 1 even is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PAR_EN,Parity Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RX_THD_VAL,This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "TX_LVL,Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS)"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RX_LVL,Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS)"
|
|
bitfld.long 0x0 7. "TX_FULL,Read-only flag indicating the TX FIFO state" "0,1"
|
|
bitfld.long 0x0 6. "TX_EM,Read-only flag indicating the TX FIFO state" "0,1"
|
|
bitfld.long 0x0 5. "RX_FULL,Read-only flag indicating the RX FIFO state" "0,1"
|
|
bitfld.long 0x0 4. "RX_EM,Read-only flag indicating the RX FIFO state" "0,1"
|
|
bitfld.long 0x0 1. "RX_BUSY,Read-only flag indicating the UART receiver status" "0,1"
|
|
bitfld.long 0x0 0. "TX_BUSY,Read-only flag indicating the UART transmit status" "0,1"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "INT_EN,Interrupt Enable control register"
|
|
bitfld.long 0x0 6. "TX_HE,Enable Interrupt For TX FIFO has half empty" "0,1"
|
|
bitfld.long 0x0 4. "RX_THD,Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD" "0,1"
|
|
bitfld.long 0x0 3. "RX_OV,Enable Interrupt For RX FIFO Overrun Error" "0,1"
|
|
bitfld.long 0x0 2. "CTS_EV,Enable Interrupt For CTS signal change Error" "0,1"
|
|
bitfld.long 0x0 1. "RX_PAR,Enable Interrupt For RX Parity Error" "0,1"
|
|
bitfld.long 0x0 0. "RX_FERR,Enable Interrupt For RX Frame Error" "0,1"
|
|
line.long 0x4 "INT_FL,Interrupt status flags Control register"
|
|
bitfld.long 0x4 6. "TX_HE,Flag for interrupt when TX FIFO is half empty" "0,1"
|
|
bitfld.long 0x4 4. "RX_THD,Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field" "0,1"
|
|
bitfld.long 0x4 3. "RX_OV,Flag for RX FIFO Overrun interrupt" "0,1"
|
|
bitfld.long 0x4 2. "CTS_EV,Flag for CTS signal change interrupt (hardware flow control disabled)" "0,1"
|
|
bitfld.long 0x4 1. "RX_PAR,Flag for RX Parity Error interrupt" "0,1"
|
|
bitfld.long 0x4 0. "RX_FERR,Flag for RX Frame Error Interrupt." "0,1"
|
|
line.long 0x8 "CLKDIV,Clock Divider register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "CLKDIV,Baud rate divisor value"
|
|
line.long 0xC "OSR,Over Sampling Rate register"
|
|
bitfld.long 0xC 0.--2. "OSR,OSR" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "TXPEEK,TX FIFO Output Peek register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA,Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field."
|
|
line.long 0x14 "PNR,Pin register"
|
|
bitfld.long 0x14 1. "RTS,This bit controls the value to apply on the RTS IO. If set to 1 the RTS IO is set to high level. If set to 0 the RTS IO is set to low level." "0,1"
|
|
rbitfld.long 0x14 0. "CTS,Current sampled value of CTS IO" "0,1"
|
|
line.long 0x18 "FIFO,FIFO Read/Write register"
|
|
bitfld.long 0x18 8. "RX_PAR,Parity error flag for next byte to be read from FIFO." "0,1"
|
|
hexmask.long.byte 0x18 0.--7. 1. "DATA,Load/unload location for TX and RX FIFO buffers."
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "DMA,DMA Configuration register"
|
|
bitfld.long 0x0 9. "RX_EN,RX DMA channel enable" "0,1"
|
|
hexmask.long.byte 0x0 5.--8. 1. "RX_THD_VAL,Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory."
|
|
bitfld.long 0x0 4. "TX_EN,TX DMA channel enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TX_THD_VAL,TX FIFO Level DMA Trigger If the TX FIFO level is less than this value then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory."
|
|
line.long 0x4 "WKEN,Wake up enable Control register"
|
|
bitfld.long 0x4 2. "RX_THD,Wake-Up Enable for RX FIFO Threshold Met" "0,1"
|
|
bitfld.long 0x4 1. "RX_FULL,Wake-Up Enable for RX FIFO Full" "0,1"
|
|
bitfld.long 0x4 0. "RX_NE,Wake-Up Enable for RX FIFO Not Empty" "0,1"
|
|
line.long 0x8 "WKFL,Wake up Flags register"
|
|
bitfld.long 0x8 2. "RX_THD,Wake-Up Flag for RX FIFO Threshold Met" "0,1"
|
|
bitfld.long 0x8 1. "RX_FULL,Wake-Up Flag for RX FIFO Full" "0,1"
|
|
bitfld.long 0x8 0. "RX_NE,Wake-Up Flag for RX FIFO Not Empty" "0,1"
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0x40044000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Control register"
|
|
bitfld.long 0x0 22. "DESM,RX Dual Edge Sampling Mode" "0,1"
|
|
bitfld.long 0x0 21. "FDM,Fractional Division Mode" "0,1"
|
|
bitfld.long 0x0 20. "UCAGM,UART Clock Auto Gating mode" "0,1"
|
|
bitfld.long 0x0 19. "BCLKRDY,Baud clock Ready read only bit" "0,1"
|
|
bitfld.long 0x0 18. "DPFE_EN,Data/Parity bit frame error detection enable" "0,1"
|
|
bitfld.long 0x0 16.--17. "BCLKSRC,To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock." "0: apb clock,1: Clock 1,2: Clock 2,3: Clock 3"
|
|
bitfld.long 0x0 15. "BCLKEN,Baud clock enable" "0,1"
|
|
bitfld.long 0x0 14. "RTSDC,Hardware Flow Control RTS Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "HFC_EN,Enables/disables hardware flow control" "0,1"
|
|
bitfld.long 0x0 12. "STOPBITS,Selects the number of stop bits that will be generated" "0,1"
|
|
bitfld.long 0x0 10.--11. "CHAR_SIZE,Selects UART character size" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
|
|
bitfld.long 0x0 9. "RX_FLUSH,Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
|
|
bitfld.long 0x0 8. "TX_FLUSH,Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
|
|
bitfld.long 0x0 7. "CTS_DIS,CTS Sampling Disable" "0,1"
|
|
bitfld.long 0x0 6. "PAR_MD,Selects parity based on 1s or 0s count (when PAREN=1)" "0,1"
|
|
bitfld.long 0x0 5. "PAR_EO,when PAREN=1 selects odd or even parity odd is 1 even is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PAR_EN,Parity Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RX_THD_VAL,This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "TX_LVL,Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS)"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RX_LVL,Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS)"
|
|
bitfld.long 0x0 7. "TX_FULL,Read-only flag indicating the TX FIFO state" "0,1"
|
|
bitfld.long 0x0 6. "TX_EM,Read-only flag indicating the TX FIFO state" "0,1"
|
|
bitfld.long 0x0 5. "RX_FULL,Read-only flag indicating the RX FIFO state" "0,1"
|
|
bitfld.long 0x0 4. "RX_EM,Read-only flag indicating the RX FIFO state" "0,1"
|
|
bitfld.long 0x0 1. "RX_BUSY,Read-only flag indicating the UART receiver status" "0,1"
|
|
bitfld.long 0x0 0. "TX_BUSY,Read-only flag indicating the UART transmit status" "0,1"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "INT_EN,Interrupt Enable control register"
|
|
bitfld.long 0x0 6. "TX_HE,Enable Interrupt For TX FIFO has half empty" "0,1"
|
|
bitfld.long 0x0 4. "RX_THD,Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD" "0,1"
|
|
bitfld.long 0x0 3. "RX_OV,Enable Interrupt For RX FIFO Overrun Error" "0,1"
|
|
bitfld.long 0x0 2. "CTS_EV,Enable Interrupt For CTS signal change Error" "0,1"
|
|
bitfld.long 0x0 1. "RX_PAR,Enable Interrupt For RX Parity Error" "0,1"
|
|
bitfld.long 0x0 0. "RX_FERR,Enable Interrupt For RX Frame Error" "0,1"
|
|
line.long 0x4 "INT_FL,Interrupt status flags Control register"
|
|
bitfld.long 0x4 6. "TX_HE,Flag for interrupt when TX FIFO is half empty" "0,1"
|
|
bitfld.long 0x4 4. "RX_THD,Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field" "0,1"
|
|
bitfld.long 0x4 3. "RX_OV,Flag for RX FIFO Overrun interrupt" "0,1"
|
|
bitfld.long 0x4 2. "CTS_EV,Flag for CTS signal change interrupt (hardware flow control disabled)" "0,1"
|
|
bitfld.long 0x4 1. "RX_PAR,Flag for RX Parity Error interrupt" "0,1"
|
|
bitfld.long 0x4 0. "RX_FERR,Flag for RX Frame Error Interrupt." "0,1"
|
|
line.long 0x8 "CLKDIV,Clock Divider register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "CLKDIV,Baud rate divisor value"
|
|
line.long 0xC "OSR,Over Sampling Rate register"
|
|
bitfld.long 0xC 0.--2. "OSR,OSR" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "TXPEEK,TX FIFO Output Peek register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA,Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field."
|
|
line.long 0x14 "PNR,Pin register"
|
|
bitfld.long 0x14 1. "RTS,This bit controls the value to apply on the RTS IO. If set to 1 the RTS IO is set to high level. If set to 0 the RTS IO is set to low level." "0,1"
|
|
rbitfld.long 0x14 0. "CTS,Current sampled value of CTS IO" "0,1"
|
|
line.long 0x18 "FIFO,FIFO Read/Write register"
|
|
bitfld.long 0x18 8. "RX_PAR,Parity error flag for next byte to be read from FIFO." "0,1"
|
|
hexmask.long.byte 0x18 0.--7. 1. "DATA,Load/unload location for TX and RX FIFO buffers."
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "DMA,DMA Configuration register"
|
|
bitfld.long 0x0 9. "RX_EN,RX DMA channel enable" "0,1"
|
|
hexmask.long.byte 0x0 5.--8. 1. "RX_THD_VAL,Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory."
|
|
bitfld.long 0x0 4. "TX_EN,TX DMA channel enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TX_THD_VAL,TX FIFO Level DMA Trigger If the TX FIFO level is less than this value then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory."
|
|
line.long 0x4 "WKEN,Wake up enable Control register"
|
|
bitfld.long 0x4 2. "RX_THD,Wake-Up Enable for RX FIFO Threshold Met" "0,1"
|
|
bitfld.long 0x4 1. "RX_FULL,Wake-Up Enable for RX FIFO Full" "0,1"
|
|
bitfld.long 0x4 0. "RX_NE,Wake-Up Enable for RX FIFO Not Empty" "0,1"
|
|
line.long 0x8 "WKFL,Wake up Flags register"
|
|
bitfld.long 0x8 2. "RX_THD,Wake-Up Flag for RX FIFO Threshold Met" "0,1"
|
|
bitfld.long 0x8 1. "RX_FULL,Wake-Up Flag for RX FIFO Full" "0,1"
|
|
bitfld.long 0x8 0. "RX_NE,Wake-Up Flag for RX FIFO Not Empty" "0,1"
|
|
tree.end
|
|
tree "UART3"
|
|
base ad:0x40145000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Control register"
|
|
bitfld.long 0x0 22. "DESM,RX Dual Edge Sampling Mode" "0,1"
|
|
bitfld.long 0x0 21. "FDM,Fractional Division Mode" "0,1"
|
|
bitfld.long 0x0 20. "UCAGM,UART Clock Auto Gating mode" "0,1"
|
|
bitfld.long 0x0 19. "BCLKRDY,Baud clock Ready read only bit" "0,1"
|
|
bitfld.long 0x0 18. "DPFE_EN,Data/Parity bit frame error detection enable" "0,1"
|
|
bitfld.long 0x0 16.--17. "BCLKSRC,To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock." "0: apb clock,1: Clock 1,2: Clock 2,3: Clock 3"
|
|
bitfld.long 0x0 15. "BCLKEN,Baud clock enable" "0,1"
|
|
bitfld.long 0x0 14. "RTSDC,Hardware Flow Control RTS Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "HFC_EN,Enables/disables hardware flow control" "0,1"
|
|
bitfld.long 0x0 12. "STOPBITS,Selects the number of stop bits that will be generated" "0,1"
|
|
bitfld.long 0x0 10.--11. "CHAR_SIZE,Selects UART character size" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
|
|
bitfld.long 0x0 9. "RX_FLUSH,Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
|
|
bitfld.long 0x0 8. "TX_FLUSH,Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed." "0,1"
|
|
bitfld.long 0x0 7. "CTS_DIS,CTS Sampling Disable" "0,1"
|
|
bitfld.long 0x0 6. "PAR_MD,Selects parity based on 1s or 0s count (when PAREN=1)" "0,1"
|
|
bitfld.long 0x0 5. "PAR_EO,when PAREN=1 selects odd or even parity odd is 1 even is 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PAR_EN,Parity Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RX_THD_VAL,This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUS,Status register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "TX_LVL,Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS)"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RX_LVL,Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS)"
|
|
bitfld.long 0x0 7. "TX_FULL,Read-only flag indicating the TX FIFO state" "0,1"
|
|
bitfld.long 0x0 6. "TX_EM,Read-only flag indicating the TX FIFO state" "0,1"
|
|
bitfld.long 0x0 5. "RX_FULL,Read-only flag indicating the RX FIFO state" "0,1"
|
|
bitfld.long 0x0 4. "RX_EM,Read-only flag indicating the RX FIFO state" "0,1"
|
|
bitfld.long 0x0 1. "RX_BUSY,Read-only flag indicating the UART receiver status" "0,1"
|
|
bitfld.long 0x0 0. "TX_BUSY,Read-only flag indicating the UART transmit status" "0,1"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "INT_EN,Interrupt Enable control register"
|
|
bitfld.long 0x0 6. "TX_HE,Enable Interrupt For TX FIFO has half empty" "0,1"
|
|
bitfld.long 0x0 4. "RX_THD,Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD" "0,1"
|
|
bitfld.long 0x0 3. "RX_OV,Enable Interrupt For RX FIFO Overrun Error" "0,1"
|
|
bitfld.long 0x0 2. "CTS_EV,Enable Interrupt For CTS signal change Error" "0,1"
|
|
bitfld.long 0x0 1. "RX_PAR,Enable Interrupt For RX Parity Error" "0,1"
|
|
bitfld.long 0x0 0. "RX_FERR,Enable Interrupt For RX Frame Error" "0,1"
|
|
line.long 0x4 "INT_FL,Interrupt status flags Control register"
|
|
bitfld.long 0x4 6. "TX_HE,Flag for interrupt when TX FIFO is half empty" "0,1"
|
|
bitfld.long 0x4 4. "RX_THD,Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field" "0,1"
|
|
bitfld.long 0x4 3. "RX_OV,Flag for RX FIFO Overrun interrupt" "0,1"
|
|
bitfld.long 0x4 2. "CTS_EV,Flag for CTS signal change interrupt (hardware flow control disabled)" "0,1"
|
|
bitfld.long 0x4 1. "RX_PAR,Flag for RX Parity Error interrupt" "0,1"
|
|
bitfld.long 0x4 0. "RX_FERR,Flag for RX Frame Error Interrupt." "0,1"
|
|
line.long 0x8 "CLKDIV,Clock Divider register"
|
|
hexmask.long.tbyte 0x8 0.--19. 1. "CLKDIV,Baud rate divisor value"
|
|
line.long 0xC "OSR,Over Sampling Rate register"
|
|
bitfld.long 0xC 0.--2. "OSR,OSR" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "TXPEEK,TX FIFO Output Peek register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "DATA,Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field."
|
|
line.long 0x14 "PNR,Pin register"
|
|
bitfld.long 0x14 1. "RTS,This bit controls the value to apply on the RTS IO. If set to 1 the RTS IO is set to high level. If set to 0 the RTS IO is set to low level." "0,1"
|
|
rbitfld.long 0x14 0. "CTS,Current sampled value of CTS IO" "0,1"
|
|
line.long 0x18 "FIFO,FIFO Read/Write register"
|
|
bitfld.long 0x18 8. "RX_PAR,Parity error flag for next byte to be read from FIFO." "0,1"
|
|
hexmask.long.byte 0x18 0.--7. 1. "DATA,Load/unload location for TX and RX FIFO buffers."
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "DMA,DMA Configuration register"
|
|
bitfld.long 0x0 9. "RX_EN,RX DMA channel enable" "0,1"
|
|
hexmask.long.byte 0x0 5.--8. 1. "RX_THD_VAL,Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory."
|
|
bitfld.long 0x0 4. "TX_EN,TX DMA channel enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TX_THD_VAL,TX FIFO Level DMA Trigger If the TX FIFO level is less than this value then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory."
|
|
line.long 0x4 "WKEN,Wake up enable Control register"
|
|
bitfld.long 0x4 2. "RX_THD,Wake-Up Enable for RX FIFO Threshold Met" "0,1"
|
|
bitfld.long 0x4 1. "RX_FULL,Wake-Up Enable for RX FIFO Full" "0,1"
|
|
bitfld.long 0x4 0. "RX_NE,Wake-Up Enable for RX FIFO Not Empty" "0,1"
|
|
line.long 0x8 "WKFL,Wake up Flags register"
|
|
bitfld.long 0x8 2. "RX_THD,Wake-Up Flag for RX FIFO Threshold Met" "0,1"
|
|
bitfld.long 0x8 1. "RX_FULL,Wake-Up Flag for RX FIFO Full" "0,1"
|
|
bitfld.long 0x8 0. "RX_NE,Wake-Up Flag for RX FIFO Not Empty" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x0
|
|
tree "WDT0"
|
|
base ad:0x40003000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Watchdog Timer Control Register."
|
|
bitfld.long 0x0 31. "RST_LATE,Windowed Watchdog Timer Reset Flag Too Late." "0: The event has not occurred.,1: The event has occurred."
|
|
bitfld.long 0x0 30. "RST_EARLY,Windowed Watchdog Timer Reset Flag Too Soon." "0: The event has not occurred.,1: The event has occurred."
|
|
newline
|
|
bitfld.long 0x0 29. "WIN_EN,Enables the Windowed Watchdog Function." "0: Windowed Mode Disabled (i.e. Compatibility Mode).,1: Windowed Mode Enabled."
|
|
bitfld.long 0x0 28. "CLKRDY,Clock Status." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CLKRDY_IE,Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock." "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "RST_EARLY_VAL,Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST.."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "INT_EARLY_VAL,Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog.."
|
|
bitfld.long 0x0 12. "INT_EARLY,Windowed Watchdog Timer Interrupt Flag Too Soon." "0: No interrupt is pending.,1: An interrupt is pending."
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newline
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bitfld.long 0x0 11. "WDT_RST_EN,Windowed Watchdog Timer Reset Enable." "0: Disable.,1: Enable."
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bitfld.long 0x0 10. "WDT_INT_EN,Windowed Watchdog Timer Interrupt Enable." "0: Disable.,1: Enable."
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newline
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bitfld.long 0x0 9. "INT_LATE,Windowed Watchdog Timer Interrupt Flag Too Late." "0: No interrupt is pending.,1: An interrupt is pending."
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bitfld.long 0x0 8. "EN,Windowed Watchdog Timer Enable." "0: Disable.,1: Enable."
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newline
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hexmask.long.byte 0x0 4.--7. 1. "RST_LATE_VAL,Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time.."
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hexmask.long.byte 0x0 0.--3. 1. "INT_LATE_VAL,Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the.."
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wgroup.long 0x4++0x3
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line.long 0x0 "RST,Windowed Watchdog Timer Reset Register."
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hexmask.long.byte 0x0 0.--7. 1. "RESET,Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT.."
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group.long 0x8++0x3
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line.long 0x0 "CLKSEL,Windowed Watchdog Timer Clock Select Register."
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bitfld.long 0x0 0.--2. "SOURCE,WWDT Clock Selection Register." "0,1,2,3,4,5,6,7"
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rgroup.long 0xC++0x3
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line.long 0x0 "CNT,Windowed Watchdog Timer Count Register."
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hexmask.long 0x0 0.--31. 1. "COUNT,Current Value of the Windowed Watchdog Timer Counter."
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tree.end
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tree "WDT1"
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base ad:0x40003400
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group.long 0x0++0x3
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line.long 0x0 "CTRL,Watchdog Timer Control Register."
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bitfld.long 0x0 31. "RST_LATE,Windowed Watchdog Timer Reset Flag Too Late." "0: The event has not occurred.,1: The event has occurred."
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bitfld.long 0x0 30. "RST_EARLY,Windowed Watchdog Timer Reset Flag Too Soon." "0: The event has not occurred.,1: The event has occurred."
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newline
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bitfld.long 0x0 29. "WIN_EN,Enables the Windowed Watchdog Function." "0: Windowed Mode Disabled (i.e. Compatibility Mode).,1: Windowed Mode Enabled."
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bitfld.long 0x0 28. "CLKRDY,Clock Status." "0,1"
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newline
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bitfld.long 0x0 27. "CLKRDY_IE,Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock." "0,1"
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hexmask.long.byte 0x0 20.--23. 1. "RST_EARLY_VAL,Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST.."
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newline
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hexmask.long.byte 0x0 16.--19. 1. "INT_EARLY_VAL,Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog.."
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bitfld.long 0x0 12. "INT_EARLY,Windowed Watchdog Timer Interrupt Flag Too Soon." "0: No interrupt is pending.,1: An interrupt is pending."
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|
newline
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bitfld.long 0x0 11. "WDT_RST_EN,Windowed Watchdog Timer Reset Enable." "0: Disable.,1: Enable."
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bitfld.long 0x0 10. "WDT_INT_EN,Windowed Watchdog Timer Interrupt Enable." "0: Disable.,1: Enable."
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newline
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bitfld.long 0x0 9. "INT_LATE,Windowed Watchdog Timer Interrupt Flag Too Late." "0: No interrupt is pending.,1: An interrupt is pending."
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bitfld.long 0x0 8. "EN,Windowed Watchdog Timer Enable." "0: Disable.,1: Enable."
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newline
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hexmask.long.byte 0x0 4.--7. 1. "RST_LATE_VAL,Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time.."
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hexmask.long.byte 0x0 0.--3. 1. "INT_LATE_VAL,Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the.."
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wgroup.long 0x4++0x3
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line.long 0x0 "RST,Windowed Watchdog Timer Reset Register."
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hexmask.long.byte 0x0 0.--7. 1. "RESET,Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT.."
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group.long 0x8++0x3
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line.long 0x0 "CLKSEL,Windowed Watchdog Timer Clock Select Register."
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bitfld.long 0x0 0.--2. "SOURCE,WWDT Clock Selection Register." "0,1,2,3,4,5,6,7"
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rgroup.long 0xC++0x3
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line.long 0x0 "CNT,Windowed Watchdog Timer Count Register."
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hexmask.long 0x0 0.--31. 1. "COUNT,Current Value of the Windowed Watchdog Timer Counter."
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tree.end
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tree.end
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AUTOINDENT.OFF
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